Method of manufacturing a semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least spaced gate oxide trenches and a first depth adjustment trench. The depth of the first depth adjustment trench can be used to increase the bottom depth of the shallow trench isolation structure of the high-voltage transistor, thereby increasing the breakdown voltage of the high-voltage transistor. The gate oxide trenches and the etching of the top of the active region in the gate oxide trenches are used to reduce the top height of the active region, thereby reducing the step height between the high-voltage transistor and other components after the formation of a thick gate oxide layer. Furthermore, after forming the side trenches, the top corner of the active region is pre-implanted with first ions. When the active region in the gate oxide trench is further etched, a convex corner of the active region can be formed. The oxidation at the convex corner of the active region is then used to solve the problem of the gate oxide layer being thin at the top corner of the active region of the high-voltage transistor, thereby improving the voltage withstand capability of the high-voltage transistor in the semiconductor device of this invention.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] High-voltage transistors (HVMOS) are devices capable of withstanding higher voltages while ensuring that the gate is not broken down under high-voltage operation. On one hand, the source / drain regions of an HVMOS are isolated from the device channel by a shallow trench isolation (STI) structure to improve the breakdown voltage. This STI structure is typically formed during the active region formation process (AA loop), along with the STI structures of other components (such as low-voltage LVMOS, medium-voltage MVMOS, or core components). The trench depth of the STI structure is limited by the process technology and its stability, making it difficult to deepen further using the AA loop. On the other hand, the gate oxide process in HVMOS involves directly growing the gate oxide layer (HV GOX) on the silicon wafer surface. However, after the HV GOX is grown, a step height (SH) inevitably exists between the HVMOS and other components because the HV GOX... The gate oxide layer (GOX) is much thicker than that formed on other device regions such as LVMOS and MVMOS (e.g., two orders of magnitude thicker). This step height will increase the process loading in subsequent processes, which may affect the performance of HVMOS. For example, this step height may cause insufficient overlap between the drift region and the gate in HVMOS, thus affecting the performance of HV devices.

[0003] Therefore, how to provide a method for manufacturing semiconductor devices that improves the performance of high-voltage transistors without degrading the performance of other components is one of the important technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can improve the performance of a high-voltage transistor without degrading the performance of other components.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] A substrate is provided, and a trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a spaced-apart gate oxide trench and a first depth adjustment trench, the first depth adjustment trench being located outside the gate oxide trench.

[0007] A hard mask layer is formed covering the substrate having the first depth adjustment groove and the gate oxide groove;

[0008] An active region manufacturing process is performed on the hard mask layer and the substrate it covers to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with the first depth adjustment trench and communicates with the first depth adjustment trench and the gate oxide trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench.

[0009] Dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench to form a shallow trench isolation structure, wherein the hard mask layer in the gate oxide trench is buried within the remaining dielectric material;

[0010] Etching removes the dielectric material in the gate oxide trench and part of the top of the shallow trench isolation structure outside the gate oxide trench, forming a side trench that exposes the apex corner of the active region at the gate oxide trench;

[0011] The first ion is used to pre-implant the shallow layer at the apex of the active region;

[0012] Remove the hard mask layer in the gate oxide trench and further etch to reduce the top height of the active region at the gate oxide trench. The first ion is used to reduce the etching rate of the top corner of the active region, so that the top corner of the active region is relatively convex after etching and becomes a convex corner of the active region.

[0013] Oxidize the convex corner of the active region and the top of the active region in the gate oxide trench to form a thick gate oxide layer.

[0014] Optionally, the step of forming the gate oxide groove and the first depth adjustment groove includes:

[0015] A first pad oxide layer, a first nitride layer, and a first photoresist layer are sequentially formed on the substrate;

[0016] The first photoresist layer is photolithographically ...

[0017] Using the first photoresist layer after photolithography as a mask, the first nitride layer, the first pad oxide layer and the substrate are etched sequentially to form the gate oxide trench and the first depth adjustment trench in the substrate;

[0018] Remove the first photoresist layer, the first nitride layer, and the first pad oxide layer.

[0019] Optionally, performing an active region fabrication process on the hard mask layer and the substrate it covers includes the following steps:

[0020] A second photoresist layer is formed on the hard mask layer;

[0021] The second photoresist layer is photolithographically etched using a second photomask to define the formation area of ​​each of the shallow trenches;

[0022] Using the second photoresist layer after photolithography as a mask, the hard mask layer and the substrate are etched to form the corresponding shallow trench;

[0023] Remove the second photoresist layer.

[0024] Optionally, while etching to reduce the top height of the active region at the gate oxide trench, the shallow layer pre-implanted by the first ion is etched away; and / or, before or after pre-implanting the shallow layer at the apex of the active region with the first ion, a deep layer at the apex of the active region is pre-implanted with a second ion, the deep layer pre-implanted by the second ion being retained in the convex corner of the active region, and the second ion being used to increase the oxidation rate of the convex corner of the active region during the formation of the thick gate oxide layer.

[0025] Optionally, the first ion includes boron fluoride ions; and / or, the second ion includes at least one of oxygen ions, amorphous ions, and halide ions, wherein the amorphous ions include at least one of silicon ions, germanium ions, and argon ions.

[0026] Optionally, while performing trench etching on the substrate area to be fabricated as a high-voltage transistor to form the gate oxide trench and the first depth adjustment trench, at least one second depth adjustment trench is also formed at the boundary of the active region of the high-voltage transistor. After performing the active region fabrication process, the second depth adjustment trench overlaps with and communicates with the corresponding shallow trench to deepen the bottom depth of the shallow trench and separate the active region of the high-voltage transistor from the active regions of other components.

[0027] Optionally, the method for manufacturing the semiconductor device further includes at least one of the following (1) to (6):

[0028] (1) After forming the first depth adjustment trench and the gate oxide trench and before forming the shallow trench, or after forming the shallow trench and before filling the dielectric material, at least the top sidewall of the active region in the gate oxide trench is ion implanted to form a first drift region.

[0029] (2) After the shallow trench isolation structure is formed and before the side trench is formed, the active region of the high voltage transistor is ion implanted to form a second drift region.

[0030] (3) Before filling the dielectric material, or after forming the trench and before pre-implanting the shallow layer at the apex of the active region with the first ion, the sidewalls of the hard mask layer in the gate oxide trench are also pulled back and etched to expose more area at the apex of the active region.

[0031] (4) After the active region convex corner is formed and before the thick gate oxide layer is formed, the surface of the active region convex corner and the top surface of the active region in the gate oxide tank are oxidized to form a first line oxide layer.

[0032] (5) After the active region convex corner is formed and before the thick gate oxide layer is formed, the steps of first forming a sacrificial oxide layer and then removing the sacrificial oxide layer are performed multiple times to adjust the height of the active region convex corner. The sacrificial oxide layer is formed by oxidizing the active region surface at the gate oxide trench.

[0033] (6) After forming the thick gate oxide layer, a thin gate oxide layer is also formed on the active region of the other elements, and a gate is formed together on the thick gate oxide layer and the thin gate oxide layer.

[0034] Optionally, a lightly doped source-drain ion implantation process is used to implant ions into at least the top sidewall of the active region of the gate oxide trench to form the first drift region.

[0035] Optionally, the step of forming the first drift region includes:

[0036] A third photoresist layer is formed on the substrate;

[0037] Photolithography is performed on the third photoresist layer to at least open the third photoresist layer on the active region convex corner and the gate oxide trench, and to mask other areas;

[0038] Using the third photoresist layer after photolithography as a mask, and employing a lightly doped source / drain ion implantation process, the first drift region is formed.

[0039] Optionally, the method for manufacturing the semiconductor device further includes at least one of the following (1) to (7):

[0040] (1) At least one first depth adjustment groove is formed on both sides of the gate oxide cell;

[0041] (2) The hard mask layer includes a second pad oxide layer and a second nitride layer sequentially stacked on the substrate;

[0042] (3) The sidewall of the first depth adjustment groove is aligned with or forms a step with the sidewall of the shallow groove it communicates with;

[0043] (4) Photolithography and trench etching are performed on the substrate area to be fabricated for high voltage transistors using the zero-layer photomask, so as to form the first depth adjustment trench and the gate oxide trench at the same time as forming the zero-layer alignment mark in the substrate.

[0044] (5) Before filling the gate oxide trench, each of the shallow trenches and the first depth adjustment trench with dielectric material, a second line oxide layer is formed on the inner surface of the gate oxide trench, each of the shallow trenches and the first depth adjustment trench.

[0045] (6) After the gate oxide trench, each of the shallow trenches and the first depth adjustment trench are filled with dielectric material, the top of the dielectric material is planarized until the top surface of the hard mask layer on the substrate region surrounding the gate oxide trench is exposed or until the top surface of the active region convex corner is exposed.

[0046] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0047] 1. Before the active region fabrication process, trench etching is performed on the substrate area to be fabricated as a high-voltage transistor to form at least spaced gate oxide trenches and a first depth adjustment trench. This increases the bottom depth (ST Itrench) of the shallow trench isolation structure used to isolate the source / drain region and channel region of the high-voltage transistor by utilizing the depth of the first depth adjustment trench, thereby increasing the charge path of the high-voltage transistor, increasing its breakdown voltage, and improving the performance of the high-voltage transistor. On the other hand, after the side trench is formed, the active region apex is pre-implanted with first ions. When the hard mask layer in the gate oxide trench is removed and the active region is further etched, the etching rate of the active region apex is low due to the first ions, forming a convex corner of the active region. This increases the contact area between the active region and oxygen at this point, thus solving the problem of the gate oxide layer being thin at the active region apex of the high-voltage transistor. This helps to reduce leakage current at the active region apex, reduce the hot carrier (HCI) effect and gate-induced drain leakage (GIDL), and further improve the voltage withstand capability of the high-voltage transistor in the semiconductor device of the present invention.

[0048] 2. By using the gate oxide trench and etching the top of the active region in the gate oxide trench, the top height of the active region can be reduced. The height and width of the convex corner of the formed active region can be controlled by the implantation range of the first ion. This can reduce the step height between the high voltage transistor and other components compared with the existing technology, reduce the load effect and defects of subsequent processes, and help control the corner thickness of the thick gate oxide layer, further improving device performance.

[0049] 3. Under the same voltage withstand capability, the high voltage transistor of the present invention can have a shorter active region length compared with the existing high voltage transistor, which is beneficial to reduce the area of ​​the high voltage transistor, thereby reducing the chip area and improving the integration density. Attached Figure Description

[0050] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0051] Figure 1 This is a schematic diagram of a semiconductor device manufacturing method according to a specific embodiment of the present invention.

[0052] Figures 2A to 2B This is a schematic cross-sectional view of an example device structure in a specific embodiment of the semiconductor device manufacturing method of the present invention.

[0053] Figures 3 to 11 This is a cross-sectional schematic diagram of other example device structures in the manufacturing method of a semiconductor device according to a specific embodiment of the present invention.

[0054] Figure 12 This is a schematic diagram of the photoresist edge rounding exposure in the existing LDD (lightly doped drain implantation) process. Detailed Implementation

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0056] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0057] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0058] S1, providing a substrate, and performing trench etching on the substrate region to be fabricated as a high-voltage transistor to form at least spaced-apart gate oxide trenches and a first depth adjustment trench, the first depth adjustment trench being located outside the gate oxide trenches;

[0059] S2, forming a hard mask layer covering the substrate having the first depth adjustment trench and the gate oxide trench;

[0060] S3, perform an active region manufacturing process on the hard mask layer and the substrate it covers to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with the first depth adjustment trench and communicates with the first depth adjustment trench and the gate oxide trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench.

[0061] S4, dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench to form a shallow trench isolation structure, wherein the hard mask layer in the gate oxide trench is buried within the remaining dielectric material;

[0062] S5, etch away the dielectric material in the gate oxide trench and part of the top of the shallow trench isolation structure outside the gate oxide trench to form a side trench that exposes the apex corner of the active region at the gate oxide trench.

[0063] S6, the first ion is used to pre-implant the shallow layer at the apex of the active region;

[0064] S7, remove the hard mask layer in the gate oxide trench, and further etch to reduce the top height of the active region at the gate oxide trench. The first ion is used to reduce the etching rate of the top corner of the active region, so that the top corner of the active region after etching protrudes relatively and becomes a convex corner of the active region.

[0065] S8, oxidize the convex corner of the active region and the top of the active region in the gate oxide trench to form a thick gate oxide layer.

[0066] Please refer to Figure 2AIn step S1, firstly, the provided substrate 100 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI). The substrate 100 can be a bare silicon wafer or a wafer that has undergone appropriate processing. Next, any suitable process can be used to form the required gate oxide trench 103 and the first depth adjustment trench 104a in the substrate region HV (which can be simply referred to as the "high-voltage transistor region HV") where the high-voltage transistor is to be fabricated. In this example, the gate oxide trench 103 and the first depth adjustment trenches 104a on both sides are connected as a single unit.

[0067] As an example, please continue to refer to Figure 2A The steps of forming the gate oxide trench 103 and the first depth adjustment trench 104a include:

[0068] S1.1, a first pad oxide layer 101, a first nitride layer 102 and a first photoresist layer 200 are sequentially formed on the substrate 100. The first pad oxide layer 101 can be formed by any suitable process such as thermal oxidation, the first nitride layer 102 can be formed by any suitable process such as chemical vapor deposition, and the first photoresist layer 200 can be formed by spin coating.

[0069] S1.2, a first photomask (not shown) is used to perform photolithography on the first photoresist layer 200 to define the formation areas of the gate oxide trench 103 and the first depth adjustment trench 104a in the substrate region HV to be fabricated for the high voltage transistor.

[0070] S1.3, using the first photoresist layer 200 after photolithography as a mask, any suitable etching process, such as dry etching, can be used to sequentially etch the first nitride layer 102, the first pad oxide layer 101, and the substrate 100 to form spaced-apart gate oxide trenches 103 and first depth adjustment trenches 104a in the substrate 100. The formation region of the gate oxide trenches 103 is located in the gate oxide region of the high-voltage transistor, and its linewidth is smaller than that of the gate oxide region of the high-voltage transistor. The first depth adjustment trenches 104a are located outside the gate oxide trenches 103, and can be set on one side or both sides of the gate oxide trenches 103. The gate oxide trenches 103 and the first depth adjustment trenches 104a are not connected, and the substrate between them is formed as an active region convex corner 100a. The distance between the gate oxide groove 103 and the first depth adjustment groove 104a determines the linewidth of the active region convex angle 100a, and the depth of the gate oxide groove 103 determines the protrusion height of the active region convex angle 100a.

[0071] S1.4, the first photoresist layer 200 is removed by any suitable photoresist removal process such as dry photoresist removal or wet photoresist removal, and the first nitride layer 102 and the first pad oxide layer 101 are removed by any suitable process such as wet etching.

[0072] It should be understood that the depths of both the gate oxide trench 103 and the first depth adjustment trench 104a are h, and h needs to meet not only the thickness requirements of the gate oxide layer of the high-voltage transistor, but also the depth requirements of the shallow trench isolation (STI) structure surrounding the gate oxide trench of the high-voltage transistor (i.e., ensuring that the active region height of the shallow trench and gate oxide region of the high-voltage transistor is reduced). As an example, h is approximately (can be) etc).

[0073] In one example, please refer to Figure 2A In step S1.2, a first photomask (not shown) is used to perform photolithography on the first photoresist layer 200, defining not only the formation area of ​​the gate oxide trench 103 but also the formation area of ​​the second depth adjustment trench 104b in the substrate region HV where the high-voltage transistor is to be fabricated. In step S1.3, using the photolithographically rendered first photoresist layer 200 as a mask, the substrate 100 is etched, forming the gate oxide trench 103 and the first depth adjustment trench 104a in the substrate 100, while also forming the second depth adjustment trench 104b. In this design, the first depth adjustment trench 104a separates the active region HVG and the source / drain region HVS / D of the gate oxide trench 103 of the high-voltage transistor. The second depth adjustment trench 104b is located at the boundary of the active region of the high-voltage transistor to be fabricated, and is used to achieve device isolation between the high-voltage transistor and other surrounding components together with the shallow trench subsequently connected to it. The substrate region between the second depth adjustment trench 104b and the first depth adjustment trench 104a is used to fabricate the source / drain region HVS / D of the high-voltage transistor. The second depth adjustment trench 104b deepens the bottom depth of the subsequently formed shallow trench isolation structure STI2, enhances the isolation performance of the shallow trench isolation structure STI2, and further improves the performance of the high-voltage transistor.

[0074] In one example, please refer to Figure 3In step S1.2, when the substrate 100 provided in step S1.1 is a bare silicon wafer, a gate oxide trench 103, a first depth adjustment trench 104a, and a second depth adjustment trench 104b can be formed in the substrate 100 through a zero-loop fabrication process. In this example, the first pad oxide layer 101, the first nitride layer 102, and the photoresist layer 200 sequentially formed on the substrate 100 are the initial layers (also called the zero layer) formed on the surface of the substrate 100, and have not yet undergone an etching step, so the surface of the substrate 100 has no uneven terrain. Therefore, the first photomask used in step S1.2 is the zero-loop photomask, which is the photomask required in the first photolithography process of substrate fabrication. This zero-loop photomask is usually used to define the formation area of ​​the zero-loop alignment mark ZM0, which is used for alignment in subsequent photolithography processes. Clearly, the zero-layer photomask in this example (i.e., the first photomask), compared to the zero-layer photomask of the prior art, not only defines the formation region of the zero-layer alignment mark ZM0 (which can be located on the periphery of the substrate region Other to be manufactured), but also simultaneously defines the formation regions of the gate oxide trench 103, the first depth adjustment trench 104a, and the second depth adjustment trench 104b (these trenches are all located in the substrate region HV to be manufactured for the high-voltage transistor), or simultaneously defines the formation regions of the gate oxide trench 103, the first depth adjustment trench 104a, and the second depth adjustment trench 104b. Thus, in step S1.3, the first depth adjustment trench 104a, the second depth adjustment trench 104b, and the zero-layer alignment mark ZM0 are formed simultaneously, with the depth of the gate oxide trench 103 being the same as the depth of the zero-layer alignment mark ZM0. The zero-layer alignment mark ZM0 can be filled with dielectric material in the subsequent step S5.

[0075] Figures 2A to 2B and Figure 3 In the example shown, a first depth adjustment groove 104a communicating with the gate oxide groove 103 is formed on one side in step S1, but the technical solution of the present invention is not limited to this.

[0076] In another example of this embodiment, please refer to Figure 3 and Figure 4 In step S1, the gate oxide trench 103 is not connected to the first depth adjustment trench 104a, and the number of first depth adjustment trenches 104a on one side of the gate oxide trench 103 can be one (e.g., Figure 3 (as shown) or 2 (such as) Figure 4(as shown) or two or more. Thus, after the subsequent step S3, the shallow trenches 107 formed on both sides of the gate oxide tank 103 are connected to one or more first depth adjustment grooves 104a on the same side, and each first depth adjustment groove 104a causes the bottom of the shallow trench 107a to form a deepening groove 107a corresponding to the first depth adjustment groove 104a.

[0077] Please refer to Figure 5 In another example of this embodiment, in step S1.2, when photolithography is performed on the first photoresist layer 200 using a first photomask (not shown), the formation region of the second depth adjustment trench is not defined at the boundary region of the substrate region HV to be fabricated for the high-voltage transistor. In step S1.3, after etching the substrate 100 using the photolithographically rendered first photoresist layer 200 as a mask, the second depth adjustment trench is not formed simultaneously while the gate oxide trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) is formed in the substrate 100. Therefore, after the subsequent step S3, the bottom depth of the shallow trench 108 formed at the boundary of the substrate region HV to be fabricated for the high-voltage transistor (hereinafter referred to as "high-voltage transistor region HV") is the same as the bottom depth of the shallow trench 109 formed in the substrate region Other to be fabricated for other components (hereinafter referred to as "other component region Other").

[0078] Furthermore, it should be understood that in the above examples, the critical dimension CD of the first depth adjustment groove needs to meet the requirements of subsequent processes, such as being at least greater than 80nm, to ensure the process window for forming the second pad oxide layer 105 and the second nitride layer 106 in the subsequent step S2.

[0079] Please continue to refer to this. Figure 2A In step S2, a second pad oxide layer 105 and a second nitride layer 106 are sequentially formed on the surface of the substrate 100 after the gate oxide trench 103 is formed. The second pad oxide layer 105 covers the inner surfaces of the gate oxide trench 103 and the first depth adjustment trench 104a, as well as the surface of the substrate 100 surrounding the gate oxide trench 103. The second pad oxide layer 105 and the second nitride layer 106 constitute the required hard mask layer. The second pad oxide layer 105 can be formed by any suitable process such as thermal oxidation or chemical vapor deposition. It serves as an etch stop layer for etching the second nitride layer 106 and protects the surface of the substrate 100 during the etching of the second nitride layer 106. The second nitride layer 106 can be formed by any suitable process such as chemical vapor deposition, and its material can be any suitable dielectric material such as silicon nitride.

[0080] Please continue to refer to this. Figure 2AIn step S3, an active region fabrication process (AA loop) is performed on the hard mask layer and the substrate 100 it covers to form corresponding shallow trenches 107, 108, and 109 in the substrate 100 at the first depth adjustment trench 104a and in the substrate 100 surrounding the first depth adjustment trench 104a, thereby defining the active regions of the high-voltage transistor and other components. The specific process of this active region fabrication process (AA loop) includes:

[0081] S3.1, A second photoresist layer 201 is formed on the second nitride layer 106 by spin coating or other processes;

[0082] S3.2, the second photoresist layer 201 is photolithographically ...

[0083] S3.3, using the second photoresist layer 201 after photolithography as a mask, the second nitride layer 106, the second pad oxide layer 105 and the substrate 100 are etched using any suitable etching process such as dry etching to form the corresponding shallow trenches 107, 108 and 109.

[0084] S3.4, Remove the second photoresist layer 201 by any suitable photoresist removal process, such as dry or wet photoresist removal.

[0085] The shallow trench 107 formed at the first depth adjustment trench 104a is located on both sides of the gate oxide trench 103, overlapping and communicating with the first depth adjustment trench 104a, and communicating with the gate oxide trench 103, thus separating the active region HVG at the gate oxide trench 103 from the source / drain region HVS / D of the high-voltage transistor. Due to the effect of the first depth adjustment trench 104a, the bottom of the shallow trench 107 formed at the first depth adjustment trench 104a is deeper than the bottom of the shallow trench 109 in the other component region. Furthermore, the shallow trench 108 is formed between the active region of the high-voltage transistor and the active regions of other components (i.e., between the HV region and the other region), serving two purposes: firstly, to achieve isolation between the active region of the high-voltage transistor and the active regions of other components; and secondly, to define the source / drain region HVS / D of the high-voltage transistor together with the shallow trench 107.

[0086] In one example, please refer to Figure 2ASince in step S1, gate oxide trenches 103, first depth adjustment trenches 104a, and second depth adjustment trenches 104b of essentially the same depth are simultaneously formed in the substrate region HV to be fabricated for the high-voltage transistor, in step S3, when performing the above-mentioned active region fabrication process, a corresponding shallow trench 108 is also formed in the substrate at the second depth adjustment trench 104b. The shallow trench 108 formed at the second depth adjustment trench 104b overlaps with and is connected to the second depth adjustment trench 104b. At this time, the bottom depth of the shallow trench 108 formed at the second depth adjustment trench 104b is essentially the same as the bottom depth of the shallow trench 107, and is deeper than the bottom of the shallow trench 109 in the other component region Other.

[0087] For other examples, please refer to Figure 5 When the second depth adjustment groove is not formed synchronously in step S1, after the above-mentioned active area manufacturing process is performed in step S3, the bottom depth of the shallow trench 108 formed is the same as the bottom depth of the shallow trench 109 in the other component area Other, and is shallower than the bottom depth of the shallow trench 107 formed at the first depth adjustment groove 104a.

[0088] Furthermore, it should be understood that the degree of overlap between the corresponding opening in the second photoresist layer 201 after photolithography and the first depth adjustment groove 104a determines the degree of overlap between the shallow trench 107 formed at the first depth adjustment groove 104a and the first depth adjustment groove 104a, and thus determines whether the sidewall of the shallow trench 107 formed at the first depth adjustment groove 104a is aligned with the sidewall of the first depth adjustment groove 104a or forms a step.

[0089] In one example, such as Figure 2A and Figure 5 As shown, the corresponding opening in the second photoresist layer 201 after photolithography is aligned with the first depth adjustment groove 104a, and the sidewall of the shallow trench 107 formed at the first depth adjustment groove 104a is aligned with the sidewall of the first depth adjustment groove 104a.

[0090] In another example, please refer to Figure 4 and Figure 6 The size of the corresponding opening in the second photoresist layer 201 after photolithography is relatively large and offset outward relative to the sidewall of the first depth adjustment groove 104a. Therefore, a step is formed between the sidewall of the shallow trench 107 formed at the first depth adjustment groove 104a and the sidewall of the first depth adjustment groove 104a.

[0091] In yet another example, please refer to Figure 7The size of the corresponding opening in the second photoresist layer 201 after photolithography is relatively small and offset inward relative to the sidewall of the first depth adjustment groove 104a. Therefore, a step is also formed between the sidewall of the shallow trench 107 formed at the first depth adjustment groove 104a and the sidewall of the first depth adjustment groove 104a. In this case, the surface of the active region exposed by the first depth adjustment groove 104a above the top surface of the step is also covered with a second pad oxide layer 105 and a second nitride layer 106.

[0092] Similarly, when the second depth adjustment groove 104b is formed at the same time as the gate oxide groove 103 and the first depth adjustment groove 104a are formed, the degree of overlap between the shallow groove 108 at the second depth adjustment groove 104b and the second depth adjustment groove 104b is different. This can also make the sidewall of the shallow groove 108 at the second depth adjustment groove 104b aligned with the sidewall of the second depth adjustment groove 104b or form a step, which will not be described in detail here.

[0093] It should be understood that, in this embodiment, by utilizing the depths of the first depth adjustment trench 104a and the second depth adjustment trench 104b, the depths of the shallow trenches 107 and 108 in the substrate region of the high-voltage transistor (STI trench) can be increased, thereby increasing the charge path of the high-voltage transistor and increasing its breakdown voltage. Moreover, under the same breakdown voltage capability, the high-voltage transistor of the present invention can have a shorter active region length compared to existing high-voltage transistors, which is beneficial to reducing the area of ​​the high-voltage transistor, and thus the chip area, and improving integration density. At the same time, the depth of the gate oxide trench 103 is also used to reduce the top height of the thick gate oxide layer subsequently formed on the active region HVG, thereby reducing the step height (SH) between the high-voltage transistor and other components.

[0094] Please refer to Figure 2A In step S4, any suitable process can be used to fill dielectric material into each shallow trench 107, 108, 109 and gate oxide trench 103, first depth adjustment trench 104a, and second depth adjustment trench 104b to form the desired shallow trench isolation structures STI1, STI2, and STI3. Before or after filling the dielectric material, the hard mask layer (i.e., the second pad oxide layer 105 and the second nitride layer 106) on the active region HVG of the gate oxide trench 103 is retained. At this time, the remaining dielectric material shallow trench isolation structure STI1 buries the hard mask layer on the active region HVG of the gate oxide trench 103. Afterward, the second nitride layer 106 in the hard mask layer of the remaining areas (including the source / drain regions HVS / D of other component regions and high voltage transistor regions HV) can be removed, and even the second pad oxide layer 105 in these remaining areas can be further removed.

[0095] In one example, the process of forming the desired shallow trench isolation structures STI1, STI2, and STI3 in step S4 includes the following steps:

[0096] S4.1, a second oxide layer is formed through processes such as thermal oxidation (e.g., Figure 10 (As shown in 115) on the inner surfaces of shallow trenches 107, 108, 109 and the first depth adjustment groove 104a and the second depth adjustment groove 104b;

[0097] S4.2, using a high aspect ratio fill process (HARP) or other suitable process, deposit dielectric material 110 (e.g., silicon oxide) into shallow trenches 107, 108, 109 and gate oxide trench 103, first depth adjustment trench 104a, and second depth adjustment trench 104b until the shallow trenches 107, 108, 109 and gate oxide trench 103, first depth adjustment trench 104a, and second depth adjustment trench 104b are filled;

[0098] S4.3, using a suitable process such as chemical mechanical polishing, the top surface of the filled dielectric material 110 is planarized until the top surface of the second nitride layer 106 is exposed. This forms a shallow trench isolation structure STI1 in the shallow trench 107 to isolate the active region HVG of the gate oxide trench 103 from the source / drain region HVS / D of the high-voltage transistor; a shallow trench isolation structure STI2 is formed in the connected shallow trench 108 and the second depth adjustment trench 104b to define the source / drain region HVS / D of the high-voltage transistor and isolate the high-voltage transistor from other components; and a shallow trench isolation structure STI3 is formed in the shallow trench 109 to isolate other components from the high-voltage transistor. At this time, due to the gate oxide trench 103, the second nitride layer 106 and the second pad oxide layer 105 on the active region HVG of the gate oxide trench 103 are retained and buried within the shallow trench isolation structure STI1.

[0099] S4.4, the second nitride layer 106 exposed by the shallow trench isolation structure STI1 (i.e., the hard mask layer on the area other than the gate oxide trench 103) is removed by any suitable process such as wet etching, and the second pad oxide layer 105 is retained. The second pad oxide layer 105 protects the surface of the substrate 100 other than the active region HVG of the gate oxide trench 103 in subsequent steps S5 and S6.

[0100] In other examples of this embodiment, in step S4.3, a suitable process such as chemical mechanical polishing can also be used to planarize the top surface of the filled dielectric material 110 until the second nitride layer 106 on the substrate other than the active region HVG of the gate oxide trench 103 is removed. The second pad oxide layer 105 in these remaining areas can even be further removed, thereby saving an etching process.

[0101] Optionally, before step S4.1, any suitable process such as dry etching is used to pull back the second nitride layer 106 in the hard mask layer, so that the pattern sidewall of the second nitride layer 106 on the top corner of the active region exposed by the gate oxide trench 103 is pulled back a certain distance, so as to expose more of the top corner of the active region.

[0102] Please refer to Figure 2B In step S5, firstly, a silicon nitride layer 111 is deposited using a process such as chemical vapor deposition; then, a photoresist layer (not shown) is spin-coated onto the silicon nitride layer 111, and photolithography is performed on the photoresist layer to open the photoresist layer on the active region HVG at the gate oxide trench 103, forming a patterned photoresist layer (not shown); then, using the patterned photoresist layer as a mask, the silicon nitride layer 111 is etched to open the silicon nitride layer 111 on the active region HVG at the gate oxide trench 103; next, the patterned photoresist layer is removed, and using the silicon nitride layer 111 as a mask, the dielectric material 111 on the hard mask layer at the gate oxide trench 103 is etched away until the active region at the gate oxide trench 103 is exposed. A second nitride layer 106 is applied to the HVG region. Then, under the protection of the second nitride layer 106, the top sidewall of the shallow trench isolation structure STI1 in the shallow trench 107 (i.e., on both sides of the active region HVG located at the gate oxide trench 103) is etched to form a side trench 112 that exposes the active region corner sidewall of the active region HVG at the gate oxide trench 103. During this process, the presence of the second nitride layer 106 can form an etching protection for the active region HVG at the gate oxide trench 103, resulting in more consumption of dielectric material 110 at the side trench 112 and less consumption of the second pad oxide layer 105 below the second nitride layer 106 and the corner of the active region, which is beneficial to optimizing the corner rounding of the active region HVG of the gate oxide trench. The thickness of the silicon nitride layer 111 is generally much thicker than that of the second nitride layer 106. Therefore, when the second nitride layer 106 is removed in step S7, even if the silicon nitride layer 111 and the second nitride layer 106 are consumed simultaneously, there will be no adverse effects.

[0103] Please continue to refer to this. Figure 2B In step S6, under the masking of the silicon nitride layer 111 and the second nitride layer 106, a suitable first ion is used to pre-implant the shallow layer at the apex of the active region at the gate oxide trench 103. This pre-implantation process can be a tilted ion implantation process or a vertical ion implantation process. The first ion is used to reduce the etching rate at the apex of the active region HVG at the gate oxide trench 103 during subsequent etching. In one example, the first ion may include boron fluoride (BF2).

[0104] It should be understood that the implantation depth of the first ion should be shallower than the active region depth required to form the convex angle 100a of the active region, so as not to affect the threshold voltage of the high voltage transistor.

[0105] Optionally, to ensure the implantation effect of the first ion in the shallow layer at the apex of the active region at gate oxide cell 103, please refer to... Figure 2B The hard mask layer located at the apex of the active region in the gate oxide trench 103 can be pulled back and etched using any suitable process, such as dry etching or wet etching, to expose more area of ​​the active region apex in the gate oxide trench 103. This pull-back etching process will thin the silicon nitride layer 11 accordingly but will not affect its function as a hard mask layer.

[0106] Optionally, to ensure the oxidation effect of the subsequently formed active region convex corner 100a, in step S6, before or after the pre-implantation of the shallow layer of the active region apex corner at the gate oxide tank 103 with the first ion, a second ion can be used to pre-implant the deep layer of the active region apex corner at the gate oxide tank 103. This second ion is retained during the subsequent formation of the active region convex corner 100a (i.e., retained within the active region convex corner 100a) to improve the oxidation rate of the active region convex corner 100a. The second ion may include at least one of oxygen ions, amorphous ions, and halide ions. The implantation of oxygen ions can increase the oxygen content in the active region convex corner 100a, thereby increasing the oxidation rate during the subsequent oxidation of the active region convex corner 100a. Amorphous ions include, for example, at least one of silicon ions, germanium ions, or argon ions. For instance, when the intrinsic material of the substrate 100 is monocrystalline silicon, the implantation of amorphous ions can transform the monocrystalline silicon in the active region convex corner 100a into amorphous silicon, thereby increasing the oxidation rate during subsequent oxidation of the active region convex corner 100a. Halogen ions include, for example, at least one of chloride ions (Cl), fluoride ions (F), and bromide ions (Br). The implantation of halide ions can act as a catalyst, weakening the Si-O bond energy in the active region convex corner 100a. Therefore, during subsequent oxidation of the active region convex corner 100a, the Si-O bond energy in the already formed upper oxide layer is further weakened, making it easier for oxygen to diffuse in, thereby increasing the oxidation rate during the oxidation of the active region convex corner 100a.

[0107] Please continue to refer to this. Figure 2BIn step S7, firstly, the second nitride layer 106 and the second pad oxide layer 105 in the gate oxide trench 103 are removed using any suitable process such as wet etching to expose the top surface of the active region HVG at the gate oxide trench 103 (including the surface of the active region convex corner 100a). It should be understood that the silicon nitride layer 111 formed in step S5 needs to be sufficiently thick, which can be thinned as a whole during the removal of the second nitride layer 106, but still provide the required masking effect. Then, under the masking effect of silicon nitride 115, the top of the active region HVG at the gate oxide trench 103 is etched using any suitable etching process such as dry etching or wet etching, further reducing the top height of the active region HVG at the gate oxide trench 103 to the required height. During this etching process, due to the implantation of the first ion in the active region apex of the gate oxide trench 103, the etching rate at the active region apex of the gate oxide trench 103 is relatively slow. Ultimately, upon completion of etching, the active region apex of the gate oxide trench 103 becomes a protrusion relative to other areas of the active region within the gate oxide trench 103, forming a self-aligned topography known as the active region convex angle 100a. The formation of the active region convex angle 100a does not require an additional mask.

[0108] In one example, during step S7, when etching the top of the active region HVG at the gate oxide trench 103, the shallow layer at the apex of the active region pre-implanted by the first ion is completely etched away to form the active region convex corner 100a. When a second ion is pre-implanted into the deep layer of the active region apex in step S6, the deep layer at the apex of the active region pre-implanted by the second ion is retained in the active region convex corner 100a in step S7 to improve the rate of subsequent oxidation of the active region convex corner 100a.

[0109] In one example, please refer to Figure 8 In step S7, after forming the active region convex corner 100a and before executing step S8, the steps of first forming a sacrificial oxide layer 116 and then removing the sacrificial oxide layer 116 are performed multiple times to adjust the height and morphology of the active region convex corner 100a in the gate oxide trench 103, making the active region convex corner 100a more rounded. The sacrificial oxide layer 116 can be formed by oxidizing the active region convex corner 100a and the active region HVG surface at the gate oxide trench 103. Thus, through the growth and removal of the sacrificial oxide layer 116, the linewidth, height, and morphology of the active region convex corner 100a are gradually controlled, and the active region convex corner 100a is rounded. This allows the active region convex corner 100a to be subsequently oxidized into a thick gate oxide layer 113, avoiding the problem of sharp corners in the active region HVG after forming the thick gate oxide layer 113, and eliminating the step height (SH) between the high-voltage transistor and other components.

[0110] Please continue to refer to this. Figure 2BIn step S8, a thick gate oxide layer 113 of the required thickness can be formed on the top surface of the active region HVG, including the active region convex corner 100a, in the gate oxide trench 103 by any suitable process such as thermal oxidation, under the masking of the silicon nitride layer 111. Since the top of the active region in the gate oxide trench 103 has been lowered, the step height (SH) between the high-voltage transistor and other components can be reduced, thereby reducing the load effect and defects in subsequent processes, improving the performance of the high-voltage transistor, and facilitating the reduction of the device area of ​​the high-voltage transistor.

[0111] In this step, the active region convex corner 100a can be completely oxidized by controlling the oxidation time.

[0112] In one example, when a second ion is pre-implanted into the deep layer of the active region apex corner in step S6, the deep layer of the active region apex corner pre-implanted with the second ion is retained in the active region convex corner 100a in step S7. In step S8, the second ion can increase the oxidation rate of the active region convex corner 100a, making the thick gate oxide layer 113 formed at the active region convex corner 100a thicker than the thick gate oxide layer 113 formed in other areas of the gate oxide trench 103. Thus, the thick gate oxide layer 113 has an overall "cat ear" shaped structure with thicker edges and slightly thinner middle.

[0113] In one example, in step S8, after forming the active region convex corner 100a and before growing the thick gate oxide layer 113, the surfaces of the active region HVG and the active region convex corner 100a of the gate oxide trench 103 are oxidized by a thermal oxidation process to form a first-line oxide layer (not shown). This process of forming the thick gate oxide layer 113 by oxidizing the active region convex corner 100a and the surface of the active region HVG at the gate oxide trench 103 allows for more favorable growth of oxide layers on each crystal plane of the active region at the gate oxide trench 103 using the first-line oxide layer. This facilitates control over the morphology of the thick gate oxide layer 113 and also helps to round the corners of the remaining active region HVG after oxidation at the bottom of the gate oxide trench 103, avoiding the problem of sharp points in the formed thick gate oxide layer 113. This further improves the voltage withstand capability of the high-voltage transistor in the semiconductor device of the present invention.

[0114] To further improve device performance, please refer to other examples in this embodiment. Figure 9 and Figure 10After completing step S1 and before executing step S3, or after completing step S3 and before executing step S4, a lightly doped source-drain (LDD) ion implantation process is used to implant ions into at least the active region HVG of the high-voltage transistor to form a first drift region 100b on the top sidewall of the active region HVG of the high-voltage transistor. Whether the conductivity type of the ions implanted in this step is n-type or p-type depends on whether the high-voltage transistor is an nMOS or pMOS. The LDD process used in this step is a tilted ion implantation process, and its conditions can be the same as those of the existing LDD process. Therefore, its vertical implantation depth is shallow, and its lateral implantation depth in the gate oxide region is also shallow, resulting in a low implantation concentration.

[0115] In one example, please refer to Figure 9 After completing step S1 and before executing step S3, under the masking of the first pad oxide layer 101 and the first nitride layer 102, a lightly doped source / drain ion implantation process (a tilted ion implantation process) is used to implant ions into the active region of the high-voltage transistor to form a first drift region 100b. This first drift region 100b extends from the source / drain region HVS / D of the high-voltage transistor to the sidewall of the active region HVG at the gate oxide trench 103. After step S3 is completed, the active region HVG at the gate oxide trench 103 exposes the first drift region 100b of a corresponding thickness near the sidewall of the shallow trench 107, and the first drift region 100b is also retained in the source / drain region HVS / D of the high-voltage transistor. The first drift region 100b is also formed in the active region convex corner 100a.

[0116] In another example, please refer to Figure 10 In step S4, before filling with dielectric material, a third photoresist layer 202 is formed on a substrate 100 having shallow trenches 107, etc., by spin coating or other processes. Then, the third photoresist layer is photolithographically etched to open the third photoresist layer 202 at the gate oxide trench 103 and mask other areas. Next, using the photolithographically etched third photoresist layer 202 as a mask, a lightly doped source / drain ion implantation process (a tilted ion implantation process) is used to implant ions into the top sidewall of the active region HVG at the gate oxide trench 103 to form a first drift region 100b. In this case, the first drift region 100b is only located in the top sidewall of the active region HVG at the gate oxide trench 103. After that, the third photoresist layer 202 is removed.

[0117] Further optional, please refer to Figure 11In step S4, before filling the dielectric material 110, a second line oxide layer 115 is formed on the inner surface of each shallow trench 107, 108, 109 by thermal oxidation. Then, a third photoresist layer 202 is coated and photolithography is performed. Then, under the mask of the third photoresist layer 202, the second line oxide layer 110 on the top sidewall of the active region HVG at the active region convex corner 100a and the gate oxide trench 103 is etched by any suitable etching process. Then, ion implantation is performed on the top sidewall of the active region HVG at the active region convex corner 100a and the gate oxide trench 103 to form a first drift region 100b, thereby ensuring the implantation effect of the first drift region 100b.

[0118] In the examples above, whether ion implantation of the first drift region 100b is performed before the shallow trench is formed, or after the shallow trench is formed and before the dielectric material is filled, ions can be effectively implanted into the corners of the area to be implanted in the LDD process. Compared with the prior art (i.e., first filling each shallow trench to form a shallow trench isolation structure, then defining the LDD process implantation area by photolithography of photoresist PR, and then performing the LDD process), the present invention can avoid the need for rounding the corners of the photoresist PR openings (e.g., ...). Figure 12 (As shown in the dashed box in the figure) This leads to imperfect corner injection of the active region HVG at the gate oxide trench in the LDD process, thus eliminating the side effect caused by the step height (SH) of the high voltage transistor in the prior art.

[0119] In addition, please refer to Figures 10 to 11 During the ion implantation process that forms the first drift region 100b, since the top of the active region HVG at the gate oxide trench 103 is also covered by the second pad oxide layer 105 and the second nitride layer 106, the ions can be implanted into the implantation region required by the LDD process and have a good protection effect on the active region below, without having a negative impact on the threshold voltage regulation of the high voltage transistor.

[0120] In one embodiment of this example, please continue to refer to... Figure 10After completing step S4 and before executing step S5, a patterned photoresist (not shown) is formed using photolithography to mask the active regions of other components (i.e., masking other component regions Other) and expose the active region of the high-voltage transistor (i.e., masking high-voltage transistor region HV). Using this patterned photoresist as a mask, ion implantation is performed on the active region of the high-voltage transistor using a suitable process such as vertical ion implantation to form a second drift region 100c. The implanted ions are suitable ions such as n-type or p-type ions. Afterward, the patterned photoresist is removed. The ion implantation depth for forming the second drift region 100c is greater than the ion implantation depth for forming the first drift region 100b. The second drift region 100c and the first drift region 100b are connected to form the drift region required for the high-voltage transistor.

[0121] As an example, ion implantation to form the second drift region 100c can include two steps: the first step involves slightly deeper ion implantation at a lower energy level, serving as channel conditioning. For pMOS transistors, this step can implant lightweight n-type ions such as phosphorus (P) ions, while for nMOS transistors, it can implant lightweight p-type ions such as boron (B) ions. The second step involves very shallow ion implantation at a very low energy level, serving as threshold voltage conditioning. This step can implant the same ions as the first step or different ions. For example, for pMOS transistors, this step can implant heavy n-type ions such as arsenic (As) or antimony (Sb) ions, which are less prone to diffusion; for nMOS transistors, this step can implant heavy n-type ions such as aluminum (Al), gallium (Ga), or indium (In), which are also less prone to diffusion.

[0122] In addition, it should be noted that after step S8, the silicon nitride layer 111 and the second pad oxide layer 105 covering it are removed first, and then a thin gate oxide layer (not shown) is formed on the active region of other components and the substrate region HV of the high voltage transistor to be fabricated, and the gate (not shown) is formed together on the thick gate oxide layer and the thin gate oxide layer.

[0123] In summary, the semiconductor device manufacturing method of the present invention first performs trench etching on the substrate region to be fabricated as a high-voltage transistor before performing the active region fabrication process, so as to form at least spaced gate oxide trenches and first depth adjustment trenches. This allows the depth of the first depth adjustment trenches to increase the bottom depth (STI) of the shallow trench isolation structure used to isolate the source / drain regions and channel regions of the high-voltage transistor. The formation of the trench increases the charge path of the high-voltage transistor, thereby increasing its breakdown voltage and improving its performance. On the other hand, after forming the trench, the active region corner is pre-implanted with first ions. When the hard mask layer in the gate oxide trench is removed and the active region is further etched, the etching rate of the active region corner is low due to the first ions, resulting in a convex corner of the active region. This increases the contact area between the active region and oxygen, thus solving the problem of the gate oxide layer being thin at the active region corner of the high-voltage transistor. This helps to reduce leakage current at the active region corner, reduce the hot carrier (HCI) effect and gate-induced drain leakage (GIDL), and further improve the voltage withstand capability of the high-voltage transistor in the semiconductor device of the present invention. Furthermore, by utilizing the gate oxide trench and etching the top of the active region within the trench, the top height of the active region is reduced. The height and width of the formed active region convex corner can be controlled by utilizing the implantation range of the first ions. This allows for a reduction in the step height between the high-voltage transistor and other components compared to existing technologies, minimizing the load effect and defects in subsequent processes. It also facilitates control over the edge thickness of the thick gate oxide layer, further improving device performance. The semiconductor device manufacturing method of this invention is simple, controllable, and effective.

[0124] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, and a trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a spaced-apart gate oxide trench and a first depth adjustment trench, the first depth adjustment trench being located outside the gate oxide trench. A hard mask layer is formed covering the substrate having the first depth adjustment groove and the gate oxide groove; An active region manufacturing process is performed on the hard mask layer and the substrate it covers to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with the first depth adjustment trench and communicates with the first depth adjustment trench and the gate oxide trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench. Dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench to form a shallow trench isolation structure, wherein the hard mask layer in the gate oxide trench is buried within the remaining dielectric material; Etching removes the dielectric material in the gate oxide trench and part of the top of the shallow trench isolation structure outside the gate oxide trench, forming a side trench that exposes the apex corner of the active region at the gate oxide trench; The first ion is used to pre-implant the shallow layer at the apex of the active region; Remove the hard mask layer in the gate oxide trench and further etch to reduce the top height of the active region at the gate oxide trench. The first ion is used to reduce the etching rate of the top corner of the active region, so that the top corner of the active region is relatively convex after etching and becomes a convex corner of the active region. Oxidize the convex corner of the active region and the top of the active region in the gate oxide trench to form a thick gate oxide layer.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The steps of forming the gate oxide trench and the first depth adjustment trench include: A first pad oxide layer, a first nitride layer, and a first photoresist layer are sequentially formed on the substrate; The first photoresist layer is photolithographically ... Using the first photoresist layer after photolithography as a mask, the first nitride layer, the first pad oxide layer and the substrate are etched sequentially to form the gate oxide trench and the first depth adjustment trench in the substrate; Remove the first photoresist layer, the first nitride layer, and the first pad oxide layer.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Performing an active region fabrication process on the hard mask layer and the substrate it covers includes the following steps: A second photoresist layer is formed on the hard mask layer; The second photoresist layer is photolithographically etched using a second photomask to define the formation area of ​​each of the shallow trenches; Using the second photoresist layer after photolithography as a mask, the hard mask layer and the substrate are etched to form the corresponding shallow trench; Remove the second photoresist layer.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, While etching to reduce the top height of the active region at the gate oxide trench, the shallow layer pre-implanted by the first ion is etched away; and / or, before or after pre-implanting the shallow layer at the apex of the active region with the first ion, a deep layer at the apex of the active region is pre-implanted with a second ion, the deep layer pre-implanted by the second ion is retained in the convex corner of the active region, and the second ion is used to increase the oxidation rate of the convex corner of the active region during the formation of the thick gate oxide layer.

5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The first ion includes boron fluoride ions; and / or, the second ion includes at least one of oxygen ions, amorphous ions, and halide ions, wherein the amorphous ions include at least one of silicon ions, germanium ions, and argon ions.

6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, While performing trench etching on the substrate area to be fabricated as a high-voltage transistor to form the gate oxide trench and the first depth adjustment trench, at least one second depth adjustment trench is also formed at the boundary of the active region of the high-voltage transistor. After performing the active region fabrication process, the second depth adjustment trench overlaps with and communicates with the corresponding shallow trench to deepen the bottom depth of the shallow trench and separate the active region of the high-voltage transistor from the active regions of other components.

7. The method for manufacturing a semiconductor device according to any one of claims 1-5, characterized in that, It also includes at least one of the following (1) to (6): (1) After forming the first depth adjustment trench and the gate oxide trench and before forming the shallow trench, or after forming the shallow trench and before filling the dielectric material, at least the top sidewall of the active region in the gate oxide trench is ion implanted to form a first drift region. (2) After the shallow trench isolation structure is formed and before the side trench is formed, the active region of the high voltage transistor is ion implanted to form a second drift region. (3) Before filling the dielectric material, or after forming the trench and before pre-implanting the shallow layer at the apex of the active region with the first ion, the sidewalls of the hard mask layer in the gate oxide trench are also pulled back and etched to expose more area at the apex of the active region. (4) After the active region convex corner is formed and before the thick gate oxide layer is formed, the surface of the active region convex corner and the top surface of the active region in the gate oxide tank are oxidized to form a first line oxide layer. (5) After the active region convex corner is formed and before the thick gate oxide layer is formed, the steps of first forming a sacrificial oxide layer and then removing the sacrificial oxide layer are performed multiple times to adjust the height of the active region convex corner. The sacrificial oxide layer is formed by oxidizing the active region surface at the gate oxide trench. (6) After forming the thick gate oxide layer, a thin gate oxide layer is also formed on the active region of the other elements, and a gate is formed together on the thick gate oxide layer and the thin gate oxide layer.

8. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The first drift region is formed by ion implantation at least on the top sidewall of the active region of the gate oxide trench using a lightly doped source-drain ion implantation process.

9. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The steps for forming the first drift region include: A third photoresist layer is formed on the substrate; Photolithography is performed on the third photoresist layer to at least open the third photoresist layer on the active region convex corner and the gate oxide trench, and to mask other areas; Using the third photoresist layer after photolithography as a mask, and employing a lightly doped source / drain ion implantation process, the first drift region is formed.

10. A method for manufacturing a semiconductor device as described in any one of claims 1-5 or 7-9, characterized in that, It also includes at least one of the following (1) to (7): (1) At least one first depth adjustment groove is formed on both sides of the gate oxide cell; (2) The hard mask layer includes a second pad oxide layer and a second nitride layer sequentially stacked on the substrate; (3) The sidewall of the first depth adjustment groove is aligned with or forms a step with the sidewall of the shallow groove it communicates with; (4) Photolithography and trench etching are performed on the substrate area to be fabricated for high voltage transistors using the zero-layer photomask, so as to form the first depth adjustment trench and the gate oxide trench at the same time as forming the zero-layer alignment mark in the substrate. (5) Before filling the gate oxide trench, each of the shallow trenches and the first depth adjustment trench with dielectric material, a second line oxide layer is formed on the inner surface of the gate oxide trench, each of the shallow trenches and the first depth adjustment trench. (6) After the gate oxide trench, each of the shallow trenches and the first depth adjustment trench are filled with dielectric material, the top of the dielectric material is planarized until the top surface of the hard mask layer on the substrate region surrounding the gate oxide trench is exposed or until the top surface of the active region convex corner is exposed.

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