Control method and control circuit for channel mismatch compensation

Abstract

A control method and control circuit for channel mismatch compensation are disclosed, applied to an electronic device including a signal transmitting circuit or a signal receiving circuit, the signal transmitting circuit or the signal receiving circuit including a first channel and a second channel, and the electronic device further including a channel mismatch compensation circuit. The control method includes: (A) determining a frequency of a test signal; (B) passing the test signal through the signal transmitting circuit or the signal receiving circuit and measuring an image signal; (C) adjusting a compensation parameter of the channel mismatch compensation circuit to change an amplitude of the image signal; (D) determining a target compensation parameter of the channel mismatch compensation circuit based on the amplitude of the image signal, the target compensation parameter corresponding to the frequency of the test signal; (E) repeating steps (A) to (D) to obtain a plurality of target compensation parameters; and (F) determining a compensation mechanism of the channel mismatch compensation circuit based on the target compensation parameters.

Description

Technical Field

[0001] This disclosure relates to radio frequency transceiver circuits, and more particularly to the control of channel mismatch compensation in radio frequency transceiver circuits. Background Technology

[0002] Figure 1A This is a functional block diagram of a well-known direct conversion transmitter. The direct conversion transmitter 100 includes a power amplifier (PA) 110, an adder circuit 115, a phase shifter 120, a local oscillator (LO) 125, an I-path 130, and a Q-path 140. The I-path 130 includes a mixer 132, a low-pass filter (LPF) 134, and a digital-to-analog converter (DAC) 136. The Q-path 140 includes a mixer 142, a low-pass filter 144, and a DAC 146. The I-path signal S_I and the Q-path signal S_Q generated by the baseband circuit (not shown) pass through the I-path 130 and Q-path 140, respectively. The combined signal (combined by the adder circuit 115) is then amplified by the power amplifier 110 and transmitted via the antenna.

[0003] Figure 1B This is a functional block diagram of a well-known direct conversion receiver. The direct conversion receiver 150 includes a low-noise amplifier (LNA) 160, a phase shifter 170, a local oscillator 175, an I-path 180, and a Q-path 190. The I-path 180 includes a mixer 182, a low-pass filter 184, and an analog-to-digital converter (ADC) 186. The Q-path 190 includes a mixer 192, a low-pass filter 194, and an ADC 196. The signal received by the antenna and amplified by the LNA 160 is divided into an I-path signal S_I (via I-path 180) and a Q-path signal S_Q (via Q-path 190), which are then processed by a downstream baseband circuit (not shown).

[0004] The operating principles of the direct conversion transmitter 100 and the direct conversion receiver 150 are well known to those skilled in the art, and therefore will not be described in detail.

[0005] The direct conversion transmitter 100 and / or direct conversion receiver 150 may encounter I / Q channel mismatch (or I / Q channel imbalance) problems. I / Q channel mismatch may be caused by the following: (1) the phase offset between the I-path signal S_I and the Q-path signal S_Q is not 90 degrees, which will produce a frequency-independent phase mismatch (e.g., ...). Figure 2A (as shown); (2) Components on the I path (130 and 180) and components on the Q path (140 and 190) will produce frequency-independent gain mismatch (as shown). Figure 2B (as shown); (3) There is a slight time difference in the transmission of the I path signal S_I and the Q path signal S_Q, which will produce a frequency-dependent phase mismatch (e.g. Figure 3 (as shown); and / or (4) the filters on the I and Q paths have different frequency responses (i.e., low-pass filter 134 and low-pass filter 144 have different frequency responses, and low-pass filter 184 and low-pass filter 194 have different frequency responses), which will simultaneously cause frequency-related phase mismatch (e.g. Figure 4A (as shown) and frequency-related gain mismatch (such as) Figure 4B (As shown).

[0006] The mismatch caused by cause (1) and / or (2) can be compensated by gain and / or phase compensation circuits; the mismatch caused by cause (3) can be compensated by time skew compensation circuits; the mismatch caused by cause (4) can be compensated by filter mismatch compensation circuits.

[0007] The order of complexity of the compensation circuits corresponding to the above four reasons is: (4) > (3) > (2) and (1). Therefore, the power consumption of the filter mismatch compensation circuit > the power consumption of the time skew compensation circuit > the power consumption of the gain and / or phase compensation circuit. However, since reasons (4) and (3) are usually not the main factors of I / Q channel mismatch (e.g., accounting for 5% and 15% respectively), the electronic device would consume a considerable amount of power if the filter mismatch compensation circuit, the time skew compensation circuit, and the gain and / or phase compensation circuit were always turned on. Therefore, a compensation mechanism is needed to reduce the power consumption of the electronic device. Summary of the Invention

[0008] In view of the shortcomings of the prior art, one object of this disclosure is to provide a control method and control circuit for channel mismatch compensation to improve the shortcomings of the prior art.

[0009] One embodiment of this disclosure provides a control method for channel mismatch compensation, applied to an electronic device. The electronic device includes a signal transmitting circuit or a signal receiving circuit, the signal transmitting circuit or the signal receiving circuit including a first channel and a second channel, and the electronic device further includes a channel mismatch compensation circuit. The control method includes: (A) determining a frequency of a test signal; (B) passing the test signal through the signal transmitting circuit or the signal receiving circuit and measuring an image signal; (C) adjusting a compensation parameter of the channel mismatch compensation circuit to change an amplitude of the image signal; (D) determining a target compensation parameter of the channel mismatch compensation circuit based on the amplitude of the image signal, the target compensation parameter corresponding to the frequency of the test signal; (E) repeating steps (A) to (D) to obtain a plurality of target compensation parameters; and (F) determining a compensation mechanism of the channel mismatch compensation circuit based on the target compensation parameters.

[0010] Another embodiment of this disclosure provides a control circuit for channel mismatch compensation, applied to an electronic device. The electronic device includes a signal transmitting circuit or a signal receiving circuit, the signal transmitting circuit or the signal receiving circuit including a first channel and a second channel. The electronic device also includes a channel mismatch compensation circuit. The control circuit performs the following steps to determine a compensation mechanism of the channel mismatch compensation circuit: (A) determining a frequency of a test signal; (B) passing the test signal through the signal transmitting circuit or the signal receiving circuit and measuring an image signal; (C) adjusting a compensation parameter of the channel mismatch compensation circuit to change an amplitude of the image signal; (D) determining a target compensation parameter of the channel mismatch compensation circuit based on the amplitude of the image signal, the target compensation parameter corresponding to the frequency of the test signal; (E) repeating steps (A) to (D) to obtain a plurality of target compensation parameters; and (F) determining the compensation mechanism of the channel mismatch compensation circuit based on the target compensation parameters.

[0011] The features, implementation, and effects of this disclosure will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1A It is a functional block diagram of a well-known direct conversion transmitter;

[0013] Figure 1B It is a functional block diagram of a well-known direct conversion receiver;

[0014] Figures 2A-2B , Figure 3 and Figures 4A-4B Show the relationship between gain mismatch or phase mismatch and frequency;

[0015] Figure 5 This is a functional block diagram of an embodiment of the signal transmitting end of the electronic device disclosed herein;

[0016] Figure 6 This is a functional block diagram of an embodiment of the signal receiving end of the electronic device disclosed herein;

[0017] Figure 7 This is a functional block diagram of one embodiment of the channel mismatch compensation circuit disclosed herein;

[0018] Figure 8 This is a flowchart of an embodiment of the control method for I / Q channel mismatch compensation disclosed herein; and

[0019] Figure 9 One embodiment of the sub-step of step S870 is shown. Detailed Implementation

[0020] The technical terms used in the following description refer to the common terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0021] This disclosure includes a control method and control circuit for channel mismatch compensation. Since some components of the control circuit for channel mismatch compensation may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device. Furthermore, part or all of the process of the control method for channel mismatch compensation may be in the form of software and / or firmware, and may be executed by the control circuit for channel mismatch compensation or its equivalent. Without affecting the full disclosure and implementability of the method, the following description of the method will focus on the steps rather than the hardware.

[0022] Figure 5 This is a functional block diagram of an embodiment of the signal transmitting end of the electronic device disclosed herein. The signal transmitting end 500 includes a signal transmitting circuit (i.e., a direct converter transmitter 100), a signal processing circuit 510, a baseband circuit 520, and a channel mismatch compensation circuit 700. The baseband circuit 520 includes a control circuit 525. One end of the signal processing circuit 510 is coupled between the power amplifier 110 and the adder circuit 115, and the other end of the signal processing circuit 510 is coupled to the baseband circuit 520 (more specifically, coupled to the control circuit 525).

[0023] Signal processing circuit 510 processes the radio frequency signal S_RF and generates a feedback signal S_FB. When I path 130 and Q path 140 are mismatched (i.e., the direct conversion transmitter 100 has at least one of the four I / Q channel mismatch causes mentioned above) and proper compensation is lacking, the feedback signal S_FB includes an unwanted image signal. Control circuit 525 controls the channel mismatch compensation circuit 700 via control signal Ctrl based on the amplitude (i.e., energy) of the image signal.

[0024] The amplitude or energy of the measured signal (e.g., mirror signal) is well known to those skilled in the art and will not be described further. In some embodiments, the signal processing circuit 510 includes a mixer, a low-pass filter, an analog-to-digital converter, and an amplifier. Operational details of the signal processing circuit 510 can be found in Taiwan Patent I466506 and will not be described further.

[0025] Figure 6 This is a functional block diagram of an embodiment of the signal receiving end of the electronic device disclosed herein. The signal receiving end 600 includes a signal receiving circuit (i.e., a direct conversion receiver 150), a baseband circuit 520, and a channel mismatch compensation circuit 700. When the I path 180 and Q path 190 are mismatched (i.e., when the direct conversion receiver 150 has at least one of the four I / Q channel mismatch causes described above), the I path signal S_I and the Q path signal S_Q include unwanted mirror signals. When the compensation parameters of the channel mismatch compensation circuit 700 are not ideal, even if the I path signal S_I and the Q path signal S_Q are compensated by the channel mismatch compensation circuit 700, the I path compensated signal S'_I and the Q path compensated signal S'_Q may still include mirror signals. The control circuit 525 controls the channel mismatch compensation circuit 700 via the control signal Ctrl according to the amplitude (i.e., energy) of the mirror signal.

[0026] Figure 7 This is a functional block diagram of one embodiment of the channel mismatch compensation circuit 700 disclosed herein. The channel mismatch compensation circuit 700 includes a gain and / or phase compensation circuit 710, a time skew compensation circuit 720, and a filter mismatch compensation circuit 730. The gain and / or phase compensation circuit 710 is used to compensate for the (1) and / or (2) of the four types of I / Q channel mismatch causes mentioned above, the time skew compensation circuit 720 is used to compensate for the (3) of the four types of I / Q channel mismatch causes mentioned above, and the filter mismatch compensation circuit 730 is used to compensate for the (4) of the four types of I / Q channel mismatch causes mentioned above. The gain and / or phase compensation circuit 710, the time skew compensation circuit 720, and the filter mismatch compensation circuit 730 have various implementation methods, and their operating principles are well known to those skilled in the art, so they will not be described in detail here.

[0027] Figure 8 This is a flowchart of an embodiment of the control method for I / Q channel mismatch compensation disclosed herein, executed by control circuit 525, and includes the following steps.

[0028] Step S810: Control circuit 525 determines the frequency fi of test signal S_T. Test signal S_T is a single-tone signal, where i represents the index (i is an integer) – f1 represents the first frequency, f2 represents the second frequency, and so on. For signal transmitter 500, test signal S_T is a baseband signal composed of I-path signal S_I and Q-path signal S_Q. For signal receiver 600, test signal S_T is a radio frequency signal generated by test signal generator 530. Control circuit 525 controls test signal generator 530 to generate test signal S_T via control signal Ct.

[0029] Step S820: Pass the test signal S_T through the direct conversion transmitter 100 or the direct conversion receiver 150, and measure the mirror signal. As mentioned earlier, when the compensation parameters of the channel mismatch compensation circuit 700 are not ideal (i.e., the compensation result of the channel mismatch compensation circuit 700 is not ideal), Figure 5 The feedback signal S_FB and Figure 6 The I-path compensation signal S'_I and the Q-path compensation signal S'_Q will include the mirror signal.

[0030] Step S830: Control circuit 525 adjusts the compensation parameters of channel mismatch compensation circuit 700 to change the amplitude of the mirror signal. More specifically, in Figure 8 In the process, control circuit 525 disables time skew compensation circuit 720 and filter mismatch compensation circuit 730 (equivalent to keeping time skew compensation circuit 720 and filter mismatch compensation circuit 730 inactive). Then, in step S830, control circuit 525 adjusts the compensation parameters (including phase compensation parameters and gain compensation parameters) of gain and / or phase compensation circuit 710. Different compensation parameters correspond to different amplitudes of the mirror signal. The more ideal the compensation parameters (i.e., the better the compensation effect of channel mismatch compensation circuit 700), the smaller the amplitude of the mirror signal. In this step, control circuit 525 sets or adjusts gain and / or phase compensation circuit 710 according to multiple compensation parameters or combinations of multiple compensation parameters, and records the relationship between compensation parameters or combinations of compensation parameters and the amplitude of the mirror signal.

[0031] Step S840: The control circuit 525 determines the target compensation parameter of the channel mismatch compensation circuit 700 based on the amplitude of the mirror signal. This target compensation parameter corresponds to a single-tone frequency fi. In some embodiments, the control circuit 525 obtains the amplitudes of multiple mirror signals in step S830, and each amplitude corresponds to a set of compensation parameters (including phase compensation parameters and gain compensation parameters). In step S840, the control circuit 525 selects the set of compensation parameters corresponding to the smallest amplitude as the target compensation parameter combination for the single-tone frequency fi (including phase compensation parameter P(i) and gain compensation parameter G(i)).

[0032] Steps S850 and S860: Control circuit 525 determines whether index i is greater than the target value N (N is an integer and N>i). If not, iteration is performed (steps S810 to S860 are repeated, and index i is updated in step S860). In this way, after the iteration is completed (assuming the initial value of index i is 1), control circuit 525 obtains N sets of target compensation parameters ((P(1),G(1)), (P(2),G(2)), (P(3),G(3)), ..., (P(N),G(N))) corresponding to N single-tone frequencies (f1, f2, f3, ..., fN).

[0033] Step S870: The control circuit 525 determines the compensation mechanism of the channel mismatch compensation circuit 700 based on these target compensation parameters, that is, whether to enable the time skew compensation circuit 720 and / or the filter mismatch compensation circuit 730 (equivalent to deciding whether to control the operation of the time skew compensation circuit 720 and the filter mismatch compensation circuit 730).

[0034] Figure 9 One embodiment of the sub-steps of step S870 includes the following steps.

[0035] Step S910: Control circuit 525 calculates the first-order and second-order differences of these target compensation parameters (including phase compensation parameters P(1), P(2), P(3), ..., P(N-1) and gain compensation parameters G(1), G(2), G(3), ..., G(N-1)). The first-order difference of the phase compensation parameter (hereinafter referred to as the first-order phase difference) is P_1st_diff(i) = P(i+1) - P(i) (i = 1, 2, ..., N-1), the first-order difference of the gain compensation parameter (hereinafter referred to as the first-order gain difference) is G_1st_diff(i) = G(i+1) - G(i) (i = 1, 2, ..., N-1), the second-order difference of the phase compensation parameter (hereinafter referred to as the second-order phase difference) is P_2nd_diff(i) = P_1st_diff(i+1) - P_1st_diff(i) (i = 1, 2, ..., N-2), and the second-order difference of the gain compensation parameter (hereinafter referred to as the second-order gain difference) is G_2nd_diff(i) = G_1st_diff(i+1) - G_1st_diff(i) (i = 1, 2, ..., N-2).

[0036] Step S920: Control circuit 525 determines the compensation mechanism of the compensation circuit based on the first-order and second-order differences of these target compensation parameters. More specifically, control circuit 525 determines whether to enable the gain and / or phase compensation circuit 710, the time skew compensation circuit 720, and / or the filter mismatch compensation circuit 730 based on the following conditions (steps S921, S923, S925) (steps S922, S924, S926).

[0037] Step S921: If for all index i, the first-order gain difference G_1st_diff(i) is less than or equal to the threshold value G_th1, and the first-order phase difference P_1st_diff(i) is less than or equal to the threshold value P_th1, then the control circuit 525 executes step S922; otherwise, the control circuit 525 executes step S923.

[0038] Step S922: Control circuit 525 enables gain and / or phase compensation circuit 710 and disables time skew compensation circuit 720 and / or filter mismatch compensation circuit 730 (disabling either time skew compensation circuit 720 or filter mismatch compensation circuit 730 can achieve the purpose of saving power, and disabling both can save even more power).

[0039] Step S923: If for all index i, the first-order gain difference G_1st_diff(i) is less than or equal to the threshold value G_th1, the first-order phase difference P_1st_diff(i) is greater than the threshold value P_th1, and the second-order phase difference P_2nd_diff(i) is less than or equal to the threshold value P_th2, then the control circuit 525 executes step S924; otherwise, the control circuit 525 executes step S925.

[0040] Step S924: The control circuit 525 enables the gain and / or phase compensation circuit 710 and the time skew compensation circuit 720, and disables the filter mismatch compensation circuit 730 to save power.

[0041] Step S925: If the second-order gain difference G_2nd_diff(i) is greater than the threshold value G_th2 or the second-order phase difference P_2nd_diff(i) is greater than the threshold value P_th2, then the control circuit 525 executes step S926.

[0042] Step S926: The control circuit 525 enables the gain and / or phase compensation circuit 710 and the filter mismatch compensation circuit 730, and disables the time skew compensation circuit 720 to save power.

[0043] The condition in step S921 being satisfied means that the relationship between phase mismatch and frequency is approximately equal to... Figure 2A Furthermore, the relationship between gain mismatch and frequency is approximately the same as... Figure 2B Therefore, in this case, the enable gain and / or phase compensation circuit 710 can achieve a considerable degree of compensation, while the disable time skew compensation circuit 720 and the filter mismatch compensation circuit 730 can save power.

[0044] If the condition in step S921 is not met but the condition in step S923 is met, it means that the relationship between phase mismatch and frequency is approximately equal to... Figure 3 The relationship between gain mismatch and frequency is approximately equal to... Figure 2B Therefore, in this case, the enable gain and / or phase compensation circuit 710 and the time skew compensation circuit 720 can achieve a considerable degree of compensation effect, while the disable filter mismatch compensation circuit 730 can save power.

[0045] If the conditions in steps S921 and S923 are not met, but the condition in step S925 is met, it means that the relationship between phase mismatch and frequency is approximately equal to... Figure 4A Furthermore, the relationship between gain mismatch and frequency is approximately the same as... Figure 4B Therefore, in this case, the enable gain and / or phase compensation circuit 710 and the filter mismatch compensation circuit 730 can achieve a considerable degree of compensation effect, while the disable time skew compensation circuit 720 can save power.

[0046] Figure 9 The judgment steps (i.e., steps S921, S923, and S925) do not necessarily have to be executed in sequence. Taking step S925 as an example, in some embodiments, when the second-order gain difference G_2nd_diff(i) is not greater than the threshold value G_th2 and the second-order phase difference P_2nd_diff(i) is not greater than the threshold value P_th2, the control circuit 525 executes step S924.

[0047] In some embodiments, when the function of the filter mismatch compensation circuit 730 includes the function of the gain and / or phase compensation circuit 710, step S926 may enable only the filter mismatch compensation circuit 730 and disable the gain and / or phase compensation circuit 710 and the time skew compensation circuit 720.

[0048] The threshold values ​​G_th1, P_th1, G_th2, and P_th2 can be adjusted based on experience and practical applications. For example, the larger the threshold values ​​G_th2 and P_th2, the lower the probability that the filter mismatch compensation circuit 730 will be enabled (i.e., more power-efficient); the smaller the threshold values ​​G_th1 and P_th1, the higher the probability that the time skew compensation circuit 720 or the filter mismatch compensation circuit 730 will be enabled (i.e., less power-efficient).

[0049] In other embodiments, step S870 can utilize regression analysis to find an objective function that approximates the relationship between parameters and frequencies; in other words, the type of mismatch can be determined based on the objective function. Figure 2A , Figure 2B , Figure 3 , Figure 4A and Figure 4B One of them). For example, when the objective function is ax 2 +bx+c, then those skilled in the art can achieve the same judgment as steps S921, S923 and S925 based on the coefficients a, b and c.

[0050] In some embodiments, the control circuit 525 may be a circuit or electronic component with program execution capability, such as a central processing unit, microprocessor, microprocessor unit, or equivalent circuit thereof. The control circuit 525 executes program code or program instructions stored in memory (including in the baseband circuit 520, not shown). Figures 8 to 9The steps are as follows. In other embodiments, those skilled in the art can design the control circuit 525 based on the above disclosure. That is, the control circuit 525 can be an application-specific integrated circuit (ASIC) or implemented by circuits or hardware such as a programmable logic device (PLD).

[0051] This disclosure first detects the characteristics of I / Q channel mismatch and then determines the compensation mechanism. In this way, unnecessary circuits can be shut down to save power.

[0052] Since those skilled in the art can understand the implementation details and variations of the method invention in this case through the disclosure of the device invention, repeated descriptions are omitted here to avoid redundancy, without affecting the disclosure claims and implementability of the method invention. Please note that the shapes, sizes, and proportions of the elements in the foregoing illustrations are merely illustrative and intended for those skilled in the art to understand this disclosure, and are not intended to limit this disclosure. Furthermore, in some embodiments, the order of the steps mentioned in the foregoing flowcharts may be adjusted according to actual operation, and they may even be performed simultaneously or partially simultaneously.

[0053] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its explicit or implicit content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the claims appended to this specification.

[0054] [Symbol Explanation]

[0055] 100: Direct Converter Transmitter

[0056] 110: Power Amplifier (PA)

[0057] 115: Adder Circuit

[0058] 120, 170: Phase shifter

[0059] 125, 175: Local Oscillator (LO)

[0060] 130, 180: I path

[0061] 140, 190: Q path

[0062] 132, 142, 182, 192: Mixers

[0063] 134, 144, 184, 194: Low-pass filter (LPF)

[0064] 136, 146: Digital-to-Analog Converter (DAC)

[0065] S_I: I path signal

[0066] S_Q: Q path signal

[0067] 150: Direct Converter Receiver

[0068] 160: Low Noise Amplifier (LNA)

[0069] 186, 196: Analog-to-digital converter (ADC)

[0070] 500: Signal transmitting end

[0071] 510: Signal processing circuit

[0072] 520: Baseband Circuit

[0073] 530: Test signal generator

[0074] 700: Channel mismatch compensation circuit

[0075] 525: Control Circuit

[0076] S_RF: Radio frequency signal

[0077] S_FB: Feedback signal

[0078] Ctrl, Ctrl+Ct: Control signals

[0079] 600: Signal receiver

[0080] S'_I: I-path compensation signal

[0081] S'_Q: Q-path compensation signal

[0082] 710: Gain and / or phase compensation circuit

[0083] 720: Time Skew Compensation Circuit

[0084] 730: Filter mismatch compensation circuit

[0085] S_T: Test signal

[0086] S810, S820, S830, S840, S850, S860, S870, S910, S920, S921, S922, S923, S924, S925, S926: Steps

[0087] G_1st_diff: First-order gain difference

[0088] P_1st_diff: First-order phase difference

[0089] G_2nd_diff: Second-order gain difference

[0090] P_2nd_diff: Second-order phase difference

[0091] G_th1, P_th1, G_th2, P_th2: Threshold values

Claims

1. A control method for channel mismatch compensation, characterized in that, This method is applied to an electronic device, which includes a signal transmitting circuit or a signal receiving circuit, the signal transmitting circuit or the signal receiving circuit including a first channel and a second channel, and the electronic device further includes a channel mismatch compensation circuit. The control method includes: (A) Determine the frequency of the test signal; (B) Pass the test signal through the signal transmitting circuit or the signal receiving circuit, and measure the mirror signal; (C) Adjust the compensation parameters of the channel mismatch compensation circuit to change the amplitude of the mirror signal; (D) Based on the amplitude of the mirror signal, determine the target compensation parameter of the channel mismatch compensation circuit, the target compensation parameter corresponding to the frequency of the test signal; (E) Repeat steps (A) to (D) to obtain a plurality of target compensation parameters; and (F) The compensation mechanism of the channel mismatch compensation circuit is determined based on these target compensation parameters. Step (F) includes: Calculate the complex number of first-order differences and complex number of second-order differences of these target compensation parameters; and The compensation mechanism of the channel mismatch compensation circuit is determined based on these first-order differences and these second-order differences.

2. The control method as described in claim 1, characterized in that, These target compensation parameters include a complex number of gain compensation parameters and a complex number of phase compensation parameters. Step (F) includes: (F1) Calculate the first-order differences of these gain compensation parameters to generate a complex number of first-order gain differences; (F2) Calculate the first-order differences of these phase compensation parameters to generate a complex number of first-order phase differences; and (F3) The compensation mechanism of the channel mismatch compensation circuit is determined based on the first-order gain difference and the first-order phase difference.

3. The control method as described in claim 2, characterized in that, The channel mismatch compensation circuit includes a filter mismatch compensation circuit and / or a time skew compensation circuit. Step (F3) includes: When the first-order gain differences are less than or equal to the first threshold value and the first-order phase differences are less than or equal to the second threshold value, the filter mismatch compensation circuit and / or the time skew compensation circuit are disabled.

4. The control method as described in claim 1, characterized in that, These target compensation parameters include a complex number of gain compensation parameters and a complex number of phase compensation parameters. Step (F) includes: (F1) Calculate the first-order differences of these gain compensation parameters to generate a complex number of first-order gain differences; (F2) Calculate the first-order differences of these phase compensation parameters to generate a complex number of first-order phase differences; (F3) Calculate the second-order differences of these phase compensation parameters to generate a complex number of second-order phase differences; and (F4) The compensation mechanism of the channel mismatch compensation circuit is determined based on the first-order gain difference, the first-order phase difference, and the second-order phase difference.

5. The control method as described in claim 4, characterized in that, The channel mismatch compensation circuit includes a filter mismatch compensation circuit, and step (F4) includes: When the first-order gain differences are less than or equal to the first threshold value, the first-order phase differences are greater than the second threshold value, and the second-order phase differences are less than or equal to the third threshold value, the filter mismatch compensation circuit is disabled.

6. The control method as described in claim 1, characterized in that, These target compensation parameters include a complex number of gain compensation parameters and a complex number of phase compensation parameters. Step (F) includes: (F1) Calculate the second-order differences of these gain compensation parameters to generate a complex number of second-order gain differences; (F2) Calculate the second-order differences of these phase compensation parameters to generate a complex number of second-order phase differences; and (F3) The compensation mechanism of the channel mismatch compensation circuit is determined based on the second-order gain difference and the second-order phase difference.

7. The control method as described in claim 6, characterized in that, The channel mismatch compensation circuit includes a filter mismatch compensation circuit, and step (F3) includes: When the second-order gain differences are not greater than the first threshold value and the second-order phase differences are not greater than the second threshold value, the filter mismatch compensation circuit is disabled.

8. A control circuit for channel mismatch compensation, characterized in that, The control circuit is applied to an electronic device, which includes a signal transmitting circuit or a signal receiving circuit. The signal transmitting circuit or the signal receiving circuit includes a first channel and a second channel. The electronic device also includes a channel mismatch compensation circuit. The control circuit performs the following steps to determine the compensation mechanism of the channel mismatch compensation circuit: (A) Determine the frequency of the test signal; (B) Pass the test signal through the signal transmitting circuit or the signal receiving circuit, and measure the mirror signal; (C) Adjust the compensation parameters of the channel mismatch compensation circuit to change the amplitude of the mirror signal; (D) Based on the amplitude of the mirror signal, determine the target compensation parameter of the channel mismatch compensation circuit, the target compensation parameter corresponding to the frequency of the test signal; (E) Repeat steps (A) to (D) to obtain multiple target compensation parameters; as well as (F) The compensation mechanism of the channel mismatch compensation circuit is determined based on these target compensation parameters. Step (F) includes: (F1) Calculate the complex number of first-order differences and complex number of second-order differences for these target compensation parameters; and (F2) The compensation mechanism of the channel mismatch compensation circuit is determined based on the first-order differences and the second-order differences.

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