Display device and driving method thereof

Abstract

The present disclosure provides a display device and a driving method thereof, which relate to the field of display technology and are used to improve the refresh rate of the display device. The display device includes a first gate line, a second gate line, and a third gate line arranged adjacent to each other in sequence. A scan driving circuit sequentially outputs a first scan signal to the first gate line, a second scan signal to the second gate line, and a third scan signal to the third gate line in a frame scan cycle. The effective scan periods of the scan signals are equal in duration, and the start time of the effective scan period of the second scan signal is delayed by a first duration compared to the start time of the effective scan period of the first scan signal. The start time of the effective scan period of the third scan signal is delayed by a second duration compared to the start time of the effective scan period of the second scan signal. The second duration is less than the first duration.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device and a driving method thereof. Background Art

[0002] Liquid crystal display (LCD) devices have become widely popular and gradually become mainstream products due to their small size, low power consumption, no radiation, and high display resolution. Summary of the Invention

[0003] Embodiments of the present invention provide a display device and a driving method thereof, which improve the refresh rate of the display device.

[0004] On the one hand, a display device is provided, which includes: a plurality of sub-pixels, which are arranged in an array; at least one gate line group, which includes a plurality of gate lines, and the plurality of gate lines include: a first gate line, a second gate line and a third gate line arranged adjacent to each other in sequence along a column direction; a scanning drive circuit, which is coupled to the plurality of gate lines in the gate line group and is configured to output scanning signals to the plurality of gate lines in the gate line group in a frame scanning cycle, including: outputting a first scanning signal to the first gate line, outputting a second scanning signal to the second gate line, and outputting a third scanning signal to the third gate line in sequence; wherein the effective scanning periods of the first scanning signal, the second scanning signal and the third scanning signal are equal in duration, and the start time of the effective scanning period of the second scanning signal is delayed by a first duration compared to the start time of the effective scanning period of the first scanning signal, and the start time of the effective scanning period of the third scanning signal is delayed by a second duration compared to the start time of the effective scanning period of the second scanning signal; and the second duration is less than the first duration.

[0005] In some embodiments, the second duration is zero.

[0006] In some embodiments, the second duration is greater than 0 and less than or equal to 1 / 2 of the first duration.

[0007] In some embodiments, the scan signals output by the scan driving circuit to any two adjacent gate lines in the gate line group along the column direction have respective effective scan periods that at least partially overlap.

[0008] In some embodiments, the gate line group also includes: a fourth gate line arranged adjacent to the third gate line along the column direction; the scan drive circuit is configured to output a fourth scan signal to the fourth gate line, the effective scan period of the fourth scan signal and the effective scan period of the third scan signal are equal in length, the start time of the effective scan period of the fourth scan signal is delayed by a third time period compared to the start time of the effective scan period of the third scan signal, and the third time period is equal to the first time period.

[0009] In some embodiments, the first scanning signal and the fourth scanning signal output by the scanning driving circuit to the gate line group have respective effective scanning periods partially overlapping.

[0010] In some embodiments, the at least one gate line group includes a first gate line group and a second gate line group arranged adjacent to each other in sequence along the column direction; compared with the start time of the effective scanning period of the fourth scanning signal output by the fourth gate line in the first gate line group, the start time of the effective scanning period of the first scanning signal output by the first gate line in the second gate line group is delayed by a fourth time length; the fourth time length is equal to the first time length.

[0011] In some embodiments, the display device further includes: a data driving circuit and a plurality of data lines, the data driving circuit being coupled to the plurality of data lines and being configured to output data signals to the plurality of data lines respectively, the data lines being configured to write data signals to sub-pixels, the data signals being sub-pixel data of the sub-pixels; the plurality of data lines including representative data lines; the plurality of sub-pixels coupled to the plurality of gate lines in a gate line group including: a first sub-pixel coupled to the representative data line and the first gate line, a second sub-pixel coupled to the representative data line and the second gate line, and a third sub-pixel coupled to the representative data line and the third gate line; the second sub-pixel and the third sub-pixel having the same color; in a frame scanning cycle, a first data signal is written to the first sub-pixel through the representative data line, and a second data signal or a third data signal is simultaneously written to the second sub-pixel and the third sub-pixel through the representative data line; the first data signal is a data signal corresponding to the pixel data of the first sub-pixel, the second data signal is a data signal corresponding to the pixel data of the second sub-pixel, and the third data signal is a data signal corresponding to the pixel data of the third sub-pixel.

[0012] In some embodiments, in a frame scanning cycle, the second duration is zero; the first data signal is written to the first sub-pixel through the representative data line, and the second data signal is written to the second sub-pixel and the third sub-pixel at the same time through the representative data line; the duration of the second data signal is equal to the first duration; the start time of the second data signal is delayed by a fifth duration compared to the start time of the effective scanning period of the second scanning signal; the fifth duration is twice the first duration.

[0013] In some embodiments, the second duration is greater than 0 and less than or equal to 1 / 2 of the first duration; in an odd frame scanning cycle, the first data signal is written to the first sub-pixel through the representative data line, and the second data signal is simultaneously written to the second sub-pixel and the third sub-pixel through the representative data line, and the end time of the second data signal is advanced by the sixth duration compared to the end time of the third scanning signal; in an even frame scanning cycle, the first data signal is written to the first sub-pixel through the representative data line, and the third data signal is simultaneously written to the second sub-pixel and the third sub-pixel through the representative data line, and the end time of the third data signal is delayed by the seventh duration compared to the end time of the effective scanning period of the second scanning signal; the duration of the second data signal and the third data signal are both equal to the first duration; the sixth duration and the seventh duration are both greater than 0.

[0014] In some embodiments, the second duration is equal to 1 / 2 of the first duration; the durations of the second data signal and the third data signal are both equal to the first duration; the sixth duration and the seventh duration are both 1 / 2 of the first duration; in an odd-numbered frame scanning cycle, the start time of the second data signal is delayed by an eighth duration compared to the start time of the effective scanning period of the second scanning signal; in an even-numbered frame scanning cycle, the start time of the third data signal is delayed by a ninth duration compared to the start time of the effective scanning period of the third scanning signal; the eighth duration and the ninth duration are both twice the first duration.

[0015] In some embodiments, the scanning signals output by the scanning driving circuit to any two adjacent gate lines in the first gate line group along the column direction have respective effective scanning periods that at least partially overlap; the two adjacent gate lines in the first gate line group along the column direction are divided into a preceding gate line and a following gate line, and the position of the preceding gate line is set before the following gate line; the data signals written into each sub-pixel coupled to the preceding gate line partially overlap with the effective scanning period of the scanning signal output by the scanning driving circuit to the following gate line.

[0016] In some embodiments, the plurality of data lines include first data lines and second data lines alternately distributed along a row direction; in a frame scanning period, the data driving circuit is configured to output a first type of data signal to the first data line and to output a second type of data signal to the second data line; wherein the polarities of the first type of data signal and the second type of data signal are different.

[0017] In some embodiments, a data line is coupled to two sub-pixels in the same row, and the two sub-pixels coupled to the data line are respectively coupled to different gate lines.

[0018] In some embodiments, the display device further includes: a timing control circuit, which is coupled to the scan drive circuit and configured to output multiple clock signals to the scan drive circuit; the scan drive circuit is configured to output scan signals to the multiple gate lines respectively according to the multiple clock signals.

[0019] On the other hand, a driving method for a display device is provided, wherein the display device is as described in any of the aforementioned embodiments, and the driving method includes: in a frame scanning cycle, the scanning driving circuit is configured to output scanning signals to the multiple gate lines in the gate line group respectively, including: outputting a first scanning signal to the first gate line, outputting a second scanning signal to the second gate line, and outputting a third scanning signal to the third gate line in sequence; wherein the effective scanning periods of the first scanning signal, the second scanning signal and the third scanning signal are equal in duration, and the effective scanning period of the second scanning signal is delayed by a first duration compared to the start time of the effective scanning period of the first scanning signal, and the start time of the effective scanning period of the third scanning signal is delayed by a second duration compared to the start time of the effective scanning period of the second scanning signal; the second duration is less than the first duration.

[0020] In some embodiments, the display device further comprises: a data driving circuit and a plurality of data lines, the data driving circuit being coupled to the plurality of data lines and being configured to output data signals to the plurality of data lines respectively, the data lines being configured to write data signals to sub-pixels, the data signals being sub-pixel data of the sub-pixels; the plurality of data lines comprising a representative data line; the plurality of sub-pixels coupled to the plurality of gate lines in a gate line group comprising: a first sub-pixel coupled to the representative data line and the first gate line, a second sub-pixel coupled to the representative data line and the second gate line, a second sub-pixel coupled to the representative data line and the third gate line the second sub-pixel and the third sub-pixel have the same color; the driving method further comprises: in one frame scanning cycle, the data driving circuit writes a first data signal to the first sub-pixel through the representative data line, and simultaneously writes a second data signal or a third data signal to the second sub-pixel and the third sub-pixel through the representative data line; the first data signal is a data signal corresponding to the pixel data of the first sub-pixel, the second data signal is a data signal corresponding to the pixel data of the second sub-pixel, and the third data signal is a data signal corresponding to the pixel data of the third sub-pixel.

[0021] In some embodiments, the multiple data lines include a first data line and a second data line arranged adjacent to each other along a row direction, and the driving method further includes: in a frame scanning period, the data driving circuit outputs a first type of data signal to the first data line and outputs a second type of data signal to the second data line; wherein the polarities of the first type of data signal and the second type of data signal are different.

[0022] A display device provided by an embodiment of the present disclosure comprises: in a frame scanning cycle, a scanning driving circuit sequentially outputs a first scanning signal, a second scanning signal and a third scanning signal to a first gate line, a second gate line and a third gate line, respectively; wherein the effective scanning periods of the scanning signals are all equal in length; the start time of the effective scanning period of the second scanning signal is delayed by a first time period compared to the start time of the effective scanning period of the first scanning signal; the start time of the effective scanning period of the third scanning signal is delayed by a second time period compared to the start time of the effective scanning period of the second scanning signal; the second time period is less than the first time period, i.e., the effective scanning periods of the second scanning signal and the third scanning signal are both started in advance; accordingly, the end time of the effective scanning periods of the second scanning signal and the third scanning signal is also advanced; the total time required to complete the scanning of the first gate line, the second gate line and the third gate line is shortened; i.e., a frame scanning cycle is also shorter, thereby increasing the number of refreshes per unit time and improving the refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0024] Figure 1 is a structural diagram of a display device according to some embodiments;

[0025] Figure 2 is a structural diagram of a display device according to some other embodiments;

[0026] Figure 3 is a structural diagram of a display device according to some other embodiments;

[0027] Figure 4 is a structural diagram of a display device according to some further embodiments;

[0028] Figure 5 is a timing diagram of a scan signal according to some embodiments;

[0029] Figure 6 is a timing diagram of scan signals according to some other embodiments;

[0030] Figure 7 is a timing diagram of scan signals according to some further embodiments;

[0031] Figure 8 is a structural diagram of a display device according to some other embodiments;

[0032] Figure 9 is a timing diagram of scan signals and data signals according to some embodiments;

[0033] Figure 10 is a timing diagram of scan signals and data signals according to some other embodiments;

[0034] Figure 11 is a timing diagram of scan signals and data signals according to yet other embodiments;

[0035] Figure 12 is a structural diagram of a display device according to some other embodiments. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0037] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0038] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0039] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0040] The use of "suitable for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices that are adapted or configured to perform additional tasks or steps. Additionally, the use of "based on" is intended to be open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0041] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0042] The liquid crystal display device includes a plurality of gate lines and a plurality of data lines, as well as a plurality of sub-pixels defined by the intersection of the plurality of gate lines and the plurality of data lines. Each sub-pixel is coupled to a gate line and a data line respectively. The gate line is configured to transmit a scan signal to the sub-pixel coupled thereto, and the data line is configured to transmit a data signal to the sub-pixel coupled thereto. The liquid crystal display device also includes a plurality of switching tubes (for example, thin film transistors, Thin Film Transistor, abbreviated as TFT), each switching tube being arranged corresponding to a sub-pixel. In the related art, the liquid crystal display device usually adopts a row-by-row scanning method to realize image display. When performing row-by-row scanning, first, the gate line of the first row outputs a scan signal to the plurality of sub-pixels coupled thereto, so that the switching transistors of the plurality of sub-pixels are in an on state, and the data line outputs a data signal to the plurality of sub-pixels in the first row. Afterwards, the gate line of the second row outputs a scan signal to the plurality of sub-pixels coupled thereto, and at the same time, the output of the scan signal of the first row stops, and the data line outputs a data signal to the plurality of sub-pixels in the second row, and so on. With the development of liquid crystal display technology, the requirements for the display effects of liquid crystal display devices are becoming increasingly higher. When the refresh rate of a liquid crystal display device is higher, the flicker of the image display is smaller and the picture quality of the displayed image is higher. Therefore, how to increase the refresh rate of a liquid crystal display device has become an urgent problem to be solved.

[0043] In order to solve the above problems, some embodiments of the present disclosure provide a display device. The display device is configured to display an image; for example, it can display a static image or a dynamic image. Exemplarily, the display device can be a liquid crystal display panel, or a product including a liquid crystal display panel and a driving circuit (the driving circuit is coupled to the liquid crystal display panel and is configured to drive the liquid crystal display panel to display an image). Specifically, the liquid crystal display panel can be an AD-SDS (Advanced-Super Dimensional Switching) type liquid crystal display panel, or an IPS (InPlane Switch) type liquid crystal display panel. Since liquid crystal molecules only modulate light and cannot emit light themselves, in order to achieve image display, exemplarily, the product can also include: a backlight module arranged on the back side of the liquid crystal display panel (the side away from the display surface), the backlight module being configured to provide backlight to the liquid crystal display panel. There is no excessive restriction on the type of the backlight module. For example, it can be an edge-entry backlight module or a direct-type backlight module.

[0044] Exemplarily, the above-mentioned products may be: displays, televisions, billboards, digital photo frames, laser printers with display functions, telephones, mobile phones, personal digital assistants (PDAs), digital cameras, camcorders, viewfinders, navigators, car display devices, spliced ​​display devices, home appliances, information query equipment (such as business query equipment for e-government, banks, hospitals, power departments, etc.), monitors, etc.

[0045] In some embodiments of the present disclosure, see Figure 1 The display device 1 has a display area (active area, referred to as AA area) and a peripheral area S. The peripheral area S is located on at least one side of the display area. Exemplarily, the peripheral area S can be arranged in a circle around the display area AA. The display device 1 may include a plurality of sub-pixels P, each switch tube is arranged corresponding to a sub-pixel P, and the plurality of sub-pixels P are located in the AA area, and the plurality of sub-pixels P are arranged in an array in the row direction and the column direction. Specifically, the sub-pixels P arranged in a row along the row direction can be called pixels in the same row, and the sub-pixels P arranged in a row along the column direction can be called pixels in the same column. The row direction is represented by X and the column direction is represented by Y.

[0046] Exemplarily, each row of sub-pixels P includes a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels. The first color, the second color, and the third color are not limited and can be three primary colors or other colors. For example, the first color, the second color, and the third color are blue, green, and red, respectively; that is, see Figure 1, the multiple sub-pixels include a blue sub-pixel B, a green sub-pixel G and a red sub-pixel R.

[0047] Continue to see Figure 1 , each sub-pixel P may include: a pixel electrode 11 and a common electrode 12, and the electric field formed between the two is applied to the liquid crystal molecules corresponding to the sub-pixel P, so that the liquid crystal molecules at the corresponding position of the sub-pixel P are arranged in a corresponding manner, thereby controlling the light output brightness of the sub-pixel P. In the present disclosure, there are no excessive restrictions on the specific shapes and relative positions of the pixel electrode 11 and the common electrode 12. For example, the pixel electrode 11 and the common electrode 12 may both include a plurality of electrode strips that are interconnected and have gaps between each other, and the electrode strips belonging to the pixel electrode 11 and the electrode strips belonging to the common electrode 12 are alternately arranged; or one may include a plurality of electrode strips that are interconnected and have gaps between each other, and the other may be a flat electrode. The pixel electrode 11 and the common electrode 12 may be arranged in the same layer or in different layers.

[0048] In some embodiments of the present disclosure, see Figure 1, similar to the above, the display device 1 includes a plurality of gate lines GL and a plurality of data lines DL, and each sub-pixel is coupled to a gate line GL and a data line DL, respectively. The display device 1 also includes a scan drive circuit (Scan Drive IC) and a data drive circuit (Data Drive IC), as well as a timing control circuit (TCON IC) coupled to both the scan drive circuit and the data drive circuit. The timing control circuit is configured to convert data signals and control signals received from an external interface into control signals suitable for the data drive circuit and the scan drive circuit, and output control signals such as RGB control signals to the data drive circuit, and output control signals such as multiple clock signals to the scan drive circuit, thereby realizing image display of the display device. The scan drive circuit can also be called a gate drive circuit (Gate Drive IC) or a column drive circuit (Row Drive IC). The scan drive circuit is coupled to the plurality of gate lines GL. In a frame scan cycle, the scan drive circuit is configured to output scan signals to the plurality of gate lines GL, respectively, according to the multiple clock signals provided by the timing control circuit. The plurality of gate lines GL are configured to transmit scan signals to the plurality of sub-pixels P coupled thereto, respectively, to control the on and off of the switch tubes in the sub-pixels P. The data drive circuit may also be referred to as a source drive circuit (Source Drive IC) or a column drive circuit (Column Drive IC). The data drive circuit is coupled to the plurality of data lines DL and is configured to output data signals to each data line DL after the switch tube is turned on. Each data line DL is configured to write a data signal to at least one (for example, one or more) sub-pixels P coupled thereto. The data signal is the pixel data of the sub-pixel P (that is, the voltage value that enables the sub-pixel to display a preset grayscale). The process of writing a data signal to the sub-pixel P is the process of charging the load capacitor formed by the pixel electrode 11 and the common electrode 12 in the sub-pixel P. After charging is completed, the voltage of the load capacitor is a grayscale voltage, which is the sub-pixel data of this sub-pixel P.

[0049] For example, see Figure 2The scanning drive circuit includes multiple rows of cascaded GOA units, namely G1, G2, G3, G4...G(n-1), Gn. Each of the cascaded multiple GOA units is coupled to a gate line GL for realizing progressive scanning of the gate line GL. Specifically, each GOA unit may include a signal input terminal IN, a signal output terminal OUT, a reset signal terminal RST, a clock signal terminal CLK, and a frame reset signal terminal Tot-Rst, etc. The signal output terminal OUT is coupled to a gate line GL. The timing control circuit can input a frame reset signal STV0 to the frame reset signal terminal Tot-Rst of the multiple GOA units through the corresponding signal line to reset the multiple GOA units before the start of each frame scanning cycle. The frame reset signal STV0 can reset the multiple GOA units, thereby avoiding the interference of the signal input to each GOA unit in the previous frame scanning cycle on the signals received by the GOA unit in the next frame scanning cycle, thereby eliminating the adverse effects that may be caused on the display effect.

[0050] For example, the scan driver circuit can be coupled to the timing control circuit via multiple clock signal lines CL. Each clock signal line CL is coupled to multiple GOA units and is configured to transmit clock signals CLK to the clock signal terminals CLK of the multiple GOA units coupled thereto. Specifically, there are no restrictions on the specific configuration of the clock signal lines CL, and a 4-CLK structure, a 6-CLK structure, an 8-CLK structure, a 12-CLK structure, or the like can be employed.

[0051] Exemplarily, n GOA units are divided into k groups, and GOA units spaced apart by k rows are divided into one group, that is, the 1st, 1+k, 1+2k... GOA units are used as the first group, the 2nd, 2+k, 2+2k... GOA units are used as the second group, and so on, until the kth, 2k, 3k... GOA units are used as the kth group. Wherein, the signal output terminal OUT of the mth GOA unit is connected to the signal input terminal IN of the m+kth GOA unit, and the signal output terminal OUT of the m+kth GOA unit is connected to the reset signal terminal RST of the mth GOA unit, and so on, to realize the cascade connection of the GOA units. The first GOA units of the 1st to kth groups are respectively the 1st to kth GOA units, and the other GOA units in each group are cascaded after the signal output terminal of the first GOA unit of each group, wherein k is a positive integer greater than or equal to 4, and m and n are both positive integers. In the entire scan driving circuit, the input signal of the signal input terminal IN of the GOA units G1, G2, G3, ... Gk is the frame start signal STV. Figure 2, n GOA units are divided into 4 groups, with every 4 rows of GOA units being divided into a group. The 1st, 5th, 9th, ... GOA units are the first group, the 2nd, 6th, 10th, ... GOA units are the second group, and so on, until the 4th, 8th, 12th, ... GOA units are the fourth group. The input signal of the signal input terminals IN of G1, G2, G3, and G4 is the frame start signal STV. The signal output terminal OUT of G1 is connected to the signal input terminal IN of G5, the signal output terminal OUT of G2 is connected to the signal input terminal IN of G6, the signal output terminal OUT of G3 is connected to the signal input terminal IN of G7, and the signal output terminal OUT of G4 is connected to the signal input terminal IN of G8. At the same time, the signal output terminal OUT of G5 is connected to the reset signal terminal RST of G1, the signal output terminal OUT of G6 is connected to the reset signal terminal RST of G2, the signal output terminal OUT of G7 is connected to the reset signal terminal RST of G3, and the signal output terminal OUT of G8 is connected to the reset signal terminal RST of G4, and so on.

[0052] Exemplarily, the above-mentioned scan drive circuit can also include multiple virtual (Dummy) GOA units (not shown in the figure), and the number of virtual GOA units is not specifically limited, as long as the signal connection relationship is adjusted accordingly according to the number of virtual GOA units. The internal structure of virtual GOA unit is basically the same as that of GOA unit, except that the signal input end of virtual GOA unit at each level is directly connected to the signal output end of virtual GOA unit of previous level. Virtual GOA unit at each level is mainly responsible for signal startup, plays the role of signal triggering for the opening of subsequent GOA unit, and does not directly control gate line scanning. Specifically, the signal input end of first-level virtual GOA unit inputs frame start signal STV, and the signal output end of last-level virtual GOA unit is connected to the signal input end of first-level GOA unit G1.

[0053] For example, see Figure 3The display device can adopt bilateral drive, that is, the display device includes two scan drive circuits arranged opposite to each other along the row direction (i.e., the X direction), and the structures of the two scan drive circuits are completely identical. The two ends of each gate line GL are coupled to the two scan drive circuits located on the left and right sides respectively, and the signals transmitted by the various signal terminals (including the signal input terminal IN, the signal output terminal OUT, the reset signal terminal RST, the clock signal terminal CLK, and the frame reset signal terminal Tot-Rst, etc.) of the GOA units in the two scan drive circuits coupled to the same gate line GL are completely identical. In this way, since the scan signal transmitted by each gate line GL is input from the two ends of this gate line GL respectively, the degree of signal attenuation on the gate line GL can be reduced to a certain extent. For medium and large-sized display devices, the effect of reducing signal attenuation is more prominent, thereby avoiding differences in display brightness at different positions in the display area AA, improving display uniformity, and enhancing display effects.

[0054] For example, see Figure 3 and Figure 4 The plurality of gate lines GL may be divided into a plurality of gate line groups GP, each gate line group GP including a plurality of gate lines GL, each of which includes a first gate line GL1, a second gate line GL2, and a third gate line GL3 adjacently arranged along a column direction (i.e., a Y direction). During progressive scanning, the gate lines GL are turned on in the order of the first gate line GL1, the second gate line GL2, and the third gate line GL3. The display device may include a plurality of gate line groups GP, each of which includes a first gate line GL1, a second gate line GL2, and a third gate line GL3 adjacently arranged along a column direction.

[0055] For example, see Figure 3 The display device includes a plurality of sub-pixels P arranged in an array. Any two adjacent sub-pixels P in the same row have different colors, and any two adjacent sub-pixels P in the same column have the same color. A gate line GL is provided between any two rows of sub-pixels P adjacent to each other along the column direction. The plurality of gate lines GL adjacent to each other along the column direction form a plurality of gate line groups GP. Each gate line group GP includes a first gate line GL1, a second gate line GL2, and a third gate line GL3 adjacent to each other along the column direction. The plurality of sub-pixels P coupled to different gate lines GL are located in different rows. For example, see Figure 3 The plurality of sub-pixels P coupled to the first gate line GL1 and the plurality of sub-pixels P coupled to the second gate line GL2 are located in different rows.

[0056] For example, see Figure 4The display device includes a plurality of sub-pixels P arranged in an array, wherein any two adjacent sub-pixels P in the same row have different colors, and any two adjacent sub-pixels P in the same column have the same color. At least one (for example, each) data line DL is coupled to two sub-pixels P in the same row, and the two sub-pixels P coupled to the same data line DL are respectively coupled to different gate lines GL, i.e., dual gate line GL (Dual Gate) technology is adopted. A plurality of gate line groups GP are adjacently arranged along a column direction, and each gate line group GP includes a first gate line GL1, a second gate line GL2, and a third gate line GL3 adjacently arranged along the column direction. Among the plurality of sub-pixels P located between two adjacent gate lines GL along the column direction, a portion of the sub-pixels P are coupled to one gate line GL of the two adjacent gate lines GL along the column direction, and the remaining sub-pixels P are coupled to the other gate line GL of the two adjacent gate lines GL along the column direction. In this example, the application of dual-gate line technology can reduce the number of data lines DL in a display device by half, while doubling the number of gate lines GL. Accordingly, the number of data driver circuits connected to the data lines DL is halved, while the number of scan driver circuits connected to the gate lines GL is doubled. Since the unit price of a scan driver circuit is lower than that of a data driver circuit, the application of dual-gate line GL technology can, to a certain extent, facilitate cost control.

[0057] For the sake of clarity, the following text Figure 4 The display device structure shown in FIG. 1 is used as an example to explain the embodiments of the present disclosure accordingly. It can be understood that the corresponding settings in any of the following embodiments can also be applied to Figure 3 The display device shown in the figure can produce the same beneficial effects, which will not be described in detail.

[0058] In the related art, see Figure 4 and Figure 5 Liquid crystal display devices typically use a progressive scanning method to display images. In a frame scanning cycle, the effective scanning period ET of the scanning signal SC transmitted by each gate line GL is equal in length, and the effective scanning period ET is T. Moreover, for any two adjacent gate lines GL along the column direction, compared to the start time of the effective scanning period ET of the scanning signal SC transmitted by the gate line GL that outputs the scanning signal SC first, the effective scanning period ET of the scanning signal SC transmitted by the gate line GL that outputs the scanning signal SC later is delayed by a fixed time length T1. That is, the absolute value of the time difference between the start time of the effective scanning period ET of the scanning signal SC transmitted by any two adjacent gate lines GL along the column direction is equal to T1. For any three adjacent gate lines GL along the column direction, the total time required to complete the progressive scanning of these three gate lines GL is T+2*T1.

[0059] In this disclosure, for example, see Figure 4and Figure 6 、 Figure 7 In a frame scan cycle, the scan drive circuit outputs scan signals SC to the plurality of gate lines GL, including: sequentially outputting a first scan signal SC1 to the first gate line GL1, a second scan signal SC2 to the second gate line GL2, and a third scan signal SC3 to the third gate line GL3. The effective scan periods ET of the first scan signal SC1, the second scan signal SC2, and the third scan signal SC3 are equal in duration, namely, T. The start time of the effective scan period ET of the second scan signal SC2 is delayed by a first duration T1 compared to the start time of the effective scan period ET of the first scan signal SC1. The start time of the effective scan period ET of the third scan signal SC3 is delayed by a second duration T2 compared to the start time of the effective scan period ET of the second scan signal SC2. The second duration T2 is less than the first duration T1. For a scan signal SC, the duration of the voltage signal that can maintain the switch tube coupled to the gate line GL transmitting the scan signal SC in an on state is the effective scan period ET, and the duration of the duration is T. When a gate line GL transmits a scan signal SC to multiple switching tubes coupled to it, the time difference between the turn-on moments of the multiple switching tubes coupled to this gate line GL is very small and can be ignored. Therefore, the multiple switching tubes coupled to the same gate line GL can be regarded as being turned on at the same time. In a frame scanning cycle, the start time of the effective scanning period ET of the second scanning signal SC2 is delayed by the first time length T1 compared with the start time of the effective scanning period ET of the first scanning signal SC1, that is, the multiple switching tubes coupled to the first gate line GL1 are turned on earlier than the multiple switching tubes coupled to the second gate line GL2, and the time difference between the start time of the multiple switching tubes coupled to the second gate line GL2 and the multiple switching tubes coupled to the first gate line GL1 is the first time length T1. Similarly, the start time of the effective scanning period ET of the third scanning signal SC3 is delayed by the second time length T2 compared with the start time of the effective scanning period ET of the second scanning signal SC2, that is, the multiple switching tubes coupled to the second gate line GL2 are turned on earlier than the multiple switching tubes coupled to the third gate line GL3, and the time difference between the start time of the multiple switching tubes coupled to the third gate line GL3 and the multiple switching tubes coupled to the second gate line GL2 is the second time length T2. There are no excessive restrictions on the size of the first duration T1. For example, the first duration T1 is not greater than the duration of the effective scanning period ET of any scanning signal SC. Specifically, the first duration T1 can be equal to 1 / 3 of the duration of the effective scanning period ET of any scanning signal SC.

[0060] For example, see Figure 6 and Figure 7, the duration of the effective scanning period ET of the scanning signal SC output by each gate line GL is also T, the first duration is T1, the second duration is T2, and the total duration required to complete the progressive scanning of the first gate line GL1, the second gate line GL2, and the third gate line GL3 is T + T1 + T2. Compared with the total duration T + 2*T1 required to complete the progressive scanning of three gate lines in the related art, since T2 < T1, so T + T1 + T2 < T + 2*T1. It can be seen that compared with the related art, when performing progressive scanning of multiple gate lines GL, the technical solution described in the present disclosure requires a shorter total duration, and the scanning period of one frame is also shorter, which is beneficial to achieving a higher refresh rate and better display effect.

[0061] Exemplarily, in one frame scanning period, there is no excessive limitation on the size of the second duration T2. For example, refer to Figure 6 , the second duration T2 is zero, that is, the multiple switching transistors coupled to the second gate line GL2 and the multiple switching transistors coupled to the third gate line GL3 are turned on simultaneously. Another example, refer to Figure 7 , the second duration T2 is greater than 0 and less than or equal to 1 / 2 of the first duration T1, and the multiple switching transistors coupled to the second gate line GL2 are turned on earlier than the multiple switching transistors coupled to the third gate line GL3. Specifically, the time difference between the turn-on moments of the multiple switching transistors coupled to the third gate line GL3 and the multiple switching transistors coupled to the second gate line GL2 can be 1 / 2 of the first duration T1. In the above schemes, the second duration T2 is less than the first duration T1. Therefore, similar to the foregoing, when performing scanning of multiple gate lines GL, the total duration required for the scanning process is reduced, and the above schemes can all shorten the scanning period of one frame and improve the refresh rate.

[0062] Exemplarily, refer to Figure 6 and Figure 7 , in one frame scanning period, in the scanning signals SC respectively output by the scanning driving circuit to any two adjacent gate lines GL in the column direction in the gate line group GP, at least part of their effective scanning periods ET overlap. Exemplarily, the scanning driving circuit sequentially outputs scanning signals SC to the first gate line GL1, the second gate line GL2, and the third gate line GL3 arranged in the column direction in the gate line group GP. If the effective scanning periods ET of the first scanning signal SC1, the second scanning signal SC2, and the third scanning signal SC3 do not overlap with each other, and the first duration is T1 and the second duration is T2, the total duration required to complete the progressive scanning of the first gate line GL1, the second gate line GL2, and the third gate line GL3 is 3*T + T1 + T2. And refer to Figure 6 and Figure 7When the effective scanning periods ET of the first scanning signal SC1, the second scanning signal SC2, and the third scanning signal SC3 overlap, and the first duration is T1 and the second duration is T2, the total duration required to complete the progressive scanning of the first gate line GL1, the second gate line GL2, and the third gate line GL3 is T+T1+T2. T+T1+T2<3*T+T1+T2. It can be seen that the above setting can further shorten the scanning period of a frame, thereby further improving the refresh rate and achieving a better display effect.

[0063] For example, see Figure 2 、 Figures 6 and 7 , the clock signal line can adopt a 4CLK structure. At this time, the gate line group GP also includes a fourth gate line GL4 adjacent to the third gate line GL3 along the column direction. The scan drive circuit outputs a fourth scan signal SC4 to the fourth gate line GL4. The starting time of the effective scan period ET of the fourth scan signal SC4 is delayed by a third duration T3 compared to the starting time of the effective scan period ET of the third scan signal SC3, wherein the third duration T3 is equal to the first duration T1. At this time, the second duration T2 is less than the first duration T1, which is equivalent to the effective scan period ET of the second scan signal SC2 transmitted by the second gate line GL2 starting in advance. Then, accordingly, the effective scan period ET of the scan signal SC of each gate line GL scanned after the second gate line GL2 also starts in advance. The total time for multiple gate lines to perform row-by-row scanning is also shortened, thereby having a shorter frame scan period and a higher refresh rate. In addition, using fewer clock signal lines CL is conducive to reducing the number of pins of the integrated circuit, reducing the frame of the display device, and allowing users to obtain a better visual experience.

[0064] For example, see Figure 4 and Figures 6 and 7When the gate line group GP also includes a fourth gate line GL4, the first scan signal SC1 and the fourth scan signal SC4 output by the scan drive circuit to the gate line group GP have at least a portion of their respective effective scan periods ET overlapping. That is, within the effective scan period ET of the first scan signal SC1, the effective scan periods ET of the scan signals SC transmitted by the second gate line GL2, the third gate line GL3, and the fourth gate line GL4 begin in sequence. For the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4, not only do the effective scan periods ET of the scan signals SC transmitted by any two adjacent gate lines GL partially overlap, but the effective scan periods ET of the scan signals SC transmitted by all four gate lines GL partially overlap. As a result, the total time required for the scan drive circuit to output the scan signals SC to each gate line GL in a gate line group GP is shortened, and accordingly, a frame scan period for scanning each gate line GL in multiple gate line groups GP is also shortened, thereby further improving the refresh rate and achieving a better display effect.

[0065] For example, see Figures 8 to 11The clock signal line CL may adopt an 8CLK structure. In this case, the plurality of gate line groups GP may include a first gate line group GP1 and a second gate line group that are sequentially adjacently arranged along a column direction (ie, a Y direction). GP2 is about to divide any two adjacent gate line groups GP along the column direction among the multiple gate line groups GP into a first gate line group GP1 and a second gate line group GP2. The first gate line group GP1 and the second gate line group GP2 both include a first gate line GL1, a second gate line GL2, a third gate line GL3 and a fourth gate line GL4 which are adjacently arranged in sequence along the column direction. The setting position of the first gate line group GP1 is before the second gate line group GP2. In a frame scanning cycle, the effective scanning period ET of the scanning signal SC output by the scanning driving circuit to each gate line GL in the second gate line group GP1 is delayed by a non-zero time length compared to the effective scanning period ET of the scanning signal SC output by the scanning driving circuit to each gate line GL in the first gate line group GP2. The effective scanning period ET of the scanning signal SC transmitted by each gate line GL in the first gate line group GP1 starts before the effective scanning period ET of the scanning signal SC transmitted by each gate line GL in the second gate line group GP2. Specifically, compared to the start time of the effective scanning period ET of the fourth scanning signal SC4 output by the fourth gate line GL4 in the first gate line GL1 group, the start time of the effective scanning period ET of the first scanning signal SC1 output by the first gate line GL1 in the second gate line GL2 group is delayed by the fourth time duration T4. Wherein, the fourth time duration T4 is equal to the first time duration T1. That is, in the first gate line GL1 group, the start time of the effective scanning period ET of the fourth scanning signal SC4 transmitted by the fourth gate line GL4 is later than the time when the effective scanning period ET of the first scanning signal SC1 transmitted by the first gate line GL1 in the second gate line group GP2 begins. Since the first gate line group GP1 and the second gate line group GP2 differ only in their placement, the timing of the scan signal SC transmitted by each gate line GL in the second gate line group GP2 is similar to the timing of the scan signal SC transmitted by each gate line GL in the first gate line group GP1. Therefore, the total time required to complete the scanning of each gate line GL in the second gate line group GP2 is also shortened. A frame scan period of a display device having multiple first gate line groups GP1 and second gate line groups GP2 can also be shortened, thereby achieving a higher refresh rate and better display effects. In addition, using more clock signal lines to transmit clock signals can reduce the load on a single clock signal line, which is beneficial for reducing power consumption.

[0066] For example, see Figure 12, the plurality of data lines DL include a representative data line RL. The plurality of sub-pixels P coupled to the plurality of gate lines GL in a gate line group GP include: a first sub-pixel P1 coupled to the representative data line RL and the first gate line GL1, a second sub-pixel P2 coupled to the representative data line RL and the second gate line GL2, a third sub-pixel P3 coupled to the representative data line RL and the third gate line GL3, and the second sub-pixel P2 and the third sub-pixel P3 have the same color. In a frame scanning period, a first data signal D1 is written to the first sub-pixel P1 through the representative data line RL, and a second data signal D2 or a third data signal D3 is simultaneously written to the second sub-pixel P and the third sub-pixel P through the representative data line RL; the first data signal D1 is a data signal corresponding to the pixel data of the first sub-pixel P1, the second data signal D2 is a data signal corresponding to the pixel data of the second sub-pixel P2, and the third data signal D3 is a data signal corresponding to the pixel data of the third sub-pixel P3. The representative data line RL is any data line DL among the plurality of data lines DL. In the related art, to write data to the first subpixel P1, the second subpixel P2, and the third subpixel P3, which are respectively coupled to different gate lines GL, it is necessary to sequentially write a first data signal D1 to the first subpixel P1, a second data signal D2 to the second subpixel P2, and a third data signal D3 to the third subpixel P3 via the data line DL. Therefore, the data driver circuit needs to perform the data signal output process three times. However, according to the embodiments of the present disclosure, it is necessary to write the first data signal D1 to the first subpixel P1 via the data line DL, and then simultaneously write the second data signal D2 or the third data signal D3 to the second subpixel P2 and the third subpixel P3 via the data line DL. The data driver circuit only needs to perform the data signal output process twice to write data to the three subpixels P respectively coupled to the three gate lines GL. Since the number of data signal Data outputs by the data driver circuit is reduced, the total time required to complete the data write is also reduced, which helps to further shorten the scanning period of a frame and improve the refresh rate. At the same time, since the second sub-pixel P2 and the third sub-pixel P3 are spatially arranged relatively close, and the second sub-pixel P2 and the third sub-pixel P3 have the same color (that is, the second sub-pixel P2 and the third sub-pixel P3 are both red sub-pixels or blue sub-pixels or green sub-pixels), the grayscale of the second sub-pixel P2 and the third sub-pixel P3 when displaying images is also relatively close, so sharing the data signal of one of them for display can not only achieve an increase in the refresh rate, but also ensure that the display device has a good display effect.

[0067] For example, see Figure 9 and Figure 12In a frame scanning cycle, the second duration T2 is zero. The first data signal D1 is written to the first sub-pixel P1 through the representative data line RL, and the second data signal D2 is simultaneously written to the second sub-pixel P and the third sub-pixel P through the representative data line RL. The duration of the second data signal D2 is equal to the first duration T1, and the start time of the second data signal D2 is delayed by a fifth duration T5 compared to the start time of the effective scanning period ET of the second scanning signal SC2. The fifth duration T5 is twice the first duration T1. For example, see Figure 9 and Figure 12 , the second time duration T2 is zero, the gate line group GP includes the first gate line GL1, the second gate line GL2, the third gate line GL3 and the fourth gate line GL4, and the multiple sub-pixels P coupled to the multiple gate lines GL in one gate line group GP also include a fourth sub-pixel P4 coupled to the representative data line RL and the fourth gate line GL4. The fourth data signal D4 is written to the fourth sub-pixel P4 through the representative data line RL. The fourth data signal D4 is a data signal corresponding to the pixel data of the fourth sub-pixel P4. There are no excessive restrictions on the specific timing of the first data signal D1 and the fourth data signal D4. For example, continue to refer to Figure 9 and Figure 12 The second data signal D2 is written simultaneously into the second subpixel P2 and the third subpixel P3. The durations of the first data signal D1, the second data signal D2, and the fourth data signal D4 are all equal to the first duration T1. The time difference between the start time of the first data signal D1 and the start time of the effective scanning period of the first scanning signal SC1 is equal to twice the first duration T1. The time difference between the start time of the fourth data signal D4 and the start time of the effective scanning period ET of the fourth scanning signal SC4 is also equal to twice the first duration T1. The start time of the second data signal D2 is delayed by a fifth duration T5 relative to the start time of the effective scanning period ET of the second scanning signal SC2. The fifth duration T5 is twice the first duration T1. Simultaneously, the time difference between the start time of the third data signal SC3 and the start time of the effective scanning period ET of the third scanning signal SC3 is also equal to twice the first duration T1. According to the above settings, the data signal Data can be written into multiple sub-pixels P of the second sub-pixel P2 and the third sub-pixel P3 through only one writing process. The number of writing times of the data signal Data is reduced, and accordingly, the total time required for data writing is reduced, which is conducive to further shortening the scanning cycle of one frame and improving the refresh rate.

[0068] For example, see Figure 9 and Figure 12In a frame scan cycle, the second duration T2 is zero, and the first data signal D1 can be written to the first subpixel P1 via the representative data line RL. The third data signal D3 can also be written to the second subpixel P2 and the third subpixel P3 simultaneously via the representative data line. The duration of the third data signal D3 is equal to the first duration T1, and the start time of the third data signal D3 is delayed by a fifth duration T5 relative to the start time of the effective scan period ET of the third scan signal SC3. The fifth duration T5 is twice the first duration T1. Similar to the above, this configuration also has a shorter data write time and can also achieve a higher refresh rate.

[0069] For example, see Figure 10 and Figure 12 , the second duration T2 is not zero. During the effective scanning period ET during which the second gate line GL2 transmits the second scanning signal SC2, the scanning of the third gate line GL3 is started in advance, and the second data signal D2 can also be written to the second sub-pixel P and the third sub-pixel P simultaneously through the representative data line RL. Similar to the above, the number of times the data signal Data is written is reduced, which can also shorten the scanning cycle and improve the refresh rate.

[0070] For example, see Figure 10 、 Figure 11 and Figure 12 , the second duration T2 is greater than 0 and less than or equal to 1 / 2 of the first duration T1. In the odd-numbered frame scanning period, the first data signal D1 is written to the first sub-pixel P1 through the representative data line RL, and the second data signal D2 is simultaneously written to the second sub-pixel P2 and the third sub-pixel P3 through the representative data line RL. The end time of the second data signal D2 is earlier than the end time of the effective scanning period ET of the third scanning signal SC3 by the sixth duration T6. Figure 11 and Figure 12During an even-numbered frame scan period, a first data signal D1 is written to the first subpixel P1 via the representative data line RL, and a third data signal D3 is simultaneously written to the second subpixel P2 and the third subpixel P3 via the representative data line RL. The end time of the third data signal D3 is delayed by the seventh duration T7 relative to the end time of the effective scan period ET of the second scan signal SC2. The durations of the second data signal D2 and the third data signal D3 are both equal to the first duration T1, and the sixth duration T6 and the seventh duration T7 are both greater than 0. The image display process of the display device includes multiple frame scan periods, which can be divided into odd-numbered frame scan periods and even-numbered frame scan periods. When the scan period is an odd-numbered frame scan period, the timing control circuit inputs an odd-numbered frame start signal STVA to the scan driver circuit. When the scan period is an even-numbered frame scan period, the timing control circuit inputs an even-numbered frame start signal STVB to the scan driver circuit. Similar to the above, this setting method can write the data line number into the second sub-pixel P2 and the third sub-pixel P3 through a data writing process, and can also reduce the number of times the data driving circuit outputs the data signal Data in a frame scanning cycle. Therefore, it also has the above-mentioned beneficial effects and will not be repeated here.

[0071] For example, when the second time duration T2 is greater than 0 and less than or equal to 1 / 2 of the first time duration T1, see Figure 11 and Figure 12 In an odd-numbered frame scanning cycle, a first data signal D1 is written to the first sub-pixel P1 through the representative data line RL, and a third data signal D3 is simultaneously written to the second sub-pixel P2 and the third sub-pixel P3 through the representative data line RL. The end time of the third data signal D3 is delayed by the seventh time duration T7 compared to the end time of the effective scanning period ET of the second scanning signal SC2. Figure 10 and Figure 12 During an even-numbered frame scan cycle, a first data signal D1 is written to the first subpixel P1 via the representative data line RL, and a second data signal D2 is simultaneously written to the second subpixel P2 and the third subpixel P3 via the representative data line RL. The end time of the second data signal D2 is earlier than the end time of the effective scan period ET of the third scan signal SC3 by the sixth duration T6. The durations of the second data signal D2 and the third data signal D3 are both equal to the first duration T1, and the sixth duration T6 and the seventh duration T7 are both greater than zero. This can also reduce the number of write operations and achieve a higher refresh rate.

[0072] Specifically, there are no excessive restrictions on the specific value of the second duration. Figure 10 、 Figure 11 and Figure 12, the second duration T2 is equal to 1 / 2 of the first duration T1. As mentioned above, the first duration T1 can be 1 / 3 of the effective scanning period ET of any scanning signal SC, so the second duration T2 can be 1 / 6 of the effective scanning period ET of any scanning signal SC. The duration of the second data signal D2 and the third data signal D3 are both equal to the first duration T1, and the sixth duration T6 and the seventh duration T7 are both 1 / 2 of the first duration T1. See Figure 10 and Figure 12 In the odd-numbered frame scanning period, the start time of the second data signal D2 is delayed by an eighth time period T8 compared to the start time of the effective scanning period ET of the second scanning signal SC2. Figure 11 and Figure 12 In an even frame scanning cycle, the start time of the third data signal D3 is delayed by a ninth time period T9 compared to the start time of the effective scanning period ET of the third scanning signal SC3. The eighth time period T8 and the ninth time period T9 are both twice the first time period. Figure 10 、 Figure 11 and Figure 12 The second duration T2 is equal to 1 / 2 of the first duration. The gate line group GP includes a first gate line GL1, a second gate line GL2, a third gate line GL3, and a fourth gate line GL4. The multiple sub-pixels P coupled to the multiple gate lines GL in the gate line group GP also include a fourth sub-pixel P4 coupled to the representative data line RL and the fourth gate line GL4. A fourth data signal D4 is written to the fourth sub-pixel P4 via the representative data line RL. The fourth data signal D4 is a data signal corresponding to the pixel data of the fourth sub-pixel P4. The specific timing of the first data signal D1 and the fourth data signal D4 is not excessively limited. For example, the durations of the first data signal D1, the second data signal D2, and the fourth data signal D4 are all equal, and are all equal to the first duration T1. The duration of the time difference between the start time of the first data signal D1 and the start time of the effective scanning period ET of the first scanning signal SC1 is equal to twice the first duration T1. The duration of the time difference between the start time of the fourth data signal D4 and the start time of the effective scanning period ET of the fourth scanning signal SC4 is also equal to twice the first duration T1. Figure 10 and Figure 12 In an odd-numbered frame scanning cycle, the start time of the second data signal D2 is delayed by an eighth time period T8 compared to the start time of the effective scanning period ET of the second scanning signal SC2. The eighth time period T8 is equal to twice the first time period T1. The end time of the second data signal D2 is advanced by a sixth time period T6 compared to the end time of the effective scanning period ET of the third scanning signal SC3. The sixth time period T6 is 1 / 2 of the first time period T1. Figure 11 and Figure 12In an even-numbered frame scanning cycle, the time difference between the start time of the third data signal D3 and the start time of the effective scanning period ET of the second scanning signal SC2 is equal to 2.5 times the first time period T1. The end time of the third data signal D3 is delayed by a seventh time period T7 relative to the end time of the effective scanning period ET of the second scanning signal SC2, and the seventh time period T7 is 1 / 2 of the first time period T1. The start time of the third data signal D3 is delayed by a ninth time period T9 relative to the start time of the effective scanning period ET of the third scanning signal SC3, and the ninth time period T9 is twice the first time period T1. According to the above configuration, the data signal Data can be written into multiple sub-pixels P of the second sub-pixel P2 and the third sub-pixel P3 through only one write process, reducing the number of data signal Data writes and, accordingly, reducing the total time required for data writing. This helps further shorten the scanning cycle of a single frame and improve the refresh rate.

[0073] For example, any two adjacent gate lines GL in the first gate line GL1 group along the column direction are divided into a preceding gate line GL and a following gate line GL, and the preceding gate line GL is positioned before the following gate line GL. That is, in a frame scanning cycle, the effective scanning period of the scanning signal output by the scanning driving circuit to the following gate line is delayed by a non-zero time period compared to the effective scanning period of the scanning signal output by the scanning driving circuit to the preceding gate line. For example, see Figure 12 In the first gate line group GP1, the first gate line GL1 is located before the second gate line GL2. Then, for the first gate line GL1 and the second gate line GL2, the first gate line GL1 is the preceding gate line and the second gate line GL2 is the following gate line. Figure 12 In the first gate line group GP1, the second gate line GL2 is located before the third gate line GL3. Therefore, the second gate line GL2 is the preceding gate line, and the third gate line GL3 is the following gate line. The preceding gate line and the following gate line are relative concepts and do not refer to specific gate lines.

[0074] The process of data signal input to the sub-pixel is the charging process of the load capacitance formed by the pixel electrode and the common electrode in the sub-pixel. 2As can be seen from t, the longer the charging time and the larger the charging current, the more charge the load capacitor is charged into. Like this, after charging is completed, the voltage of the load capacitor is a grayscale voltage (even if the sub-pixel can display the voltage value of the preset grayscale), and the voltage holding ability of the sub-pixel is also stronger. However, for liquid crystal display devices, when the refresh rate of the liquid crystal display device is high, the problem of insufficient charging of the load capacitor is easy to occur. When each data line DL is configured to write data signals respectively in each sub-pixel of at least one (for example, can be three) sub-pixel row, it is possible to make a plurality of sub-pixels coupled to the previous gate line carry out data signal writing (i.e. charging) while a plurality of sub-pixels coupled to the next gate line are pre-charged (i.e., to a plurality of sub-pixels coupled to the next gate line, write the data signals of a plurality of sub-pixels coupled to the previous gate line respectively), so that the voltage of the load capacitor in a plurality of sub-pixels coupled to the next gate line is a pre-charge voltage.

[0075] Exemplarily, during a frame scan period, the data signals written into each sub-pixel coupled to the preceding gate line overlap with the effective scan period of the scan signal output by the scan driver circuit to the succeeding gate line. Specifically, the effective scan period of the scan signal output by the scan driver circuit to the preceding gate line overlaps with the effective scan period of the scan signal output by the scan driver circuit to the succeeding gate line, so that when the switching tubes corresponding to each sub-pixel coupled to the preceding gate line are in an on state, the switching tubes corresponding to each sub-pixel coupled to the preceding gate line are also turned on. Simultaneously, the data signals written into each sub-pixel coupled to the preceding gate line overlap with the effective scan period of the scan signal output by the scan driver circuit to the succeeding gate line, so that while the load capacitors of each sub-pixel coupled to the preceding gate line are charged, the data signals of each sub-pixel coupled to the succeeding gate line can be written into each sub-pixel coupled to the succeeding gate line, thereby precharging the load capacitors of each sub-pixel coupled to the succeeding gate line. Since in a frame scanning cycle, the difference between the current frame grayscale voltage and the pre-charge voltage of the sub-pixel is smaller than the difference between the current frame grayscale voltage and the previous frame grayscale voltage of the sub-pixel, some pixels are pre-charged in the current frame, which shortens the time required for the sub-pixel to reach the grayscale voltage, avoids the problem of insufficient charging of the load capacitor, and is conducive to increasing the refresh rate.

[0076] For example, see Figure 10 and Figure 12In a frame scanning cycle, the effective scanning periods ET of the first scanning signal SC1 and the second scanning signal SC2 partially overlap, and the data signal Data written into the first sub-pixel P1 overlaps with part of the effective scanning period ET in the second scanning signal SC2. In this way, while the first sub-pixel P1 is being charged, the second sub-pixel P2 can be pre-charged, thereby shortening the charging time of the load capacitor corresponding to the second sub-pixel P2, which is beneficial to improving the refresh rate.

[0077] For example, see Figure 10 、 Figure 11 and Figure 12 As described above, when the gate line group GP further includes the fourth gate line GL4, the effective scanning periods ET of the first scan signal SC1, the second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4 partially overlap, and the effective scanning periods ET of the first data signal D1 and the second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4 partially overlap. That is, while each sub-pixel P coupled to the first gate line GL1 is being charged, each sub-pixel P coupled to the second gate line GL2, the third gate line GL3, and the fourth gate line GL4 can be pre-charged simultaneously, thereby shortening the time required for the four sub-pixels P to reach the grayscale voltage, achieving a higher refresh rate and better display effect.

[0078] In the process of using liquid crystal display devices to realize image display, in order to avoid the solidification of the characteristics of liquid crystal molecules, alternating current is usually used for driving. Specifically, the data signal of the liquid crystal display device changes positively and negatively with the common voltage as the reference. When the voltage of the data signal is greater than the common voltage, the driving signal is positive, and vice versa. If a positive polarity data signal is charged into a sub-pixel, the sub-pixel is positive; if a negative polarity data signal is charged into a sub-pixel, the sub-pixel is negative. For the same sub-pixel, when the polarity of the input data signal is different, its luminous brightness is different. For example, see Figure 12 The plurality of data lines DL include first data lines DL1 and second data lines DL2 that are alternately distributed along the row direction (i.e., the X direction). In one frame scanning period, the data driving circuit is configured to output a first type of data signal to the first data line DL1 and a second type of data signal to the second data line DL, wherein the polarities of the first type of data signal and the second type of data signal are different. For example, see Figure 3, the first data line DL1 outputs a first type of data signal, the polarity of the first type of data signal is positive, and the second data line DL2 outputs a second type of data signal, the polarity of the second type of data signal is negative. The above-mentioned data signal Data input method makes the polarity of multiple sub-pixels P with the same color in the same column (i.e., Y direction) the same, and among the multiple sub-pixels P with the same color in any two adjacent columns, the polarity of the multiple sub-pixels P in one column is different from the polarity of the multiple sub-pixels P in the other column, so that in one frame scanning cycle, the brightness of multiple columns of sub-pixels P with the same color but different polarity can be averaged in the row direction to achieve a more uniform display brightness. For another example, see Figure 4 The data lines DL and the data signals they transmit are configured similarly to those described above. This data signal input method ensures that multiple sub-pixels P of the same color in the same column have different polarities, and multiple sub-pixels P of the same color in the same row also have different polarities. During a single frame scan cycle, the polarities of the multiple sub-pixels P of the same color in the same row are arranged in a repeating pattern of positive, positive, negative, and negative, while the polarities of the multiple sub-pixels P of the same color in the same column are arranged in an alternating pattern of positive and negative. This allows the use of a column-inverted data signal input method to achieve a display effect similar to dot inversion. For multiple sub-pixels P of the same color, average brightness is achieved in both row and column directions, resulting in a superior display quality.

[0079] If liquid crystal molecules are constantly operating at a fixed voltage, their properties will solidify. Once these properties solidify, even if the fixed voltage is removed, the liquid crystal molecules will no longer respond to changes in the applied voltage. For example, drive methods such as row inversion, column inversion, and dot inversion can be used to drive a liquid crystal display device to avoid the problem of solidified physical properties of the liquid crystal molecules, thereby achieving better display effects and extending the life of the device. For example, a column inversion drive method can be used, where the data driver circuit outputs different polarities of the data signal to the same data signal in two adjacent frame scanning cycles.

[0080] In other embodiments of the present disclosure, a method for driving a display device is provided. The driving method may be performed by the above-mentioned display device or a product including the above-mentioned display device. Figure 10 、 Figure 11 and Figure 12The driving method includes: in a frame scanning period, the scanning driving circuit is configured to output scanning signals SC to the plurality of gate lines GL in the gate line group GP, specifically, the scanning driving circuit sequentially outputs the first scanning signal SC1 to the first gate line GL1, outputs the second scanning signal SC2 to the second gate line GL2, and outputs the third scanning signal SC3 to the third gate line GL3. The effective scanning periods ET of the first scanning signal SC1, the second scanning signal SC2, and the third scanning signal SC3 are equal in duration, and the starting time of the effective scanning period ET of the second scanning signal SC2 is delayed by a first duration T1 compared to the starting time of the effective scanning period ET of the first scanning signal SC1, and the starting time of the effective scanning period ET of the third scanning signal SC3 is delayed by a second duration T2 compared to the starting time of the effective scanning period ET of the second scanning signal SC2, and the second duration T2 is less than the first duration T1. There are no excessive restrictions on the length of the first duration T1. For example, the first duration T1 is no longer than the duration of the effective scanning period ET of any scanning signal SC. Specifically, the first duration T1 can be equal to 1 / 3 of the duration of the effective scanning period ET of any scanning signal SC. Similar to the above, this driving method is equivalent to advancing the effective scanning period ET of the third scanning signal SC3 by the second duration T2. ​​The timing of the scanning signals SC output sequentially after the third scanning signal SC3 is also advanced as a whole. This shortens the total time required to complete a frame scanning cycle when performing progressive scanning of multiple gate lines GL, thereby facilitating a higher refresh rate and achieving a better display effect.

[0081] For example, there are no particular limitations on the specific duration (i.e., the second duration T2) by which the effective scanning period ET of the third scanning signal SC3 is advanced. For example, the second duration T2 may be zero. For another example, the second duration R2 may be greater than zero and less than or equal to 1 / 2 of the first duration R1. Similar to the configuration of a display device, the use of this driving method can also achieve the purpose of increasing the refresh rate and improving the display quality.

[0082] For example, see Figure 10 、 Figure 11 and Figure 12When the display device 1 further includes a data driving circuit and a plurality of data lines DL, the data driving circuit is coupled to the plurality of data lines DL and is configured to output data signals Data to the plurality of data lines DL, respectively. The data lines DL are configured to write data signals Data to the sub-pixels P, where the data signals Data are pixel data of the sub-pixels P. The plurality of data lines DL include a representative data line RL. The plurality of sub-pixels P coupled to the plurality of gate lines GL in a gate line group GP include: a first sub-pixel P1 coupled to the representative data line RL and a first gate line GL1, a second sub-pixel P2 coupled to the representative data line RL and a second gate line GL2, and a third sub-pixel P3 coupled to the representative data line RL and a third gate line GL3. The second sub-pixel P2 and the third sub-pixel P3 have the same color. In this case, the driving method of the display device further includes, during a frame scan period, the data driving circuit writing a first data signal D1 to the first subpixel P1 via the representative data line RL, and simultaneously writing a second data signal D2 or a third data signal D3 to the second subpixel P2 and the third subpixel P3 via the representative data line RL; the first data signal D1 is a data signal corresponding to the pixel data of the first subpixel P1, the second data signal D2 is a data signal corresponding to the pixel data of the second subpixel P2, and the third data signal D3 is a data signal corresponding to the pixel data of the third subpixel P3. The representative data line RL is any data line DL from among the plurality of data lines DL. According to the above driving method, the number of data signal outputs by the data driving circuit is reduced, and accordingly, the total time required to complete data writing is also reduced, thereby further shortening the scanning period of a frame and improving the refresh rate.

[0083] For example, see Figure 12 The multiple data lines DL include first data lines DL1 and second data lines DL2, which are alternately arranged along the row direction (i.e., the X direction). During a single scan cycle, the data driver circuit outputs a first data signal to the first data line DL1 and a second data signal to the second data line DL2. The first and second data signals have different polarities. This arrangement enables the brightness of multiple columns of sub-pixels P with the same color but different polarities to be averaged in both the row and column directions during the display of a single frame of image, resulting in a more uniform display brightness and a better display effect.

[0084] Some embodiments of the present disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium), which stores computer program instructions. When the computer program instructions are executed on a computer (e.g., a liquid crystal display device), the computer executes a method for driving a display device as described in any of the above embodiments.

[0085] Exemplarily, the above-mentioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes, etc.), optical disks (e.g., CDs (Compact Disks), DVDs (Digital Versatile Disks), etc.), smart cards, and flash memory devices (e.g., EPROMs (Erasable Programmable Read-Only Memory), cards, sticks, or key drives, etc.). The various computer-readable storage media described in the present disclosure may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0086] Some embodiments of the present disclosure further provide a computer program product comprising computer program instructions, which, when executed on a computer (eg, a liquid crystal display device), cause the computer to execute the display device driving method described in the above embodiments.

[0087] Some embodiments of the present disclosure further provide a computer program. When the computer program is executed on a computer (eg, a liquid crystal display device), the computer program causes the computer to execute the method for driving the display device as described in the above embodiments.

[0088] The beneficial effects of the above-mentioned computer-readable storage medium, computer program product, and computer program are the same as the beneficial effects of the display device driving method described in some of the above-mentioned embodiments, and are not repeated here.

[0089] The beneficial effects of the above-mentioned computer-readable storage medium, computer program product, and computer program are the same as the beneficial effects of the display device driving method described in some of the above-mentioned embodiments, and are not repeated here.

[0090] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display device, characterized in that: include: A plurality of sub-pixels, wherein the plurality of sub-pixels are arranged in an array; At least one gate line group, the gate line group including a plurality of gate lines, the plurality of gate lines including: a first gate line, a second gate line, and a third gate line sequentially arranged adjacent to each other along a column direction; A scan driving circuit, the scan driving circuit being coupled to a plurality of gate lines in the gate line group and configured to output scan signals to the plurality of gate lines in the gate line group in a frame scanning period, comprising: sequentially outputting a first scan signal to the first gate line, outputting a second scan signal to the second gate line, and outputting a third scan signal to the third gate line; The effective scanning periods of the first scanning signal, the second scanning signal, and the third scanning signal are equal in duration, and a start time of the effective scanning period of the second scanning signal is delayed by a first time period compared to a start time of the effective scanning period of the first scanning signal, and a start time of the effective scanning period of the third scanning signal is delayed by a second time period compared to a start time of the effective scanning period of the second scanning signal; The second duration is less than the first duration; the second duration is zero, or the second duration is greater than 0 and less than or equal to 1 / 2 of the first duration; The display device further includes: a data driving circuit and a plurality of data lines, the data driving circuit being coupled to the plurality of data lines and configured to output data signals to the plurality of data lines respectively, the data lines being configured to write data signals to the sub-pixels, the data signals being sub-pixel data of the sub-pixels; The plurality of data lines includes a representative data line; The plurality of sub-pixels coupled to the plurality of gate lines in a gate line group include: a first sub-pixel coupled to the representative data line and the first gate line, a second sub-pixel coupled to the representative data line and the second gate line, and a third sub-pixel coupled to the representative data line and the third gate line; The second duration is zero, and a second data signal is simultaneously written to the second sub-pixel and the third sub-pixel through the representative data line; a start time of the second data signal is delayed by a fifth duration compared to a start time of an effective scanning period of the second scanning signal; The fifth duration is twice as long as the first duration.

2. The display device according to claim 1, wherein In the scan signals respectively output by the scan driving circuit to any two adjacent gate lines in the gate line group along the column direction, respective effective scan periods at least partially overlap.

3. The display device according to claim 1, wherein The gate line group further includes: a fourth gate line arranged adjacent to the third gate line along the column direction; The scan drive circuit is configured to output a fourth scan signal to the fourth gate line, the effective scan periods of the fourth scan signal and the third scan signal are equal in length, the start time of the effective scan period of the fourth scan signal is delayed by a third time period compared to the start time of the effective scan period of the third scan signal, and the third time period is equal to the first time period.

4. The display device according to claim 3, wherein: The first scanning signal and the fourth scanning signal output by the scanning driving circuit to the gate line group have respective effective scanning periods partially overlapping.

5. The display device according to any one of claims 2 to 4, characterized in that The at least one gate line group includes a first gate line group and a second gate line group that are sequentially adjacent to each other along the column direction; Compared to the start time of the effective scanning period of the fourth scanning signal output by the fourth gate line in the first gate line group, the start time of the effective scanning period of the first scanning signal output by the first gate line in the second gate line group is delayed by a fourth time period; The fourth duration is equal to the first duration.

6. The display device according to claim 1, wherein The second sub-pixel and the third sub-pixel have the same color; In a frame scanning cycle, a first data signal is written to the first sub-pixel through the representative data line, and a second data signal or a third data signal is simultaneously written to the second sub-pixel and the third sub-pixel through the representative data line; the first data signal is a data signal corresponding to the pixel data of the first sub-pixel, the second data signal is a data signal corresponding to the pixel data of the second sub-pixel, and the third data signal is a data signal corresponding to the pixel data of the third sub-pixel.

7. The display device according to claim 6, wherein: In a frame scanning cycle, the second duration is zero; writing the first data signal to the first sub-pixel through the representative data line; The duration of the second data signal is equal to the first duration.

8. The display device according to claim 6, wherein: The second duration is greater than 0 and less than or equal to 1 / 2 of the first duration; In an odd-numbered frame scanning period, the first data signal is written to the first sub-pixel through the representative data line, and the second data signal is simultaneously written to the second sub-pixel and the third sub-pixel through the representative data line, and an end time of the second data signal is earlier than an end time of the third scanning signal by a sixth time duration; In an even-numbered frame scanning period, the first data signal is written into the first sub-pixel through the representative data line, and the third data signal is simultaneously written into the second sub-pixel and the third sub-pixel through the representative data line, and an end time of the third data signal is delayed by a seventh time period compared to an end time of an effective scanning period of the second scanning signal; The durations of the second data signal and the third data signal are both equal to the first duration; The sixth duration and the seventh duration are both greater than 0.

9. The display device according to claim 8, wherein The second duration is equal to 1 / 2 of the first duration; The durations of the second data signal and the third data signal are both equal to the first duration; The sixth duration and the seventh duration are both 1 / 2 of the first duration; In an odd-numbered frame scanning cycle, a start time of the second data signal is delayed by an eighth time period compared to a start time of an effective scanning period of the second scanning signal; In an even-numbered frame scanning cycle, a start time of the third data signal is delayed by a ninth time period compared to a start time of an effective scanning period of the third scanning signal; The eighth duration and the ninth duration are both twice as long as the first duration.

10. The display device according to any one of claims 6 to 9, characterized in that The scanning signals outputted by the scanning driving circuit to any two adjacent gate lines in the first gate line group along the column direction respectively have respective effective scanning periods at least partially overlapping; Any two adjacent gate lines in the first gate line group along the column direction are divided into a preceding gate line and a succeeding gate line, and the preceding gate line is arranged before the succeeding gate line; The data signals written into the sub-pixels coupled to the preceding gate line respectively partially overlap with the effective scanning period of the scanning signal output by the scanning driving circuit to the succeeding gate line.

11. The display device according to claim 6, wherein The plurality of data lines include first data lines and second data lines alternately distributed along a row direction; In one frame scanning period, the data driving circuit is configured to output a first type of data signal to the first data line and output a second type of data signal to the second data line; The first type of data signal and the second type of data signal have different polarities.

12. The display device according to claim 6, wherein: A data line is coupled to two sub-pixels in the same row, and the two sub-pixels coupled to the data line are respectively coupled to different gate lines.

13. The display device according to claim 1, wherein Also includes: a timing control circuit, the timing control circuit being coupled to the scan driving circuit and configured to output a plurality of clock signals to the scan driving circuit; The scan driving circuit is configured to output scan signals to the plurality of gate lines respectively according to the plurality of clock signals.

14. A method for driving a display device, characterized in that: The display device according to any one of claims 1 to 13, wherein the driving method comprises: In a frame scanning period, the scanning driving circuit is configured to output scanning signals to the plurality of gate lines in the gate line group respectively, including: sequentially outputting a first scanning signal to the first gate line, outputting a second scanning signal to the second gate line, and outputting a third scanning signal to the third gate line; The effective scanning periods of the first scanning signal, the second scanning signal, and the third scanning signal are equal in duration, and the effective scanning period of the second scanning signal is delayed by a first duration compared to the start time of the effective scanning period of the first scanning signal, and the start time of the effective scanning period of the third scanning signal is delayed by a second duration compared to the start time of the effective scanning period of the second scanning signal; The second duration is less than the first duration; the second duration is zero, or the second duration is greater than 0 and less than or equal to 1 / 2 of the first duration; The display device further includes: a data driving circuit and a plurality of data lines, wherein the data driving circuit is coupled to the plurality of data lines and configured to output data signals to the plurality of data lines respectively, wherein the data lines are configured to write data signals to sub-pixels, wherein the data signals are sub-pixel data of the sub-pixels; The plurality of data lines includes a representative data line; The plurality of sub-pixels coupled to the plurality of gate lines in a gate line group include: a first sub-pixel coupled to the representative data line and the first gate line, a second sub-pixel coupled to the representative data line and the second gate line, and a third sub-pixel coupled to the representative data line and the third gate line; The driving method further includes: when the second duration is zero, writing the second data signal to the second sub-pixel and the third sub-pixel simultaneously through the representative data line; and delaying the start time of the second data signal by a fifth duration compared to the start time of the effective scanning period of the second scanning signal; The fifth duration is twice as long as the first duration.

15. The driving method according to claim 14, wherein: The second sub-pixel and the third sub-pixel have the same color; The driving method also includes: in a frame scanning cycle, the data driving circuit writes a first data signal to the first sub-pixel through the representative data line, and simultaneously writes a second data signal or a third data signal to the second sub-pixel and the third sub-pixel through the representative data line; the first data signal is a data signal corresponding to the pixel data of the first sub-pixel, the second data signal is a data signal corresponding to the pixel data of the second sub-pixel, and the third data signal is a data signal corresponding to the pixel data of the third sub-pixel.

16. The driving method according to claim 15, wherein: The plurality of data lines include a first data line and a second data line adjacently arranged along a row direction, and the driving method further includes: In one frame scanning period, the data driving circuit outputs a first type of data signal to the first data line and outputs a second type of data signal to the second data line; The first type of data signal and the second type of data signal have different polarities.

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