A variable-length interface data transmission structure based on FPGA
Through the variable-length interface data transmission structure based on FPGA, the robustness problem of variable-length packet transmission in data link communication is solved, and a stable, general and resource-saving data transmission solution is realized.
Patent Information
- Application Number
- CN202211485109.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-24
- Publication Date
- 2025-08-22
- Estimated Expiration
- 2042-11-24
AI Technical Summary
In data link communication, the prior art is difficult to effectively handle the transmission of fixed-length data packets and variable-length data packets, resulting in poor robustness, prone to data loss and errors, and lack of generalized solutions.
The variable-length interface data transmission structure based on FPGA is adopted, including an interface processing module, a data verification module and a delay ping-pong asynchronous reconstruction module. Through the cache unit, an asynchronous reset module and a timing interrupt mechanism, the sequential transmission and stability of data are ensured.
It realizes high robustness and versatility data transmission, suitable for a variety of communication scenarios, with extremely small resource usage and stable timing, and is suitable for fixed-length and variable-length data packet transmission.
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Figure CN115712589B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to data transmission technology in the field of communication data links, and in particular to a variable-length interface data transmission structure based on FPGA. Background Art
[0002] In data link communication scenarios, the effective data length modulated by the physical layer and the interface data length are generally the same. That is, the central control machine sends a fixed-length data packet to the task machine's FPGA via an interface (such as a serial port, network port, or SRIO). The FPGA stores the data in a cache and triggers the physical layer to complete framing, encoding, and modulation. The data is then sent to the ADC, where the modulated signal is transmitted into free space via the power amplifier and antenna.
[0003] However, there is a special scenario where the physical layer needs to transmit multiple packets of data sent by the central control computer through the physical layer. This means that during each physical layer transmission period, the FPGA will receive multiple packets of data sent by the central control computer through the interface. The number of packets received each time is not fixed. The physical layer must send all interface data in full and in the order received. This first requires that the interface data be sent in sequential packets, and each packet of data should not be scattered across multiple physical layer transmission processes.
[0004] Existing papers and patents rarely propose clear, universal processing methods. In practical applications, conventional processing procedures are often overly complex, lack robustness, and are unstable, prone to cross-references, stale data, and even outliers. Summary of the Invention
[0005] The purpose of the present invention is to provide a variable-length interface data transmission structure based on FPGA, which has strong robustness and versatility, clear components, stable timing, and minimal resource occupation.
[0006] In order to achieve the above object, the present invention provides a variable-length interface data transmission structure based on FPGA, comprising an interface processing module, a data verification module and a delay ping-pong asynchronous reconstruction module;
[0007] The interface processing module is used to receive data from the central control machine;
[0008] The data verification module is used to verify the data received by the interface processing module and then send it to the delayed ping-pong asynchronous reconstruction module for data processing;
[0009] The delayed ping-pong asynchronous reconstruction module sends the processed data to the physical layer modulation module;
[0010] The delayed ping-pong asynchronous reconstruction module includes:
[0011] a first data cache unit, whose input end is connected to the output end of the interface data verification module and is used for storing the received interface data in a time-sharing manner;
[0012] a second data cache unit, whose input end is connected to the output end of the interface data verification module and is used for storing the received interface data in a time-sharing manner;
[0013] a first asynchronous reset module, whose output end is connected to the first data cache unit, and is used to perform a fast reset after the data in the first data cache unit is moved to the terminal fan-out cache unit;
[0014] a second asynchronous reset module, whose output end is connected to the second data cache unit, and is used to perform a fast reset after the data in the second data cache unit is moved to the terminal fan-out cache unit;
[0015] a delayed ping-pong control module, whose output ends are respectively connected to the first data cache unit and the second data cache unit, and is used to control the ping-pong switching between the first data cache unit and the second data cache unit;
[0016] a data reconstruction reading module, whose input end is connected to the output end of the first data cache unit and the output end of the second data cache unit, and is used to promptly move data from the first data cache unit and the second data cache unit when an asynchronous timing interrupt is generated;
[0017] an asynchronous timing interruption generating module, the output end of which is connected to the data reconstruction and reading module, for generating an asynchronous timing interruption;
[0018] a terminal fan-out buffer unit, whose input end is connected to the output end of the data reconstruction and reading module, and is used to provide data to the physical layer modulation module in a timely manner when an asynchronous read interrupt is generated;
[0019] An asynchronous read interruption generating module, whose output end is connected to the terminal fan-out buffer unit and whose input end is connected to the physical layer modulation module, is used for generating an asynchronous read interruption.
[0020] The interface processing module, data verification module and delayed ping-pong asynchronous reconstruction module are realized by using FPGA chip.
[0021] The central control machine sends N data to the interface processing module every T1 time, the sending interval of the physical layer modulation module is T2 (T2>T1), and the actual data volume that the channel can accommodate each time is M data;
[0022] If floor(T2 / T1) is not an integer, the physical layer modulation module actually sends a data packet at each time at floor(T2 / T1) or floor(T2 / T1)+1, and M>N*(floor(T2 / T1)+1).
[0023] The delayed ping-pong control module needs to wait until the first data cache unit or the second data cache unit stores a complete data packet before executing the ping-pong switch.
[0024] The data reconstruction and reading module fills the data moved from the first data cache unit and the second data cache unit, so that the amount of data stored in the terminal fan-out cache unit is M data.
[0025] When the first asynchronous timing interrupt arrives, the data reconstruction and reading module moves the data in the first data cache unit. When the second asynchronous timing interrupt arrives, the data reconstruction and reading module moves the data in the second data cache unit. When the third asynchronous timing interrupt arrives, the data reconstruction and reading module moves the data in the first data cache unit again, and so on.
[0026] The periods of the asynchronous timing interrupt and the asynchronous reading interrupt are both T2.
[0027] The present invention has extremely high versatility and is applicable to various application scenarios such as trigger-type and response-type, as well as variable-length or fixed-length application scenarios. When the almost negligible excess resource consumption is not considered, the entire architecture does not need any modification and can be directly applied. Therefore, the present invention has the possibility of truly achieving tape-out. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 The present invention provides a block diagram of a variable-length interface data transmission structure based on FPGA.
[0029] Figure 2 This is the structural block diagram of the delayed ping-pong asynchronous reconstruction module.
[0030] Figure 3 Reconstruct the state machine jump diagram for delayed ping-pong asynchronous.
[0031] Figure 4 This is a schematic diagram of a two-level interrupt. DETAILED DESCRIPTION
[0032] The following is based on Figures 1 to 4 , specifically describe the preferred embodiments of the present invention.
[0033] like Figure 1As shown, to ensure accurate data transmission in sequence, an FPGA-based variable-length interface data transmission structure is provided, comprising an interface processing module 1, a data verification module 2, and a delay ping-pong asynchronous reconstruction module 3. Central control unit 0 sends data to the FPGA via the interface according to the agreed protocol. The FPGA receives the data through interface processing module 1. After successful verification by interface data verification module 2, the interface data is sent to delay ping-pong asynchronous reconstruction module 3 for data processing. The data is then sent to physical layer modulation module 4 for subsequent operations. The data is then sent to ADC module 5, where the modulated signal is transmitted into free space via the power amplifier and antenna.
[0034] For ease of explanation, assume that central control machine 0 sends N data packets to the FPGA every T1, that physical layer modulation module 4 transmits data at an interval of T2 (T2 > T1), and that the channel can accommodate M data packets at a time. If floor(T2 / T1) is not an integer, physical layer modulation module 4 actually sends data packets at a time of floor(T2 / T1) or floor(T2 / T1)+1, satisfying the condition M > N*(floor(T2 / T1)+1).
[0035] like Figure 2 As shown, the delayed ping-pong asynchronous reconstruction module 3 includes:
[0036] A first data cache unit 301, whose input end is connected to the output end of the interface data verification module 2, is used for time-sharing storage of the interface data received within time T2;
[0037] A second data cache unit 302, whose input end is connected to the output end of the interface data verification module 2, is used for time-sharing storage of the interface data received within time T2;
[0038] A first asynchronous reset module 303, whose output end is connected to the first data cache unit 301, is used to perform a fast reset after the data in the first data cache unit 301 is moved to the terminal fan-out cache unit 308, so as to avoid residual data in the storage area causing ghosting, resulting in outliers in subsequent data;
[0039] A second asynchronous reset module 304, whose output end is connected to the second data cache unit 302, is used to perform a fast reset after the data in the second data cache unit 302 is moved to the terminal fan-out cache unit 308, so as to avoid residual data in the storage area causing ghosting, resulting in outliers in subsequent data;
[0040] The delayed ping-pong control module 305 has its output terminals connected to the first data cache unit 301 and the second data cache unit 302, respectively, and is used to control the ping-pong switching between the first data cache unit 301 and the second data cache unit 302. In particular, the module addresses a problem: when data is currently being stored during the switching, assuming that the current data is being written to the first data cache unit, before executing the ping-pong switching, the module must first wait for the current packet data to be completely stored in the first data cache unit before storing subsequent data in the second data cache unit. This prevents a packet data from being split in two, resulting in errors in the physical layer data of the two packets.
[0041] A data reconstruction and reading module 306 has an input end connected to an output end of the first data cache unit 301 and an output end of the second data cache unit 302, and is used to promptly move data from the first data cache unit 301 and the second data cache unit 302 when an asynchronous timing interrupt is generated. The data moved from the first data cache unit 301 and the second data cache unit 302 by the data reconstruction and reading module 306 needs to be padded so that the amount of data stored in the terminal fan-out cache unit 308 is M data. This saves an asynchronous reset module, that is, the terminal fan-out cache unit 308 does not need to be reset, and only the data reading function is retained.
[0042] The asynchronous timing interruption generating module 307 has an output terminal connected to the data reconstruction reading module 306 for generating an asynchronous timing interruption T2 (e.g. Figure 4 As shown in FIG5 , when the asynchronous timing interrupt arrives, the data reconstruction and reading module 306 moves data from the first data cache unit 301 and the second data cache unit 302 in sequence. That is, when the first T2 arrives, the data in the first data cache unit 301 is moved. When the second T2 arrives, the data in the second data cache unit 302 is moved. When the third T2 arrives, the data in 301 is moved again, and so on.
[0043] A terminal fan-out buffer unit 308, whose input end is connected to the output end of the data reconstruction reading module 306, is used to provide data to the physical layer modulation module 4 in a timely manner when an asynchronous reading interrupt is generated;
[0044] The asynchronous read interruption generating module 309 has an output end connected to the terminal fan-out buffer unit 308 and an input end connected to the physical layer modulation module 4, and is used to generate an asynchronous read interruption T2 (such as Figure 4 As shown), when the asynchronous read interrupt arrives, the physical layer modulation module 4 takes data from the terminal fan-out buffer unit 308 for framing, and promptly reads data from the terminal fan-out buffer module for the physical layer modulation module 4 to call.
[0045] The delay ping-pong asynchronous reconstruction module 3 is universal, robust, and has the possibility of being tape-out.
[0046] like Figure 3 As shown, the interface processing module 1 sends the verified correct data into the delayed ping-pong asynchronous reconstruction module 3 in packets, first executes the default order, and writes all the data in sequence into the first data cache unit 301. When the asynchronous timing interrupt arrives, it first makes a judgment to see whether the last packet of data is being stored in the first data cache unit 301. If so, it waits for all the current data to be written into the first data cache unit 301. After the writing is completed, the data reconstruction reading module 306 starts working, reads out the data of the first data cache unit 301 in sequence, fills it with M data, and then stores it into the terminal fan-out cache unit 308. After the access is completed, the first data cache unit 301 is asynchronously reset to prevent the current data from affecting the next cache, and to prevent the data from being half-new and half-old. Next, all interface data is sequentially written to the second data cache unit 302. When an asynchronous timing interrupt occurs, a check is performed to determine whether the last packet of data is being stored in the second data cache unit 302. If so, the module waits for all current data to be written to the second data cache unit 302. Once writing is complete, the data reconstruction and reading module 306 begins to read the data from the second data cache unit 302 sequentially, filling it with M data, and then storing it in the terminal fan-out cache unit 308. After the access is complete, the second data cache unit 302 is asynchronously reset to prevent the current data from affecting the next buffer, thereby preventing data from being half-new and half-old. This process then repeats. When an asynchronous read interrupt occurs, the physical layer modulation module 4 retrieves data from the terminal fan-out cache unit 308 for framing. It is important to note that the writing and reading clock domains of the terminal fan-out cache unit 308 must be consistent. This has the advantage that even in the unlikely event that the writing and reading of the terminal fan-out cache unit 308 occur synchronously, the data will be read normally without any corruption.
[0047] Depend on Figure 3 It can be seen that the asynchronous timing interrupt is used to store data in the terminal fan-out buffer module in a timely manner, and the asynchronous read interrupt is used to read data from the terminal fan-out buffer module in a timely manner for the physical layer modulation module to call. Figure 4 As shown, the asynchronous timing interrupt and asynchronous read interrupt both have a time interval of T2, and there are no restrictions. Although the asynchronous timing interrupt and asynchronous read interrupt are generated at different times, their generation rhythm is consistent, and the two interrupts have the same interval, so the two asynchronous operations do not interfere with each other. This ensures that the internal storage ping-pong switching cycle and the external read cycle are consistent. Whenever the external device is ready to read (corresponding to the arrival of the asynchronous read interrupt), the internal data to be read is already ready (the starting point of this preparation corresponds to the generation of the asynchronous timing interrupt).
[0048] At this point, the entire processing flow ends.
[0049] The present invention provides a universal variable-length interface data transmission architecture based on FPGA, especially the delayed ping-pong asynchronous reconstruction module, which has clear components, stable timing, and minimal resource occupation. Even for fixed-length interface transmission, the architecture can remain unchanged. It is applicable to different communication scenarios such as trigger-type and response-type. Therefore, it has strong versatility and good robustness. When the three cache units (first data cache unit, second data cache unit, terminal fan-out cache unit) are set to be large, it can ensure the adaptation of arbitrary parameters. The architecture can be embedded between the FPGA engineering interface processing and the physical layer transmission. Without considering the negligible excess resource consumption, the architecture can be directly applied to separate the function, and it can even exist in the form of a chip.
[0050] It should be noted that in the embodiments of the present invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the embodiments. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0051] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A variable-length interface data transmission structure based on FPGA, characterized in that: Contains interface processing module, data verification module and delayed ping-pong asynchronous reconstruction module; The interface processing module is used to receive data from the central control machine; The data verification module is used to verify the data received by the interface processing module and then send it to the delayed ping-pong asynchronous reconstruction module for data processing; The delayed ping-pong asynchronous reconstruction module sends the processed data to the physical layer modulation module; The delayed ping-pong asynchronous reconstruction module includes: a first data cache unit, whose input end is connected to the output end of the interface data verification module and is used for storing the received interface data in a time-sharing manner; a second data cache unit, whose input end is connected to the output end of the interface data verification module and is used for storing the received interface data in a time-sharing manner; a first asynchronous reset module, whose output end is connected to the first data cache unit, and is used to perform a fast reset after the data in the first data cache unit is moved to the terminal fan-out cache unit; a second asynchronous reset module, whose output end is connected to the second data cache unit, and is used to perform a fast reset after the data in the second data cache unit is moved to the terminal fan-out cache unit; a delayed ping-pong control module, whose output ends are respectively connected to the first data cache unit and the second data cache unit, and is used to control the ping-pong switching between the first data cache unit and the second data cache unit; a data reconstruction reading module, whose input end is connected to the output end of the first data cache unit and the output end of the second data cache unit, and is used to promptly move data from the first data cache unit and the second data cache unit when an asynchronous timing interrupt is generated; an asynchronous timing interruption generating module, the output end of which is connected to the data reconstruction and reading module, for generating an asynchronous timing interruption; a terminal fan-out buffer unit, whose input end is connected to the output end of the data reconstruction and reading module, and is used to provide data to the physical layer modulation module in a timely manner when an asynchronous read interrupt is generated; An asynchronous read interruption generating module, whose output end is connected to the terminal fan-out buffer unit and whose input end is connected to the physical layer modulation module, is used for generating an asynchronous read interruption.
2. The variable-length interface data transmission structure based on FPGA according to claim 1, characterized in that: The interface processing module, data verification module and delayed ping-pong asynchronous reconstruction module are realized by using FPGA chip.
3. The variable-length interface data transmission structure based on FPGA according to claim 2, characterized in that: The central control machine sends N data to the interface processing module every T1 time, the sending interval of the physical layer modulation module is T2 (T2>T1), and the actual data volume that the channel can accommodate each time is M data; If floor(T2 / T1) is not an integer, the physical layer modulation module actually sends a data packet at each time at floor(T2 / T1) or floor(T2 / T1)+1, and M>N*(floor(T2 / T1)+1).
4. The variable-length interface data transmission structure based on FPGA according to claim 3, characterized in that: The delayed ping-pong control module needs to wait until the first data cache unit or the second data cache unit stores a complete data packet before executing the ping-pong switch.
5. The variable-length interface data transmission structure based on FPGA according to claim 4, characterized in that: The data reconstruction and reading module fills the data moved from the first data cache unit and the second data cache unit, so that the amount of data stored in the terminal fan-out cache unit is M data.
6. The variable-length interface data transmission structure based on FPGA according to claim 5, characterized in that: When the first asynchronous timing interrupt arrives, the data reconstruction and reading module moves the data in the first data cache unit. When the second asynchronous timing interrupt arrives, the data reconstruction and reading module moves the data in the second data cache unit. When the third asynchronous timing interrupt arrives, the data reconstruction and reading module moves the data in the first data cache unit again, and so on.
7. The variable-length interface data transmission structure based on FPGA according to claim 6, characterized in that: The periods of the asynchronous timing interrupt and the asynchronous reading interrupt are both T2.
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