Low-voltage high-power anti-reverse pressure and overvoltage surge circuit

Abstract

The application discloses a low-voltage high-power anti-reverse pressure and overvoltage surge circuit, which simultaneously realizes the functions of low-voltage high-power anti-reverse pressure and overvoltage surge, when a MOSFET is closed, a body diode blocks reverse current, when the MOSFET is opened in a forward conduction process, forward voltage drop and power loss are significantly reduced. An ideal diode controller senses the reverse current through the MOSFET and quickly closes it, so that the body diode blocks the reverse current. When the input voltage is normal, the MOS tube is opened, and normal voltage is output; when there is a surge in the input voltage, a feedback voltage control circuit controls the MOS tube drive, so that the MOS tube is in a linear working state, and the surge voltage is suppressed. High-voltage and low-energy peaks are absorbed by a capacitor and a transient suppressor connected in parallel at the input end. The rest of the circuit is used for processing high-energy surges. Compared with traditional overvoltage circuits, the application has the advantages of low cost, high efficiency and small loss.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power electronics of airborne electronic equipment, and particularly relates to a low-voltage and high-power anti-reverse voltage and overvoltage surge circuit. BACKGROUND

[0002] The traditional anti-reverse voltage circuit generally adopts the following two ways: one is to connect a Schottky diode in series in the circuit, and to realize the anti-reverse connection of the circuit by using the single-phase conduction of the diode; under high-power load, the forward conduction loss is large, and a radiator needs to be designed, which increases the design cost and the circuit space; in addition, the reverse leakage current of the high-voltage Schottky diode increases sharply with the increase of the junction temperature, which leads to the increase of power dissipation in the reverse direction. The other is a MOS tube anti-reverse connection protection circuit, and the protection field effect tube is a PMOS field effect tube or an NMOS field effect tube. If it is a PMOS, the gate and the source thereof are connected to the ground end and the power supply end of the protected circuit respectively, and the drain thereof is connected to the substrate of the PMOS element in the protected circuit. If it is an NMOS, the gate and the source thereof are connected to the power supply end and the ground end of the protected circuit respectively, and the drain thereof is connected to the substrate of the NMOS element in the protected circuit; once the polarity of the power supply of the protected circuit is reversed, the protection field effect tube will form an open circuit to prevent the current from burning out the field effect tube element in the circuit and to protect the overall circuit. The drain-source level conduction resistance RDS(on) of the PMOS increases sharply with the decrease of the input voltage, and in a wide input voltage range, the power consumption caused by the increase of RDS(on) will reduce the efficiency. For high-power load, the size and cost of the PMOS tube are also greatly increased. The NMOS is connected in the ground loop, and during the switching of the switch or the switching of the load current, the ground voltage may fluctuate. The above two ways are not conducive to the high efficiency and miniaturization of the anti-reverse connection circuit.

[0003] In addition, overvoltage surge suppression is generally divided into passive surge suppression and active surge suppression. One kind of passive surge suppression is to connect a ZnO voltage-dependent resistor in parallel with the input end of the protected electrical appliance, and the other kind is a transient voltage suppressor (TVS), but the loss of the voltage-dependent resistor is large, and the suppression time of the TVS is short, and for 80V / 50ms continuous surge voltage, it cannot play a good suppression effect. One kind of active surge suppression is a Buck type surge suppression circuit, and the two main circuit devices of the circuit increase in size and cost, and the main load current flows through the field tube and the inductor under normal voltage, which affects the system efficiency under normal state. The other is a double-transistor control type surge suppression circuit, and the circuit structure is simple, but the on-resistance of the P-channel MOS tube is large, and under high-power occasions, the on-state loss of the switching device is large, which affects the efficiency under normal state.

[0004] Therefore, it is necessary to provide a circuit which can realize the functions of low-voltage and high-power anti-reverse voltage and overvoltage surge at the same time. SUMMARY

[0005] To solve the above problems, the purpose of the present application is to provide a low-voltage high-power anti-reverse pressure and overvoltage surge circuit, which realizes the functions of low-voltage high-power anti-reverse pressure and overvoltage surge.

[0006] To achieve the above purpose, the present application provides the following technical solutions, a low-voltage high-power anti-reverse pressure and overvoltage surge circuit, the circuit includes anti-reverse connection control loop, detection and charging circuit and feedback circuit,

[0007] The anti-reverse connection control loop is used for voltage anti-reverse connection; the detection and charging circuit and the feedback circuit form an overvoltage surge sub-circuit;

[0008] The anti-reverse connection control loop includes a first MOS tube Q1 for reverse polarity protection and reverse current blocking, a first triode Q3 for clamping MOS tube gate-source voltage during reverse connection, and a second resistor R2 for forming a first triode Q3 conduction current.

[0009] The low-voltage high-power anti-reverse pressure and overvoltage surge circuit provided by the present application also has the following characteristics, the anti-reverse connection control loop includes a first MOS tube Q1, a first diode D1, a first triode Q3, a second resistor R2, a first resistor R1 and a fourth resistor R4,

[0010] The S end of the first MOS tube Q1, the positive end of the first diode D1, and the E end of the first triode Q3 are connected with the DC input positive end; the negative end of the first diode D1 and the B end of the first triode Q3 are connected with one end of the second resistor R2; the other end of the second resistor R2 is connected with the DC bus negative end; the C end of the first triode Q3 is connected with one end of the first resistor R1 and the negative end of the second diode D2; the other end of the first resistor R1 is connected with the G end of the first MOS tube Q1; the positive end of the second diode D2 is connected with one end of the fourth resistor R4 to form an anti-reverse connection control loop.

[0011] The low-voltage high-power anti-reverse pressure and overvoltage surge circuit provided by the present application also has the following characteristics, the detection and charging circuit includes a second MOS tube Q2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a second voltage stabilizing tube D6, a first voltage stabilizing tube D3, a third diode D4, a fourth diode D5,

[0012] The D end of the second MOS Q2 is connected with the D end of the first MOS Q1, the G end of the second MOS Q2 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5, the other end of the fourth resistor R4, one end of the third resistor R3, one end of the first capacitor C1, the negative end of the first voltage stabilizer D3, the negative end of the second voltage stabilizer D6 and the negative end of the fourth diode D5 are connected, the other end of the third resistor R3 is connected with the C end of the second triode Q4, the E end of the second triode Q4, the other end of the first capacitor C1, the positive end of the second voltage stabilizer D6, one end of the ninth resistor R9, the direct current input negative end and the direct current output negative end are connected, the S end of the second MOS Q2, the positive end of the first voltage stabilizer D3, the positive end of the third diode D4, one end of the eighth resistor R8 and the direct current output positive end are connected, the negative end of the third diode D4 and one end of the second capacitor C2 and the positive end of the fourth diode D5 are connected, the other end of the second capacitor C2 is connected with one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected with the square wave output device U1.

[0013] The low-voltage high-power anti-reverse pressure and overvoltage surge circuit provided by the application also has the characteristics that the feedback loop comprises an eighth resistor R8 / R9 / R6, a comparator U2, a second triode Q4 and a voltage stabilizing source V1,

[0014] The positive end of the comparator U2 is connected with the other end of the eighth resistor R8 and one end of the ninth resistor R9, the negative end of the comparator U2 is connected with the positive end of the voltage stabilizing source V1, the negative end of the voltage stabilizing source V1 is connected with the direct current output negative end, one end of the sixth resistor R6 is connected with the output end of the comparator U2, and the other end of the sixth resistor R6 is connected with the B end of the second triode Q4.

[0015] Beneficial effects

[0016] When the MOSFET is closed, the body diode blocks the reverse current. When the MOSFET is opened during the forward conduction process, the forward voltage drop and power loss are significantly reduced. The ideal diode controller senses the reverse current through the MOSFET and quickly closes it, so that the body diode blocks the reverse current. In this way, the reverse polarity and reverse current blocking functions can be realized at the same time, and the circuit has the characteristics of high power consumption, good heat dissipation performance and the like. When the input voltage is normal, the MOS tube is opened, and the output normal voltage is obtained. When the input voltage exists surge, the feedback voltage control circuit controls the MOS tube drive, so that it is in a linear working state, and the surge voltage is suppressed. The high-voltage, low-energy peak is absorbed by the capacitor and transient suppressor connected across the input end. The remaining circuit is used to process high-energy surges. Compared with traditional overvoltage circuits, the circuit has the advantages of low cost, high efficiency and small loss.

[0017] The low-voltage high-power anti-reverse pressure and overvoltage surge circuit provided by the application is advanced in principle, reliable, can realize anti-reverse connection of power supply and overvoltage surge resistance function, can work in a high-power environment, has small loss, small space size and high integration compared with a traditional circuit, and is built by general discrete components, and the number of components is not large and no special requirements are needed. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0019] Figure 1 The circuit principle block diagram provided by the embodiment of the present application is provided.

[0020] Figure 2 The working flow block diagram of the circuit provided by the embodiment of the present application is provided.

[0021] Figure 3 The working principle diagram of the circuit provided by the embodiment of the present application when anti-reverse connection is performed is provided.

[0022] Figure 4 The working principle diagram of the circuit provided by the embodiment of the present application when overvoltage surge resistance is performed is provided. DETAILED DESCRIPTION

[0023] The present application will be further described in detail below in combination with the drawings and embodiments. It should be noted that these embodiments are not a limitation on the present application, and equivalent transformations or substitutions of function, method or structure made by those skilled in the art based on these embodiments are within the protection scope of the present application.

[0024] In the description of the embodiments of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application.

[0025] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0026] The terms "mounting", "connection", "connection" should be broadly understood, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood by specific circumstances.

[0027] As shown in Figures 1-4 The present application provides a low-voltage high-power anti-reverse pressure and overvoltage surge circuit, which comprises an anti-reverse connection control circuit, a detection and charging circuit and a feedback circuit,

[0028] The anti-reverse connection control circuit is used for voltage anti-reverse connection; the detection and charging circuit and the feedback circuit form an overvoltage surge sub-circuit;

[0029] The anti-reverse connection control circuit comprises a first MOS tube Q1 for reverse polarity protection and reverse current blocking, a first triode Q3 for MOS tube gate-source voltage clamping during reverse connection, and a second resistor R2 for forming the conduction current of the first triode Q3.

[0030] In some embodiments, the anti-reverse connection control circuit comprises a first MOS tube Q1, a first diode D1, a first triode Q3, a second resistor R2, a first resistor R1 and a fourth resistor R4,

[0031] The S end of the first MOS tube Q1, the positive end of the first diode D1 and the E end of the first triode Q3 are connected with the DC input positive end; the negative end of the first diode D1 and the B end of the first triode Q3 are connected with one end of the second resistor R2; the other end of the second resistor R2 is connected with the DC bus negative end; the C end of the first triode Q3 is connected with one end of the first resistor R1 and the negative end of the second diode D2; the other end of the first resistor R1 is connected with the G end of the first MOS tube Q1; one end of the fourth resistor R4 is connected with the positive end of the second diode D2 to form the anti-reverse connection control circuit.

[0032] In some embodiments, the detection and charging circuit includes a second MOS tube Q2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a second voltage stabilizing tube D6, a first voltage stabilizing tube D3, a third diode D4, a fourth diode D5,

[0033] The D end of the second MOS tube Q2 is connected to the D end of the first MOS tube Q1, the G end of the second MOS tube Q2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5, the other end of the fourth resistor R4, one end of the third resistor R3, one end of the first capacitor C1, the negative end of the first voltage stabilizing tube D3, the negative end of the second voltage stabilizing tube D6, and the negative end of the fourth diode D5 are connected, the other end of the third resistor R3 is connected to the C end of the second triode Q4, the E end of the second triode Q4, the other end of the first capacitor C1, the positive end of the second voltage stabilizing tube D6, one end of the ninth resistor R9, the direct current input negative end, and the direct current output negative end are connected, the S end of the second MOS tube Q2, the positive end of the first voltage stabilizing tube D3, the positive end of the third diode D4, one end of the eighth resistor R8, and the direct current output positive end are connected, the negative end of the third diode D4 and one end of the second capacitor C2 and the positive end of the fourth diode D5 are connected, the other end of the second capacitor C2 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the square wave output device U1.

[0034] In some embodiments, the feedback circuit includes an eighth resistor R8 / R9 / R6, a comparator U2, a second triode Q4, and a voltage stabilizing source V1.

[0035] The positive end of the comparator U2 is connected to the other end of the eighth resistor R8 and one end of the ninth resistor R9, the negative end of the comparator U2 is connected to the positive end of the voltage stabilizing source V1, the negative end of the voltage stabilizing source V1 is connected to the direct current output negative end, the output end of the comparator U2 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the B end of the second triode Q4.

[0036] As shown in Figures 2-4 , the working principle of the circuit provided in the foregoing embodiments is as follows:

[0037] As shown in Figure 3 , when the reverse voltage is input, the current is input from the direct current bus negative end, flows through the second resistor R2, the BE end PN junction of the first triode Q3, and then returns to the direct current bus positive end. The first triode Q3 is turned on, the first triode Q3 collector voltage is pulled down to approximately the direct current bus positive end potential, and the gate-source voltage (Ugs) of the first MOS tube Q1 is the transistor turn-on voltage. Therefore, the gate-source voltage (Ugs) of the first MOS tube Q1 is clamped at about 0.3V, and the first MOS tube Q1 is turned off. As shown in Figure 3As shown, the anode of the body diode of the first MOS Q1 corresponds to the positive end of the DC bus, when a reverse voltage is applied, the first MOS Q1 cuts off the transmission path of the current from the negative end of the DC bus through the load and returns to the positive end of the DC bus, finally makes the output voltage keep 0, has the function of preventing reverse voltage.

[0038] Figure 4 As shown, when the input voltage is normal, the square wave generator generates a high-frequency square wave, which charges the first capacitor C1 through the seventh resistor R7, the second capacitor C2 and the fourth diode D5, and the second zener diode D6 limits the maximum voltage of the charging. Since the first capacitor C1 has no discharge path, the voltage continues to accumulate, and the voltage of the first capacitor C1 supplies power to the gate (G) of the first MOS Q1 and Q2, until the first MOS Q1 and Q2 are turned on, and a DC power supply path is established. After voltage division by R8 and R9, feedback is fed back to the operational amplifier, and the design value of the voltage stabilizing source of the operational amplifier is V1. When the voltage division is V1, the output voltage of the operational amplifier is 0V, and the transistor Q4 is turned off. When the square wave generator outputs a low level, the DC bus charges the second capacitor C2 through the third diode D4 until the bus voltage is reached. When the square wave generator outputs a high level, the second capacitor C2 charges the first capacitor C1 together through the fourth diode D5, raising the voltage across the first capacitor C1, realizing capacitor bootstrap, and after the voltage build-up is completed, the voltage on the first capacitor C1 is stable, and D4 and D5 are in the off state. At this time, the first MOS Q1 and Q2 are always on, and the circuit enters a stable working state.

[0039] When an overvoltage surge occurs, the voltage division of the eighth resistor R8 and the ninth resistor R9 is input to the inverting input terminal of the operational amplifier U2 as feedback, and the difference between the given voltage V1 is subjected to PI operation. When the overvoltage continues to occur, the output voltage of the operational amplifier is a certain value, the transistor Q4 is turned on, and is in the amplification zone. The voltage across the first capacitor C1 begins to decrease, and the gate-source voltage of the first MOS Q1 and Q2 continuously decreases until it enters the linear region, and the output voltage is clamped within a certain range.

[0040] When the overvoltage surge disappears, the feedback voltage begins to decrease, and when the feedback voltage is lower than the given voltage V1, the output of the operational amplifier continuously decreases until the voltage at the first MOS Q1 and Q2 begins to decrease, and then returns to the fully on state, and the circuit normally outputs.

[0041] The above only describes the preferred embodiments of the present application, and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. The above only describes the preferred embodiments of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should be regarded as the protection scope of the present application.

Claims

1. A low-voltage, high-power reverse voltage protection and overvoltage surge withstand circuit, characterized in that, The circuit includes a reverse connection protection control circuit, a detection and charging circuit, and a feedback circuit. The reverse connection protection control circuit is used for voltage reverse connection protection; the detection and charging circuit and the feedback circuit form an overvoltage surge withstand sub-circuit. The reverse connection protection control circuit includes a first MOSFET Q1 for reverse polarity protection and reverse current blocking, a first transistor Q3 for clamping the gate-source voltage of the MOSFET during reverse connection, and a second resistor R2 for forming the on-state current of the first transistor Q3. The reverse connection protection control circuit includes a first MOSFET Q1, a first diode D1, a first transistor Q3, a second resistor R2, a first resistor R1, and a second diode D2. The source (S) terminal of the first MOSFET Q1, the positive terminal of the first diode D1, and the emitter (E) terminal of the first transistor Q3 are connected to the positive terminal of the DC input. The negative terminal of the first diode D1 and the base (B) terminal of the first transistor Q3 are connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the negative terminal of the DC bus. The collector (C) terminal of the first transistor Q3 is connected to one end of the first resistor R1 and the negative terminal of the second diode D2. The other end of the first resistor R1 is connected to the gate (G) terminal of the first MOSFET Q1. The positive terminal of the second diode D2 is connected to one end of the fourth resistor R4 to form a reverse connection protection control circuit. The detection and charging circuit includes a second MOSFET Q2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a second Zener diode D6, a first Zener diode D3, a third diode D4, and a fourth diode D5. The drain (D) terminal of the second MOSFET Q2 is connected to the drain (D) terminal of the first MOSFET Q1. The gate (G) terminal of the second MOSFET Q2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5, the other end of the fourth resistor R4, one end of the third resistor R3, one end of the first capacitor C1, the negative terminal of the first Zener diode D3, the negative terminal of the second Zener diode D6, and the negative terminal of the fourth diode D5 are connected. The other end of the third resistor R3 is connected to the collector (C) terminal of the second transistor Q4. The emitter (E) terminal of the second transistor Q4 and the other end of the first capacitor C1 are also connected to the second MOSFET Q4. The positive terminal of the second Zener diode D6, one end of the ninth resistor R9, the negative terminal of the DC input, and the negative terminal of the DC output are connected. The source terminal of the second MOSFET Q2, the positive terminal of the first Zener diode D3, the positive terminal of the third diode D4, one end of the eighth resistor R8, and the positive terminal of the DC output are connected. The negative terminal of the third diode D4 is connected to one end of the second capacitor C2 and the positive terminal of the fourth diode D5. The other end of the second capacitor C2 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the square wave output unit U1. The feedback loop includes an eighth resistor R8, a ninth resistor R9, a sixth resistor R6, a comparator U2, a second transistor Q4, and a voltage regulator V1. The positive terminal of comparator U2 is connected to the other end of the eighth resistor R8 and the other end of the ninth resistor R9. The negative terminal of comparator U2 is connected to the positive terminal of the voltage regulator V1. The negative terminal of the voltage regulator V1 is connected to the negative terminal of the DC output. The output terminal of comparator U2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the B terminal of the second transistor Q4.

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