In-memory associative processing for vectors

Abstract

This application is directed to in-memory associative processing for vectors. An apparatus can perform a compute operation on a first contiguous bit set of a first vector and a first contiguous bit set of a second vector. The first contiguous bit set can be stored in a first plane of a memory die, and the compute operation can be based on a truth table for the compute operation. The apparatus can perform a second compute operation on a second contiguous bit set of the first vector and a second contiguous bit set of the second vector. The second contiguous bit set can be stored in a second plane of the memory die and the compute operation is based on the truth table for the compute operation.

Description

[0001] CROSS-REFERENCE

[0002] The present application claims priority to U.S. Patent Application No. 17 / 647,944, titled “IN-MEMORY ASSOCIATIVE PROCESSING FOR VECTORS,” filed January 13, 2022, for EILERT et al., and U.S. Provisional Patent Application No. 63 / 239,112, titled “IN-MEMORY ASSOCIATIVE PROCESSING FOR VECTORS,” filed August 31, 2021, for EILERT et al., each of which is assigned to the assignee hereof and expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The technical field relates to in-memory associative processing for vectors. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communications devices, cameras, digital displays, etc. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, often represented by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a memory die comprising a plurality of tiles, each of the plurality of tiles comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a computational operation on data representing a first contiguous set of bits of a vector, the vector being an operand for the computational operation, the data representing the first contiguous set of bits stored in a first plane of a tile of the plurality of tiles using associative processing; and perform the computational operation on data representing a second contiguous set of bits of the vector based at least in part on performing the computational operation on the data representing the first contiguous set of bits using associative processing, the data representing the second contiguous set of bits stored in a second plane of the tile of the plurality of tiles.

[0007] An apparatus is described. The apparatus can include a memory die comprising a plurality of tiles, each of the plurality of tiles comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a computational operation on data representing a first contiguous set of bits of a vector, the vector being an operand for the computational operation, the data representing the first contiguous set of bits stored in a first plane of a first tile of the plurality of tiles using associative processing; and perform the computational operation on data representing a second contiguous set of bits of the vector based at least in part on performing the computational operation on the first contiguous set of bits using associative processing, the data representing the second contiguous set of bits stored in a first plane of a second tile of the plurality of tiles.

[0008] An apparatus is described. The apparatus can include a memory die comprising a plurality of tiles, each of the plurality of tiles comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a computational operation on data representing a first contiguous set of bits of a vector, the vector being an operand for the computational operation, the data representing the first contiguous set of bits stored in a first plane of a tile of the plurality of tiles using associative processing; and perform the computational operation on data representing a second contiguous set of bits of the vector based at least in part on performing the computational operation on the first contiguous set of bits using associative processing, the data representing the second contiguous set of bits stored in a first plane of a second tile of the plurality of tiles.

[0009] An apparatus is described. The apparatus can include a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to perform a computation operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table that computes results of the computation operation for indications of various combinations of logic values, the data representing the first set of contiguous bits stored in a first plane of a first tile of the plurality of tiles; and perform the computation operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the computation operation, the data representing the second set of contiguous bits stored in a first plane of a second tile of the plurality of tiles.

[0010] A method is described. The method can include performing a computation operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table that computes results of the computation operation for indications of various combinations of logic values, the data representing the first set of contiguous bits stored in a first plane of a first tile of a plurality of tiles; and performing the computation operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the computation operation, the data representing the second set of contiguous bits stored in a first plane of a second tile of the plurality of tiles.

[0011] A method is described. The method can include performing a computation operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table that computes results of the computation operation for indications of various combinations of logic values, the data representing the first set of contiguous bits stored in a first plane of a first tile of a plurality of tiles; and performing the computation operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the computation operation, the data representing the second set of contiguous bits stored in a first plane of a second tile of the plurality of tiles. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 Examples of a system that supports in-memory associative processing for vectors are described in accordance with the examples disclosed herein.

[0013] Figure 2 Examples of vector computation using associative processing are described in accordance with the examples disclosed herein.

[0014] Figure 3 An example of a process flow that supports in-memory associative processing for vectors is illustrated in accordance with examples disclosed herein.

[0015] Figure 4 An example of associative computation using tiles configured according to a vector mapping scheme is illustrated in accordance with examples disclosed herein.

[0016] Figure 5 An example of associative computation using tiles configured according to a vector mapping scheme is illustrated in accordance with examples disclosed herein.

[0017] Figure 6 An example of a process flow that supports in-memory associative processing for vectors is illustrated in accordance with examples disclosed herein.

[0018] Figure 7 A block diagram illustrating an apparatus that supports in-memory associative processing for vectors is shown in accordance with examples disclosed herein.

[0019] Figures 8 to 12 A flow diagram illustrating one or more methods that support in-memory associative processing for vectors is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0020] In some systems, a host device can offload various processing tasks to an electronic device, such as an accelerator. For example, a host device can offload vector computations to an electronic device, which can perform the vector computations using a compute engine and processing techniques. This vector computation offload can involve communicating vectors or vector information from the host device to the electronic device, and then communicating results from the electronic device to the host device. As a result, the bandwidth of the electronic device can be constrained by the communication interface between the electronic device and the host device, as well as the size of the compute engine and serial processing. In accordance with the techniques described herein, a host device can substantially increase processing bandwidth by offloading processing tasks to an associative processor memory (APM) system that performs vector computations in parallel using in-memory associativity processing, among other aspects.

[0021] In some examples, an APM system can support a plurality of different vector mapping schemes, where a vector mapping scheme can refer to an organization scheme for writing vectors to a memory of the APM system. For example, an APM system can support a first vector mapping scheme and a second vector mapping scheme. The APM system can select between the vector mapping schemes (e.g., can select one of the vector mapping schemes), after which vectors are written to a memory of the APM system according to the selected vector mapping scheme. After the vectors are written to the memory, the APM system can perform computation operations on the vectors according to the selected vector mapping scheme using associative processing.

[0022] Features of the disclosure are first described in the context of systems and vector calculations as described with reference to Figure 1 and 2 Features of the disclosure are described in the context of planar, vector mapping schemes and process flows as described with reference to Figures 3-6 Features of the disclosure are further illustrated and described with reference to device diagrams and flow diagrams relating to in-memory associative processing systems as described with reference to Figures 7 to 12

[0023] An example of a system 100 that supports in-memory associative processing for vectors in accordance with examples disclosed herein is illustrated. The system 100 can include a host device 105 and an associative processing memory (APM) system 110. The host device 105 can interact with (e.g., communicate with, control) the APM system 110 and other components of a device that includes the system 100. In some examples, the host device 105 and the APM system 110 can interact through an interface 115, which can be an example of a compute express link (CXL) interface or other type of interface. Figure 1 In some examples, the system 100 can be included in or coupled with a computing device, an electronic device, a mobile computing device, or a wireless device. The device can be a portable electronic device. For example, the device can be a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, etc. The host device 105 can be or include a system on a chip (SoC), a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In some examples, the host device 105 can be referred to as a host, a host system, or other suitable term.

[0024]

[0025] ​The APM system 110 can be used as an accelerator (e.g., a high-speed processor) for the host device 105 such that the host device 105 can offload various processing tasks to the APM system 110, which can be configured to perform processing tasks more quickly than the host device 105. For example, the device 105 can send a program (e.g., a set of instructions, such as a Reduced Instruction Set V (RISC-V), vector instructions) to the APM system 110 for execution by the APM system 110. As part of, or directed by, the program, the APM system 110 can perform various computational operations on vectors (e.g., the APM system 110 can perform vector computations). Computational operations can refer to logical operations, arithmetic operations, or other types of operations involving manipulation of vectors. A vector can include one or more elements each having a respective number of bits. The length or size of a vector can refer to the number of elements in the vector and the length or size of an element can refer to the number of bits in the element.

[0026] The APM controller 120 can be configured to interface with the host device 105 on behalf of the APM device 125. Upon receiving a program from the host device 105, the APM controller 120 can parse the program and direct or otherwise prompt the APM device 125 to perform various computational operations associated with or indicated by the program. In some examples, the APM controller 120 can retrieve vectors for the computational operations (e.g., from the memory 130) and can communicate the vectors to the APM device 125 for associated processing. In some examples, the APM controller 120 can indicate vectors for the computational operations to the APM device 125 such that the APM device 125 can retrieve the vectors from the memory 130. In some examples, the host device 105 can provide the vectors to the APM system 110. Accordingly, the memory 130 can be configured to store vectors that can be accessed by the APM controller 120, the APM device 125, the host device 105, or a combination thereof.

[0027] Vectors for computational operations at the APM device 125 can be indicated by (or accompany) a program received from the host device 105 or by other control signaling (e.g., other separate control signaling) associated with the program. For example, a program indicating computational operations for a pair of vectors can include one or more addresses of the memory 130 in which the vectors are stored (or one or more pointers to the one or more addresses). Although shown as included in the APM system 110, the memory 130 can be external to the APM system 110, but still coupled with the APM system 110. Although shown as a single component, the functionality of the memory 130 can be provided by multiple memories 130.

[0028] The APM device 125 can include a memory unit, such as a content addressable memory unit (CAM) configured to store contents of vectors (e.g., vector operands, vector results) associated with computation operations. A vector operand can be a vector, i.e., an operand (e.g., a vector operand can be a vector for which a computation operation is performed) for a computation operation. A vector result can be a vector resulting from a vector computation.

[0029] The APM system 110 can be configured to store information, such as truth tables, for various computation operations, where the information (e.g., truth tables) for a given computation operation can indicate results of the computation operation for various combinations of logic values. For example, the APM system 110 can store information (e.g., one or more truth tables) for logical operations (e.g., AND operations, OR operations, XOR operations, NOT operations, NAND operations, NOR operations, XNOR operations) and arithmetic operations (e.g., addition operations, subtraction operations) and other types of operations. A memory unit storing information (e.g., one or more truth tables) for a computation operation can store various combinations of logic values for operands of the computation operation and corresponding results and carry bits (if applicable) for each combination of logic values. The APM system 110 can store truth tables for associative processing in one or more memories (e.g., in one or more on-die mask ROMs) that can be coupled with or included in the APM system 110. For example, the truth tables can be stored in the memory 130, in a local memory of the APM device 125, or both. In any instance, the APM device 125 can cache common instructions on the device (e.g., rather than fetching the common instructions or receiving the common instructions).

[0030] At least some of the APM devices 125, if not all of the APM devices 125, can perform computation operations on vectors stored in that APM device 125 using associative processing. Unlike serial processing, where vectors are moved back and forth between a processor and a memory, associative processing can involve searching and writing vectors within a memory (also referred to as "in-place"), which can allow for increased parallelism of processing bandwidth. Performing computation operations in-place can also allow the system 100 to avoid bottlenecks at an interface between the host device 105 and the APM system 110, among other advantages, which can reduce latency and power consumption compared to other processing techniques, such as serial processing. Associative processing can also be referred to as associative computation or other suitable terminology.

[0031] In some examples, APM devices 125 that perform computational operations using associative processing can utilize information (e.g., truth tables) to perform computational operations in a bit-wise manner using, for example, a "search and write" technique. For example, if an APM device 125 includes CAM cells that store vector operands for a computational operation, the APM device 125 can search the CAM cells for bits of a vector operand that match an entry of a truth table corresponding to that computational operation, determine a result for the bits based on the matching entry of the truth table, and write the result back to the content addressable memory. The APM device 125 can then proceed to the next significant bits of the vector and perform the computational operation on those bits using associative processing. In some examples, the computational operation for the bits can involve a carry bit that is determined as part of the computational operation on the less significant bits.

[0032] Each APM device 125 can include one or more dies 135, which can also be referred to as memory dies, semiconductor dies, or other suitable terminology. A die 135 can include a plurality of tiles 140, which can in turn each include a plurality of planes 145. In some examples, tiles 140 can be configured such that a single plane 145 per tile can operate or can be activated at the same time (e.g., one plane per tile can perform an associative computation at the same time). However, any number of tiles 140 can be active at the same time (e.g., any number of tiles can perform an associative computation at the same time). Thus, tiles 140 can operate in parallel, which can increase the number of computational operations that can be performed during a time interval, which in turn can increase the bandwidth of APM devices 125 relative to other different technologies. Using multiple APM devices 125 can further increase the bandwidth of APM system 110 relative to other systems than using a single APM device 125. Each APM device 125 can include a local controller or logic that controls the operation of the APM device 125.

[0033] Each plane 145 can include a memory array that includes memory cells, such as CAM cells. The memory cells in the memory array can be arranged in columns and rows and can be non-volatile memory cells or volatile memory cells. A memory array that includes CAM cells can be configured to search the CAM cells by content rather than by address. For example, a memory array that includes CAM cells that store a vector for a computational operation can compare logical values of operand bits of the vector to entries of a truth table associated with the computational operation to determine which results correspond to those logical values.

[0034] As mentioned, the APM device 125 can be configured to store vectors associated with compute operations in memory units of that APM device 125. To assist with associated processing, vectors can be stored in a columnar fashion across multiple planes. For example, given a vector v0 having a plurality of n-bit (e.g., n = 32) elements (denoted as E0through En), the APM device 125 can partition each element into sets of contiguous bits (e.g., four sets of eight contiguous bits). The APM device 125 can store the first set of contiguous bits (e.g., the least significant set of contiguous bits) of each element of the vector v0 in a first plane 145, where each row of the plane 145 stores the first set of contiguous bits of a respective element of the vector v0. Thus, in some examples, a column 150 can store the first eight bits of each element of the vector v0 (e.g., the column 150 can span eight columns). In a similar manner, the APM device 125 can store the next significant set of contiguous bits from each element of the vector v0 in a second plane 145. And so on for the remaining sets of contiguous bits of the vector v0. Thus, the vector v0 can be stored in a columnar fashion across multiple planes. The bits of other vectors vi through vnmay be stored in a similar columnar fashion across the planes 145. N ) of a vector v0, the APM device 125 can partition each element into sets of contiguous bits (e.g., four sets of eight contiguous bits). The APM device 125 can store the first set of contiguous bits (e.g., the least significant set of contiguous bits) of each element of the vector v0 in a first plane 145, where each row of the plane 145 stores the first set of contiguous bits of a respective element of the vector v0. Thus, in some examples, a column 150 can store the first eight bits of each element of the vector v0 (e.g., the column 150 can span eight columns). In a similar manner, the APM device 125 can store the next significant set of contiguous bits from each element of the vector v0 in a second plane 145. And so on for the remaining sets of contiguous bits of the vector v0. Thus, the vector v0 can be stored in a columnar fashion across multiple planes. The bits of other vectors vi through vnmay be stored in a similar columnar fashion across the planes 145.

[0035] Spreading vectors across multiple planes using the columnar storage technique can allow the APM device 125 to store more vectors per plane 145 relative to other techniques, which in turn can allow the APM device 125 to operate on more vector combinations relative to other techniques. For example, consider a 256 row x 256 column plane. Rather than store eight vectors having 32-bit elements across a single plane, which can limit the APM device 125 to operate on those eight vectors (without time-consuming vector movement), the APM device 125 can store 32 vectors having 32-bit elements across four planes, which allows the APM device 125 to operate on those 32 bit vectors (e.g., one plane at a time) and without performing time-consuming vector movement.

[0036] In some examples, the APM device 125 can store vectors according to a vector mapping scheme, which can be one of a plurality of vector mapping schemes supported by the APM device 125. A vector mapping scheme can refer to a scheme for mapping (and writing) vectors to the planes 145 of the APM device 125. For example, the APM device 125 can support a first vector mapping scheme, referred to as vector mapping scheme 1, and a second vector mapping scheme, referred to as vector mapping scheme 2. In vector mapping scheme 1, vectors can be spread across planes of the same tile 140. In vector mapping scheme 2, vectors can be spread across planes of different tiles 140. Vector mapping schemes can also be referred to as storage schemes, layout schemes, or other suitable terminology.

[0037] The APM system 110 can select between vector mapping schemes, after which the vector is written to the APM device 125 according to the selected vector mapping scheme. For example, the APM system 110 can select a vector mapping scheme for a set of compute operations based on a size of a vector associated with the set of compute operations, a type of compute operation (e.g., arithmetic versus logic) in the set of compute operations, a number of compute operations in the set, or a combination thereof, among other aspects. In some instances, the APM system 110 can select a vector mapping scheme in response to an indication of a vector mapping scheme provided by the host device 105. For example, the host device 105 can indicate a vector mapping scheme associated with an instruction set for the set of compute operations. After the vector mapping scheme has been selected, the APM device 125 can perform compute operations on the vector according to the selected vector mapping scheme using associative processing. Alternatively, a compiler or pre-processor can determine the vector mapping scheme.

[0038] The associative processing of the techniques described herein can be implemented by logic at the APM system 110, logic at the APM device 125, or logic distributed between the APM system 110 and the APM device 125. The logic can include one or more controllers, access circuitry, communication circuitry, or a combination thereof, among other components and circuitry. The logic can be configured to perform aspects of the techniques described herein, cause components of the APM system 110 and / or the APM device 125 to perform aspects of the techniques described herein, or both.

[0039] Figure 2 An example of a vector computation 200 that supports in-memory associative processing according to examples disclosed herein is illustrated. The vector computation 200 can be an example of vector addition and can be performed on operand vectors vA and vB, which can be stored in memory cells (e.g., CAM cells) of a plane of an APM device. The result of the vector addition can be a vector vD. Each operand vector can include four bits (e.g., the operand vectors can include a single 4-bit element), and the position of each bit can be denoted as i. The operand vectors can be as referenced with respect to FIG. 1. Figure 1 The vector computation 200 discussed is stored in a plane of an APM device and can be associated with a set of vector instructions (e.g., RISC-V vector instructions). The vector computation 200 can be performed using a truth table 205, which can be a truth table for adding two bits and a potential carry bit. The truth table 205 can be stored in a memory coupled with or included in the APM device, and entries (e.g., rows) of the truth table 205 can be compared to operand bits of the vectors vA and vB using CAM techniques.

[0040] The examples provided using associative processing for compute operations on vectors are for illustrative purposes only and are not limiting in any way.

[0041] To perform addition of vector vA and vector vB, the APM device can retrieve (e.g., using a sequencer) entries of truth table 205 from memory and compare the entries to operand bits of vectors vA and vB (e.g., in place using CAM technology). Upon finding a match, the APM device can immediately write the corresponding result (e.g., vDi and carry bit ci) of the matching entry to a plane (or a different plane) storing the vectors, after which it moves to the next significant operand bit of the vectors. i+1 ) of the matching entry to a plane (or a different plane) storing the vectors, after which it moves to the next significant operand bit of the vectors.

[0042] For i = 0, for example, the APM device can compare entries of truth table 205 to corresponding operand bits from vectors vA and vB (e.g., c0 = 0, vA0 = 1, and vB0 = 0). Upon detecting a match between the operand bits and an entry of truth table 205, the APM device can immediately write the result (e.g., vD0 = 0 and carry bit ci = 1) corresponding to the matching entry to a plane storing the operand vectors (or the device can compare entries from truth table 205 to operand bits in a serial fashion for i = 0 (e.g., starting from the top entry and moving down one entry at a time in truth table 205)). In some examples, the APM device can compare entries from truth table 205 to multiple operand bits in parallel (e.g., simultaneously).

[0043] Upon determining the result of the ith operand bit, the APM device can proceed to the next significant operand bit (which can include the carry-in bit i+1 carry bit determined from the ith operand bit). For example, upon determining the result of the i = 0 operand bit, the APM device can proceed to the i = 1 operand bit (which can include the carry-in bit ci determined from the i = 0 operand bit). In some contexts, however (e.g., when the computational operation is a logical operation), the APM device can perform the computational operation on some or all of the operand bits in parallel.

[0044] For i = 1, the APM device can compare entries of truth table 205 to corresponding operand bits from vectors vA and vB (e.g., ci = 1, vAi = 0, and vBi = 0). Upon detecting a match between the operand bits and an entry of truth table 205, the APM device can immediately write the result (e.g., vDi = 1 and carry bit ci = 0) corresponding to the matching entry to a plane (or a different plane) storing the operand vectors. The APM device can compare entries from truth table 205 to operand bits in a serial fashion for i = 1 (e.g., starting from the top entry and moving down one entry at a time in truth table 205). Upon determining the result of the i = 1 operand bit, the APM device can proceed to the i = 2 operand bit (which can include the carry-in bit ci determined from the i = 1 operand bit).

[0045] For i=2, the APM device can compare the entry in truth table 205 with the corresponding operand bits from vectors vA and vB (e.g., c2=0, vA2=0, and vB2=0). After detecting a match between the operand bits and the entry in truth table 205, the APM device can immediately write the result corresponding to the matching entry (e.g., vD2=0 and carry c3=0) to the plane storing the operand vectors (or a different plane). The APM device can compare the entry from truth table 205 with the operand bits serially for i=2 (e.g., starting from the top entry and moving down one entry at a time in truth table 205). After determining the result for operand bit i=2, the APM device can continue to operand bit i=3 (which may contain the carry c3 determined from operand bit i=2).

[0046] For i=3, the APM device can compare the entries in truth table 205 with the corresponding operand bits from vectors vA and vB (e.g., c3=0, vA3=0, and vB3=1). After detecting a match between the operand bits and the entries in truth table 205, the APM device can immediately write the result corresponding to the matching entry (e.g., vD3=1 and carry c4=0) to the plane storing the operand vectors (or a different plane). The APM device can compare the entries from truth table 205 with the operand bits serially for i=3 (e.g., starting from the top entry and moving down one entry at a time in truth table 205).

[0047] Therefore, the APM device can use correlation processing to determine that adding vA (e.g., 0b0001) and vB (e.g., 0b1001) results in vD = 0b1010. After completing the addition operation, the APM device can transmit the vector vD to the host device, using the resulting vector vD to perform other computational operations, or combinations thereof.

[0048] An APM device can use associative processing for computational operations on vectors regardless of the vector mapping scheme. However, the propagation of carry bits caused by associative processing can vary between vector mapping schemes. For example, if vector mapping scheme 1 is chosen, then specific carry bits (e.g., those applicable to the second-most-valid sets of adjacent bits) can be propagated between planes of the same tile. If vector mapping scheme 2 is chosen, then specific carry bits (e.g., those applicable to the second-most-valid sets of adjacent bits) can be propagated between different tiles.

[0049] Figure 3 This describes an instance of plane 300 that supports in-memory associative processing of vectors, based on the examples disclosed herein. Plane 300 may be used as a reference. Figure 1An instance of plane 145 is described. Therefore, plane 300 can be configured to store vectors of computational operations performed using associative processing. In some instances, plane 300 may be in the same tile, as discussed in Reference Vector Mapping Scheme 1. In other instances, plane 300 may be in different tiles, as discussed in Reference Vector Mapping Scheme 2.

[0050] In a given instance, n vectors with multiple (e.g., 256) multi-bit elements (e.g., 32-bit elements) are mapped to four planes. However, other numbers of these factors are considered and are within the scope of this disclosure.

[0051] The APM device can handle n vectors (denoted as v0 to v1). n-1 The vector is mapped and written to four planes. The number of planes to which a vector is mapped can be a function of the element length and the number of bits mapped to each plane. For example, the number of planes to which a vector is mapped can be equal to the element length divided by the number of bits mapped to each plane. In a given instance, the number of planes to which a vector is mapped is four, equal to the element length (e.g., 32) divided by the number of bits mapped to each plane (e.g., eight).

[0052] At least some (if not all) planes can store connected bit sets of at least some (if not all) elements from at least some (if not all) vectors. For example, plane 0 can store connected bits 0-7 of each element of each vector; plane 1 can store connected bits 8-15 of each element of each vector; plane 2 can store connected bits 16-23 of each element of each vector; and plane 3 can store connected bits 24-31 of each element of each vector. Bits from different vectors can be stored in different columns of the plane, while bits from different elements can be stored in different rows of the plane. For example, bits from vector 0 can be stored in the first set of eight columns of each plane; bits from vector 1 can be stored in the second set of eight columns of each plane; bits from vector 2 can be stored in the third set of eight columns of each plane; and so on. For each vector, bits from element 0 can be stored in the first row of a given plane; bits from element 1 can be stored in the second row of the plane; bits from element 2 can be stored in the third row of the plane, and so on.

[0053] Thus, a plane having x rows (e.g., 256 rows) can be able to store a vector having x elements or fewer (a vector having a length of 256 or less). If a vector has more than x elements, the elements of the vector can be split across multiple planes (e.g., the elements of a vector having a length of 512 can be stored in two planes, with a first plane storing bits from the first 256 elements and a second plane storing bits from the last 256 elements). Thus, a system using the vector mapping schemes described herein can support vectors having a size greater than other systems (e.g., serial processing systems) that can be constrained by the size of processing circuitry (e.g., compute engines).

[0054] A vector can be stored according to vector mapping scheme 1 or vector mapping scheme 2. In vector mapping scheme 1, the planes to which a vector is mapped can be in the same tile. For example, planes 0 through 3 can be in tile A. In vector mapping scheme 2, the planes to which a vector is mapped can be in different tiles. For example, plane 0 can be in tile A, plane 1 can be in tile B, plane 2 can be in tile C, and plane 3 can be in tile D. Collectively, tiles A through D (e.g., the tiles in which a vector is spread across) can be referred to as a superplane. These two vector mapping schemes can allow an APM device to perform compute operations on multiple vectors in parallel (e.g., during partially or fully overlapping times). For example, given h tiles, an APM device can perform h different compute operations at a time.

[0055] Thus, in vector mapping scheme 1, an APM device can use a single tile to complete compute operations on a vector. For example, an APM device can use tile A to perform compute operations on bits 0-7 of elements in a vector, can use tile A to perform compute operations on bits 8-15 of elements in a vector, can use tile A to perform compute operations on bits 16-23 of elements in a vector, and can use tile A to perform compute operations on bits 24-31 of elements in a vector. If a carry bit is produced by a compute operation, an APM device can transfer the carry bit (denoted as ‘C’) between the planes of tile A. For example, if a carry bit is produced by a compute operation on bits 0-7, an APM device can transfer that carry bit from plane 0 to plane 1 in tile A.

[0056] In vector mapping scheme 2, an APM device can use multiple tiles to complete a compute operation on a vector. For example, an APM device can use tile A to perform a compute operation on bits 0-7 of elements in a vector, can use tile B to perform a compute operation on bits 8-15 of elements in a vector, can use tile C to perform a compute operation on bits 16-23 of elements in a vector, and can use tile D to perform a compute operation on bits 24-31 of elements of a vector. If a carry bit is produced by a compute operation, an APM device can transfer the carry bit between tiles. For example, if a carry bit is produced by a compute operation on bits 0-7, an APM device can transfer that carry bit from tile A to tile B.

[0057] The correlation processing techniques described herein can be implemented by logic at an APM system, logic at an APM device, or logic distributed between an APM system and an APM device. The logic can include one or more controllers, access circuitry, communication circuitry, or combinations thereof, among other components and circuitry. Logic can be configured to perform, cause the components of an APM system and / or an APM device to perform, or both, aspects of the techniques described herein.

[0058] Figure 4 An example of a tile 400 that supports in-memory correlation processing is illustrated in accordance with examples disclosed herein. Tile 400 can include tile A, tile B, and tile C. Each tile can store respective sets of vectors on three planes and the vectors can include n multi-bit (e.g., 24-bit) elements. For example, the three planes of tile A can store one or more vectors V I and other information for a first compute operation, referred to as compute operation I. The three planes of tile B can store one or more vectors V II and other information for a second compute operation, referred to as compute operation II. And the three planes of tile C can store one or more vectors V III and other information for a third compute operation, referred to as compute operation III. While described with reference to different vectors V I , V II , and V III , two or more of the compute operations can involve the same vector (e.g., different compute operations can be performed in parallel on the same vector).

[0059] Between time to and time ti, tile A can perform compute operation I on bits 0-7 of elements of vector V I for compute operation I, where the 0-7 bits of vector V I are stored in the first plane of tile A; tile B can perform compute operation II on bits 8-15 of elements of vector V IIThe elements 0-7 of the vector V are used to perform computation operation II, where vector V is used to perform computation operation II. II Bits 0-7 are stored in the first plane of tile B; and tile C can be used to compute the vector V used for operation III. III The elements 0-7 of the vector V are used to perform computation operation III, where vector V is used to perform computation operation III. III Bits 0-7 are stored in the first plane of tile C. Computational operations can be performed using associative processing as described in this document.

[0060] The result of a computation operation on bits 0-7 can be stored in the same plane as the operands or in a different plane. For example, vector V I The result of the computation operation I on bits 0-7 can be stored (e.g., as a vector) in the first plane of patch A. Similarly, vector V II The result of computation operation II on bits 0-7 can be stored (e.g., as a vector) in the first plane of patch B. And vector V III The result of computation operation III on bits 0-7 can be stored (e.g., as a vector) in the first plane of the puzzle C.

[0061] In some instances (e.g., where the computation operation is arithmetic), computation operations on bits 0-7 can produce a carry bit. In such scenarios, the carry bit (denoted as 'C') can be propagated from the plane storing bits 0-7 to the plane storing bits 8-15 (e.g., the second most contiguous set of bits). For example, if vector V I If the computation operation I on bits 0-7 generates a carry bit, then the carry bit can be transmitted from the first plane of tile A to the second plane of tile A (storage vector V). I (8-15 bits). Therefore, in vector mapping scheme 1, carry bits can be propagated between planes of the same piece.

[0062] Between time t1 and time t2, piece A can be used to compute the vector V for operation I. I The elements 8-15 of the vector V are computed using operation I, where vector V is used to compute the vector V. I Bits 8-15 are stored in the second plane of tile A; tile B can store the vector V used for computation operation II. II The elements 8-15 of the vector V undergo computation operation II, where vector V... II Bits 8-15 are stored in the second plane of tile B; and tile C can be used to compute the vector V used for operation III. III The elements 8-15 of the vector V undergo computation operation III, where the vector V... III Bits 8-15 are stored in the second plane of tile C. Computational operations can be performed using associative processing as described herein, and these operations can be based on any carry bits received from the first plane.

[0063] The results of the compute operations on bits 8-15 can be stored in the same plane as the operand bits or in a different plane. For example, the results of compute operation I on bits 8-15 of vector V I may be stored (e.g., as a vector) in the second plane of tile A. Similarly, the results of compute operation II on bits 8-15 of vector V II may be stored (e.g., as a vector) in the second plane of tile B. And the results of compute operation III on bits 8-15 of vector V III may be stored (e.g., as a vector) in the second plane of tile C.

[0064] In some instances (e.g., where the compute operations are arithmetic operations), the compute operations on bits 8-15 can produce a carry bit. In such scenarios, the carry bit (denoted as 'C') can be communicated from the plane storing the 8-15 bits to the plane storing bits 16-23 (e.g., the set of less significant contiguous bits). For example, if compute operation I on bits 8-15 of vector V I produces a carry bit, the carry bit can be communicated from the second plane of tile A to the third plane of tile A (storing bits 16-23 of vector V I ).

[0065] Between time t2 and time t3, tile A can perform compute operation I on bits 16-23 of the elements of vector V I for compute operation I, where the 16-23 bits of vector V I are stored in the third plane of tile A; tile B can perform compute operation II on bits 16-23 of the elements of vector V II for compute operation II, where the 16-23 bits of vector V II are stored in the third plane of tile B; and tile C can perform compute operation III on bits 16-23 of the elements of vector V III for compute operation III, where the 16-23 bits of vector V III are stored in the third plane of tile C. The compute operations can be performed using associated processing as described herein, and can be based on any carry bits received from the first plane.

[0066] The results of the compute operations on bits 16-23 can be stored in the same plane as the operand bits or in a different plane. For example, the results of compute operation I on bits 16-23 of vector V I may be stored (e.g., as a vector) in the third plane of tile A. Similarly, the results of compute operation II on bits 16-23 of vector V II may be stored (e.g., as a vector) in the third plane of tile B. And the results of compute operation III on bits 16-23 of vector VIII The result of computation operation III on bits 16-23 can be stored (e.g., as a vector) in the third plane of the puzzle C.

[0067] Therefore, the APM device can perform computational operations using associative processing and tiles configured according to vector mapping scheme 1. After completing the computational operation, the APM device can communicate the result of the computational operation to the host device, using the result to perform one or more additional computational operations, or both.

[0068] Compared to vector mapping scheme 2, vector mapping scheme 1 allows the APM device to process longer vectors. Therefore, the APM device can choose vector mapping scheme 1 instead of vector mapping scheme 2 based on the length of the vector it will process. For example, if the threshold quantity of a vector has a length that satisfies (e.g., is greater than) a threshold length, then the APM device can choose vector mapping scheme 1. In some instances, the threshold length can be equal to the number of rows per plane.

[0069] Compared to other vector mapping schemes (such as vector mapping scheme 2), vector mapping scheme 1 allows the APM device to process arithmetic vectors more efficiently. Therefore, the APM device can choose vector mapping scheme 1 over vector mapping scheme 2 based on the type of computational operations it will perform. For example, if the ratio of arithmetic operations to logical operations meets (e.g., is greater than) a threshold ratio, then the APM device can choose vector mapping scheme 1. Vector mapping scheme 1 also allows the APM device to execute multiple vector execution threads in parallel (e.g., multiple disparate computational operations) because the splices are not limited to executing the same instruction.

[0070] Figure 5 This describes an example of a tile 500 supporting in-memory associative processing, based on the examples disclosed herein. Tile 500 may include tile A, tile B, and tile C. Each tile may store three distinct vector sets on three distinct planes, and each vector may contain n multi-bit (e.g., 24-bit) elements. For example, the first plane of tile A may store one or more vectors V from a first computational operation (referred to as computational operation I). I The elements are bits 0-7, and other information; the second plane of patch A may store one or more vectors V from the second computational operation (referred to as computational operation II). II The elements are bits 0-7, and other information; and the third plane of patch A can store one or more vectors V from the third computational operation (referred to as computational operation III). III The elements are stored in bits 0-7, along with other information. Puzzle B and puzzle C can be configured similarly, except that puzzle B can store bits 8-15 of the vector and puzzle C can store bits 16-23 of the vector.

[0071] Between time t0 and time t1, piece A can be used to compute the vector V for operation I. I The elements 0-7 of the vector are used to perform computational operations II. Associative processing, as described herein, can be used to perform computational operations. Vector V I The result of the computation operation I on bits 0-7 of an element can be stored in the same plane as the operand bits or in a different plane. For example, vector V I The result of the computation operation I on bits 0-7 of the element can be stored (e.g., as a vector) in the first plane of the puzzle A.

[0072] In some instances (e.g., where computation operation I is an arithmetic operation), vector V I Computational operations on bits 0-7 can produce carry bits. In this type of scenario, the carry bit (denoted as 'C') can be obtained from the storage vector V. I The 0-7 bit pieces (e.g., piece A) are communicated to the 8-15 bit pieces (e.g., the second most contiguous set of bits) (e.g., piece B). Therefore, in vector mapping scheme 2, carry bits can be communicated between pieces (e.g., between planes of different pieces).

[0073] Between time t1 and time t2, piece A can be used to compute the vector V for operation II. II The elements 0-7 of the array are used to perform computation operation II. Additionally, piece B can be used on the vector V used for computation operation I. I The calculation operation I is performed on bits 8-15 of the element. The calculation operation can be performed using the association processing described herein, and the calculation operation can be based on any carry bit received from other pieces.

[0074] Vector V II The result of operation II on bits 0-7 can be stored in the same plane as the operand bits or in a different plane. For example, vector V II The result of computation operation II on bits 0-7 can be stored (e.g., as a vector) in the second plane of patch A. Similarly, vector V I The result of computation operation I on bits 8-15 can be stored (e.g., as a vector) in the first plane of patch B.

[0075] In some instances (e.g., where the computation operation is arithmetic), the computation performed between t1 and t2 may produce one or more carry bits. For example, vector V... II The computational operation II on bits 0-7 can generate carry bits, vector V I Computational operation I on bits 8-15 can produce a carry bit, or both. In this type of scenario, the carry bit from computational operation II can be obtained from the storage vector V.II the bits 0-7 of tile A of vector V II the bits 8-15 of tile B of vector V I the bits 8-15 of tile B of vector V I the bits 16-23 of tile C of vector V, or both.

[0076] Between time t2 and time t3, tile A can perform a compute operation III on the bits 0-7 of the elements of vector V III II I The compute operations can be performed using associated processing as described herein, and can be based on any carry bits received from other tiles.

[0077] The results of the compute operations on the 0-7 bits of vector V III may be stored in the same plane as the operand bits or in a different plane. For example, the results of the compute operation III on the bits 0-7 of vector V III may be stored (e.g., as a vector) in a third plane of tile A. Similarly, the results of the compute operation II on the bits 8-15 of vector V II may be stored (e.g., as a vector) in a second plane of tile B. And the results of the compute operation I on the bits 16-23 of vector V I may be stored (e.g., as a vector) in a first plane of tile C.

[0078] Accordingly, an APM device can perform compute operations using associated processing and tiles configured according to vector mapping scheme 2. After completing the compute operations, the APM device can communicate an indication of the results of the compute operations to a host device, perform one or more additional compute operations using the results, or both.

[0079] Vector mapping scheme 2 can allow an APM device to interleave (or "pipeline") compute operations in a manner not supported by vector mapping scheme 1, and thus can be more efficient for certain processing tasks. However, vector mapping scheme 2 can support smaller vector lengths compared to vector mapping scheme 1. Accordingly, an APM device can select vector mapping scheme 2 based on the length of a vector that the APM device is to process. For example, an APM device can select vector mapping scheme 2 if a threshold amount of the vector has a length that satisfies (e.g., is less than) a threshold length. ​​

[0080] Vector mapping scheme 2 can allow an APM device to more efficiently process logical vectors compared to other vector mapping schemes, such as vector mapping scheme 1. For example, vector mapping scheme 2 can allow an APM device to perform logical operations on all 24 bits of a vector V I in parallel (e.g., using tiles A, B, and C) between time to and time ti to completely finish the logical operations on vector V I . Such parallelism can be possible for logical operations because, unlike arithmetic operations, logical operations can not produce carry bits. Thus, each tile in vector mapping scheme 2 can operate without having to wait for a lower-order tile to finish operating on a lower-order (e.g., less efficient) set of contiguous bits. Thus, an APM device can select vector mapping scheme 1 over vector mapping scheme 2 based on the type of computational operations that the APM device will perform. For example, an APM device can select vector mapping scheme 2 if the ratio of logical operations to arithmetic operations satisfies (e.g., is greater than) a threshold ratio.

[0081] Vector mapping scheme 2 can also enable “pipelining” of different computational operations on the same plane (as opposed to stitching together different planes in each tile to create such a pipeline). For example, at time to, plane 0 in tile A can perform computational operation 1 (e.g., logical operation 1); at time ti, plane 0 in tile A can perform computational operation 2 (e.g., logical operation 2) and plane 0 in tile B can perform computational operation 1 (e.g., logical operation 1), and so on.

[0082] Figure 6 An example of a process flow 600 for supporting in-memory associative processing of vectors in accordance with examples disclosed herein is illustrated. Process flow 600 can be implemented by a device such as an APM system or APM device as described herein. The device can support multiple vector mapping schemes, such as vector mapping scheme 1 and vector mapping scheme 2. In some examples, the device can switch between vector mapping schemes (e.g., for different instruction sets).

[0083] At 605, the device can receive an instruction set (e.g., a program, a vector instruction set) issued by a host device. The instruction set can indicate or be associated with a set of computational operations. In some examples, the host device can communicate the instruction set via a CXL interface. In some examples, the instruction set can indicate memory addresses of a set of vectors that are operands for the computational operations. Alternatively, the instruction set can be accompanied by the set of vectors. In some examples, the instruction set can indicate one of the vector mapping schemes supported by the device.

[0084] At 610, the device can retrieve the set of vectors from a memory coupled with the device. For example, the device can retrieve the set of vectors from a memory address of the memory indicated by the set of instructions. Alternatively, the device can receive the set of vectors from a host device or determine that the set of vectors has been stored in an APM die of the device.

[0085] At 615, the device can determine various characteristics of the set of computation operations, various characteristics of the set of vectors, or both, among other aspects. For example, the device can determine a length of the set of vectors (e.g., a number of elements per vector). Additionally or alternatively, determine a number of arithmetic operations in the set of computation operations, a number of logical operations in the set of computation operations, or both. In some examples, the device can determine a ratio of arithmetic operations to logical operations.

[0086] At 620, the device can select a vector mapping scheme from a set of vector mapping schemes supported by the device. For example, the device can select vector mapping scheme 1 or vector mapping scheme 2. In some examples, the device can select the vector mapping scheme indicated by the host device at 605. In other examples, the device can select the vector mapping scheme based on one or more characteristics. In some examples, the device can select vector mapping scheme 1 based on one or more of the set of vectors having a length greater than a threshold length (e.g., greater than a number of rows per plane). In some examples, the device can select vector mapping scheme 1 based on the set of computation operations having a ratio of arithmetic operations to logical operations that satisfies a threshold ratio. In some examples, the device can select vector mapping scheme 2 based on one or more of the set of vectors having a length less than the threshold length. In some examples, the device can select vector mapping scheme 2 based on the set of computation operations having a ratio of logical operations to arithmetic operations that satisfies a threshold ratio.

[0087] At 625, the device can write the set of vectors according to the selected vector mapping scheme. For example, if the device selected vector mapping scheme 1, the device can write the set of vectors to a plane of the device according to vector mapping scheme 1 as described herein and as shown in Figure 3 and 4 At 625, the device can write the set of vectors according to the selected vector mapping scheme. For example, if the device selected vector mapping scheme 1, the device can write the set of vectors to a plane of the device according to vector mapping scheme 1 as described herein and as shown in Figure 3 and 5 At 625, the device can write the set of vectors according to the selected vector mapping scheme. For example, if the device selected vector mapping scheme 1, the device can write the set of vectors to a plane of the device according to vector mapping scheme 1 as described herein and as shown in

[0088] At 630, the device can perform the set of computation operations on the set of vectors using associative processing and according to the selected vector mapping scheme. For example, if the device selected vector mapping scheme 1, the device can perform the set of computation operations on the set of vectors using associative processing and according to vector mapping scheme 1 as described herein and as shown in Figure 3 and4 Vector mapping scheme 1, shown in FIG. 6, performs a set of compute operations on a set of vectors. If the device selects vector mapping scheme 2, the device can use associative processing and perform the set of compute operations on the set of vectors according to as described herein and as shown in Figure 3 and 5 Vector mapping scheme 2, shown in FIG. 7, performs a set of compute operations on a set of vectors.

[0089] At 635, the device can write results of the set of compute operations to a plane of the device. At 640, the device can communicate some or all of the results to a host device. Additionally or alternatively, the device can use some or all of the results to perform additional processing tasks.

[0090] Thus, the device can perform a set of compute operations on a set of vectors using associative processing.

[0091] Figure 7 A block diagram 700 showing a device 720 that supports in-memory associative processing for vectors in accordance with examples as disclosed herein is shown. The device 720 can be an example of aspects of the devices described with reference to Figures 1 to 6 The device 720, or various components thereof, can be an example of means for performing various aspects of in-memory associative processing for vectors as described herein. For example, the device 720 can include associative processing circuitry 725, access circuitry 730, communication circuitry 735, receiving circuitry 740, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0092] The associative processing circuitry 725 can be configured as, or otherwise support, a device for performing a compute operation on data representing a first set of contiguous bits of a vector, the vector being an operand for the compute operation, the data representing the first set of contiguous bits stored in a first plane of a tile of a plurality of tiles. In some examples, the associative processing circuitry 725 can be configured as, or otherwise support, a device for performing the compute operation on data representing a second set of contiguous bits of the vector based at least in part on performing the compute operation on the first set of contiguous bits, the data representing the second set of contiguous bits stored in a second plane of the tile of the plurality of tiles using associative processing.

[0093] In some examples, the access circuitry 730 can be configured as, or otherwise support, a device for writing data representing results of the compute operation on the first set of contiguous bits to the first plane of the tile. In some examples, the access circuitry 730 can be configured as, or otherwise support, a device for writing data representing results of the compute operation on the second set of contiguous bits to the second plane of the tile.

[0094] In some examples, the vector includes a plurality of elements each having a respective length. In some examples, a first element of the vector includes the first set of contiguous bits and the second set of contiguous bits.

[0095] In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing a second computational operation on data representing a first set of contiguous bits of a second vector, the data representing the first set of contiguous bits of the second vector stored in a first plane of a second tile. In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing the second computational operation on data representing a second set of contiguous bits of the second vector based at least in part on performing the second computational operation on data representing the first set of contiguous bits of the second vector, the data representing the second set of contiguous bits of the second vector stored in a second plane of the second tile.

[0096] In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing the second computational operation on the data representing the first set of contiguous bits of the second vector in parallel with performing the computational operation on the data representing the first set of contiguous bits of the vector. In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing the second computational operation on the data representing the second set of contiguous bits of the second vector in parallel with performing the computational operation on the data representing the second set of contiguous bits of the vector.

[0097] In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing the computational operation on data representing a first set of contiguous bits of a second vector, the second vector being an operand for the computational operation, the data representing the first set of contiguous bits of the second vector stored in the first plane of the tile. In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing the computational operation on data representing a second set of contiguous bits of the second vector, the data representing the second set of contiguous bits of the second vector stored in the second plane of the tile.

[0098] In some examples, the computational operation includes an arithmetic operation, and the communication circuitry 735 can be configured as or otherwise support a means for communicating a carry bit resulting from performing the arithmetic operation on data representing the first set of contiguous bits from the first plane of the tile to the second plane of the tile, wherein the arithmetic operation on the data representing the second set of contiguous bits is based at least in part on the carry bit.

[0099] In some examples, the correlation processing circuitry 725 can be configured as or otherwise support a means for performing a second compute operation on data representing a first set of contiguous bits of a second vector stored in a second plane of a second tile using correlation processing and in parallel with performing the compute operation on the data representing the first set of contiguous bits of the vector.

[0100] In some examples, the receiving circuitry 740 can be configured as or otherwise support a means for receiving signaling from a host device indicating an instruction set indicating the vector and the compute operation. In some examples, the accessing circuitry 730 can be configured as or otherwise support a means for writing data representing the vector to the first plane and the second plane according to a vector mapping scheme and based at least in part on the instruction set.

[0101] In some examples, the compute operation includes a logical operation or an arithmetic operation.

[0102] In some examples, the memory die is configured such that a single plane per tile can be operated for correlation processing at the same time.

[0103] In some examples, the correlation processing circuitry 725 can be configured as or otherwise support a means for performing a compute operation on data representing a first set of contiguous bits of a vector using correlation processing, the vector being an operand for the compute operation, the data representing the first set of contiguous bits stored in a first plane of a first tile of the plurality of tiles. In some examples, the correlation processing circuitry 725 can be configured as or otherwise support a means for performing the compute operation on data representing a second set of contiguous bits of the vector using correlation processing based at least in part on performing the compute operation on the first set of contiguous bits, the data representing the second set of contiguous bits stored in the first plane of a second tile of the plurality of tiles.

[0104] In some examples, the accessing circuitry 730 can be configured as or otherwise support a means for writing data representing a result of the compute operation on the data representing the first set of contiguous bits to the first plane of the first tile. In some examples, the accessing circuitry 730 can be configured as or otherwise support a means for writing data representing a result of the compute operation on the data representing the second set of contiguous bits to the first plane of the second tile.

[0105] In some examples, the vector includes a plurality of elements each having a respective length. In some examples, a first element of the vector includes the first set of contiguous bits and the second set of contiguous bits.

[0106] In some examples, the associated processing circuitry 725 can be configured as, or otherwise support, a means for performing a second computational operation on data representing a first contiguous bit set of a second vector, the data representing the first contiguous bit set of the second vector stored in a second plane of the first tile. In some examples, the associated processing circuitry 725 can be configured as, or otherwise support, a means for performing the second computational operation on data representing a second contiguous bit set of the second vector based at least in part on performing the second computational operation on the data representing the first contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in a second plane of the second tile.

[0107] In some examples, the associated processing circuitry 725 can be configured as, or otherwise support, a means for performing the computational operation on data representing a first contiguous bit set of a second vector, the second vector being an operand for the computational operation, the data representing the first contiguous bit set of the second vector stored in the first plane of the first tile. In some examples, the associated processing circuitry 725 can be configured as, or otherwise support, a means for performing the computational operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in the first plane of the second tile.

[0108] In some examples, the computational operation includes an arithmetic operation, and the communication circuitry 735 can be configured as, or otherwise support, a means for communicating a carry bit resulting from performing the arithmetic operation on the data representing the first contiguous bit set from the first plane of the first tile to the first plane of the second tile, wherein the arithmetic operation on the data representing the second contiguous bit set is based at least in part on the carry bit.

[0109] In some examples, the associated processing circuitry 725 can be configured as, or otherwise support, a means for performing a second computational operation on data representing a first contiguous bit set of a second vector stored in a second plane of the first tile using associated processing and in parallel with performing the computational operation on the data representing the second contiguous bit set of the vector.

[0110] In some examples, the associated processing circuitry 725 can be configured as, or otherwise support, a means for performing a logical operation on data representing the second contiguous bit set in parallel with performing the logical operation on the data representing the first contiguous bit set based at least in part on the computational operation including a logical operation.

[0111] In some examples, the receiving circuitry 740 can be configured as or otherwise support a means for receiving, from a host device, signaling indicative of an instruction set indicative of the vector and the compute operation. In some examples, the accessing circuitry 730 can be configured as or otherwise support a means for writing data representative of the vector to the first plane and the second plane according to a vector mapping scheme and based at least in part on the instruction set.

[0112] In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing, based at least in part on a truth table indicative of results of the compute operation for various combinations of logical values, the compute operation on data representative of a first contiguous bit set of a first vector and data representative of a first contiguous bit set of a second vector, the data representative of the first contiguous bit set stored in a first plane of a tile of the plurality of tiles. In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing, based at least in part on the truth table for the compute operation, the compute operation on data representative of a second contiguous bit set of the first vector and data representative of a second contiguous bit set of the second vector, the data representative of the second contiguous bit set stored in a second plane of the tile.

[0113] In some examples, the communication circuitry 735 can be configured as or otherwise support a means for communicating a carry bit resulting from the performance of the compute operation on the data representative of the first contiguous bit set from the first plane of the tile to the second plane of the tile, where the performance of the compute operation on the data representative of the second contiguous bit set is based at least in part on the carry bit.

[0114] In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing, in parallel with the performance of the compute operation on the data representative of the first contiguous bit set, a second compute operation on data representative of a first contiguous bit set of a third vector stored in a first plane of a second tile.

[0115] In some examples, the receiving circuitry 740 can be configured as or otherwise support a means for receiving, from a host device, signaling indicative of an instruction set indicative of the first vector, the second vector, and the compute operation. In some examples, the accessing circuitry 730 can be configured as or otherwise support a means for writing the data representative of the first contiguous bit set to the first plane of the tile and the data representative of the second contiguous bit set to the second plane of the tile based at least in part on the instruction set.

[0116] In some examples, the correlation processing circuitry 725 can be configured or otherwise support a means for performing a computation operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table indicating results of the computation operation for various combinations of logical values, the data representing the first set of contiguous bits stored in a first plane of a first tile of the plurality of tiles. In some examples, the correlation processing circuitry 725 can be configured or otherwise support a means for performing the computation operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the computation operation, the data representing the second set of contiguous bits stored in a first plane of a second tile of the plurality of tiles.

[0117] In some examples, the communication circuitry 735 can be configured or otherwise support a means for communicating a carry bit resulting from the performing the computation operation on the data representing the first set of contiguous bits from the first plane of the first tile to the second plane of the second tile, where the performing the computation operation on the data representing the second set of contiguous bits is based at least in part on the carry bit.

[0118] In some examples, the correlation processing circuitry 725 can be configured or otherwise support a means for performing a second computation operation on data representing a first set of contiguous bits of a third vector stored in a second plane of the first tile in parallel with the performing the computation operation on the data representing the second set of contiguous bits.

[0119] In some examples, the receiving circuitry 740 can be configured or otherwise support a means for receiving signaling from a host device indicating an instruction set, the instruction set indicating the first vector, the second vector, and the computation operation. In some examples, the access circuitry 730 can be configured or otherwise support a means for writing the data representing the first set of contiguous bits to the first plane of the first tile and the data representing the second set of contiguous bits to the first plane of the second tile based at least in part on the instruction set.

[0120] In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing a computation operation on data representing a first contiguous bit set of a first vector and data representing a first contiguous bit set of a second vector based at least in part on a truth table indicating results of the computation operation for various combinations of logical values, the data representing the first contiguous bit set stored in a first plane of a die including a plurality of tiles, the plurality of tiles each including a plurality of planes. In some examples, the associated processing circuitry 725 can be configured as or otherwise support a means for performing the computation operation on data representing a second contiguous bit set of the first vector and data representing a second contiguous bit set of the second vector based at least in part on the truth table for the computation operation, the data representing the second contiguous bit set stored in a second plane of the die.

[0121] In some examples, the first plane and the second plane have a same tile, and the communication circuitry 735 can be configured as or otherwise support a means for communicating a carry bit resulting from performing the computation operation on the data representing the first contiguous bit set from the first plane of the tile to the second plane of the tile, where the computation operation performed on the data representing the second contiguous bit set is based at least in part on the carry bit.

[0122] In some examples, the first plane has a first tile and the second plane has a second tile, and the communication circuitry 735 can be configured as or otherwise support a means for communicating a carry bit resulting from performing the computation operation on the data representing the first contiguous bit set from the first plane of the first tile to the second plane of the second tile, where the computation operation performed on the data representing the second contiguous bit set is based at least in part on the carry bit.

[0123] In some examples, the first plane and the second plane have a first tile, and the associated processing circuitry 725 can be configured as or otherwise support a means for performing a second computation operation on data representing a first contiguous bit set of a third vector stored in a first plane of a second tile in parallel with performing the computation operation on the data representing the first contiguous bit set.

[0124] In some examples, the first plane has a first tile and the second plane has a second tile, and the associated processing circuitry 725 can be configured as or otherwise support a means for performing a second computation operation on data representing a first contiguous bit set of a third vector stored in a second plane of the first tile in parallel with performing the computation operation on the data representing the second contiguous bit set.

[0125] In some examples, access circuitry 730 can include association processing circuitry 725, communication circuitry 735, and receive circuitry 740, among other components and circuitry. The logic can be included in an APM system, included in an APM device, or can be distributed between an APM system and an APM device. Access circuitry 730 can be configured to perform, cause the components of an APM system and / or APM device to perform, or both, aspects of the techniques described herein.

[0126] Figure 8 A flow diagram illustrating a method 800 that supports in-memory association processing for vectors in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a device as described herein or its components. For example, the operations of method 800 can be performed by an APM system or APM device as described with reference to FIGS. 1-6. Figures 1 to 7 In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0127] At 805, the method can include performing a compute operation on data representing a first contiguous set of bits of a vector using association processing, the vector being an operand for the compute operation, the data representing the first contiguous set of bits stored in a first plane of a tile of the plurality of tiles. The operations of 805 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 805 can be performed by association processing circuitry 725 as described with reference to FIGS. 1-6. Figure 7 In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0128] At 810, the method can include performing the compute operation on data representing a second contiguous set of bits of the vector using association processing based at least in part on performing the compute operation on the first contiguous set of bits, the data representing the second contiguous set of bits stored in a second plane of the tile of the plurality of tiles. The operations of 810 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 810 can be performed by association processing circuitry 725 as described with reference to FIGS. 1-6. Figure 7 In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0129] In some examples, an apparatus as described herein can perform method 800. The apparatus can include a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells. The apparatus can also include logic coupled with the die and configured to cause the apparatus to perform a method, including method 800, as described herein.

[0130] In some examples, an apparatus as described herein can perform one or more methods, such as the method 800. The apparatus can include features, circuitry, logic, means, or instructions (e.g., instructions stored by a non-transitory computer-readable medium and executable by a processor) for performing a computational operation on data representing a first contiguous bit set of a vector, the vector being an operand for the computational operation, the data representing the first contiguous bit set stored in a first plane of a tile of a plurality of tiles using coherency processing; and based at least in part on performing the computational operation on the first contiguous bit set, performing the computational operation on data representing a second contiguous bit set of the vector, the data representing the second contiguous bit set stored in a second plane of the tile using coherency processing.

[0131] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for writing data representing results of the computational operation on the first contiguous bit set to the first plane of the tile; and writing data representing results of the computational operation on the second contiguous bit set to the second plane of the tile.

[0132] In some examples of the method 800 and apparatus described herein, the vector includes a plurality of elements each having a respective length, and a first element of the vector includes the first contiguous bit set and the second contiguous bit set.

[0133] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing a second computational operation on data representing a first contiguous bit set of a second vector, the data representing the first contiguous bit set of the second vector stored in a first plane of a second tile; and based at least in part on performing the second computational operation on data representing the first contiguous bit set of the second vector, performing the second computational operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in a second plane of the second tile.

[0134] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing the second computational operation on the data representing the first contiguous bit set of the second vector in parallel with performing the computational operation on the data representing the first contiguous bit set of the vector; and performing the second computational operation on the data representing the second contiguous bit set of the second vector in parallel with performing the computational operation on the data representing the second contiguous bit set of the vector.

[0135] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing the compute operation on data representing a first contiguous bit set of a second vector, the second vector can be an operand for the compute operation, the data representing the first contiguous bit set of the second vector stored in the first plane of the tile; and performing the compute operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in the second plane of the tile.

[0136] In some examples of the method 800 and apparatus described herein the compute operation includes an arithmetic operation, and the method, apparatus, and non-transitory computer- readable medium can further include operations, features, circuitry, logic, means, or instructions for communicating a carry bit resulting from performing the arithmetic operation on data representing the first contiguous bit set from the first plane of the tile to the second plane of the tile, wherein the arithmetic operation on the data representing the second contiguous bit set can be based at least in part on the carry bit.

[0137] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing a second compute operation on data representing a first contiguous bit set of a second vector stored in a second plane of a second tile using associated processing and in parallel with performing the compute operation on the data representing the first contiguous bit set of the vector.

[0138] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving signaling from a host device indicating an instruction set, the instruction set indicating the vector and the compute operation; and writing data representing the vector to the first plane and the second plane according to a vector mapping scheme and based at least in part on the instruction set.

[0139] In some examples of the method 800 and apparatus described herein the compute operation includes a logical operation or an arithmetic operation.

[0140] In some examples of the method 800 and apparatus described herein the memory die can be configured such that a single plane per tile can be simultaneously operable for associated processing.

[0141] Figure 9A flow chart illustrating a method 900 that supports in-memory associative processing for vectors in accordance with the examples as disclosed herein is shown. The operations of method 900 can be implemented by a device as described herein or its components. For example, the operations of method 900 can be performed by a device as described with reference to FIGS. 1-8, 10, and 11, or its components as described with reference to FIGS. 1-8, 10, and 11. Figures 1 to 7 The APM system or APM device described is executed. In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0142] At 905, the method can include performing a computational operation on data representing a first contiguous set of bits of a vector using associative processing, the vector being an operand for the computational operation, the data representing the first contiguous set of bits stored in a first plane of a first tile of the plurality of tiles. The operations of 905 can be performed according to the examples as disclosed herein. In some examples, the operations of 905 can be performed by an associative processing circuitry 725 as described with reference to FIGS. 1-8, 10, and 11. Figure 7 The associative processing circuitry 725 described can perform aspects of the operations of 905.

[0143] At 910, the method can include performing the computational operation on data representing a second contiguous set of bits of the vector using associative processing based at least in part on performing the computational operation on the first contiguous set of bits, the data representing the second contiguous set of bits stored in a first plane of a second tile of the plurality of tiles. The operations of 910 can be performed according to the examples as disclosed herein. In some examples, the operations of 910 can be performed by an associative processing circuitry 725 as described with reference to FIGS. 1-8, 10, and 11. Figure 7 The associative processing circuitry 725 described can perform aspects of the operations of 910.

[0144] In some examples, an apparatus as described herein can perform the method 900. The apparatus can include a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells. The apparatus can also include logic coupled with the memory die and configured to cause the apparatus to perform a method, including the method 900, as described herein.

[0145] In some examples, an apparatus as described herein can perform one or more methods, such as the method 900. The apparatus can include features, circuitry, logic, means, or instructions (e.g., instructions stored by a non-transitory computer-readable medium and executable by a processor) for performing a computational operation on data representing a first contiguous bit set of a vector, the vector being an operand for the computational operation, the data representing the first contiguous bit set stored in a first plane of a first tile of a plurality of tiles using associative processing; and based at least in part on performing the computational operation on the first contiguous bit set, performing the computational operation on data representing a second contiguous bit set of the vector, the data representing the second contiguous bit set stored in a first plane of a second tile of the plurality of tiles using associative processing.

[0146] Some examples of the method 900 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for writing data representing results of the computational operation on the data representative of the first contiguous bit set to the first plane of the first tile; and writing data representing results of the computational operation on the data representative of the second contiguous bit set to the first plane of the second tile.

[0147] In some examples of the method 900 and apparatus described herein, the vector includes a plurality of elements each having a respective length, and a first element of the vector includes the first contiguous bit set and the second contiguous bit set.

[0148] Some examples of the method 900 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing a second computational operation on data representing a first contiguous bit set of a second vector, the data representing the first contiguous bit set of the second vector stored in a second plane of the first tile; and based at least in part on performing the second computational operation on data representing the first contiguous bit set of the second vector, performing the second computational operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in a second plane of the second tile.

[0149] Some examples of the method 900 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing the compute operation on data representing a first contiguous bit set of a second vector, the second vector can be an operand for the compute operation, the data representing the first contiguous bit set of the second vector stored in the first plane of the first tile; and performing the compute operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in the first plane of the second tile.

[0150] In some examples of the method 900 and apparatus described herein the compute operation includes an arithmetic operation, and the method, apparatus, and non-transitory computer- readable medium can further include operations, features, circuitry, logic, means, or instructions for communicating a carry bit resulting from performing the arithmetic operation on data representing the first contiguous bit set from the first plane of the first tile to the first plane of the second tile, wherein the arithmetic operation on the data representing the second contiguous bit set can be based at least in part on the carry bit.

[0151] Some examples of the method 900 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing a second compute operation on data representing a first contiguous bit set of a second vector stored in a second plane of the first tile using associative processing and in parallel with performing the compute operation on the data representing the second contiguous bit set of the vector.

[0152] Some examples of the method 900 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for performing a second compute operation on data representing a first contiguous bit set of a second vector stored in a second plane of the first tile using associative processing and in parallel with performing the compute operation on the data representing the second contiguous bit set of the vector.

[0153] Some examples of the method 900 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving signaling from a host device indicating an instruction set, the instruction set indicating the vector and the compute operation; and writing data representing the vector to the first plane and the second plane according to a vector mapping scheme and based at least in part on the instruction set.

[0154] Figure 10A flow chart illustrating a method 1000 that supports in-memory associative processing for vectors in accordance with examples as disclosed herein is shown. The operations of method 1000 can be implemented by a device as described herein or its components. For example, the operations of method 1000 can be performed by a device as described with reference to FIGS. 1-6, 8, 9, 11, and 12, or a component of such a device. Figures 1 to 7 The described APM system or APM device performs. In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0155] At 1005, the method can include performing a computational operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table indicating results of the computational operation for various combinations of logical values, the data representing the first set of contiguous bits stored in a first plane of a tile of the plurality of tiles. The operations of 1005 can be performed according to the examples as disclosed herein. In some examples, the operations of 1005 can be performed by an associative processing circuitry 725 as described with reference to FIGS. 1-6, 8, 9, 11, and 12, or a component of such a device. Figure 7 The described associative processing circuitry 725 performs aspects of the operations of 1005.

[0156] At 1010, the method can include performing the computational operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the computational operation, the data representing the second set of contiguous bits stored in a second plane of the tile of the plurality of tiles. The operations of 1010 can be performed according to the examples as disclosed herein. In some examples, the operations of 1010 can be performed by an associative processing circuitry 725 as described with reference to FIGS. 1-6, 8, 9, 11, and 12, or a component of such a device. Figure 7 The described associative processing circuitry 725 performs aspects of the operations of 1010.

[0157] In some examples a device as described herein can perform the method 1000. The device can include a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells. The device can also include logic coupled with the memory die and configured to cause the device to perform a method, including the method 1000, as described herein.

[0158] In some instances, the device as described herein may perform one or more methods, such as method 1000. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: performing the computation operation on data representing a first connected bit set of a first vector and data representing a first connected bit set of a second vector, at least in part based on a truth table indicating the result of a computation operation for various combinations of logical values, the data representing the first connected bit set in a first plane of the tiles among the plurality of tiles; and performing the computation operation on data representing a second connected bit set of the first vector and data representing a second connected bit set of the second vector, at least in part based on the truth table for the computation operation, the data representing the second connected bit set in a second plane of the tiles among the plurality of tiles.

[0159] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for conveying a carry bit generated by performing the computational operation on the data representing the first connected bit set from the first plane of the tile to the second plane of the tile, wherein the computational operation performed on the data representing the second connected bit set may be at least partially based on the carry bit.

[0160] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for performing a second computational operation on data representing the first connected bit set stored in the first plane of the second patch, in parallel with performing the computational operation on the data representing the first connected bit set.

[0161] Some examples of the method 1000 and apparatus described herein may additionally include operations, features, circuitry, logic, means, or instructions for: receiving signaling from a host device indicating a set of instructions, the set of instructions indicating the first vector, the second vector, and the computation operation; and writing, at least in part, based on the set of instructions, the data representing the first connected bit set to the first plane of the tile and the data representing the second connected bit set to the second plane of the tile.

[0162] Figure 11 A flowchart illustrating a method 1100 for supporting in-memory associative processing of vectors according to an example disclosed herein is shown. Operation of method 1100 may be implemented by means of apparatus or components thereof as described herein. For example, operation of method 1100 may be performed by reference to... Figures 1 to 7The described APM system or APM device performs. In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, a device can perform aspects of the described functions using special-purpose hardware.

[0163] At 1105, the method can include performing a computation operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table indicating results of the computation operation for various combinations of logical values, the data representing the first set of contiguous bits stored in a first plane of a first tile of the plurality of tiles. The operations of 1105 can be performed according to the examples disclosed herein. In some examples, the operations of 1105 can be performed by the Figure 7 The described associated processing circuitry 725 performs aspects of the operations of 1105.

[0164] At 1110, the method can include performing the computation operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the computation operation, the data representing the second set of contiguous bits stored in a first plane of a second tile of the plurality of tiles. The operations of 1110 can be performed according to the examples disclosed herein. In some examples, the operations of 1110 can be performed by the Figure 7 The described associated processing circuitry 725 performs aspects of the operations of 1110.

[0165] At 1115, the method can include communicating a carry bit resulting from performing the computation operation on the data representing the first set of contiguous bits from the first plane of the first tile to the second plane of the second tile, wherein the computation operation performed on the data representing the second set of contiguous bits is based at least in part on the carry bit. The operations of 1115 can be performed according to the examples disclosed herein. In some examples, the operations of 1115 can be performed by the Figure 7 The described communication circuitry 735 performs aspects of the operations of 1115.

[0166] In some examples, an apparatus as described herein can perform the method 1100. The apparatus can include a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells. The apparatus can also include logic coupled with the memory die and configured to cause the apparatus to perform a method, including the method 1100, as described herein.

[0167] In some instances, the device as described herein may perform one or more methods, such as method 1100. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: performing the computation operation on data representing a first connected bit set of a first vector and data representing a first connected bit set of a second vector, the data representing the first connected bit set stored in a first plane of a first piece of the plurality of tiles, based at least in part on a truth table indicating the result of the computation operation for various combinations of logical values; and performing the computation operation on data representing a second connected bit set of the first vector and data representing a second connected bit set of the second vector, the data representing the second connected bit set stored in a first plane of a second piece of the plurality of tiles, based at least in part on the truth table for the computation operation.

[0168] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for conveying a carry bit generated by performing the computational operation on the data representing the first connected bit set from the first plane of the first tile to the second plane of the second tile, wherein the computational operation performed on the data representing the second connected bit set is at least partially based on the carry bit.

[0169] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for performing a second computational operation on data representing a third vector stored in a second plane of the first piece of the puzzle, in parallel with performing the computational operation on the data representing the second connected bit set.

[0170] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuitry, logic, means, or instructions for: receiving signaling from a host device indicating a set of instructions, the set of instructions indicating the first vector, the second vector, and the computation operation; and writing, at least in part, based on the set of instructions, the data representing the first connected bit set to the first plane of the first tile and the data representing the second connected bit set to the first plane of the second tile.

[0171] Figure 12 A flowchart illustrating a method 1200 for supporting in-memory associative processing of vectors according to an example disclosed herein is shown. Operation of method 1200 may be implemented by means of apparatus or components thereof as described herein. For example, operation of method 1200 may be performed by reference to... Figures 1 to 7The described APM system or APM device performs. In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, a device can perform aspects of the described functions using special-purpose hardware.

[0172] At 1205, the method can include performing a computation operation on data representing a first contiguous bit set of a first vector and data representing a first contiguous bit set of a second vector based at least in part on a truth table that computes results of the computation operation for indications of various combinations of logical values, the data representing the first contiguous bit set stored in a first plane of a die including a plurality of tiles, the plurality of tiles each including a plurality of planes. The operations of 1205 can be performed according to the examples disclosed herein. In some examples, the operations of 1205 can be performed by the reference Figure 7 The described correlation processing circuitry 725 performs aspects of the operations of 1205.

[0173] At 1210, the method can include performing the computation operation on data representing a second contiguous bit set of the first vector and data representing a second contiguous bit set of the second vector based at least in part on the truth table for the computation operation, the data representing the second contiguous bit set stored in a second plane of the die. The operations of 1210 can be performed according to the examples disclosed herein. In some examples, the operations of 1210 can be performed by the reference Figure 7 The described correlation processing circuitry 725 performs aspects of the operations of 1210.

[0174] In some examples, an apparatus as described herein can perform one or more methods, such as method 1200. The apparatus can include features, circuitry, logic, means, or instructions (e.g., instructions stored by a non-transitory computer-readable medium and executable by a processor) for performing the following operations: performing a computation operation on a first contiguous bit set of a first vector and a first contiguous bit set of a second vector based at least in part on a truth table that computes results of the computation operation for indications of various combinations of logical values, the first contiguous bit set stored in a first plane of a die including a plurality of tiles, the plurality of tiles each including a plurality of planes; and performing the computation operation on a second contiguous bit set of the first vector and a second contiguous bit set of the second vector based at least in part on the truth table for the computation operation, the second contiguous bit set stored in a second plane of the die.

[0175] In some examples of the method 1200 and apparatus described herein, the first plane and the second plane can have a same tile, and the method, apparatus, and non-transitory computer-readable medium can further include operations, features, circuitry, logic, means, or instructions for communicating a carry bit resulting from performing the computational operation on the first set of contiguous bits from the first plane of the tile to the second plane of the tile, where the computational operation performed on the data representing the second set of contiguous bits can be based at least in part on the carry bit.

[0176] In some examples of the method 1200 and apparatus described herein, the first plane can have a first tile and the second plane can have a second tile, and the method, apparatus, and non-transitory computer-readable medium can further include operations, features, circuitry, logic, means, or instructions for communicating a carry bit resulting from performing the computational operation on the first set of contiguous bits from the first plane of the first tile to the second plane of the second tile, where the computational operation performed on the second set of contiguous bits can be based at least in part on the carry bit.

[0177] In some examples of the method 1200 and apparatus described herein, the first plane and the second plane can have a first tile, and the method, apparatus, and non-transitory computer-readable medium can further include operations, features, circuitry, logic, means, or instructions for performing, in parallel with performing the computational operation on the first set of contiguous bits, a second computational operation on a first set of contiguous bits of a third vector stored in a first plane of a second tile.

[0178] In some examples of the method 1200 and apparatus described herein, the first plane can have a first tile and the second plane can have a second tile, and the method, apparatus, and non-transitory computer-readable medium can further include operations, features, circuitry, logic, means, or instructions for performing, in parallel with performing the computational operation on the second set of contiguous bits, a second computational operation on a first set of contiguous bits of a third vector stored in a second plane of the first tile.

[0179] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods can be combined.

[0180] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by persons of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0181] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which electrons are supported to flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) can be open or closed at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, e.g., using one or more intervening components such as switches or transistors.

[0182] The term "coupled" refers to the condition of moving from an open relationship between components, in which signals cannot currently be conveyed between the components through a conductive path, to a closed relationship between the components, in which signals can be conveyed between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path through which signals were not previously permitted to flow.

[0183] Two or more actions can be performed "in parallel" if the actions are performed at the same time, at substantially the same time, at partially overlapping times, or at completely overlapping times.

[0184] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0185] In the drawings, like reference numerals can be used to denote similar components throughout the several views. Additionally, various components of the same type can be distinguished from each other by following the convention of using the first three characters of the reference label to indicate the component type. Where component types have been distinguished using only the first character or characters of a reference label, the different instance can be referred to by appending a different character or characters to the reference label, consistent with the assignment of reference labels described herein. For example, a first component of a type can be referred to as 101, a second component of the same type can be referred to as 102, and a third component of the same type can be referred to as 103.

[0186] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0187] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0188] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0189] Computer-readable media includes both non-transitory computer-readable storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0190] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a computational operation on data representing a first contiguous set of bits of a vector, the vector being an operand for the computational operation, the data representing the first contiguous set of bits stored in a first plane of a tile of the plurality of tiles, wherein the computational operation comprises an arithmetic operation; communicate a carry bit resulting from performing the arithmetic operation on the first contiguous set of bits from the first plane of the tile to a second plane of the tile; and perform the computational operation on data representing a second contiguous set of bits of the vector based at least in part on performing the computational operation on the data representing the first contiguous set of bits, the data representing the second contiguous set of bits stored in the second plane of the tile of the plurality of tiles, wherein the arithmetic operation on the data representing the second contiguous set of bits is based at least in part on the carry bit.

2. The apparatus of claim 1, wherein the logic is further configured to: write data representing a result of the computational operation on the first contiguous set of bits to the first plane of the tile; and write data representing a result of the computational operation on the second contiguous set of bits to the second plane of the tile.

3. The apparatus of claim 1, wherein the vector comprises a plurality of elements each having a respective length, and wherein a first element of the vector comprises the first contiguous set of bits and the second contiguous set of bits.

4. The apparatus of claim 1, wherein the logic is further configured to: perform a second computational operation on data representing a first contiguous set of bits of a second vector, the data representing the first contiguous set of bits of the second vector stored in a first plane of a second tile; and perform the second computational operation on data representing a second contiguous set of bits of the second vector based at least in part on performing the second computational operation on the first contiguous set of bits of the second vector, the data representing the second contiguous set of bits of the second vector stored in a second plane of the second tile.

5. The apparatus of claim 4, wherein the logic is further configured to: perform the second computational operation on the data representing the first contiguous set of bits of the second vector in parallel with performing the computational operation on the data representing the first contiguous set of bits of the vector; and perform the second computational operation on the data representing the second contiguous set of bits of the second vector in parallel with performing the computational operation on the data representing the second contiguous set of bits of the vector.

6. The apparatus of claim 1, wherein the logic is further configured to: performing the compute operation on data representing a first contiguous bit set of a second vector, the second vector being an operand for the compute operation, the data representing the first contiguous bit set of the second vector stored in the first plane of the tile; and performing the compute operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in the second plane of the tile.

7. The apparatus of claim 1, wherein the logic is further configured to: perform a second compute operation on data representing a first contiguous bit set of a second vector stored in a second plane of a second tile using associative processing and in parallel with performing the compute operation on the data representing the first contiguous bit set of the vector.

8. The apparatus of claim 1, wherein the logic is further configured to: receive signaling from a host device indicating an instruction set, the instruction set indicating the vector and the compute operation; and write data representing the vector to the first plane and the second plane according to a vector mapping scheme and based at least in part on the instruction set.

9. The apparatus of claim 1, wherein the compute operation comprises a logical operation or an arithmetic operation.

10. The apparatus of claim 1, wherein the memory die is configured such that a single plane per tile can be operated on for associative processing at the same time.

11. An apparatus comprising: a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a compute operation on data representing a first contiguous bit set of a vector using associative processing, the vector being an operand for the compute operation, the data representing the first contiguous bit set stored in a first plane of a first tile of the plurality of tiles, wherein the compute operation comprises an arithmetic operation; communicate a carry bit resulting from performing the arithmetic operation on the data representing the first contiguous bit set from the first plane of the first tile to a first plane of a second tile; and perform the compute operation on data representing a second contiguous bit set of the vector using associative processing based at least in part on performing the compute operation on the first contiguous bit set, the data representing the second contiguous bit set stored in the first plane of the second tile of the plurality of tiles, wherein the arithmetic operation on the data representing the second contiguous bit set is based at least in part on the carry bit.

12. The apparatus of claim 11, wherein the logic is further configured to: write data representing a result of the compute operation on the data representing the first contiguous bit set to the first plane of the first tile; and write data representing a result of the compute operation on the data representing the second contiguous bit set to the first plane of the second tile.

13. The apparatus of claim 11, wherein the vector comprises a plurality of elements each having a respective length, and wherein a first element of the vector comprises the first contiguous bit set and the second contiguous bit set.

14. The apparatus of claim 11, wherein the logic is further configured to: perform a second computational operation on data representing a first contiguous bit set of a second vector, the data representing the first contiguous bit set of the second vector stored in a second plane of the first tile; and perform the second computational operation on data representing a second contiguous bit set of the second vector based at least in part on performing the second computational operation on the data representing the first contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in a second plane of the second tile.

15. The apparatus of claim 11, wherein the logic is further configured to: perform the computational operation on data representing a first contiguous bit set of a second vector, the second vector being an operand for the computational operation, the data representing the first contiguous bit set of the second vector stored in the first plane of the first tile; and perform the computational operation on data representing a second contiguous bit set of the second vector, the data representing the second contiguous bit set of the second vector stored in the first plane of the second tile.

16. The apparatus of claim 11, wherein the logic is further configured to: perform a second computational operation on data representing a first contiguous bit set of a second vector stored in a second plane of the first tile in parallel with performing the computational operation on the data representing the second contiguous bit set of the vector using an associative process.

17. The apparatus of claim 11, wherein the logic is further configured to: perform a logical operation on data representing the second contiguous bit set in parallel with performing the logical operation on the data representing the first contiguous bit set based at least in part on the computational operation comprising the logical operation.

18. The apparatus of claim 11, wherein the logic is further configured to: receive signaling from a host device indicating an instruction set, the instruction set indicating the vector and the computational operation; and write data representing the vector to the first plane of the first tile and the first plane of the second tile according to a vector mapping scheme and based at least in part on the instruction set.

19. An apparatus comprising: a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a computational operation on data representing a first contiguous bit set of a vector, the data representing the first contiguous bit set of the vector stored in a first plane of a first tile of the memory die; and perform the computational operation on data representing a second contiguous bit set of the vector based at least in part on performing the computational operation on the data representing the first contiguous bit set of the vector, the data representing the second contiguous bit set of the vector stored in a first plane of a second tile of the memory die. performing the compute operation on data representing a first contiguous bit set of a first vector and data representing a first contiguous bit set of a second vector based at least in part on a truth table indicating results of the compute operation for various logical value combinations, the data representing the first contiguous bit set stored in a first plane of a tile of the plurality of tiles; communicating a carry bit resulting from performing the compute operation on the data representing the first contiguous bit set from the first plane of the tile to a second plane of the tile; and performing the compute operation on data representing a second contiguous bit set of the first vector and data representing a second contiguous bit set of the second vector based at least in part on the truth table for the compute operation, the data representing the second contiguous bit set stored in the second plane of the second tile, wherein the compute operation performed on the data representing the second contiguous bit set is based at least in part on the carry bit.

20. The apparatus of claim 19, wherein the logic is further configured to: perform a second compute operation on data representing a first contiguous bit set of a third vector stored in a first plane of a second tile in parallel with performing the compute operation on the data representing the first contiguous bit set.

21. The apparatus of claim 19, wherein the logic is further configured to: receive signaling from a host device indicating an instruction set, the instruction set indicating the first vector, the second vector, and the compute operation; and write the data representing the first contiguous bit set to the first plane of the tile and the data representing the second contiguous bit set to the second plane of the tile based at least in part on the instruction set.

22. An apparatus comprising: a memory die comprising a plurality of tiles, the plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content addressable memory cells; and logic coupled with the memory die and configured to: perform a compute operation on data representing a first contiguous bit set of a first vector and data representing a first contiguous bit set of a second vector based at least in part on a truth table indicating results of the compute operation for various logical value combinations, the data representing the first contiguous bit set stored in a first plane of a first tile of the plurality of tiles; communicate a carry bit resulting from performing the compute operation on the data representing the first contiguous bit set from the first plane of the first tile to a first plane of a second tile; and perform the compute operation on data representing a second contiguous bit set of the first vector and data representing a second contiguous bit set of the second vector based at least in part on the truth table for the compute operation, the data representing the second contiguous bit set stored in the first plane of the second tile, wherein the compute operation performed on the data representing the second contiguous bit set is based at least in part on the carry bit.

23. The apparatus of claim 22, wherein the logic is further configured to: perform a second compute operation on data representing a first set of contiguous bits of a third vector stored in a second plane of the first tile in parallel with performing the compute operation on the data representing the second set of contiguous bits.

24. The apparatus of claim 22, wherein the logic is further configured to: receive signaling from a host device indicating an instruction set, the instruction set indicating the first vector, the second vector, and the compute operation; and write the data representing the first set of contiguous bits to the first plane of the first tile and the data representing the second set of contiguous bits to the first plane of the second tile based at least in part on the instruction set.

25. A method comprising: performing a compute operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table indicating results of the compute operation for various combinations of logic values, the data representing the first set of contiguous bits stored in a first plane of a first tile of a plurality of tiles; communicating a carry bit resulting from performing the compute operation on the data representing the first set of contiguous bits from the first plane of the first tile to a first plane of a second tile; and performing the compute operation on data representing a second set of contiguous bits of the first vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the compute operation, the data representing the second set of contiguous bits stored in the first plane of the second tile of the plurality of tiles, wherein the compute operation performed on the data representing the second set of contiguous bits is based at least in part on the carry bit.

26. The method of claim 25, further comprising: performing a second compute operation on data representing a first set of contiguous bits of a third vector stored in a second plane of the first tile in parallel with performing the compute operation on the data representing the second set of contiguous bits.

27. The method of claim 25, further comprising: receiving signaling from a host device indicating an instruction set, the instruction set indicating the first vector, the second vector, and the compute operation; and writing the data representing the first set of contiguous bits to the first plane of the first tile and the data representing the second set of contiguous bits to the first plane of the second tile based at least in part on the instruction set.

28. A method comprising: performing a compute operation on data representing a first set of contiguous bits of a first vector and data representing a first set of contiguous bits of a second vector based at least in part on a truth table indicating results of the compute operation for various combinations of logic values, the data representing the first set of contiguous bits stored in a first plane of a memory die including a plurality of tiles, the plurality of tiles each including a plurality of planes; communicating a carry bit resulting from performing the compute operation on the data representing the first set of contiguous bits from the first plane to a second plane; and performing the compute operation on data representing a second set of contiguous bits of a second vector and data representing a second set of contiguous bits of the second vector based at least in part on the truth table for the compute operation, the data representing the second set of contiguous bits stored in the second plane of the memory die, wherein the compute operation performed on the data representing the second set of contiguous bits is based at least in part on the carry bit.

29. The method of claim 28, wherein the first plane and the second plane have a same tile.

30. The method of claim 28, wherein the first plane has a first tile and the second plane has a second tile.

31. The method of claim 28, wherein the first plane and the second plane have a first tile, the method further comprising: performing a second compute operation on data representing a first set of contiguous bits of a third vector stored in a first plane of a second tile in parallel with performing the compute operation on the data representing the first set of contiguous bits.

32. The method of claim 28, wherein the first plane has a first tile and the second plane has a second tile, the method further comprising: performing a second compute operation on data representing a first set of contiguous bits of a third vector stored in a second plane of the first tile in parallel with performing the compute operation on the data representing the second set of contiguous bits.

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