Display module and display device

Abstract

The present invention provides a display module and a display device. The display module includes a chamfering circuit, and the chamfering circuit includes a detection module that outputs a control signal according to the rising edge of a clock input signal. The control signal includes a first control signal and a second control signal. A first output module is configured to output a third clock voltage to a clock signal output terminal according to the first control signal. A second output module is configured to output the clock input signal to the clock signal output terminal according to the second control signal. Within one clock cycle of the clock output signal, the clock output signal sequentially has a first clock voltage, a third clock voltage, and a second clock voltage. By reducing the duration of the second clock voltage of the clock output signal without changing the duration of the high level of the clock output signal, the resistive power consumption of the WOA is effectively reduced, thereby reducing the WOA temperature. And since the duration of the high level of the clock output signal is not changed, the influence on the charging rate of the pixel unit is small.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display module and a display device. Background Art

[0002] With the increasing demands of users for the refresh rate, resolution, and narrow bezel of liquid crystal display screens, the temperature and power consumption of WOA (Wire On Array) also increase accordingly. However, too high a temperature of WOA may cause risks such as the polarizer being burned out. Summary of the Invention

[0003] An embodiment of the present invention provides a display panel to reduce the temperature of WOA.

[0004] To solve the above problems, the technical solutions provided by the present invention are as follows:

[0005] A display module includes a display panel and a control circuit board. The display panel includes a gate driving circuit. The control circuit board includes:

[0006] A chamfering circuit, including:

[0007] A detection module for outputting a control signal according to the rising edge of a clock input signal. The control signal includes a first control signal and a second control signal. The clock input signal has a first clock voltage and a second clock voltage that change periodically, and the first clock voltage is less than the second clock voltage;

[0008] A first output module for outputting a third clock voltage to a clock signal output terminal according to the first control signal. The third clock voltage is greater than the first clock voltage and less than the second clock voltage;

[0009] A second output module for outputting the clock input signal to the clock signal output terminal according to the second control signal;

[0010] Wherein, the clock signal output terminal is electrically connected to the gate driving circuit to transmit a clock output signal. Within one clock cycle of the clock output signal, the clock output signal sequentially has the first clock voltage, the third clock voltage, and the second clock voltage.

[0011] According to a preferred embodiment of the present invention, the first output module includes a first transistor. A first end of the first transistor is used to receive the third clock voltage. A second end of the first transistor is electrically connected to the clock signal output terminal. A control end of the first transistor is electrically connected to the detection module to turn on the first transistor under the control of the first control signal.

[0012] According to a preferred embodiment of the present invention, the chamfering circuit further includes a delay module, and the first output module further includes a second transistor. A first end of the second transistor is electrically connected to the second end of the first transistor. A second end of the second transistor is electrically connected to the clock signal output terminal to electrically connect the first transistor and the clock signal output terminal. A control end of the second transistor is electrically connected to the detection module to turn on the second transistor under the control of the first control signal. The delay module is electrically connected to a connection node between the second end of the first transistor and the first end of the second transistor to control the voltage rising rate of the connection node.

[0013] According to a preferred embodiment of the present invention, the delay module includes a first resistor and a delay capacitor. A first end of the first resistor is electrically connected to the second end of the first transistor. A second end of the first resistor is electrically connected to a first end of the delay capacitor. A second end of the delay capacitor receives a fourth voltage, and the fourth voltage is less than the third clock voltage.

[0014] According to a preferred embodiment of the present invention, the second output module includes a third transistor. A first end of the third transistor is configured to receive the clock input signal. A second end of the third transistor is electrically connected to the clock signal output terminal. A control end of the third transistor is electrically connected to the detection module to turn on the third transistor under the control of the second control signal.

[0015] According to a preferred embodiment of the present invention, the chamfering circuit further includes a second resistor. A first end of the second resistor is electrically connected to the control ends of the first transistor, the second transistor, and the third transistor. A second end of the second resistor is grounded.

[0016] According to a preferred embodiment of the present invention, the second output module further includes an inverter. An input end of the inverter is electrically connected to the detection module to receive the second control signal. An output end of the inverter is electrically connected to the control end of the third transistor. The first transistor, the second transistor, and the third transistor are transistors of the same type.

[0017] According to a preferred embodiment of the present invention, the first transistor and the second transistor are N-type transistors, and the third transistor is a P-type transistor.

[0018] According to a preferred embodiment of the present invention, the duration of the second clock voltage of the clock input signal is T1, and the duration of the first control signal is 15%-20% of the T1.

[0019] An embodiment of the present invention further provides a display device, including the display module described in any one of the above embodiments.

[0020] The beneficial effects of the present invention are as follows: by reducing the duration of the second clock voltage of the clock output signal and without changing the duration of the high level of the clock output signal, the resistive power consumption of the WOA is effectively reduced, thereby reducing the temperature of the WOA. And since the duration of the high level of the clock output signal is not changed, the influence on the charging rate of the pixel unit is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Attached Figure 1 is a schematic structural diagram of the chamfering circuit of the present invention;

[0023] Attached Figure 2 is a schematic flow diagram of the chamfering circuit of the present invention;

[0024] Attached Figure 3 is a schematic circuit diagram of the chamfering circuit of the present invention;

[0025] Attached Figure 4 is a waveform diagram of the clock output signal CK of the prior art out1 ;

[0026] Attached Figure 5 is a waveform diagram of the clock output signal CK of the present invention out ;

[0027] Attached Figure 6 is a waveform diagram of the clock output signal CK of the present invention out in another form;

[0028] Attached Figure 7 is a point position diagram of the test points for testing the charging rate of the pixel unit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0030] With the increasing demands for the refresh rate, resolution, and narrow bezel of liquid crystal display panels, the temperature and power consumption of the WOA in the panel also increase when implementing the above demands. This embodiment provides a display module to reduce the temperature of the WOA in the panel.

[0031] A display module includes a display panel and a control circuit board. The display panel includes a gate driving circuit, a data driving circuit, and a plurality of pixel units arranged in an array. The gate driving circuit includes a plurality of cascaded gate driving units, and each gate driving unit is connected to a clock signal output terminal to receive a clock output signal CK out , and each gate driving unit includes a scan signal line for transmitting a scan signal to the plurality of pixel units. The data driving circuit includes a plurality of data lines for transmitting data signals to the plurality of pixel units. The plurality of pixel units emit light under the action of the scan signal and the data signal.

[0032] As Figure 1 shown, the control circuit board includes a chamfering circuit for providing the clock output signal CK to the gate driving circuit out , and the chamfering circuit includes a clock signal input terminal, a detection module 10, a first output module 20, a second output module 30, and the clock signal output terminal.

[0033] The clock signal input terminal is used to input a clock input signal CK in , and the clock input signal CK in has a first clock voltage V ck1 and a second clock voltage V ck2 with a periodic change. The first clock voltage V ck1 is less than the second clock voltage V ck2 . When the first clock voltage V ck1 rises to the second clock voltage V ck2 , it is the rising edge of the clock input signal CK in . When the second clock voltage V ck2 drops to the first clock voltage V ck1 , it is the falling edge of the clock input signal CK in . The second clock voltage V ck2 can enable the gate driving circuit to output a scan signal to control the pixel unit to start charging.

[0034] As Figure 1 , Figure 2 shown, the detection module 10 is electrically connected to the clock signal input terminal and is used to according to the clock input signal CK inThe rising-edge output control signal K, where the control signal K includes a first control signal and a second control signal. For example, in this embodiment, when the detection module 10 detects the rising edge of the clock input signal CK in , it outputs the first control signal with a duration of T, and then outputs the second control signal. It should be noted that the duration T of the first control signal is less than the duration T1 of any of the second clock voltages V in of the clock input signal CK ck2 , that is, less than the high-level duration of the clock input signal CK in .

[0035] Both the first output module 20 and the second output module 30 are electrically connected to the detection module 10. The first output module 20 outputs a third clock voltage V in to the clock signal output terminal. The third clock voltage V in is greater than the first clock voltage V ck1 , less than the second clock voltage V ck2 , and the third clock voltage V in can also cause the gate drive circuit to output the scan signal to control the pixel unit to charge.

[0036] The second output module 30 outputs the clock input signal CK in to the clock signal output terminal. It can be known that the clock output signal CK out output by the clock signal output terminal is composed of the first clock voltage V ck1 , the second clock voltage V ck2 , and the third clock voltage V in .

[0037] Specifically, as Figure 5 shown, when the detection module 10 detects the rising edge of the clock input signal CK in , the detection module 10 outputs the first control signal to cause the first output module 20 to output the third clock voltage V in to the clock signal output terminal. The clock signal output terminal outputs the third clock voltage V in , that is, at this time, the clock output signal CK out has the third clock voltage V in . When the duration T of the first control signal ends, the detection module 10 outputs the second control signal to cause the second output module 30 to output the clock input signal CK into the clock signal output terminal. Since the duration T of the first control signal is less than the duration T1 of any of the clock input signals CK in of the second clock voltage V ck2 , therefore, at this time, the clock input signal CK in is still the second clock voltage V ck2 , and the clock signal output terminal outputs the second clock voltage V ck2 , that is, the clock output signal CK out at this time has the second clock voltage V ck2 . When the falling edge of the clock input signal CK in arrives, the clock input signal CK in drops from the second clock voltage V ck2 to the first clock voltage V ck1 , and the clock signal output terminal outputs the first clock voltage V ck1 , that is, the clock output signal CK out at this time has the first clock voltage V ck1 . When each rising edge and falling edge arrives, the above process will be repeated. Therefore, within one clock period of the clock output signal CK out , the clock output signal CK out successively has the first clock voltage V ck1 , the third clock voltage V in and the second clock voltage V ck2 , the first clock voltage V ck1 .

[0038] It can be known that, compared with the clock output signal CK out in the prior art (such as Figure 4 ), the clock output signal CK out in this embodiment reduces the duration of the second clock voltage V ck2 without reducing the high-level duration. According to the resistor heating power formula:

[0039]

[0040] P is the heating power of the trace in the display panel, U is the voltage of the clock output signal CK out , and R is the equivalent resistance of the trace in the display panel. It can be seen that reducing the duration of the second clock voltage V ck2 can effectively reduce the resistance power consumption of WOA, thereby reducing the temperature. And since the high-level duration of the clock output signal CK out is not changed, and the third clock voltage V inIt can also enable the gate driving circuit to control the pixel unit to start charging, resulting in a relatively small impact on the charging rate of the pixel unit.

[0041] In this embodiment, by reducing the out duration of the second clock voltage V of the clock output signal CK ck2 and without changing the duration of the high level of the clock output signal CK out effectively reduces the resistive power consumption of the WOA, thereby reducing the WOA temperature. And since the duration of the high level of the clock output signal CK out is not changed, the impact on the charging rate of the pixel unit is relatively small.

[0042] As Figure 3 shown, in some embodiments of the present invention, the first output module 20 includes a first transistor Q1. The first end of the first transistor Q1 is electrically connected to the third power signal line to receive the third clock voltage V in , the second end of the first transistor Q1 is electrically connected to the clock signal output terminal, and the control end of the first transistor Q1 is electrically connected to the detection module 10 to be turned on under the control of the first control signal.

[0043] In this embodiment, when the detection module 10 detects the rising edge of the clock input signal CK in , it outputs the first control signal, and the first transistor Q1 is turned on, outputting the third clock voltage V in to the clock signal output terminal, so that the clock signal has the third clock voltage V in after the rising edge. It can be known that the first control signal has a first control voltage K1 that turns on the first transistor Q1.

[0044] As Figure 3 shown, in some embodiments of the present invention, the chamfering circuit further includes a delay module 40. The first output module 20 further includes a second transistor Q2. The first end of the second transistor Q2 is electrically connected to the second end of the first transistor Q1. The second end of the second transistor Q2 is electrically connected to the clock signal output terminal to electrically connect the first transistor Q1 and the clock signal output terminal. The control end of the second transistor Q2 is electrically connected to the detection module 10 to be turned on under the control of the first control signal. The first end of the delay module 40 is electrically connected to the connection node of the second end of the first transistor Q1 and the first end of the second transistor Q2. When the first transistor Q1 is turned on, it outputs the third clock voltage V inWhen the time is up, the delay module 40 becomes effective, so that the first end of the second transistor Q2 is delayed to reach the third clock voltage V in , that is, after the first transistor Q1 is turned on, the second transistor Q2 will not immediately have the third clock voltage V in , but gradually rises to the third clock voltage V under the delay effect of the delay module 40 in . Similarly, the clock signal output terminal also gradually rises to the third clock voltage V in , that is, the clock output signal CK out rises from the first clock voltage V ck1 to the third clock voltage V in . At this time, the waveform diagram of the clock output signal CK out is as shown in Figure 6 .

[0045] In this embodiment, the rising slope of the clock output signal CK is controlled by the delay module 40, and then the rising slope of the clock output signal CK out is controlled, so that the clock output signal CK out is changed from the first clock voltage V ck1 to the third clock voltage V in . The time of transformation can flexibly control the waveform of the clock output signal CK out .

[0046] Specifically, the delay module 40 in this embodiment includes a first resistor R1 and a delay capacitor C. The first end of the first resistor R1 is electrically connected to the second end of the first transistor Q1, the second end of the first resistor R1 is electrically connected to the first end of the delay capacitor C, the second end of the delay capacitor C receives the fourth voltage, and the fourth voltage is less than the third clock voltage. For example, the second end of the delay capacitor C is grounded.

[0047] It can be known that since the fourth voltage is less than the third voltage, when the first transistor Q1 is turned on and outputs the third clock voltage V in to the first end of the second transistor Q2, the first end of the delay capacitor C will be charged simultaneously. As the charging progresses, the voltage at the first end of the second transistor Q2 will gradually rise until the first end of the delay capacitor C is charged to the third clock voltage V in , and the second transistor Q2 can input the third clock voltage V in completely to the clock signal output terminal. Therefore, the clock output signal CK out will rise from the first clock voltage V ck1 to the third clock voltage V in at a certain slope, the slope is determined by the values of the first resistor R1 and the delay capacitor C. After understanding the concept of this application, those skilled in the art can adjust the values of the first resistor R1 and the delay capacitor C to obtain the required slope, which will not be elaborated here.

[0048] As Figure 3 shown, in an embodiment of the present invention, the second output module 30 includes a third transistor Q3, and a first end of the third transistor Q3 is used to receive the clock input signal CK in , a second end of the third transistor Q3 is electrically connected to the clock signal output end, and a control end of the third transistor Q3 is electrically connected to the detection module 10 to be turned on under the control of the second control signal. It can be known that the second control signal has a second control voltage K2 for turning on the third transistor Q3.

[0049] In this embodiment, when the detection module 10 detects the rising edge of the clock input signal CK in and outputs the first control signal with a duration of T, the detection module 10 outputs the second control signal, so that the third transistor Q3 is turned on to transmit the clock input signal CK in to the clock signal output end. Since the duration T of the first control signal is less than the duration T1 of any of the second clock voltages V in of the clock input signal CK ck2 , at this time, the clock input signal CK in is still the second clock voltage V ck2 , and the clock signal output end outputs the second clock voltage V ck2 , that is, the clock output signal CK out at this time has the second clock voltage V ck2 . When the falling edge of the clock input signal CK in arrives, the clock input signal CK in drops from the second clock voltage V ck2 to the first clock voltage V ck1 , and the clock signal output end outputs the first clock voltage V ck1 , then the clock output signal CK out at this time has the first clock voltage V ck1 .

[0050] When each rising edge and falling edge arrives, the above process will be repeated. Therefore, within one clock cycle of the clock output signal CK out , the clock output signal CK out sequentially has the first clock voltage Vck1 and the third clock voltage V in and the second clock voltage V ck2 and the first clock voltage V ck1 .

[0051] As Figure 3 shown, in some embodiments of the present invention, the first transistor Q1 and the second transistor Q2 are N-type transistors, and the third transistor Q3 is a P-type transistor. When the detection module 10 detects the rising edge of the clock input signal CK in , the detection module 10 outputs the first control signal with a duration of T to turn on the first transistor Q1 and the second transistor Q2, and then outputs the second control signal to turn on the third transistor Q3. Therefore, the first control voltage K1 of the first control signal is higher than the second control voltage K2 of the second control signal. Then, after detecting the rising edge of the clock input signal CK in , the control signal K has the first control voltage K1 with a duration of T, and the waveform diagram of the control signal K is as Figure 6 shown.

[0052] In this embodiment, in order to quickly turn off the first transistor Q1 and the second transistor Q2 under the control of the second control signal, and quickly turn on the third transistor Q3 under the control of the second control signal, the control ends of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are grounded through a resistor. Specifically, the chamfering circuit further includes a second resistor R2. The first end of the second resistor R2 is electrically connected to the control ends of the first transistor Q1, the second transistor Q2, and the third transistor Q3, and the second end of the second resistor R2 is grounded. The above setting can enable the third transistor Q3 to be quickly turned on, so as to output the clock input signal CKin to the clock signal output terminal, ensuring the stability of the clock output signal CK out .

[0053] In the above embodiment, the types of the first transistor Q1 and the second transistor Q2 are different from those of the third transistor Q3 (N-type or P-type). In this embodiment, in order to unify the types of the first transistor Q1, the second transistor Q2, and the third transistor Q3 to ensure the stability of the entire circuit, the second output module 30 further includes an inverter D. The input end of the inverter D is electrically connected to the detection module 10, and the output end of the inverter D is electrically connected to the control end of the third transistor Q3. The first transistor Q1, the second transistor Q2, and the third transistor Q3 can all be N-type transistors or P-type transistors.

[0054] In the above embodiments, the duration T of the first control signal is 15%-20% of the duration T1 of the second clock voltage V of the clock input signal CK, preferably, T / T1 = 18%. in of the clock input signal CK ck2 of the second clock voltage V

[0055] In the above embodiments, the function of the detection module 10, i.e., rising edge detection and outputting a control signal K for a period of time after detection, is implemented based on a power management chip of model VPMS3SM. After those skilled in the art know the function of the detection module 10 of the present application, they are capable of using other detection circuits with rising edge detection and outputting a control signal for a certain period of time according to the detection result, which will not be elaborated here.

[0056] The following Table 1 shows the WOA temperature test of three display modules OC1, OC2, and OC3 with a size of 65 inches and a 4K resolution at a refresh rate of 120 Hz. Test conditions: ambient temperature 45°C, the low potential of the clock output signal CK of the display module of the present application out is -10V (the first clock voltage V ck1 ), and the high potentials are 12V (the third clock voltage V in ), 30V (the second clock voltage V ck2 ) in sequence. The low potential of the clock output signal CK of the display module of the prior art out is -10V, and the high potential is 30V.

[0057] Display module OC1 OC2 OC3 WOA temperature of the present application / °C 36.1 36.1 35.4 WOA temperature of the existing one / °C 37.5 36.7 36.7 Difference / °C 1.4 0.6 1.3

[0058] Table 1

[0059] The following Table 2 shows the WOA temperature test of three display modules OC1, OC2, and OC3 with a size of 65 inches and an 8K resolution at a refresh rate of 120 Hz. The test conditions are the same as above except that the ambient temperature is 60°C.

[0060] Display module OC1 OC2 OC3 WOA temperature of the present application / °C 52 55.9 54.4 WOA temperature of the existing one / °C 55.4 58.7 57.9 Difference / °C 3.4 2.8 3.5

[0061] Table 2

[0062] It can be seen from the above test results that the solution of the present application can effectively reduce the WOA temperature, and has a greater improvement for products with an 8K resolution and 120 Hz.

[0063] The present application also tested the charging rate of 9 points (as shown in Figure 7 ) of a display module with a size of 65 inches, a 4K resolution, and a refresh rate of 120 Hz. The formula for the test is: charging rate = heavy load brightness / light load brightness. The test results are shown in Table 3 below:

[0064]

[0065] Table 3

[0066] As can be seen from the above test results, the solution of the present application has little influence on the charging rate of the pixel unit.

[0067] An embodiment of the present invention further provides a display device, including the display panel described in any one of the above embodiments.

[0068] In summary, although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims

1. A display module, characterized in that, It includes a display panel and a control circuit board. The display panel includes a gate driving circuit. The control circuit board includes: A chamfering circuit, including: A detection module, configured to output a control signal according to the rising edge of a clock input signal. The control signal includes a first control signal and a second control signal. The clock input signal has a first clock voltage and a second clock voltage with a periodic change, and the first clock voltage is less than the second clock voltage; A first output module, configured to output a third clock voltage to a clock signal output terminal according to the first control signal. The third clock voltage is greater than the first clock voltage and less than the second clock voltage; A second output module, configured to output the clock input signal to the clock signal output terminal according to the second control signal; Wherein, the clock signal output terminal is electrically connected to the gate driving circuit to transmit a clock output signal. Within one clock period of the clock output signal, the clock output signal sequentially has the first clock voltage, the third clock voltage, and the second clock voltage; The first output module includes a first transistor. A first end of the first transistor is configured to receive the third clock voltage. A second end of the first transistor is electrically connected to the clock signal output terminal. A control end of the first transistor is electrically connected to the detection module to turn on the first transistor under the control of the first control signal; The chamfering circuit further includes a delay module. The first output module further includes a second transistor. A first end of the second transistor is electrically connected to the second end of the first transistor. A second end of the second transistor is electrically connected to the clock signal output terminal to electrically connect the first transistor to the clock signal output terminal. A control end of the second transistor is electrically connected to the detection module to turn on the second transistor under the control of the first control signal. The delay module is electrically connected to a connection node between the second end of the first transistor and the first end of the second transistor to control the voltage rising rate of the connection node.

2. The display module according to claim 1, characterized in that, The delay module includes a first resistor and a delay capacitor. A first end of the first resistor is electrically connected to the second end of the first transistor. A second end of the first resistor is electrically connected to a first end of the delay capacitor. A second end of the delay capacitor receives a fourth voltage, and the fourth voltage is less than the third clock voltage.

3. The display module according to claim 2, characterized in that, The second output module includes a third transistor. A first end of the third transistor is configured to receive the clock input signal. A second end of the third transistor is electrically connected to the clock signal output terminal. A control end of the third transistor is electrically connected to the detection module to turn on the third transistor under the control of the second control signal.

4. The display module according to claim 3, characterized in that, The chamfering circuit further includes a second resistor. A first end of the second resistor is electrically connected to the control ends of the first transistor, the second transistor, and the third transistor. A second end of the second resistor is grounded.

5. The display module according to claim 4, characterized in that, The second output module further includes an inverter. The input end of the inverter is electrically connected to the detection module to receive the second control signal, and the output end of the inverter is electrically connected to the control end of the third transistor. The first transistor, the second transistor, and the third transistor are transistors of the same type.

6. The display module according to claim 5, characterized in that, The first transistor and the second transistor are N-type transistors, and the third transistor is a P-type transistor.

7. The display module according to claim 1, characterized in that, The duration of the second clock voltage of the clock input signal is T1, and the duration of the first control signal is 15%-20% of the T1.

8. A display device, characterized in that, A display module includes the display module according to any one of claims 1-7.

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