Cross temperature management on the die of memory devices

Abstract

This application relates to on-die crossover temperature management of a memory device. Control logic in the memory device receives a request to read data from a memory array, the request including an indication of a segment of the memory array in which the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. In response to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a crossover temperature of the data based on the write temperature and a read temperature at the time the request to read the data is received, determines a program / erase cycle count associated with the segment of the memory array, and determines whether to perform a calibration action to calibrate the read voltage level to be applied to the memory array to read the data from the segment based on the crossover temperature and the program / erase cycle count.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to on-die cross temperature management of memory devices for memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application relates to a memory device comprising: a memory array; and control logic operably coupled to the memory array to perform operations including: receiving a request to read data from the memory array, the request including an indication of a segment of the memory array in which the data is stored; determining whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array; in response to determining that the write temperature associated with the data is stored in the flag byte, determining a cross temperature of the data based on the write temperature and a read temperature at the time the request to read the data is received; determining a program / erase cycle count associated with the segment of the memory array; and determining whether to perform a calibration action to calibrate a read voltage level to be applied to the memory array to read the data from the segment based on the cross temperature and the program / erase cycle count.

[0004] In another aspect, this application relates to a method comprising: receiving a request to read data from a memory array of a memory device, the request including an indication of a segment of the memory array in which the data is stored; determining whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array; in response to determining that the write temperature associated with the data is stored in the flag byte, determining a cross temperature of the data based on the write temperature and a read temperature at the time the request to read the data is received; determining a program / erase cycle count associated with the segment of the memory array; and determining, based on the cross temperature and the program / erase cycle count, whether to perform a calibration action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

[0005] In another aspect, this application relates to a memory device comprising: a memory array; and control logic operably coupled to the memory array to perform operations including: receiving a request to program data into the memory array, the request including an indication of a program / erase cycle count associated with a segment of the memory array in which the data is to be stored; determining a write temperature at the time the request to program the data is received; programming the data into the segment of the memory array; and programming the write temperature and the program / erase cycle count into a flag byte corresponding to the segment of the memory array. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of this disclosure may be used for reference. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 This is a flowchart of an example method for storing cross-temperature data on a memory device during programming operations, according to some embodiments of the present disclosure.

[0011] Figure 4 This is a flowchart of an example method for on-die cross temperature management of a memory device for a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] Various aspects of this disclosure relate to on-die cross-temperature management of memory devices for memory subsystems. A memory subsystem may be a memory device, a memory module, or a combination of both. Examples of memory devices and memory modules are described below with reference to Figure 1. Typically, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0014] A memory subsystem may contain high-density non-volatile memory devices where data is expected to be retained when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states related to the number of bits stored. Logical states may be represented as binary values, such as “0” and “1”, or combinations of such values.

[0015] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in arrays of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, used in conjunction with one or more bit lines to generate the address of each memory cell. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a unit in a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device to allow parallel operation on each plane.

[0016] When the corresponding threshold voltage (V) of two adjacent bit levels (also known as "states") t When there is insufficient separation between states, bit flip errors may occur in some memory devices. Typically, each binary value stored in a memory cell has a different associated threshold voltage, with the lowest binary value having the highest threshold voltage, the highest binary value having the lowest threshold voltage, and intermediate states having progressively different threshold voltage values. For example, a memory cell configured as a three-level cell (TLC) memory may have eight states, where each state has a corresponding V... t Similarly, a memory cell configured as a four-level cell (QLC) memory can have 16 states, where each state has a corresponding V. t In some memory devices, this can be achieved by applying a threshold voltage (V). t A better level separation in a distribution can reduce (e.g., minimize) bit flip errors. However, as more bits are stored per memory cell, the separation between two adjacent levels decreases.

[0017] In many memory devices, the level separation of the threshold voltage becomes further reduced (or shifted) due to changes in environmental conditions, such as cross-temperature effects. Cross-temperature negatively impacts level separation when memory cells operate (e.g., read) at a temperature range different from the temperature at which the memory cells are programmed. For example, cross-temperature effects can occur when data is read from a memory cell at a temperature different from the temperature at which data is written to the memory cell. Errors caused by cross-temperature can accumulate due to one or both of the offset levels across the threshold boundary, resulting in bit-flip errors and / or level overlap, leading to an increased number of bit-flip errors. The increased error rate reduces reliability and data retention. The data error rate also increases due to level shift and level overlap as the difference between the data write temperature and the data read temperature increases.

[0018] As the storage capacity of memory cells increases to store more bits, additional error correction operations can be used to meet the reliability requirements of the memory subsystem. For example, error correction codes (ECC) can be used to correct cross-temperature-dependent bit errors. Compared to SSDs using SLC, MLC, or TLC NAND flash memory, QLC NAND-based SSDs can utilize more complex error correction operations. Therefore, under certain cross-temperature conditions, a large number of error correction operations will be performed to correct cross-temperature-dependent bit flip errors. These error correction operations reduce the processing load in the memory subsystem and increase read command latency.

[0019] Some memory devices and memory subsystems attempt to reduce error rates using various techniques, including adjusting read voltage levels. This may involve determining a compensation offset value to account for a threshold voltage offset for a given memory cell. Since the threshold voltage offset can vary depending on process variations within each memory cell, the location of the memory cell (i.e., die-to-die changes), and the number of program / erase cycles performed on the cell, such calibration processes can be complex. For example, some memory devices perform instantaneous read voltage calibration to adjust the read voltage level applied during a read operation based on the ambient temperature at which the read operation is performed. Such devices typically do not consider the temperature at which the data being read was initially programmed and therefore do not address the specific issues associated with crossover temperature. Other memory devices do attempt to apply a read voltage offset based on crossover temperature; however, since most memory devices do not track the temperature at which data is written, they rely on the memory subsystem controller to determine the crossover temperature, which increases latency and complexity of read operations. Still other memory devices attempt to reduce error rates by calibrating the read voltage level based on the number of program / erase cycles performed on a given segment (e.g., a page or block) of the memory device. Because the number of programming / erase loops can vary greatly in each segment, this type of tracing can be complex and requires the memory subsystem to maintain a large number of expensive additional data structures.

[0020] The aspects of this disclosure address the above and other deficiencies by providing on-die cross-temperature management for the memory device of the memory subsystem. In one embodiment, when a write operation is performed to write host data to a page of the memory device, control logic on the memory device may store an indication of the temperature at which the data is written (i.e., the "write temperature") in a flag byte associated with a segment of the memory device. Additionally, the control logic may store an indication of the segment's program / erase cycle count in the flag byte. Depending on the embodiment, one or both of the write temperature and the program / erase cycle count may be directly tracked by the control logic on the memory device, or may be received from the memory subsystem controller or the host system that issues the write command associated with the write operation. This information may be retained in the flag byte on the memory device and may be quickly accessed later when reading the host data written to the segment and used for read voltage calibration.

[0021] When a read command is received at the memory device from a memory subsystem controller or host system, control logic on the memory device may identify a segment of the memory device to be read and determine whether the write temperature of the requested data is stored in a flag byte associated with the segment. If so, the control logic may determine the crossover temperature (i.e., the difference between the write temperature at the time the read command is received and the ambient temperature) and the number of program / erase cycles associated with the segment. Depending on the embodiment, the number of program / erase cycles may be read from the flag byte or received in conjunction with the read command. In one embodiment, using the crossover temperature and the number of program / erase cycles as input, the control logic may determine a read voltage offset (e.g., based on a lookup table or other data structure stored on the memory device). In one embodiment, the control logic may further determine whether the crossover temperature meets a threshold criterion (e.g., greater than or equal to a threshold level), and if so, determine whether the number of program / erase cycles meets a threshold criterion (e.g., greater than or equal to a threshold level). If both the crossover temperature and the number of program / erase cycles meet the respective threshold criteria, the control logic may take corrective action to calibrate the read voltage offset before applying a read voltage to the memory array of the memory device to read the requested data. Depending on the implementation, correction may include, for example, calibrating the read voltage offset during operation or enabling smarter and longer read commands that reduce the number of bit flips. Alternatively, if the write temperature is not stored in the flag byte, or the crossover temperature does not meet a threshold criterion (e.g., below a threshold level), the control logic may determine whether the ambient temperature at the time the read command is received meets a threshold criterion (e.g., above a high threshold or below a low threshold). If it does, the control logic may analyze the number of program / erase cycles, as described above, to determine whether to take corrective action. If the ambient temperature does not meet a threshold criterion (e.g., below a high threshold and above a low threshold), or the number of program / erase cycles does meet a threshold criterion (e.g., below a threshold level), the control logic may perform a read operation without calibrating the read voltage offset.

[0022] The advantages of this approach include, but are not limited to, improved memory device performance. The technique described herein provides a simple on-die cross-temperature solution that utilizes the write temperature, read temperature, and number of program / erase cycles for a given segment of the memory device. This approach detects workload conditions and adjusts read voltage offset and read commands to achieve a balance between performance and quality of service under both normal and extreme operating conditions. Longer latency and lower error rate commands can be selectively deployed only under stringent operating conditions to reduce the error handling trigger rate in the memory subsystem. Despite the longer latency, reducing the error handling trigger rate in this manner improves average throughput and quality of service. Therefore, normal latency read conditions are used at normal temperatures without affecting latency. The control logic on the memory device can selectively handle extreme conditions, meaning the memory device has more margin at one extreme temperature (e.g., high temperature, such as high temperature in a system without temperature regulation), while read calibration and corrective read operations can be deployed at the other extreme.

[0023] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can also utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. In general, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, or a QLC portion. Memory cells in the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] While a 3D cross-point array of non-volatile memory cells and a non-volatile memory component of NAND flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1A The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, unused cell collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0039] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 handles interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to a read command or confirmation that a programming command has been successfully executed. In some embodiments, memory subsystem controller 115 includes at least a portion of memory interface 113. For example, memory subsystem controller 115 may include processor 117 (e.g., processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, memory interface component 113 is part of host system 110, an application program, or an operating system.

[0040] In one embodiment, memory device 130 includes a local media controller 135 and a memory array 104. As described herein, memory array 104 may be logically or physically divided into several segments (e.g., dies, blocks, pages, etc.). Each segment may contain one or more flag bytes, which are restricted areas within memory array 104 storing system data or other metadata and are generally not accessible or usable by host system 120. In one embodiment, local media controller 135 may utilize the flag bytes in memory array 104 to store certain information associated with host data written to a corresponding segment of memory array 104. For example, in response to receiving a write (i.e., programming) request or command from memory interface 113, and upon performing a write operation corresponding to a request to write host data to a page of memory array 104, local media controller 135 may store an indication of the temperature at which the data was written (i.e., "write temperature") in the flag byte associated with said page. Additionally, local media controller 135 may store an indication of the page's programming / erase cycle count in the flag byte. Depending on the embodiment, one or both of the write temperature and the program / erase cycle count may be directly tracked by the local media controller 135 or received by the memory interface 113 along with the write request. This information may be stored in a flag byte on the memory device 130 and may be used for read voltage calibration when later reading host data written to the page. Because the write temperature and program / erase cycle count are stored in a flag byte on the memory device 130, the local media controller 135 can quickly and easily access the information in the flag byte when a read operation is performed later, perform associated calculations (e.g., determine the cross temperature, compare the cross temperature and / or the number of program / erase cycles with corresponding thresholds, etc.), and determine whether the calibration of the read voltage applied to the memory array 104 as part of the read operation is appropriate. In this way, the local media controller 135 can selectively take corrective action to adjust the read voltage level only when necessary (e.g., apply a read voltage offset to the default read voltage level), and can prevent increased latency when performing read operations that are associated with taking unauthorized corrective action and must access cross-temperature data and / or program / erase cycle counts from the memory subsystem controller 115. Further details regarding the operation of the local media controller 135 are described below.

[0041] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1AA simplified block diagram of communication between a second device and a memory subsystem controller 115 (of the memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0042] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the text) can be programmed as one of at least two target data states.

[0043] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 130 also includes an input / output (I / O) control circuitry 160 to manage inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. Address register 114 communicates with I / O control circuitry 160, row decoding circuitry 108, and column decoding circuitry 109 to latch the address signal before decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0044] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 109 to control them in response to addresses. As described herein, the local media controller 135 may utilize information stored in flag bytes 150 of memory array 104 to perform on-die cross-temperature management of memory device 130. In one embodiment, the local media controller 135 communicates with a temperature sensor 170 disposed within or adjacent to memory device 130. The temperature sensor 170 can be used to measure ambient temperature at certain points in time, which may represent, for example, write temperature or read temperature.

[0045] The local media controller 135 also communicates with cache register 172. Cache register 172 latches incoming or outgoing data as instructed by the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 172 to data register 170 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry system 160 into cache register 172. During read operations, data can be transferred from cache register 172 to I / O control circuitry system 160 for output to memory subsystem controller 115; then, new data can be transferred from data register 170 to cache register 172. Cache register 172 and / or data register 170 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may additionally include sensing devices (in... Figure 1B (Not shown in the diagram) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry system 160 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0046] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0047] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 160, and then written to command register 124. Addresses can be received at I / O control circuitry system 160 via the input / output (I / O) pins [7:0] of the I / O bus 134, and then written to address register 114. Data can be received at I / O control circuitry system 160 via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices, and then written to cache register 172. The data can then be written to data register 170 for programming memory cell array 104.

[0048] In this embodiment, cache register 172 may be omitted, and data may be written directly to data register 170. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0049] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functions of the various block components described do not necessarily need to be divided into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 1BThe functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0050] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of a memory cell array 104 (e.g., a NAND memory array) in a memory of the described type. The memory array 104 includes, for example, word lines 2020 to 202... N Access lines and, for example, bit lines 2040 to 204 M The data cable. Word line 202 can be connected in a many-to-one relationship to data cables not in... Figure 2 The global access lines (e.g., global word lines) shown in the diagram. In some embodiments, the memory array 104 may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or to have a conductivity type such as n-type conductivity to form an n-well.

[0051] The memory array 104 can be arranged in rows (each row corresponds to word lines 202) and columns (each column corresponds to bit lines 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 208 in each NAND string 206 may be connected in series, for example, via select gates 2100 to 210. M One of the selection gates 210 (e.g., a field-effect transistor) (e.g., it may be a source-select transistor, commonly referred to as a selection gate source) and, for example, selection gates 2120 to 212... M Between one of the selection gates 212 (e.g., a field-effect transistor) (e.g., it could be a drain-select transistor, often referred to as a select gate drain). Selection gates 2100 to 210 M They can be commonly connected to select line 214, such as the source select line (SGS), and select gates 2120 to 212. MThey can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0052] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 in the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0053] The drain of each select gate 212 can be connected to bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to memory cell 208 in the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to memory cell 208 in the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0054] Figure 2 The memory array 104 in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a generally parallel plane. Alternatively, Figure 2 The memory array 104 in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 extends substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204 (which may be substantially parallel to the plane containing the common source 216).

[0055] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., floating gate, charge trap, etc.) that can determine the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as... Figure 2As shown in the diagram. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may also have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0056] Columns of memory cells 208 may be selectively connected to NAND strings 206 or multiple NAND strings 206 given positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may contain, but does not need to contain, all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically contain memory cells 208 commonly connected to a given word line 202 every other one. For example, commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be memory cells 208 that are physical pages (e.g., even-numbered memory cells), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be a memory cell 208 of another physical page (e.g., an odd memory cell).

[0057] Although Figure 2 Although bit lines 2043 to 2045 are not explicitly depicted in the figure, it is evident from the figure that the bit lines 204 of the memory cell array 104 can be consecutively numbered from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered as a single physical page of memory cells. A portion of the physical page of a memory cell read during a single read operation or programmed during a single programmable operation (which in some embodiments may still be an entire line) (e.g., the upper or lower page of the memory cell) may be considered as a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. NAll memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, references to memory cell pages herein refer to the memory cells of the logical pages of the memory cells. This is in conjunction with the discussion of NAND flash memory. Figure 2 Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0058] Figure 3 This is a flowchart of an example method for storing cross-temperature data on a memory device during programming operations, according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1A and Figure 1B The local media controller 135 executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0059] At operation 305, a request is received. For example, control logic (e.g., local media controller 135) may receive a request to program data into a memory array (e.g., memory array 104) of a memory device (e.g., memory device 130). In one embodiment, the request is received from a requesting party such as memory interface 113 of memory subsystem controller 115 or host system 120. In one embodiment, the request includes data of a segment (e.g., page, block, etc.) to be programmed into memory device 130, such as host data or user data, and an indication of a program / erase (P / E) cycle count associated with the segment of data to be stored. In one embodiment, memory subsystem controller 115 tracks the number of program / erase cycles that have been performed on the segment during the lifetime of memory device 130 (e.g., by incrementing a corresponding counter). Depending on the embodiment, the program / erase cycle count included in the request indicates the number of previously performed program / erase cycles or the updated number of program / erase cycles (e.g., including programming operations to be performed in response to the current request).

[0060] At operation 310, the write temperature is determined. For example, the control logic may determine the write temperature upon receiving a request to program data. In one embodiment, the request received at operation 305 includes an indication of the write temperature provided by the memory subsystem controller 115, and therefore the control logic may read the indication of the write temperature from the request. In another embodiment, the control logic may receive a value from a temperature sensor (e.g., temperature sensor 170) on the memory device 130. Depending on the embodiment, the control logic may query temperature sensor 170 for a new write temperature measurement in response to receiving a write request at operation 305, or may use a recently measured temperature value as the write temperature (e.g., when temperature measurements are routinely acquired at periodic intervals on the memory device 130).

[0061] At operation 315, the data is programmed. For example, the control logic may program host data received with a request at operation 305 into an identifier segment of the memory array 104. In one embodiment, the control logic may cause one or more programming voltage signals to be applied to word lines 202 of the memory array 104 corresponding to the identifier segment.

[0062] At operation 320, the cross-temperature data is programmed. For example, the control logic may program the write temperature determined at operation 310 and the program / erase cycle count received with the request at operation 305 to one of the designated areas corresponding to the segment of memory array 104, such as flag bytes 150. In one embodiment, each segment (e.g., page) of memory array 104 is one or more corresponding flag bytes 150 for storing metadata associated with programmed host data. Flag bytes 150 may be a restricted area in memory array 104 storing system data or other metadata and are generally not accessible or usable by host system 120. In other embodiments, the control logic may store the write temperature and program / erase cycle count in some other designated area on memory device 130. In one embodiment, the write temperature and program / erase cycle count are held in flag bytes 150 until host data is read from the segment of memory array 104. At this point, the control logic can determine whether to perform a correction action based on the crossover temperature and programming / erase cycle count to calibrate the read voltage level to be applied to the memory array 104 to read host data from the segment, as described below relative to... Figure 4 To describe in more detail.

[0063] Figure 4This is a flowchart of an example method for on-die cross-temperature management of a memory device for a memory subsystem according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1A and Figure 1B The local media controller 135 executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0064] At operation 405, a request is received. For example, control logic (e.g., local media controller 135) may receive a request to read data from a memory array (e.g., memory array 104) of a memory device (e.g., memory device 130). In one embodiment, the request is received from a requester such as memory interface 113 of memory subsystem controller 115 or host system 120. In one embodiment, the request includes an indication of a segment (e.g., page) in memory array 104 where the data is stored.

[0065] At operation 410, a determination is made. For example, the control logic may determine whether the write temperature associated with the data is stored in the flag byte 150 corresponding to the segment of memory array 104. As described above relative to... Figure 3 As described, in some embodiments, the control logic may program write temperature data to flag byte 150 when host data is programmed into a segment of memory array 104. In one embodiment, when a read request is received at operation 405, the control logic may identify flag byte 150 corresponding to the segment indicated in the read request and determine whether the write temperature (i.e., an indication of the ambient temperature when data is programmed into memory array 104) is stored in flag byte 150. The write temperature in flag byte 150 may be identified by a unique identifier, or a designated field storing the write temperature may exist in flag byte 150.

[0066] In response to determining that the write temperature associated with the data is stored in flag byte 150, a crossover temperature is determined at operation 415. For example, the control logic may determine the crossover temperature of the data at operation 405 based on the write temperature and the read temperature at which a request to read data is received. In one embodiment, to determine the crossover temperature, the control logic may determine the difference between the write temperature and the read temperature. In one embodiment, the request received at operation 405 includes an indication of the read temperature provided by memory subsystem controller 115, and therefore the control logic may read the indication of the read temperature from the request. In another embodiment, the control logic may receive a value from a temperature sensor (e.g., temperature sensor 170) on memory device 130. Depending on the embodiment, the control logic may query temperature sensor 170 for a new read temperature measurement in response to receiving a read request at operation 405, or may use a recently measured temperature value as the read temperature (e.g., when temperature measurements are routinely acquired at periodic intervals on memory device 130).

[0067] At operation 420, the cycle count is determined. For example, the control logic may determine the program / erase (P / E) cycle count associated with a segment of memory array 104. As described above relative to... Figure 3 As described, in some embodiments, the control logic may program a program / erase cycle count to a flag byte 150 when host data is programmed to a segment of memory array 104. Therefore, in one embodiment, the control logic may read the program / erase cycle count from the flag byte 150. In another embodiment, the request received at operation 405 includes an indication of the program / erase cycle count of the segment of memory array 104.

[0068] At operation 425, a read voltage offset is determined. For example, control logic may determine a read voltage offset by which the default read voltage level is adjusted when applied to memory array 104 to read data from the segment. In one embodiment, using the crossover temperature determined at operation 415 and the program / erase cycle count determined at operation 420 as inputs, the control logic may identify a corresponding entry in a data structure (e.g., a lookup table) stored on memory device 130, where the entry contains an indication of the appropriate read voltage offset. In one embodiment, different combinations of crossover temperature and program / erase cycle count may have different read voltage offsets (i.e., the amount by which the default read voltage may be increased or decreased when a read operation is performed). In one embodiment, the control logic further determines, based on the crossover temperature and program / erase cycle count, whether to perform a correction action to calibrate the read voltage level to be applied to memory array 104 to read data from the segment.

[0069] At operation 430, a determination is made. For example, the control logic may determine whether the cross temperature determined at operation 415 satisfies a cross temperature threshold criterion. In one embodiment, if the cross temperature is greater than or equal to a cross temperature threshold level, the control logic may determine that the cross temperature threshold criterion is satisfied.

[0070] In response to determining that the cross temperature meets the cross temperature threshold criterion, another determination is made at operation 435. For example, the control logic may determine whether the programming / erase cycle count determined at operation 420 meets the cycle threshold criterion. In one embodiment, if the programming / erase cycle count is greater than or equal to the cycle threshold level, the control logic may determine that the cycle threshold criterion is met. In embodiments where programming / erase cycle count information is unavailable, the control logic may default to assuming that the programming / erase cycle count meets the threshold criterion, causing processing to continue to operation 440.

[0071] In response to determining that the programming / erase cycle count meets the cycle threshold criterion, the control logic may determine to perform a correction action to calibrate the read voltage level. At operation 440, the correction action is performed. For example, the control logic may perform a correction action to calibrate the read voltage level. In one embodiment, performing the correction action includes executing a read voltage calibration command to modify the read voltage level. In another embodiment, performing the correction action includes executing a correction read command to decouple the overlapping threshold voltage distributions in the data. When the read voltage calibration command is executed, a read voltage offset is applied based on the write-read temperature difference. These offsets are discrete offsets and have some associated noise. At extreme write-read temperature differences, the noise can be significant. In one embodiment, instead of relying on the read voltage offset in a lookup table, the read voltage offset is scanned to identify the optimal read voltage that achieves the maximum separation between Vt levels (or states). Regarding the correction read command, a NAND page may contain tens of thousands to hundreds of thousands of cells. Each cell experiences a different degree of Vt offset due to the influence of neighboring cells. This influence varies with the Vt level programmed to by neighboring attackers and the Vt level programmed to by the victim. Therefore, the Vt offset is non-uniform across each cell in the victim page. Therefore, this can lead to Vt state widening, reduced separation between levels, and an increased number of bit flips. In one embodiment, instead of reading all cells in a page in one iteration, the control logic can read cells in a page in multiple iterations based on the intruder state. For example, all cells with adjacent intruders in state X are read in one iteration, while all cells with adjacent intruders in state Y are read in a separate iteration. In this way, the control logic can filter out Vt widening noise caused by different intruder Vt states, thus decoupling the distribution. At the end of the read command, the data read from different iterations can be combined to form the entire page. After performing a correction action, the control logic can perform the read operation using a calibrated read voltage level. For example, the control logic can apply one or more read voltage signals to word lines 202 in memory array 104 corresponding to the identified segment.

[0072] If the control logic determines at operation 410 that the write temperature associated with the data is not stored in flag byte 150, or at operation 430 that the cross temperature does not meet the cross temperature threshold criterion, then another determination is made at operation 445. For example, the control logic may determine whether the read temperature meets the read temperature threshold criterion. In one embodiment, if the read temperature is greater than or equal to a high read temperature threshold level, or less than or equal to a low read temperature threshold level, the control logic may determine that the read temperature threshold criterion is met. Therefore, if the read temperature is extremely high or extremely low, the read temperature threshold criterion is met.

[0073] In response to determining that the read temperature meets the read temperature threshold criterion, the control logic may proceed to operation 435 to determine whether the programming / erase cycle count meets the cycle threshold criterion, as described above. If the control logic determines at operation 445 that the read temperature does not meet the read temperature threshold criterion, or at operation 435 that the programming / erase cycle count does not meet the cycle threshold criterion, then a read operation is performed at operation 450. For example, the control logic may perform read operation 450 without calibrating the read voltage level, and may use a default read voltage level or a default read voltage level modified by the read voltage offset determined at operation 425.

[0074] Figure 5 Example machines of computer system 500 are described, within which an instruction set can be executed to cause the machine to perform any one or more methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., host system 120 of FIG1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of FIG1), or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to local media controller 135 of FIG1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0075] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine has been described, the term "machine" should be understood to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any of the methods discussed herein.

[0076] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0077] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may also include a network interface device 508 for communication via network 520.

[0078] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) storing one or more sets of instructions 526 or software embodying any one or more methods or functions described herein. Instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to memory subsystem 110 of FIG1.

[0079] In one embodiment, instruction 526 includes instructions for implementing the functions corresponding to the local media controller 135 of FIG1. ​​Although machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms here, and generally are considered, are self-consistent sequences of operations that produce desired results. These operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, it has proven convenient to refer to these signals primarily for general reasons as bits, values, elements, symbols, characters, items, numbers, etc.

[0081] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0082] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each media coupled to a computer system bus.

[0083] The algorithms and demonstrations presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be proven convenient to construct more specialized devices to perform the methods. The architectures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0084] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0085] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: Memory array; as well as Control logic, which is operatively coupled to the memory array, performs operations including the following: Receive a request to read data from the memory array, the request including an indication of a segment of the memory array in which the data is stored; Determine whether the write temperature associated with the data is stored in the flag byte corresponding to the segment of the memory array; In response to determining that the write temperature associated with the data is stored in the flag byte, the cross temperature of the data is determined based on the write temperature and the read temperature when the request to read the data is received; Determine the programming / erase cycle count associated with the segment of the memory array; Based on the cross temperature and the programming / erasing cycle count, determine whether to perform a correction action to calibrate the read voltage level to be applied to the memory array to read the data from the segment; as well as In response to determining to perform a correction action, the correction action is performed to calibrate the read voltage level, wherein performing the correction action includes at least one of: executing a read voltage calibration command to modify the read voltage level, or executing a correction read command to decouple the overlapping threshold voltage distributions in the data.

2. The memory device of claim 1, wherein determining the cross temperature of the data includes determining the difference between the write temperature and the read temperature.

3. The memory device of claim 1, wherein determining the program / erase cycle count comprises at least one of: reading the program / erase cycle count from the flag byte corresponding to the segment of the memory array, or receiving an indication of the program / erase cycle count in conjunction with the request to read the data from the memory array.

4. The memory device of claim 1, wherein determining whether to perform the calibration action to calibrate the read voltage level comprises: Determine whether the cross temperature meets the cross temperature threshold criterion; as well as In response to determining that the cross temperature meets the cross temperature threshold criterion, it is determined whether the programming / erasing cycle count meets the cycle threshold criterion.

5. The memory device of claim 4, wherein determining whether to perform the calibration action to calibrate the read voltage level further comprises: In response to determining that the programming / erasing cycle count meets the cycle threshold criterion, it is determined to perform the correction action to calibrate the read voltage level.

6. The memory device of claim 1, wherein the control logic is configured to perform an operation comprising: In response to determining that the write temperature associated with the data is not stored in the flag byte, it is determined whether the read temperature meets the read temperature threshold criterion; and In response to determining that the read temperature meets the read temperature threshold criterion, determine whether the programming / erase cycle count meets the cycle threshold criterion.

7. The memory device of claim 6, wherein the control logic is configured to perform an additional operation comprising: In response to determining that the programming / erase cycle count meets the cycle threshold criterion or that the programming / erase cycle count is unavailable, the correction action is performed to calibrate the read voltage level.

8. A method comprising: Receive a request to read data from a memory array of a memory device, the request including an indication of a segment of the memory array in which the data is stored; Determine whether the write temperature associated with the data is stored in the flag byte corresponding to the segment of the memory array; In response to determining that the write temperature associated with the data is stored in the flag byte, the cross temperature of the data is determined based on the write temperature and the read temperature when the request to read the data is received; Determine the programming / erase cycle count associated with the segment of the memory array; Based on the cross temperature and the programming / erasing cycle count, determine whether to perform a correction action to calibrate the read voltage level to be applied to the memory array to read the data from the segment; as well as In response to determining to perform a correction action, the correction action is performed to calibrate the read voltage level, wherein performing the correction action includes at least one of: executing a read voltage calibration command to modify the read voltage level, or executing a correction read command to decouple the overlapping threshold voltage distributions in the data.

9. The method of claim 8, wherein determining the cross temperature of the data includes determining the difference between the write temperature and the read temperature.

10. The method of claim 8, wherein determining the programming / erasing cycle count comprises at least one of: reading the programming / erasing cycle count from the flag byte corresponding to the segment of the memory array, or receiving an indication of the programming / erasing cycle count along with the request to read data from the memory array.

11. The method of claim 8, wherein determining whether to perform the calibration action to calibrate the read voltage level comprises: Determine whether the cross temperature meets the cross temperature threshold criterion; as well as In response to determining that the cross temperature meets the cross temperature threshold criterion, it is determined whether the programming / erasing cycle count meets the cycle threshold criterion.

12. The method of claim 11, wherein determining whether to perform the calibration action to calibrate the read voltage level further comprises: In response to determining that the programming / erasing cycle count meets the cycle threshold criterion, it is determined to perform the correction action to calibrate the read voltage level.

13. The method of claim 8, further comprising: In response to determining that the write temperature associated with the data is not stored in the flag byte, determine whether the read temperature meets the read temperature threshold criterion; as well as In response to determining that the read temperature meets the read temperature threshold criterion, determine whether the programming / erase cycle count meets the cycle threshold criterion.

14. The method of claim 13, further comprising: In response to determining that the programming / erase cycle count meets the cycle threshold criterion or that the programming / erase cycle count is unavailable, the correction action is performed to calibrate the read voltage level.

15. A memory device comprising: Memory array; as well as Control logic, which is operatively coupled to the memory array, performs operations including the following: Receive a request to program data into the memory array, the request including an indication of a programming / erase cycle count associated with a segment of the memory array in which the data is to be stored; Determine the write temperature when the request to program the data is received; The data is programmed into the segment of the memory array; as well as The write temperature and the program / erase cycle count are programmed into a flag byte corresponding to the segment of the memory array, wherein the control logic is used to determine whether to perform a correction action to calibrate the read voltage level to be applied to the memory array to read the data from the segment based on the write temperature and the program / erase cycle count, and wherein the write temperature and the program / erase cycle count are maintained in the flag byte until the data is read from the segment of the memory array.

16. The memory device of claim 15, wherein determining the write temperature includes reading an indication of the write temperature included in the request to program the data into the memory array.

17. The memory device of claim 15, further comprising: A temperature sensor, which is coupled to the control logic in an operative manner, wherein determining the write temperature includes receiving a value from the temperature sensor.

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