Memory device using dynamic latches to provide multiple bias voltages

Abstract

Embodiments of the present application relate to a memory device that provides multiple bias voltages using a dynamic latch. The memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is connected to the SA latch and coupled to the sense node. A sense line includes the sense node and is selectively connected to the SA latch, the DL, and a bit line coupled to a string of memory cells. Control logic is coupled to the SA latch and the DL and causes a preprogrammed verify voltage to boost the sense node; and in response to detecting a high bit value stored in the SA latch, causes a voltage to turn on a DL set transistor so that either a first bias voltage or a second bias voltage is stored at a latch transistor. The first bias voltage can be used for slow programming of a selected memory cell and the second bias voltage can be used for fast programming of the selected memory cell.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory devices that use dynamic latches to provide multiple bias voltages. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to embodiments of this disclosure, a memory device is provided, and the memory device includes: a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node, the dynamic latch including a latch transistor having a source coupled to a source bias node and a drain selectively connected to the sense node; and one or more setting transistors coupled between the SA latch and the gate of the latch transistor, the one or more setting transistors also selectively connected to the sense node. The memory device further includes: a sense line including the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line coupled to a series-connected string of memory cells; and control logic coupled to at least the SA latch and the dynamic latch. The control logic is used to perform operations including boosting the pre-programmed verification voltage to the sensing node; and in response to detecting a high-order value stored in the SA latch, turning on the one or more setting transistors with a setting voltage, such that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein: the first bias voltage can be used for slow programming of selected memory cells in the series-connected memory cell string; and the second bias voltage can be used for fast programming of the selected memory cells in the series-connected memory cell string, wherein the fast programming is faster than the slow programming.

[0004] According to embodiments of this disclosure, a method is provided and the method is configured to operate a memory device including a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node, the dynamic latch including a latch transistor and one or more set transistors; and a sense line including the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line coupled to a series-connected string of memory cells. The method of operating the memory device includes performing a plurality of operations, including: providing a boost voltage to the sense node with a pre-programming verification voltage; and, in response to detecting a high-order value stored in the SA latch, turning on the one or more set transistors of the dynamic latch with a set voltage, such that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein: the first bias voltage is available for slow programming of selected memory cells in the series-connected string of memory cells; and the second bias voltage is available for fast programming of the selected memory cells in the series-connected string of memory cells, wherein the fast programming is faster than the slow programming.

[0005] According to embodiments of this disclosure, a memory device is provided, and the memory device includes: a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node; a sense line including the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line, wherein the bit line is coupled to a series-connected string of memory cells; and control logic coupled to the SA latch and the dynamic latch. For programming a bit line bias, the control logic performs operations including: sending a programming pulse down the bit line to program selected memory cells of the series-connected string of memory cells; sending an output voltage of the SA latch to the sense node, wherein the output voltage of the SA latch is a common collector voltage (Vcc); selectively discharging a first voltage of the sense node by the dynamic latch to generate an updated first voltage at the sense node; and selectively flipping a bit value stored in the SA latch depending on the value of the updated first voltage of the sense node. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0007] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figures 2A to 2C This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 This is a diagrammatic illustration depicting a group of memory cells for a three-level cell (TLC) memory according to at least one embodiment.

[0011] Figure 4 This is a timing diagram depicting a portion of a programming operation that programs a selected TLC memory cell to a target threshold voltage, according to an embodiment.

[0012] Figure 5A and Figure 5B It is a diagrammatic illustration of a group of memory cells during a programming operation that uses selective slow programming convergence to program selected memory cells to a target voltage, according to at least one embodiment.

[0013] Figure 6A It is based on some embodiments and may be used for reference. Figures 1A to 1B A schematic diagram of a portion of the page buffer in a memory of the described type.

[0014] Figure 6B According to at least one embodiment Figure 6A A detailed schematic diagram of a dynamic latch.

[0015] Figures 7A to 7C This describes, according to some embodiments, the method for storing voltage bias in a dynamic latch. Figures 6A to 6B The diagram shows a set of graphs related to the control and voltage level waveforms.

[0016] Figure 8 This is a flowchart of an example method, according to some embodiments, of selectively storing one of a first bias voltage or a second bias voltage, respectively corresponding to a slow selective slow programming convergence voltage or a fast selective slow programming convergence voltage, in a dynamic latch of a page buffer.

[0017] Figures 9A to 9C This describes, according to some embodiments, a method for programming bit line biases into a page buffer. Figures 6A to 6B The diagram shows a set of graphics related to the control and voltage level waveforms.

[0018] Figures 10A to 10BThis describes, according to some embodiments, the method for accumulating bias voltage levels between programming operations at multiple threshold voltage levels. Figures 6A to 6B The diagram shows a set of graphics related to the control and voltage level waveforms.

[0019] Figure 10C Based on the description and illustration of some embodiments Figures 10A to 10B The graph is annotated with the data stream through the page buffer.

[0020] Figure 11 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0021] Embodiments of this disclosure relate to memory devices that use dynamic latches to provide multiple bias voltages. The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. The following description, in conjunction with... Figure 1A Other examples of non-volatile memory devices are described. These memory devices contain memory cells in which data is stored. For example, the threshold voltage (Vt) of a memory cell changes with the data state (or data value) of each memory cell through programming (often referred to as writing) of a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization).

[0022] When programming memory, memory cells can generally be programmed as Single-Level Cell (SLC) or Multi-Level Cell (MLC). A single-level cell uses a single memory cell to represent a number of bits (e.g., a bit) of data. For example, in an SLC, a Vt of 2.5V can indicate a programmed memory cell (e.g., representing logic 0), while a Vt of -0.5V can indicate an erased cell (e.g., representing logic 1). As an example, the erase state in an SLC can be represented by any threshold voltage less than or equal to 0V, while the programmed data state can be represented by any threshold voltage greater than 0V. A multi-level cell uses more than two Vt ranges, where each Vt range indicates a different data state. For example, dead-space margins (e.g., a specific number of volts) can separate adjacent Vt ranges to distinguish data states. Multi-level cells can utilize the analog properties of traditional non-volatile memory cells by assigning bit patterns to specific Vt ranges.

[0023] When programming MLC memory, data values ​​are typically programmed in more than one pass; for example, one or more numbers are programmed in each pass. For instance, in a four-level MLC (often simply called MLC), a first number, such as the least significant bit (LSB), commonly referred to as lower page (LP) data, is programmed into the memory cell in the first pass, resulting in two (e.g., first and second) threshold voltage ranges. Subsequently, a second number, such as the most significant bit (MSB), commonly referred to as upper page (UP) data, is programmed into the memory cell in the second pass, typically moving a portion of those memory cells in the first threshold voltage range into the third threshold voltage range, and a portion of those memory cells in the second threshold voltage range into the fourth threshold voltage range. Similarly, an eight-level MLC (often called TLC) can represent a three-bit bit pattern, containing a first number, such as the least significant bit (LSB) or lower page (LP) data; a second number, such as upper page (UP) data; and a third number, such as the most significant bit (MSB) or extra page (XP) data. When operating a TLC, LP data can be programmed into memory cells in the first pass to generate two threshold voltage ranges, and then UP and XP data can be programmed into memory cells in the second pass to generate eight threshold voltage ranges. Similarly, a 16-level MLC (commonly known as a QLC) can represent a four-bit bit pattern, and a 32-level MLC (commonly known as a PLC) can represent a five-bit bit pattern.

[0024] To program a group of memory cells to each Vt state of an SLC or MLC memory, according to some embodiments, local media control (e.g., control logic) of some memory device causes different voltage levels to be applied to the data lines (or bit lines), thereby resulting in the programming of selected memory cells, such as a group of memory cells. In these embodiments, the control logic may send control signals to a signal driver selectively connected between a page buffer and the bit lines. The page buffer may provide a voltage level to the signal driver, which, when turned on by the control signal, can use the voltage level to generate a voltage on the bit lines, which programs the selected memory cells in the group of memory cells. As will be explained, these voltage levels may vary depending on the level (or speed) of the programming to occur.

[0025] In some embodiments, programming of memory cells can occur in a programming scheme known as Selective Slow Programming Convergence (SSPC). For example, in SSPC programming, memory cells closer to their corresponding expected data state are programmed more slowly (e.g., partially enabled for programming) compared to memory cells further away from their corresponding expected data state (e.g., for fully enabled programming), while receiving the same voltage level at their respective control gates. The target voltage may correspond to a minimum threshold voltage (PV) for the target Vt level. TARGET This can be referred to as the final programming verification voltage for the target voltage. A first pre-programming verification voltage (PPV1) can be selected to be less than the final programming verification voltage to enable slow SSPC programming. A second pre-programming verification voltage (PPV2) can be selected to be less than the slow SSPC programming verification voltage (PPV1) to enable fast SSPC programming, where fast SSPC programming is faster than slow SSPC programming.

[0026] Depending on the proximity of the memory cell to the target voltage, page buffers can be directed to provide bias voltages (via signal drivers) to the memory cell, selectively controlling the voltage level actually applied to a group or cluster of memory cells. As the memory cell gets closer to its corresponding target voltage, the applied bias voltage typically increases, causing the actual programming pulse voltage to decrease, thus slowing down the programming rate. For example, four bias voltages may correspond to at least four voltage levels, including non-SSPC programming, fast SSPC programming, slow SSPC programming, and blocking programming. Of these four bias voltages, any given page buffer may provide one of the bias voltages at any given time, depending on the programming stage associated with SSPC, where the memory cell is being programmed by that particular page buffer. These bias voltages may also be applied during programming verification operations associated with determining how close the memory cell has been programmed to the target voltage, which may then lead to switching to apply different, possibly slower, programming voltage bias levels for subsequent stages of SSPC programming.

[0027] In some memory devices, the page buffer stores these four bias voltages in a combination of the main data cache (PDC) and dynamic latches. While each PDC can be understood as a separate memory latch, the dynamic latch stores the bias voltages within one or more transistors (and / or other parasitic capacitances) of the page buffer circuitry. As the complexity of SSPC programming has increased, additional latches containing PDCs have been added to store multiple SSPC-related bias voltage levels. This has resulted in a larger page buffer size and thus increased cost, as well as slower performance due to additional data access from external latches.

[0028] This disclosure addresses the above and other drawbacks by adding an additional dynamic latch to the page buffer—providing at least two bias voltages associated with both a slow SSPC voltage (e.g., PPV1) and a fast SSPC voltage (e.g., PPV2). For example, adding this dynamic latch eliminates static PDC, where the static latch is significantly larger than the dynamic latch. In various embodiments, this additional dynamic latch is connected to a sense amplifier (SA) latch that stores one of two locations, such as a high bit value (or "1") or a low bit value (or "0"). The SA latch is selectively connected to the sense node of the page buffer.

[0029] In at least some embodiments, the dynamic latch includes a latch transistor having a source coupled to a source bias node and a drain selectively connected to a sensing node. The latch transistor may further include one or more setting transistors coupled between the SA latch and the gate of the latch transistor, the setting transistors also selectively connected to the sensing node. A sensing line may include a sensing node and be selectively connected to the SA latch, the dynamic latch, and a bit line coupled to a series-connected string of memory cells.

[0030] In these embodiments, in addition to other page buffer circuitry, a local media controller (or simply controller) of the memory device may be coupled to an SA latch or a dynamic latch. The controller may be configured to perform operations such as boosting a preprogrammed verification voltage to a sensing node and, in response to detecting a high-order value stored in the SA latch, turning on one or more setting transistors with a setting voltage, such that one of a first bias voltage or a second bias voltage is stored at the latch transistor. For example, the first bias voltage or the second bias voltage may be stored in the gate capacitance of the latch transistor. In at least some embodiments, the preprogrammed verification voltage and the setting voltage may be at different voltages, depending on whether the first bias voltage or the second bias voltage will be stored in the latch transistor, as will be discussed. In various embodiments, the first bias voltage may be used for slow programming of selected memory cells in a series-connected string of memory cells, for example, associated with a slow SSPC voltage (e.g., PPV1). In these embodiments, the second bias voltage may be used for fast programming of selected memory cells in a series-connected string of memory cells, for example, associated with a fast SSPC voltage (e.g., PPV2).

[0031] In addition, the additional dynamic latch can also be used to provide a first bias voltage or a second bias voltage to the sensing node for SSPC programming at PPV1 or PPV2 voltage levels, respectively, to include SSPC programming verification operations. Furthermore, for example, when MLC programming moves from programming to the lower Vt range of the first bit level to programming to the higher Vt range of the second bit level, the additional dynamic latch can also be used to accumulate bias voltage levels for slow and fast SSPC voltage levels.

[0032] Therefore, the advantages of the systems and methods according to some embodiments of this disclosure include, but are not limited to, eliminating external PDC latches that cause page buffer area growth. Furthermore, eliminating these latches improves the speed and performance of programming memory cells in MLC memory devices. Other advantages will be apparent to those skilled in the art of memory programming, including selective slow programming convergence associated with the memory devices discussed below.

[0033] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0034] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory units (“units”). A unit is an electronic circuit that stores information. Depending on the unit type, a unit may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0035] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, used together with one or more bit lines to generate the address of each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0036] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0037] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device containing memory and processing device.

[0038] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0039] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, host system 120 uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0040] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0041] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0042] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0043] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0044] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0045] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0046] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0047] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in FIG1 is illustrated to include a memory subsystem controller 115, in another embodiment of this disclosure, memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0048] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into instructions for accessing the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0049] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0050] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0051] In some embodiments, memory device 130 includes page buffer 150, which can be used to encode data into and read data from memory cells of memory device 130. The control logic of local media controller 135 can be configured to coordinate the timing and manner of applying one of four different voltage biases for selective slow programming convergence voltage programming, as will be explained in detail. These four different bias voltages may be, for example, a programming verification pass voltage (e.g., a blocking bias voltage), a slow selective slow programming convergence voltage (e.g., PPV1), a fast selective slow programming convergence voltage (e.g., PPV2), and a programming verification failure voltage (e.g., ground or Vss).

[0052] In at least some embodiments, the local media controller 135 includes an instruction register 128, which represents computer-available memory for storing computer-readable instructions. In some embodiments, the instruction register 128 may represent firmware. Alternatively, the instruction register 128 may represent a grouping of memory cells in the memory cell array 104, such as a reserved block of memory cells.

[0053] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0054] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the text) can be programmed to be one of at least two target data states.

[0055] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 130 and outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0056] A controller (e.g., a local media controller 135 within memory device 130) responds to a command to control access to memory cell array 104 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control row decoding circuitry 108 and column decoding circuitry 111 in response to an address.

[0057] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer 150 of memory device 130 (e.g., at least a portion thereof). Page buffer 150 may further include sensing devices such as a sense amplifier to sense the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells of memory cell array 104. Status register 122 may communicate with I / O control circuitry system 112 and local memory controller 135 to latch status information for output to memory subsystem controller 115.

[0058] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0059] For example, commands can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. Data can then be written to data register 121 for programming memory cell array 104.

[0060] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0061] Those skilled in the art will understand that additional circuitry and signals can be provided and the process has been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0062] Figures 2A to 2C It can be, for example, part of memory cell array 104 according to an embodiment in reference. Figure 1B A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 M The data line. Word line 202 can be coupled to a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0063] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells connected in series (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. The memory cells 208 of each NAND string 206 may be connected in series between select gate 210 (e.g., a field-effect transistor) and select gate 212 (e.g., a field-effect transistor), wherein select gate 210 is, for example, select gates 2100 to 210. M One of them (for example, it may be a source-select transistor, commonly referred to as a select-gate-source), and the select-gate 212 is, for example, select-gate 2120 to 212. M One of them (for example, it could be a drain-select transistor, often referred to as a select-gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as the source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate is configured in series to receive the same or independent control signal.

[0064] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0065] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0066] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, and the plane containing the bit line 204 may be substantially parallel to the plane containing the common source 216.

[0067] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236, such as... Figure 2A As shown in the diagram. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to the word line 202 (and in some cases forming the word line).

[0068] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may contain (but not necessarily) all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd memory cell).

[0069] Despite Figure 2A Bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is evident from the figure that bit lines 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Memory cells 208 that are commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered as physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered as a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell. Although discussed in conjunction with NAND flash memory... Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure, and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0070] Figure 2B This can be used as a reference. Figure 1B Another schematic diagram of a portion of a memory cell array 200B in a memory of the described type, for example as part of a memory cell array 104. Figure 2B Elements with the same number in the text correspond to elements about Figure 2A The description provided. Figure 2BFurther details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, wherein portions of the pillars may serve as channel regions for the memory cells of the NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, commonly referred to as a select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via bias selection lines 2150 to 215. K Each word line 202 is connected to its corresponding bit line 204 to selectively activate a specific selection transistor 212 located between the NAND string 206 and the bit line 204. Selection transistors 210 can be activated via bias selection line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells interconnected via specific sub-lines 202 can be collectively referred to as a layer.

[0071] Figure 2C This can be used as a reference. Figure 1B Another schematic diagram of a portion of a memory cell array 200C in a memory of the described type, for example as part of a memory cell array 104. Figure 2C Elements with the same number in the text correspond to elements about Figure 2A The provided description. The memory cell array 200C may contain, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, an access (e.g., a word) line 202, a data (e.g., a bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C.

[0072] Figure 2C The diagram depicts the NAND string 206 being grouped into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may represent those NAND strings 206 typically associated with, for example, a single select line 215 of select line 2150. The source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250L They can be selectively connected together to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 can be connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 of any other memory cell block may not have direct connections.

[0073] Bit line 2040-204 M It can be connected (e.g., selectively connected) to a buffer portion 240 that may be part of a page buffer of memory device 130. Buffer portion 240 may correspond to a memory plane (e.g., a set of memory cell blocks 2500 to 2500). L The buffer section 240 may include sensing circuitry (which may include a sensing amplifier) ​​for sensing the data value indicated on the corresponding bit line 204.

[0074] Figure 3 This is a schematic illustration depicting a group of memory cells for a three-level cell (TLC) memory according to at least one embodiment. For simplicity, Figure 3 and afterwards Figure 4 The programming operations assumed to be for a TLC memory cell (e.g., an eight-level memory cell), which, for example, uses eight threshold voltage ranges to represent data states L0, L1, L2, L3, L4, L5, L6, and L7, each threshold voltage range representing a bit pattern of data state corresponding to three digits. Although discussed with reference to a TLC memory cell, the programming operations performed on lower-density memory cells (e.g., SLC (two data states)) or higher-density memory cells (e.g., QLC (16 data states) or PLC (32 data states) memory cells) are equally applicable.

[0075] In this example, memory cell group 310 may be an erased memory cell and represent the logical data value '111', memory cell group 311 may represent the logical data value '011', memory cell group 312 may represent the logical data value '001', memory cell group 313 may represent the logical data value '101', memory cell group 314 may represent the logical data value '100', memory cell group 315 may represent the logical data value '000', memory cell group 316 may represent the logical data value '010', and memory cell group 317 may represent the logical data value '110'. The rightmost digit may represent the lower page data of a memory cell having a threshold voltage within the threshold voltage range of its respective memory cell group, the middle digit may represent the upper page data of the memory cell, and the leftmost digit may represent additional page data of the memory cell. Although a specific example of binary representation is provided, embodiments may use other arrangements of bit patterns to represent various data states.

[0076] At 320, a read window is indicated between memory cell groups 310 and 311, representing the distance (e.g., in voltmeters) between adjacent Vt distributions of memory cells representing data states L0 and L1. At 321, a read window is indicated between memory cell groups 311 and 312, representing the distance (e.g., in voltmeters) between adjacent Vt distributions of memory cells representing data states L1 and L2. Similarly, at 322, 323, 324, 325, and 326, read windows are indicated between memory cell groups 312, 313, 314, 315, and 316 and memory cell groups 313, 314, 315, 316, and 317, representing the distance between adjacent Vt distributions of memory cells representing data states L2, L3, L4, L5, L6, and L7. The read window budget (RWB) may refer to the cumulative value of read windows used for a set of programmed cells (e.g., one or more pages of cells). In this example, RWB can be the cumulative value (e.g., in voltmeter form) of seven reading windows 320 to 326 between eight Vt distributions.

[0077] Figure 4 According to the description of the embodiment, selected TLC memory cells are programmed to target Vt levels L0 to L7 (e.g., as shown in the example). Figure 3 This is a timing diagram of a portion of the programming operation (described in [reference]). Once a selected memory cell has been programmed to its target Vt level, further programming of the memory cell is prevented. Before time t0, the selected memory cells used for programming can be erased, such that each selected memory cell has a threshold voltage corresponding to level L0. At time t0, a first programming pulse is applied to the selected access line (e.g., [reference]). Figure 2A(e.g., 202), the selected access line is connected to the control gate (e.g., 236) of the selected memory cell (e.g., 208). After the first programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L1 or L2. At time t1, a second programming pulse, for example higher than the first programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the second programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level Vt L1 or L2.

[0078] At time t2, a third programming pulse, for example higher than the second programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the third programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to Vt level L1, L2, or L3. At time t3, a fourth programming pulse, for example higher than the third programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the fourth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to Vt level L2, L3, or L4. At time t4, a fifth programming pulse, for example higher than the fourth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the fifth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to Vt level L2, L3, L4, or L5.

[0079] At time t5, a sixth programming pulse, for example higher than the fifth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the sixth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to Vt level L3, L4, L5, or L6. At time t6, a seventh programming pulse, for example higher than the sixth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the seventh programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to Vt level L3, L4, L5, L6, or L7. At time t7, an eighth programming pulse, for example higher than the seventh programming pulse, can be applied to a selected access line connected to the control gate of the selected memory cell, and the process can be repeated until the selected memory cell has been programmed to its target level.

[0080] Figure 5A and Figure 5B This is a diagrammatic illustration of a group 500 of memory cells during a programming operation that uses selective slow programming convergence to program selected memory cells to a target voltage (e.g., a target Vt level) according to at least one embodiment. Figure 5AThe memory cell group 500 is depicted following a specific programming pulse, as indicated by memory cell group 502, indicating that a selected memory cell is programmed to a target voltage (or Vt level). The use of different voltage levels on the data line for programming enable may occur in a programming scheme called Selective Slow Programming Convergence (SSPC), in which memory cells closer to their respective expected data state are programmed more slowly (e.g., partially enabled for programming) compared to memory cells further away from their respective expected data state (e.g., for fully enabled for programming), while receiving the same voltage level at their respective control gates. The target voltage may correspond to a minimum threshold voltage (PV) for the target level. TARGET This can be referred to as the final programming verification voltage 504 for the target voltage. A first pre-programming verification voltage (PPV1) 506 can be selected to be less than the final programming verification voltage 504 to enable slow SSPC programming. A second pre-programming verification voltage (PPV2) 508 can be selected to be less than the slow SSPC programming verification voltage (PPV1) 506 to enable fast SSPC programming.

[0081] Following a specific programming pulse, a programming verification operation is performed to sense the threshold voltage (Vt) of each memory cell within the memory cell group 500. Memory cells having a threshold voltage less than the second pre-programming verification voltage 508, as indicated, for example at 510, are biased for non-SSPC programming (e.g., fully enabled for programming). Memory cells having a threshold voltage between the second pre-programming verification voltage 508 and the first pre-programming verification voltage 506, as indicated, for example at 512, are biased for fast SSPC programming (e.g., partially enabled for programming at a first rate), because the memory cells are within the fast SSPC range. Memory cells having a threshold voltage between the first pre-programming verification voltage 506 and the final programming verification voltage 504, as indicated, for example at 514, are biased for slow SSPC programming (e.g., partially enabled for programming at a second rate less than the first rate), because the memory cells are within the slow SSPC range. Memory cells having a threshold voltage greater than the final programming verification voltage 504, as indicated, for example at 516, are prevented from further programming.

[0082] like Figure 5BAs described, when each memory cell within the memory cell group 500 is biased for non-SSPC programming, fast SSPC programming, slow SSPC programming, or blocked programming, a subsequent programming pulse is applied to the memory cell group 500 to increase the threshold voltage of the memory cell to a target level as indicated by the memory cell group 502. The subsequent programming pulse may immediately follow a specific programming pulse. When memory cell 510 is biased for non-SSPC programming, the threshold voltage of memory cell 510 may be increased above the final programming verification voltage 504 in response to a subsequent programming pulse, as indicated by 520. When memory cell 512 is biased for fast SSPC programming, the threshold voltage of memory cell 512 may be increased above the final programming verification voltage 504 in response to a subsequent programming pulse, as indicated by 522. When memory cell 514 is biased for slow SSPC programming, the threshold voltage of memory cell 514 may be increased above the final programming verification voltage 504 in response to a subsequent programming pulse, as indicated by 524. Following a subsequent programming pulse, a programming verification operation is performed to sense the threshold voltage of each memory cell within the memory cell group 502. In this example, all memory cells have a threshold voltage greater than the final programming verification voltage 504 and are prevented from further programming.

[0083] A memory cell can be biased for fast SSPC programming by biasing the data lines connected to the memory cell to a fast SSPC voltage (e.g., Vt level) during a programming pulse. A memory cell can be biased for slow SSPC programming by biasing the data lines connected to the memory cell to a slow SSPC voltage during a programming pulse. A memory cell can be biased for non-SSPC programming by biasing the data lines connected to the memory cell to a non-SSPC voltage level during a programming pulse. A memory cell can be prevented from programming by biasing the data lines connected to the memory cell to a blocking voltage level during a programming pulse. The fast SSPC voltage level (e.g., 0.5V, 0.75V, 1.0V, etc.) can be greater than the non-SSPC voltage level (e.g., 0V). The slow SSPC voltage level (e.g., 1.0V, 1.5V, 2.0V, etc.) can be greater than the fast SSPC voltage level and less than the blocking voltage level (e.g., 3V, 3.5V, or common collector voltage (Vcc), etc.). By using four data line bias voltages during programming, the number of programming pulses required to program a selected memory cell to its target Vt level can be reduced compared to the number of programming pulses required to program a selected memory cell to its target Vt level using fewer than four data line bias voltages, thereby reducing programming time. Furthermore, by using four data line bias voltages, programming time can be reduced without reducing the read window budget.

[0084] Figure 6A It is based on some embodiments and may be used for reference. Figures 1A to 1B A schematic diagram of a portion of a page buffer 600 in a memory of the described type. In some embodiments, the page buffer 600 is Figures 1A to 1B One of the page buffers 150. Page buffer 600 can be... Figure 2C The buffer portion 240. Page buffer 600 includes a selected access line (e.g., word line) 202, selected memory cells 208 of a serially connected string of memory cells (not shown), and a selected data line (e.g., bit line) 204 attached to the serially connected string of memory cells. The selected access line 202 is connected to the control gate of the selected memory cell 208. The source of the selected memory cell 208 is connected to a common source 216 (e.g., via other memory cells in the serially connected string of memory cells and corresponding select gates 210). The drain of the selected memory cell 208 is connected to the selected access line 204 (e.g., via other memory cells in the serially connected string of memory cells and corresponding select gates 212).

[0085] In various embodiments, the page buffer 600 further includes transistors 602, 603, 609, 610, 613, 617, 622, 623, 627, 630, 631, 634, 642, 646, 662, 670, 678, and 696, a sensing capacitor 654, a sensing amplifier latch 686 (e.g., an SA latch 686), a first latch 691, and a second latch 692. In some embodiments, the first latch 691 and the second latch 692 are each PDC latches coupled to the page buffer circuitry, as will be explained. Transistor 622 may be a p-channel metal-oxide-semiconductor (PMOS) transistor, while transistors 602, 603, 609, 610, 613, 617, 623, 627, 630, 631, 634, 642, 646, 662, 670, 678, and 696 may be n-channel metal-oxide-semiconductor (NMOS) transistors. The sense amplifier latch 686 includes inverters 683 and 684, and transistors 687 and 688 (e.g., NMOS transistors). Bit line 204 is connected to one side of the source-drain path of transistor 602 and one side of the source-drain path of transistor 631. The gate of transistor 631 is connected to the SRC_GATE control signal path 633. The other side of the source-drain path of transistor 631 is connected to the common source 216. The gate of transistor 602 is connected to the DW_GATE control signal path 604.

[0086] In some embodiments, the other side of the source-drain path of transistor 602 is connected to one side of the source-drain path of transistor 610 via DW signal path 606. The gate of transistor 610 (e.g., a bit line clamping transistor) is connected to BLCLAMP control signal path 612. The other side of the source-drain path of transistor 610 is connected to one side of the source-drain path of transistor 630 (e.g., a second bit line clamping transistor), one side of the source-drain path of transistor 634, and one side of the source-drain path of transistor 646 via signal path 614. The gate of transistor 630 is connected to BLCLAMP2 control signal path 632. The other side of the source-drain path of transistor 630 is connected to one side of the source-drain path of transistor 622 (e.g., an upper bias transistor) via signal path 626. The gate of transistor 622 is connected via BL_SA_OUT signal path 690 to one side of the source-drain path of transistor 617 and the gate of transistor 642 (e.g., a lower-biased transistor). The gate of transistor 617 is connected to SAB_BL_PRE control signal path 619. The other side of the source-drain path of transistor 617 is connected via SA_OUT signal path 621 to the input of inverter 683, the output of inverter 684, and one side of the source-drain path of transistor 687. The other side of the source-drain path of transistor 622 is connected to power node (e.g., VREG2) 618. The gate of transistor 634 is connected to EN_DATA control signal path 636. The other side of the source-drain path of transistor 634 is connected via signal path 638 to one side of the source-drain path of transistor 642. The other side of the source-drain path of transistor 642 is connected to power node (e.g., VREG0) 639.

[0087] The gate of transistor 646 is connected to TC_ISO control signal path 648. The other side of the source-drain path of transistor 646 is connected via TC signal path 650 to one side of sensing capacitor 654, one side of the source-drain path of transistor 662, and the gate of transistor 678. This first side of sensing capacitor 654 is also connected to a sensing node (TC) of TC signal path 650. In some embodiments, signal path 614 and TC signal path 650 are selectively connected to each other and may be collectively referred to as a sensing line. Therefore, this sensing line may include a sensing node (TC). The other (or second) side of sensing capacitor 654 is connected to a sensing capacitor bias node (e.g., BOOST node) 658. The gate of transistor 662 is connected to BLC1 control signal path 664. The other side of the source-drain path of transistor 662 is connected via the TDC_INT signal path 666 to one side of the source-drain path of transistor 670, the other side of the source-drain path of transistor 687, one side of the source-drain path of transistor 688, one side of the source-drain path of transistor 603, one side of the source-drain path of transistor 609, one side of the source-drain path of transistor 696, and the gate of transistor 623. The gate of transistor 670 is connected to the SEN control signal path 672. The other side of the source-drain path of transistor 670 is connected via signal path 674 to one side of the source-drain path of transistor 678. The other side of the source-drain path of transistor 678 is connected to the source bias node 682 (e.g., SRC_GND). Transistor 678 may be referred to as a sensing transistor with a gate connected to a sensing node (TC).

[0088] The gate of transistor 687 in sense amplifier latch 686 is connected to the DRST_SA control signal path 675. The gate of transistor 688 is connected to the DST_SA signal path 676. The other side of the source-drain path of transistor 688 is connected to the output of inverter 683 and the input of inverter 684 via signal path 677. The control input of inverter 683 is connected to the SEN_SAB control signal path 685. The control input of inverter 684 is connected to the LAT_SAB control signal path 689.

[0089] The gate of transistor 603 is connected to the TDCINT_DIS control signal path 605. The other side of the source-drain path of transistor 603 is connected to a common or ground (e.g., GND) node 607. The gate of transistor 609 is connected via the DATA_TRANSFER signal path 693 to the other side of the source-drain path of transistor 696, one side of the source-drain path of transistor 623, the first latch 691, and the second latch 692. The other side of the source-drain path of transistor 609 is connected via signal path 611 to one side of the source-drain path of transistor 613. The gate of transistor 613 is connected to the EN_SA control signal path 615. The other side of the source-drain path of transistor 613 is connected to a common or ground node 607. The gate of transistor 696 is connected to the BLC2 control signal path 697. The other side of the source-drain path of transistor 623 is connected via signal path 625 to one side of the source-drain path of transistor 627. The gate of transistor 627 is connected to the EN_LATCH control signal path 629. The other side of the source-drain path of transistor 627 is connected to the common or ground node 607.

[0090] In some embodiments, page buffer 600 includes a data refiner 601, which in turn includes a combination of transistors 609, 613, 623, 627, and 696. The data refiner 601 is controllable to manipulate data transmitted to or read from the first latch 691, the second latch 692, and / or the dynamic latch 680. In some embodiments, the data refiner 601 includes parasitic capacitance at a portion of the metalline of the DATA_TRANSFER signal path 693 between the data refiner 601 and the first latch 691. This parasitic capacitance, along with the data refiner 601, can also function as a dynamic latch, where data values ​​can accumulate during transitions between programming memory cells to higher Vt levels, as referenced. Figures 10A to 10B Let's discuss this in more detail.

[0091] (For example, Figures 1A to 1BThe control logic of the local media controller 135 can be connected to the following control signal paths: SRC_GATE control signal path 633, DW_GATE control signal path 604, BLCLAMP control signal path 612, BLCLAMP2 control signal path 632, EN_DATA control signal path 636, TC_ISO control signal path 648, BLC1 control signal path 664, SEN control signal path 672, SAB_BL_PRE control signal path 619, LAT_SAB control signal path 689, SEN_SAB control signal path 685, DRST_SA control signal path 675, DST_SA control signal path 676, TDCINT_DIS control signal path 605, EN_SA control signal path 615, BCL2 control signal path 697, and EN_LATCH control signal path 629 to control the operation of the page buffer 600. The control logic can activate transistor 631 to selectively connect bit line 204 to the common source 216. The control logic can activate transistor 602 to selectively connect bit line 204 to DW signal path 606. The control logic can activate transistor 610 to selectively connect DW signal path 606 to signal path 614. The control logic can activate transistor 630 to selectively connect signal path 614 to signal path 626. The control logic can activate transistor 634 to selectively connect signal path 614 to signal path 638.

[0092] Control logic can activate transistor 617 to selectively connect SA_OUT signal path 621 to BL_SA_OUT signal path 690. Control logic can activate transistor 646 to selectively connect signal path 614 to TC signal path 650. Control logic can activate transistor 662 to selectively connect TC signal path 650 to TDC_INT signal path 666. Control logic can activate transistor 670 to selectively connect TDC_INT signal path 666 to signal path 674. Control logic can activate transistor 687 of the sense amplifier latch 686 to selectively connect TDC_INT signal path 666 to SA_OUT signal path 621. Control logic can activate transistor 688 to selectively connect TDC_INT signal path 666 to signal path 677. Control logic can control inverter 683 to latch the sensed state of a selected memory cell into the sense amplifier latch 686. The control logic controls inverter 684 to output a latched state from sense amplifier latch 686. The control logic activates transistor 603 to selectively connect TDC_INT signal path 666 to common or ground node 607. The control logic activates transistor 696 to selectively connect TDC_INT signal path 666 to DATA_TRANSFER signal path 693. The control logic activates transistor 613 to selectively connect signal path 611 to common or ground node 607. The control logic activates transistor 627 to selectively connect signal path 625 to common or ground node 607.

[0093] In at least some embodiments, the page buffer 600 further includes a dynamic latch 680 connected on one side to the SA latch 686 and selectively connected to the sense node (TC), for example via a transistor 662, and connected on the other side to a source bias node (e.g., SRC_GND). Reference Figure 6BThe dynamic latch 680 is discussed in more detail. As will be discussed in more detail, an analog voltage value applied to or modified at the sensing node can be digitized and stored in the SA latch 686. Furthermore, the data bit value stored in the SA latch 686 can be applied to the sensing node and manipulated by a bias voltage stored in the dynamic latch 680, thereby generating an updated voltage value at the sensing node. This updated voltage can selectively toggle the data bit value of the SA latch 686. This interchange between the SA latch 686 and the dynamic latch 680 allows the updated TC sensing node to program memory cells using either a slow SSPC voltage (PPV1) or a fast SSPC voltage (PPV2) based on the bias voltage stored in the dynamic latch 680. In this way, the combination of the dynamic latch 680 and the SA latch 686 facilitates the application of multiple bias voltages to SSPC programming. In some embodiments, the bias voltage stored in the dynamic latch 680 can also be used, for example, to perform a programming verification (PV) pass by preventing programming during the next programming pulse.

[0094] In some embodiments, the control logic of the local media controller 135 performs an operation to pass a programming verification voltage (e.g., a blocking bias voltage) to the data refiner 601. This can be performed because the selected memory cell has reached the target Vt voltage to prevent further programming. For example, the operation may include coupling the sensing node (TC) to ground (GND) and, in response to detecting a high-order value stored in the SA latch 686, passing a programming verification voltage (PV pass) to the data refiner 601.

[0095] Figure 6B According to at least one embodiment Figure 6AA detailed schematic diagram of the dynamic latch 680 is provided. In at least one embodiment, the dynamic latch 680 includes an enable transistor 620 connected in series with a latch transistor 608, for example, a source-drain path connecting each transistor. The latch transistor 608 includes a source coupled to a source bias node 682, and the enable transistor 620 includes a drain selectively connected to a sensing node (TC), for example, via a transistor 662. Thus, the enable transistor 620 is coupled between the latch transistor 608 and a sensing line (e.g., TC signal path 650). The dynamic latch 680 may further include one or more setting transistors 628 coupled between the drain of the enable transistor 620 and the gate of the latch transistor 608. For example, the source-drain paths of one or more setting transistors 628 are coupled between the drain of the enable transistor 620 and the gate of the latch transistor 608. The drains of enable transistor 620 and one or more set transistors 628 may also be coupled to SA latch 686, for example, via TCD_INT signal path 666. In various embodiments, the transistors of dynamic latch 680 may be NMOS, PMOS, or a combination of NMOS and PMOS transistors. In some embodiments, page buffer 600 further includes transistor 637, which, for reference... Figures 10A to 10C The purpose of this discussion is to couple the TDC_INT signal path 666 between the dynamic latch 680 and the data refiner 601. Transistor 637 can be turned on by the prech_N signal.

[0096] In some embodiments, capacitor 640 may optionally be coupled between the gates of latch transistor 608, but can also be understood as representing the gate capacitance of latch transistor 608. Thus, one of the gate capacitances of latch transistor 608 or capacitor 640 may store a bias voltage, which is then passed to the latch transistor by one or more set transistors 628. In these embodiments, the gate of latch transistor 608 is connected to D_LATCH signal path 616, the gate of enable transistor 620 is connected to EN_SSPC2 signal path 624, and the gates of one or more set transistors 628 are connected to DL_SET signal path 635.

[0097] In at least some embodiments, the control logic of the local media controller 135 may be coupled to the D_LATCH signal path 616, the EN_SSPC2 signal path 624, and the DL_SET signal path 635. This control logic may perform operations including boosting a preprogrammed verification voltage (PPV) to a sensing node (TC), for example, via a BOOST node 658. In response to detecting a high-order value stored in the SA latch 686, the operation may further include turning on one or more setting transistors 628 such that one of a first bias voltage or a second bias voltage is stored at the latch transistor 608 and / or the capacitor 640.

[0098] For example, a first bias voltage can be used for slow programming of selected memory cells in a series-connected string of memory cells. Furthermore, a second bias voltage can be used for fast programming of selected memory cells in the series-connected string of memory cells, where fast programming is faster than slow programming. In some embodiments, the first bias voltage is higher than the second bias voltage. In some embodiments, the pre-programming verification voltage includes one of a first pre-programming verification voltage (e.g., PPV1) applied when the first bias voltage is stored at the latch transistor or a second pre-programming verification voltage (e.g., PPV2) applied when the second bias voltage is stored at the latch transistor, wherein the first pre-programming verification voltage is lower than the second pre-programming verification voltage. In some embodiments, the first pre-programming verification voltage is approximately half the second pre-programming verification voltage. References below... Figure 7A The programming operation of programming the selected memory cell 208 to the target level is described in more detail in section 9.

[0099] Figures 7A to 7C This describes, according to some embodiments, the method for storing voltage bias in a dynamic latch. Figures 6A to 6B The diagram is a set of graphs showing the associated control and voltage level waveforms (or signals). The control and voltage level waveforms marked on the left side of each graph correspond to... Figures 6A to 6B The control labels in the schematic diagram (e.g., from top to bottom DST_SA, DRST_SA, TDCINT_DIS, SEN, SEN_SAB, LAT_SAB, BLC1, SRC_GND, EN_SSPC, DL_SET, BOOST, TC, SA_OUT, TDC_INT, and D_LATCH) are described generally in chronological order from left to right. The values ​​described for the control and voltage level waveforms are only relative instance values ​​that enable page buffer 600 to function; however, these values ​​can be adjusted uniformly within a certain range and still perform as discussed. Furthermore, some of the control and voltage level waveforms containing the labels "pass," "sspc," and "sspc2" represent general voltage ranges for implementing differential bias voltage levels, but should not be construed as absolute or precise.

[0100] At the start of this memory operation, the control and voltage level waveforms correspond to the programming verification that prepares to perform Vt-level L1 programming in the selected memory cell. Therefore, refer to Figures 7A to 7C The operation described and explained enables the value in SA latch 686 to trigger the storage of a specific value in dynamic latch 680, such as corresponding to one of the slow SSPC voltage (PPV1) or fast SSPC voltage (PPV2).

[0101] At time point 702, the SA latch 686 is reset by asserting the DST_SA, TDCINT_DIS, SEN_SAB, and LAT_SAB control signals, as follows: Figure 7A As explained in the document. Therefore, it can be observed that the SA_OUT and TDC_INT voltage signals drop to ground (GND), while the D_LATCH voltage drops slightly.

[0102] At time point 706, the control logic can enable the value from the SA latch 686 to activate the tdc_int signal, such as... Figure 7B As described in the documentation, the value of the SA latch 686 can be gated by asserting the DRST_SA, TDCINT_DIS, SEN_SAB, and LAT_SAB control signals. Operation at time point 706 provides an initial voltage to the TDC_INT signal path 666. Simultaneously, the control logic can cause a first pre-programmed verification voltage (e.g., PPV1) to be applied as a voltage boost to the sensing node (TC), and thus also to the gate of the sensing transistor 678. Although described as ground (or 0V), in various embodiments other low voltage boosts, such as those in the range of 0 to 0.5V, may also be used, causing all sensing levels of the page buffer 600 to be increased by the boost voltage.

[0103] At time 710, the control logic updates the dynamic latch 680 to store a first bias voltage, which can be used, for example, for slow programming of selected memory cells using a slow SSPC voltage (SSPC). For example, the control logic can assert the DL_SET signal, for example, to a set voltage Vsg (…). Figure 7A This causes the voltage at latch transistor 608 (and D_LATCH signal path 616) to hit the first bias voltage programmed at the level of the common collector voltage (Vcc), as referenced. Figure 7C As illustrated by curve 701. For example, the Vsg voltage can be understood as greater than Vcc plus the threshold voltage (Vtn_set) of one or more set transistors 628. Therefore, after the Vtn_set voltage drops, the voltage remains Vcc stored at latch transistor 608.

[0104] At time 714, the control logic applies a boost voltage to the sensing node (TC). Figure 7A In one embodiment, the boost voltage is a second pre-programmed verification voltage (e.g., PPV2). As illustrated, this second pre-programmed verification voltage can be approximately 0.5V, but other voltage ranges can also be used, such as between 0.5 and 1.0V, where the first pre-programmed verification voltage is lower than the second pre-programmed verification voltage. This additional boost voltage allows all sensing levels of the page buffer 600 to be increased by a target higher boost voltage. It can also be observed that the sa_out voltage signal is always at a high bit value between time points 710 and 714. Furthermore, the assertion BLC1 signal is always de-asserted, thereby enabling the storage of a value into the dynamic latch 680 without loss of charge along the sensing line containing the TC signal path 650.

[0105] At time 718, the control logic can re-enable the SA latch 686 to adjust the TDC_INT voltage signal, such as... Figure 7B As explained in the previous section, the value of the SA latch 686 can be selected by asserting the DRST_SA, TDCINT_DIS, SEN_SAB, and LAT_SAB control signals, as previously described. However, due to the higher boost voltage at the boost node 658, this selection will result in a lower voltage at the TCD_INT node.

[0106] At time 722, the control logic updates the dynamic latch 680 to store a second bias voltage, which can be used for rapid programming of selected memory cells employing a fast SSPC voltage (SSPC2). For example, the control logic can assert the DL_SET control signal to a set voltage, such as approximately Vcc. Figure 7A This causes the voltage at latch transistor 608 (and D_LATCH signal path 616) to hit a second bias voltage programmed at the level of the common collector voltage (Vcc) minus the threshold voltage (Vtn_set) of one or more set transistors 628, as referenced. Figure 7C The curve 705 in the figure illustrates this.

[0107] In various embodiments, storing a bias voltage in dynamic latch 680 can be understood as performing an operation to store a first bias voltage, a second bias voltage, or zero voltage in the dynamic latch such that a given page buffer (e.g., page buffer 600) is configured for a slow programming / verification operation (using an SSPC value), a fast programming / verification operation (using an SSPC2 value), or a programming / verification failure (using zero voltage or a ground value). Once one of these bias voltages is stored in dynamic latch 680, the page buffer can proceed to operations that apply the corresponding bias voltage to a sensing node (TC) to supply one of the bit line biases discussed herein to, for example, a signal driver.

[0108] In some embodiments, to apply a first bias voltage to the sensing node, the control logic of the local media controller 135 may perform operations including applying a trigger voltage to the SA latch 686 (e.g., at the SEN_SAB control signal path 685) and the source bias node 682 (SRC_GND). These operations may further include turning on the enable transistor 620 of the dynamic latch 680, such that after asserting the BLC1 control signal path 664, the first bias voltage stored at the latch transistor 608 is applied to the sensing node (TC) via, for example, transistor 662. In one embodiment, the trigger voltage is a low voltage, for example, between 0.3 and 0.6V.

[0109] In at least one alternative embodiment, after applying the trigger voltage to the source bias node 682, the operation may alternatively further include applying a local voltage source (VSSL) voltage to the SA latch 686 (which is different from the trigger voltage applied to the source bias node 682). The operation may further include turning on the enable transistor 620 such that a first bias voltage stored at the latch transistor 608 is applied to the sensing node (TC).

[0110] In some embodiments, to apply a second bias voltage to the sensing node, the control logic of the local media controller 135 may perform operations including applying a ground voltage to the SA latch 686 (e.g., at the SEN_SAB control signal path 685) and the source bias node 682 (or SRC_GND). These operations may further include turning on the enable transistor 620 of the dynamic latch 680, such that after asserting the BLC1 control signal path 664, the second bias voltage stored at the latch transistor 608 is applied to the sensing node (TC) via, for example, transistor 662. In one embodiment, the ground voltage is, for example, an extremely low voltage of 0 to 0.2V.

[0111] In at least one alternative embodiment, after applying a ground voltage to source bias node 682, the operation may alternatively further include applying a local voltage source (VSSL) voltage to SA latch 686 (which is different from the ground voltage applied to source bias node 682). The operation may further include turning on enable transistor 620 such that a second bias voltage stored at latch transistor 608 is applied to sense node (TC).

[0112] Figure 8 This is a flowchart of an example method 800, according to some embodiments, in which one of a first bias voltage or a second bias voltage, respectively corresponding to a slow selective slow programming convergence voltage or a fast selective slow programming convergence voltage, is selectively stored in a dynamic latch of a page buffer. Method 800 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figures 1A to 1B The local media controller 135, which includes instruction register 128, executes the command.

[0113] Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0114] At operation 810, the sensing node is boosted. More specifically, the processing logic causes a pre-programmed verification voltage (e.g., PPV1 or PPV2) to be boosted to the sensing node (TC) to increase the sensing level of the page buffer. In some embodiments, the processing logic first checks the voltage level at the sensing node (TC) and assigns a sensing boost voltage level (e.g., PPV1, PPV2, or another sensing level) based on the current voltage level at the sensing node (TC).

[0115] At operation 815, SA latch 686 is accessed. More specifically, the processing logic determines whether SA latch 686 stores a high-order or low-order data value. In response to detecting that SA latch 686 stores a low-order value, at operation 820, the processing logic programs an approximate zero voltage level in dynamic latch 680 indicating that SSPC-related operations will not be performed.

[0116] At operation 830, the Selective Slow Programming Convergence Voltage (SSPC) level is stored. More specifically, in response to the SA latch 686 storing a high-order value, the processing logic turns on one or more set transistors 628, causing one of the first bias voltages or a second bias voltage to be stored at latch transistor 608. Depending on the values ​​of the PPV boost voltage and the set voltage, the SSPC voltage level may vary based on whether slow or fast programming is selected for subsequent programming / verification operations.

[0117] At operation 840, a fast or slow SSPC voltage is determined. More specifically, the processing logic determines whether the page buffer is configured to perform programming and verification operations at a slow SSPC voltage (e.g., PPV1) or a fast SSPC voltage (e.g., PPV2). If for slow programming / verification operations, at operation 850, the processing logic applies a first bias voltage for slow programming of selected memory cells in a series-connected string of memory cells. If for fast programming / verification, the processing logic applies a second bias voltage for fast programming of selected memory cells in a series-connected string of memory cells, where fast programming is faster than slow programming.

[0118] Figures 9A to 9C This is according to the description of some embodiments for programming bit line biases into page buffer 600. Figures 6A to 6B The diagram is a set of graphs showing the associated control and voltage level waveforms. The control and voltage level waveforms marked on the left side of each graph correspond to... Figures 6A to 6B The control labels in the schematic diagram (e.g., from top to bottom: DST_SA, DRST_SA, SEN, SEN_SAB, LAT_SAB, SAB_BL_PRE, BLC1, SRC_GND, EN_SSPC2, DL_SET, BLCLAMP2, BLCLAMP, TC_ISO, VREG0, TC, SA_OUT, D_LATCH, BL_SA_OUT, DW) are generally arranged chronologically and described from left to right according to stages (along the top). The values ​​described for the control and voltage level waveforms are only relative instance values ​​that enable the page buffer 600 to function; however, these values ​​can be adjusted uniformly within a certain range and still perform as discussed.

[0119] During phase 1, the control logic sends programming pulses down the bit lines to program selected memory cells in a cascaded string of memory cells, as shown in... Figure 9C The DW signal location is marked in the programming description. It can be accessed via DW signal path 606 ( Figure 6A This DW signal is sent. Furthermore, the control logic increasingly prevents programming during Phase 1, such as... Figure 9CThe curve “Block” illustrates this. To perform this programming / blocking operation, the control logic can also assert the DRST_SA control signal and raise the BLC1 control signal to the Vsg voltage, then lower it to the Vcc voltage. For example, the Vsg voltage can be understood as greater than Vcc plus the threshold voltage (Vtn_tciso) of the sensing node isolation transition (e.g., transistor 646). The control logic can further assert the BLCLAMP2 and BLCLAMP control signals to allow Vcc on the VREG2 signal path to block selected memory cells on bitline 204. Otherwise, for the Vt level used for SSPC, SSPC2, or programming, the SAB_BL_PRE control signal is asserted, causing the ground voltage at the VREG0 power node to couple to selected memory cells on bitline 204.

[0120] Additionally, if possible Figure 9B The D_LATCH voltage signal mentioned in the document states that a value corresponding to one of the programming bias voltage, SSPC2 bias voltage, or SSPC bias voltage is stored in the dynamic latch 680, wherein the bias voltage is referenced. Figures 7A to 7B The operation discussed is stored here. As discussed, one of these bias voltages (if stored) will be used for programming / verification purposes during programming of the page buffer 600 at a specific bias voltage.

[0121] During phase 2-1, although voltage will be blocked from being supplied to the selected cell, the control logic can cause the page buffer 600 to be programmed with three bit-line bias voltages (e.g., for programming bias, SSPC2 bias voltage, or SSPC bias voltage), all of which are at... Figure 9C This is explained in the DW signal. Therefore, in some embodiments and at time period 906, the control logic causes the output voltage (SA_OUT) of the SA latch to be sent to the sensing node (TC) (both in...). Figure 9B (As explained in the text), the output voltage of the SA latch is either ground or the common collector voltage (Vcc). For example, in some embodiments, the SA_OUT output voltage may be Vcc to program a blocking bias level or ground (e.g., approximately zero or other low voltages) to program any of SSPC, SSPC2, or a programming bias voltage. This SA_OUT output voltage can be sent to the sensing node while the BLC1 control signal is still asserted as the Vcc voltage level.

[0122] Furthermore, during phase 2-1 at time period 910, the control logic can further manipulate the first voltage of the sensing node (TC) by the second voltage (D_LATCH) of the dynamic latch 680, such as... Figure 9BAs described, an updated first voltage is generated at the sensing node (TC). For example, manipulating the first voltage of the sensing node (TC) by a second voltage of the dynamic latch 680 may include applying a trigger voltage to the SA latch 686 and the source-biased node 682 (or SRC_GND). In one embodiment, the trigger voltage is, for example, a low voltage between 0.3 and 0.6V. Control logic may further turn on the enable transistor 620 of the dynamic latch 680 (e.g., using the EN_SSPC2 control signal) to send the voltage stored in the latch transistor 608 to the sensing node (TC).

[0123] Furthermore, during phase 2-1 at time period 914, the control logic can further selectively flip the bit value stored in SA latch 686, depending on the updated value of the first voltage of the sensing node (TC), such as Figure 9B As explained in the documentation. For example, if the voltage at the sensing node (TC) is higher than the threshold voltage (Vtn) of transistor 678, the bit value of SA latch 686 flips. During this period, the control logic can also assert the DRST_SA, SEN, SEN_SAB, and LAT_SAB control signals, such as... Figure 9A As explained in the document, this allows for the selective flipping of bit values ​​in the SA latch 686 when necessary.

[0124] More specifically, and continuing to refer to phase 2-1 at and after time period 914, if the voltage at the sensing node (TC) is selectively discharged to a low voltage (e.g., 0.2 to 0.5V), the bit value of the SA latch 686 can remain at a high bit value. However, if the voltage at the sensing node (TC) remains at a voltage higher than the Vtn voltage of the transistor 678, the bit value in the SA latch 686 can be flipped from approximately Vcc to a low bit value, for example, to ground. In this way, the SA latch 686 can store the bit value of the sensing node (TC) corresponding to the voltage of the selective discharge (or the updated first voltage).

[0125] Continue to refer to Figures 6A to 6B According to some embodiments, a bit line clamping transistor 610 is coupled between a sensing line (e.g., a combination of signal path 614 and TC signal path 650) and bit line 204. An enable transistor 634 is coupled between the bit line clamping transistor 610 and a first regulator voltage (VREG0). A second bit line clamping transistor 630 is coupled between the bit line clamping transistor 610 and a second regulator voltage (VREG2).

[0126] Continue to refer to Figures 9A to 9B At the end of stage 2-1, referring to time period 918, the control logic can further turn off the second bit-line clamping transistor 630, for example, in stage 2-1 ( Figure 9AAt the start, the assertion of the BLCLAMP2 control signal is released (or forced to low voltage). The control logic can further move the gate voltage of the bit-line clamp transistor 610 to the clamp voltage, wherein in stage 2-1 ( Figure 9A At the start, the BLCLAMP control signal is adjusted. In some embodiments, this clamping voltage is the difference between the slow selective slow programming convergence voltage (e.g., PPV2) and the fast selective slow programming convergence voltage (e.g., PPV1). The control logic may further enable transistor 634, for example, asserting the EN_DATA control signal (not shown) to send a first regulator voltage (VREG0) to the sensing line as a pre-voltage level for the selective slow programming convergence (SSPC) bias voltage.

[0127] Continue to refer to Figures 6A to 6B According to some embodiments, a lower bias transistor 642 is coupled between a bit line clamping transistor 610 and a first regulator voltage (VREG0). An upper bias transistor 622 is coupled between a second bit line clamping transistor 630 and a second regulator voltage (VREG2). A bit line precharge transistor 617 is coupled between the gates of the lower and upper bias transistors and the SA latch 686.

[0128] Continue to refer to Figures 9A to 9B At approximately the beginning of phase 2-2, for example to include time period 922, the control logic may further keep the second bit line clamp transistor 630 off, and if it remains on, turn off the bit line precharge transistor 617 (although in Figure 9A In this specific instance, the SAB_BL_PRE control signal has already been turned off near the end of phase 2-1. With the bit line precharge transistor 617 off, the BL_SA_OUT voltage signal and the SA_OUT voltage signal can carry different data values. In this way, the BL_SA_OUT voltage signal can be understood as using the parasitic capacitance of the BL_SA_OUT control signal path 690 as another dynamic latch.

[0129] During this first part of phase 2-2, the control logic may also cause an SSPC2-related update to the SA latch 686. For example, the control logic may apply a ground voltage to the source bias node 682 (e.g., SRC_GND), such as Figure 9A As explained in the documentation, the control logic can further assert multiple control signals of the SA latch 686 to update the output voltage (SA_OUT) of the SA latch. For example, these multiple control signals may include the DST_SA, SEN_SAB, and LAT_SAB control signals. Figure 9A ).

[0130] The control logic can be further enhanced, for example, by asserting the EN_SSPC2 control signal ( Figure 9A Turning on the enable transistor 620 of the dynamic latch 680 causes the output voltage of the SA latch 686 to selectively discharge, depending on the voltage stored in the latch transistor ( Figure 9B The bias voltage in the latch transistor 608. For example, if the voltage stored at the latch transistor 608 is approximately Vcc minus the threshold voltage (Vtn_DL) of the transistor in the dynamic latch 680, the bit value in the SA latch 686 can be discharged to ground potential, such as a low bit value. This low bit value may correspond to the fast SSPC bias voltage (e.g., SSPC2).

[0131] Continue to refer to Figures 6A to 6B The isolation transistor 646 is connected to the sensing line and coupled between the bit line clamping transistor 610 and the dynamic latch 680. (Continue to the previous section) Figures 9A to 9C In some embodiments, during the latter part of phase 2-2 (e.g., at approximately time period 926), the control logic of the local media controller 135 further causes bit line 204 to be biased with an SSPC2 level bias voltage, wherein the SA latch 686 is updated earlier.

[0132] Therefore, in various embodiments, the control logic can be achieved by deasserting the BLCLAMP2 and SAB_BL_PRE control signals respectively. Figure 9A The second bit-line clamp transistor 630 remains off, and the bit-line precharge transistor 617 remains off. Furthermore, the control logic can apply a Vcc voltage to the source-biased node 682 of the dynamic latch 680 (e.g., SRC_GND). The control logic can further trigger the SA latch 686 to release fast programming for the selected memory cell. Figure 9B The bias voltage, such as the fast SSPC2 bias voltage, is used. Simultaneously, the control logic can, for example, turn on transistor 662 by asserting the BLC1 control signal as voltage Vsg. The control logic can further cause isolation transistor 646 to, for example, add a threshold voltage (Vtn_tciso) to VSSPC2 by asserting the TC_ISO control signal as VSSPC2. Figure 9A The clamping bias voltage.

[0133] Furthermore, the control logic can drive bit line 204 via a slow SSPC bias voltage from VREG0, and can shift the BLCLAMP control signal up to the Vsspc clamp level to clamp the bit line clamp transistor 610 with the slow SSPC bias voltage. More specifically, the control logic can increase the clamp voltage applied to the gate of bit line clamp transistor 610, where the increased clamp voltage is the slow selective slow programming convergence (SSPC) voltage plus the threshold voltage (Vtn_tciso) of the isolation transistor. The control logic can further turn on the lower bias transistor 642 to pass the first regulator voltage (VREG0) to bit line clamp transistor 610. Figure 9C The DW voltage signal indicates either the SSPC or SSPC2 bias voltage applied during time period 926.

[0134] Figures 10A to 10B This describes, according to some embodiments, the method for accumulating bias voltage levels between programming operations at multiple threshold voltage levels. Figures 6A to 6B The diagram shows a set of graphics related to the control and voltage level waveforms. Figure 10C Based on the description and illustration of some embodiments Figures 10A to 10B The graph is annotated with the data stream through page buffer 600. Figure 10C The annotation table contains several time periods (TPs) referenced in the leftmost column, which correspond to the time periods in Figures 10A to 10B The same time period is marked on the graph.

[0135] In various embodiments, the accumulation indicated by the control logic reference page buffer 600 has an SSPC-related bias voltage, which will be used in SSPC-related programming and programming verification of a second Vt level (e.g., L2) within the multi-level cell (MLC). For example, the control logic of the local media controller 135 may guide the accumulation of a first-level (L1) Vt bias voltage (LV1) stored in dynamic latch 680 and a second-level (L2) Vt bias voltage (LV2) stored at the sensing node (TC), and once combined, the accumulated LV1 and LV2 values ​​associated with L2 SSPC2 programming are stored in dynamic latch 680. Once this accumulation has been completed, page buffer 600 is ready to perform programming / verification based on L2 selective slow programming convergence (SSPC) that will follow the initial programming / verification of the selected memory cell.

[0136] In various embodiments, at the start of the cumulative operation, described as time period 1002, the initial state of page buffer 600 is that the selected memory cell has been programmed and verified at the LV2 threshold voltage (Vt), and therefore, one of the LV2 SSPC bias voltage or the LV2 SSPC2 bias voltage is stored at the sensing node (TC). This LV2 (SSPC or SSPC2) bias voltage will depend on the sensed Istring voltage value of the memory cell string. Furthermore, at dynamic latch 680, for example at the D_LATCH signal 616, one of the LV1 SSPC bias voltage or the LV1 SSPC2 bias voltage is stored.

[0137] Furthermore, at time period 1006, in at least some embodiments, the control logic resets the SA latch 686. In at least one embodiment, the SA latch 686 is reset by asserting the DST_SA, TDCINT_DIS, SEN_SAB, and LAT_SAB control signals, such as... Figure 10A As explained in the text. Therefore, it can be observed that the SA_OUT data signal goes high and the TDC_INT voltage signal drops to ground (GND), while the D_LATCH voltage signal drops slightly ( Figure 10B ).

[0138] Additionally, at time period 1010, in at least some embodiments, for example by bringing the source bias node 682 (e.g., SRC_GND) to a low voltage above ground to turn off the LV1 SSPC2 value stored in dynamic latch 680, the control logic copies the LV2 SSPC value to SA latch 686. Therefore, SA latch 686 can then store the data bit value corresponding to the LV1 SSPC bias voltage, such as... Figure 10B As explained earlier, the EN_SSPC2 signal is asserted to enable transistor 620 and the bias voltage stored at latch transistor 608 is read.

[0139] Furthermore, at time period 1014, in at least some embodiments, the control logic will be stored in the sensing node (TC) ( Figure 10A The voltage at point ) is selected to the SA latch 686 ( Figure 10B At the same time, the PPV1 boost voltage (boost_ppv1) is applied to the boost node 658 to provide boost modulation.

[0140] Additionally, at time period 1018, in at least some embodiments, the control logic causes the data stored in dynamic latch 680 to... Figure 10B The LV1 SSPC2 bias voltage in ) is backed up to the DATA_TRANSFER signal path 693, which acts as another dynamic latch. Figure 10BFor example, the DATA_TRANSFER signal path 693 adjacent to the data refiner 601 can act as a parasitic capacitance to store voltage levels / data, as referenced. Figure 6A To elaborate further. For the purpose of this backup of storing the LV1 SSPC bias voltage to the DATA_TRANSFER signal path 693, the control logic can be configured via the prech_N signal ( Figure 10A ) Turn on transistor 637 ( Figure 6B This provides the voltage supply to the TDC_INT signal path 666. A slightly extended time period 1018 is used to provide time for obtaining the value of the D_LATCH signal from the LV1 SSPC2 bias voltage discharge for the DATA_TRANSFER signal path 693.

[0141] Furthermore, at time period 1022, in at least some embodiments, the control logic may cause the data value in SA latch 686 to be copied to dynamic latch 680, for example, stored in latch transistor 608. For this purpose, the control logic may cause the dl_set control signal to reach a voltage of approximately Vsg. For example, the Vsg voltage can be understood as greater than Vcc plus the threshold voltage (Vtn_set) of one or more set transistors 628.

[0142] Additionally, at time period 1028, in at least some embodiments, the control logic resets the SA latch 686 again. In at least one embodiment, the SA latch 686 is reset by asserting the DST_SA, TDCINT_DIS, SEN_SAB, and LAT_SAB control signals, such as... Figure 10A As explained in the text. Therefore, it can be observed that the SA_OUT data signal goes low and the TDC_INT voltage signal drops to ground (GND), while the D_LATCH voltage signal drops slightly ( Figure 10B When the TDCINT_DIS signal is asserted, the SA latch 686 can be discharged through transistor 603. Figure 10B ).

[0143] Additionally, at time period 1032, in at least some embodiments, the control logic copies the value of the LV1 SSPC2 bias voltage from the DATA_TRANSFER signal path 693 to the SA latch 686. All bias voltages can then correspond to the high-order values ​​in the SA latch 686, such as the programming verification value for LV1, which is also held in the high-order value. Time period 1032 is also slightly extended to provide time for discharging the DATA_TRANSFER signal path 693. Furthermore, the EN_SA control signal of the data refiner 601, as well as the DST_SA, LAT_SAB, and SEN_SAB control signals, are asserted.

[0144] Furthermore, at time period 1036, in at least some embodiments, the control logic gates the voltage stored at the sensing node (TC) to the SA latch 686, while simultaneously applying a second pre-programmed verification boost voltage (boost_ppv2) to the boost node 658 to provide boost modulation. Therefore, the SA latch 686 now stores a bit value associated with both the LV1 SSPC2 and LV2 SSPC2 bias voltages, thus completing the accumulation of the two bias voltages as a bit value stored in the SA latch 686. If the bit value is now low, it again corresponds to a programming verification failure (or ground) voltage level. The other three bias voltages correspond to high bit values.

[0145] Finally, at time period 1040, in at least some embodiments, the control logic causes the dynamic latch 680 to be updated to store the bias voltage corresponding to the accumulated bias voltage of LV1 SSPC2 and LV2 SSPC2, as in Figure 10B The increased voltage at the D_LATCH signal 616 is explained in the diagram. During this accumulation step, the DL_SET signal can be set to the common collector voltage (Vcc), while the boost node 658 can be held at the boost_ppv2 level. The TDC_INT signal is also increased during this time.

[0146] Figure 11 The example machine illustrating computer system 1100 is described, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 1100 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A The operation of the local media controller 135, also referred to herein as control logic, is described herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0147] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0148] Example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1110 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1118, which communicate with each other via a bus 1130.

[0149] Processing device 1102 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1102 is configured to execute instructions 1128 for performing the operations and steps discussed herein. Computer system 1100 may further include a network interface device 1112 for communication on network 1120.

[0150] Data storage system 1118 may include machine-readable storage medium 1124 (also referred to as computer-readable medium) on which one or more sets of instructions 1128 or software embodying any one or more methods or functions described herein are stored. Data storage system 1118 may further include the previously discussed local media controller 135. Instructions 1128 may also reside wholly or at least partially within main memory 1104 and / or processing device 1102 during execution by computer system 1100, which also constitute machine-readable storage medium. Machine-readable storage medium 1124, data storage system 1118, and / or main memory 1104 may correspond to... Figure 1A The memory subsystem 110.

[0151] In one embodiment, instruction 1126 includes instructions for implementing a controller (e.g., Figure 1A The memory subsystem controller 115) provides functional instructions. Although the machine-readable storage medium 1124 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0152] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0153] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that control and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or similar data represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0154] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each media coupled to a computer system bus.

[0155] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices for performing the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0156] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., non-transitory computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0157] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: The sensing amplifier SA latch is selectively connected to the sensing node; A dynamic latch, connected to the SA latch and selectively connected to the sensing node, the dynamic latch comprising: A latch transistor having a source coupled to a source bias node and a drain selectively connected to the sensing node; and One or more setting transistors are coupled between the SA latch and the gate of the latch transistor, and the one or more setting transistors are also selectively connected to the sensing node; A sensing line, comprising the sensing node and selectively connected to the SA latch, the dynamic latch, and a bit line coupled to a serially connected string of memory cells; and Control logic, coupled to at least the SA latch and the dynamic latch, is configured to perform operations including: The pre-programmed verification voltage is used to boost the sensing node; and In response to detecting a high-order value stored in the SA latch, a setting voltage is turned on by one or more setting transistors, such that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein: The first bias voltage can be used for slow programming of selected memory cells in the series-connected string of memory cells; and The second bias voltage can be used for fast programming of selected memory cells in the series-connected string of memory cells, wherein the fast programming is faster than the slow programming.

2. The memory device of claim 1, wherein the first bias voltage is higher than the second bias voltage, and wherein the preprogramming verification voltage includes one of a first preprogramming verification voltage applied when the first bias voltage is stored at the latch transistor or a second preprogramming verification voltage applied when the second bias voltage is stored at the latch transistor, wherein the first preprogramming verification voltage is lower than the second preprogramming verification voltage.

3. The memory device of claim 2, wherein the amplitude of the first preprogramming verification voltage is approximately half the amplitude of the second preprogramming verification voltage.

4. The memory device of claim 1, wherein the first bias voltage is associated with a first pre-programming verification voltage and programmed at the level of a common collector voltage (Vcc), and wherein the setting voltage is greater than Vcc plus the threshold voltage of the one or more setting transistors.

5. The memory device of claim 4, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sensing line, and wherein, in order to apply the first bias voltage to the sensing node, the operation further comprises: A trigger voltage is applied to the SA latch and the source bias node; and Turning on the enable transistor causes the first bias voltage stored at the latch transistor to be applied to the sensing node.

6. The memory device of claim 4, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sensing line, and wherein, in order to apply the first bias voltage to the sensing node, the operation further comprises: A trigger voltage is applied to the source bias node; The local voltage source VSSL voltage is applied to the SA latch; and Turning on the enable transistor causes the first bias voltage stored at the latch transistor to be applied to the sensing node.

7. The memory device of claim 1, wherein the second bias voltage is associated with a second pre-programming verification voltage and is programmed at a level of common collector voltage (Vcc) minus the threshold voltage of the latch transistor, and wherein the setting voltage is approximately the pre-programming verification voltage plus the threshold voltage of the one or more setting transistors.

8. The memory device of claim 7, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sensing line, and wherein, in order to apply the second bias voltage to the sensing node, the operation further comprises: Apply a ground voltage to the SA latch and the source bias node; and Turning on the enable transistor causes the second bias voltage stored at the latch transistor to be applied to the sensing node.

9. The memory device of claim 7, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sensing line, and wherein, in order to apply the second bias voltage to the sensing node, the operation further comprises: Apply a ground voltage to the source bias node; The local voltage source VSSL voltage is applied to the SA latch; and Turning on the enable transistor causes the second bias voltage stored at the latch transistor to be applied to the sensing node.

10. The memory device of claim 1, further comprising a data refiner coupled to the SA latch, wherein the operation further comprises: Couple the sensing node to ground; and In response to the detection of the high-order value stored in the SA latch, programming verification is transmitted to the data refiner via voltage.

11. A method of operating a memory device, the memory device comprising a sense amplifier SA latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node, the dynamic latch comprising a latch transistor and one or more setting transistors; A sensing line, including the sensing node and selectively connected to the SA latch, the dynamic latch, and a bit line coupled to a serially connected string of memory cells, wherein the method of operating the memory device includes performing a plurality of operations, including: The pre-programmed verification voltage is used to boost the sensing node; and In response to detecting a high-order value stored in the SA latch, a setting voltage is turned on by one or more setting transistors of the dynamic latch, such that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein: The first bias voltage can be used for slow programming of selected memory cells in the series-connected string of memory cells; and The second bias voltage can be used for fast programming of selected memory cells in the series-connected string of memory cells, wherein the fast programming is faster than the slow programming.

12. The method of claim 11, wherein the first bias voltage is higher than the second bias voltage, and wherein the pre-programmed verification voltage includes one of a first pre-programmed verification voltage for storing the first bias voltage at the latch transistor or a second pre-programmed verification voltage for storing the second bias voltage at the latch transistor, wherein the first pre-programmed verification voltage is lower than the second pre-programmed verification voltage.

13. A memory device comprising: The sensing amplifier SA latch is selectively connected to the sensing node; A dynamic latch, which is connected to the SA latch and selectively connected to the sensing node; A sensing line, which includes the sensing node and is selectively connected to the SA latch, the dynamic latch, and a bit line, wherein the bit line is coupled to a series-connected string of memory cells; and Control logic, coupled to the SA latch and the dynamic latch, wherein, in order to program the bit line bias, the control logic performs operations including the following: A programming pulse is sent down the bit line to program a selected memory cell in the serially connected string of memory cells. The output voltage of the SA latch is sent to the sensing node, wherein the output voltage of the SA latch is the common collector voltage (Vcc); The first voltage of the sensing node is selectively discharged by the dynamic latch to generate a new first voltage at the sensing node; and Depending on the value of the updated first voltage of the sensing node, the bit value stored in the SA latch is selectively flipped.

14. The memory device of claim 13, wherein the dynamic latch comprises: An enable transistor is connected in series with a latch transistor, the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively connected to the sensing node; and One or more setting transistors are coupled between the drain of the enable transistor and the gate of the latch transistor; and The selective discharge of the first voltage of the sensing node by the second voltage of the dynamic latch includes: A trigger voltage is applied to the SA latch and the source bias node; and The enable transistor is turned on to selectively discharge the updated first voltage at the sensing node via the dynamic latch.

15. The memory device of claim 13, further comprising: Bit line clamping transistor, which is coupled between the sensing line and the bit line; Enable the transistor, which is coupled between the bit-line clamping transistor and the first regulator voltage; and A second bit-line clamping transistor is coupled between the bit-line clamping transistor and the second regulator voltage; and The operation further includes: Turn off the second bit-line clamping transistor; Shift the voltage at the gate of the bit-line clamping transistor to the clamping voltage; and The enable transistor is turned on to send the first regulator voltage to the sensing line as a pre-voltage level for selectively and slowly programming the convergence voltage.

16. The memory device of claim 15, wherein the clamping voltage includes the difference between a first preprogramming verification voltage and a second preprogramming verification voltage.

17. The memory device of claim 15, further comprising: The lower bias transistor is coupled between the bit line clamping transistor and the first regulator voltage; The upper bias transistor is coupled between the second bit-line clamping transistor and the second regulator voltage; and Bit-line precharge transistor, which is coupled between the gates of the lower and upper bias transistors and the SA latch; and The operation further includes: Keep the second bit-line clamp transistor off; and Turn off the bit line precharge transistor.

18. The memory device of claim 17, wherein the dynamic latch comprises: An enable transistor is connected in series with a latch transistor, the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively connected to the sensing node; and One or more setting transistors are coupled between the drain of the enable transistor and the gate of the latch transistor; and The operation further includes: Apply a ground voltage to the source bias node; Assert multiple control signals of the SA latch to update the output voltage of the SA latch; and The enable transistor is turned on according to the bias voltage stored in the latch transistor, so that the output voltage of the SA latch is selectively discharged.

19. The memory device of claim 17, further comprising: An isolation transistor is connected to the sensing line and coupled between the bit line clamping transistor and the dynamic latch; and The operation further includes: Keep the second bit-line clamp transistor off; Keep the bit line precharge transistor off; The Vcc is applied to the source bias node of the dynamic latch; Trigger the SA latch to release the bias voltage used for fast programming of the selected memory cell; and The isolation transistor clamps the bias voltage.

20. The memory device of claim 19, wherein the operation further comprises: Increase the clamping voltage applied to the gate of the bit line clamping transistor, wherein the increased clamping voltage comprises a first pre-programmed verification voltage plus the threshold voltage of the isolation transistor; and Turn on the lower bias transistor to pass the first regulator voltage to the bit line clamp transistor.

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