Semiconductor element with programmable cell and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a first dielectric layer disposed on a substrate; first / second upper minor axis portions extending along a first direction, disposed apart from each other, and disposed on the first dielectric layer; a common source region disposed in the substrate and adjacent to the first / second upper minor axis portions; a first branch drain region disposed in the substrate, adjacent to the first upper minor axis portion, and disposed opposite the common source region; a second branch drain region disposed in the substrate, adjacent to the second upper minor axis portion, and disposed opposite the common source region; and an upper electrode disposed on the first dielectric layer and topographically disposed on the first branch drain region and the second branch drain region. The upper electrode, the first dielectric layer, and the first / second branch drain regions together configure a programmable cell.

Description

[0001] Cross-references

[0002] This application claims priority and benefits from U.S. formal application No. 17 / 464,619, filed September 1, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. More particularly, it relates to a semiconductor device having programmable units and a method for fabricating the semiconductor device. Background Technology

[0004] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasing problems, both in number and complexity. Therefore, the challenge of improving quality, yield, performance, and reliability, while reducing complexity, continues.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device including a first dielectric layer disposed on a substrate; a first upper short axis portion and a second upper short axis portion extending along a first direction, spaced apart from each other, and disposed on the first dielectric layer; a first common source region disposed in the substrate and adjacent to the first upper short axis portion and the second upper short axis portion; a first branch drain region disposed in the substrate, adjacent to the first upper short axis portion, and disposed opposite to the first common source region; a second branch drain region disposed in the substrate, adjacent to the second upper short axis portion, and disposed opposite to the first common source region; and an upper electrode disposed on the first dielectric layer and topologically disposed on the first branch drain region and the second branch drain region. The upper electrode, the first dielectric layer, the first branch drain region, and the second branch drain region are configured together to form a first programmable unit.

[0007] In some embodiments, the semiconductor device further includes a first long axis portion and a second long axis portion. The first long axis portion is disposed on the first dielectric layer, extends along a second direction perpendicular to the first direction, and is connected to one end of the first upper short axis portion, the end of which is disposed opposite to the second upper short axis portion. The second long axis portion is disposed on the first dielectric layer, extends along the second direction, and is connected to one end of the second upper short axis portion, the end of which is disposed opposite to the first upper short axis portion.

[0008] In some embodiments, the semiconductor device further includes a first lower short axis portion, a second lower short axis portion, a second common source region, and a second programmable unit. The first lower short axis portion is disposed on the first dielectric layer, parallel to the first upper short axis portion, and connected to the first long axis portion. The second lower short axis portion is disposed on the first dielectric layer, parallel to the second upper short axis portion, connected to the second long axis portion, and located opposite to the first lower short axis portion. The second common source region is disposed in the substrate, separated from the first common source region, and adjacent to the first lower short axis portion and the second lower short axis portion. The second programmable unit is disposed separately from the first programmable unit along the second direction and includes a first branch drain region disposed in the substrate, adjacent to the first lower short axis portion, and disposed opposite to the second common source region; a second branch drain region disposed in the substrate, adjacent to the second lower short axis portion, and disposed opposite to the second common source region; and an upper electrode disposed on the first dielectric layer and disposed on the first branch drain region and the second branch drain region in a topographic structure.

[0009] In some embodiments, the semiconductor element further includes an upper contact point disposed on the upper electrode of the first programmable unit.

[0010] In some embodiments, the width of the upper contact point is less than a horizontal distance between the first branch drain region and the second branch drain region of the first programmable unit.

[0011] In some embodiments, the length of the upper contact point is greater than or equal to the width of the upper electrode of the first programmable unit.

[0012] In some embodiments, the semiconductor element further includes an upper conductive layer disposed on the upper contact point and extending along the first direction.

[0013] In some embodiments, the semiconductor element further includes a plurality of second spacers disposed on each sidewall of the upper conductive layer; wherein the plurality of second spacers include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

[0014] In some embodiments, the semiconductor element further includes a source contact point disposed on the first common source region.

[0015] In some embodiments, the semiconductor element further includes a bit line disposed at the source contact point and extending along the first direction.

[0016] In some embodiments, the width of the upper electrode is greater than or equal to the width of the source contact point.

[0017] In some embodiments, the semiconductor device further includes a third upper short axis portion, a fourth upper short axis portion, a second common source region, and a second programmable unit. The third upper short axis portion is disposed on the first dielectric layer, disposed opposite to the second upper short axis portion and the second long axis portion sandwiched therebetween, and extends along the first direction. The fourth upper short axis portion is disposed on the first dielectric layer, spaced apart from the third upper short axis portion, disposed opposite to the second long axis portion, and extends along the first direction; wherein the second common source region is disposed in the substrate and adjacent to the third upper short axis portion and the fourth upper short axis portion. The second programmable unit is disposed separately from the first programmable unit along the first direction and includes a first branch drain region disposed in the substrate, adjacent to the third upper short axis portion, and disposed opposite to the second common source region; a second branch drain region disposed in the substrate, adjacent to the fourth upper short axis portion, and disposed opposite to the second common source region; and an upper electrode disposed on the first dielectric layer and disposed on the first branch drain region and the second branch drain region in a topographic structure.

[0018] In some embodiments, the semiconductor device further includes a first upper contact, a second upper contact, and an upper conductive layer. The first upper contact is disposed on the upper electrode of the first programmable unit. The second upper contact is disposed on the upper electrode of the second programmable unit. The upper conductive layer extends along the first direction and is disposed on the first upper contact and the second upper contact.

[0019] In some embodiments, the semiconductor device further includes a first source contact, a second source contact, and a bit line. The first source contact is disposed on the first common source region. The second source contact is disposed on the second common source region. The bit line extends along the first direction and is disposed on the first source contact and the second source contact.

[0020] In some embodiments, the width of the first source contact is greater than the width of the first upper contact.

[0021] In some embodiments, the width of the first source contact is greater than or equal to a distance between the first branch drain region and the second branch drain region of the first programmable unit.

[0022] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including forming a common source region, a first branch drain region, and a second branch drain region in a substrate; wherein the first branch drain region and the second branch drain region are parallel to each other and are both separated from the common source region; forming a first dielectric layer on the substrate; forming a first upper short axis portion and a second upper short axis portion on the first dielectric layer; wherein the first upper short axis portion and the second upper short axis portion extend along a first direction and are separated from each other; wherein the first upper short axis portion is disposed between the common source region and the first branch drain region, and the second upper short axis portion is disposed between the common source region and the second branch drain region; and forming an upper electrode on the first dielectric layer, and topologically disposed on the first branch drain region and the second branch drain region. The first branch drain region, the second branch drain region, the first dielectric layer, and the upper electrode are configured together to form a programmable unit.

[0023] In some embodiments, the method for fabricating the semiconductor element further includes: forming an upper contact point on the upper electrode; forming a source contact point on the common source region along the first direction; forming an upper conductive layer on the upper contact point and extending along the first direction; and forming a bit line on the source contact point and extending along the first direction.

[0024] In some embodiments, the upper electrode and the first upper short shaft portion are formed simultaneously.

[0025] In some embodiments, the upper contact point and the source contact point are formed simultaneously.

[0026] Due to the design of the semiconductor device disclosed herein, the resistance of the programmable cell can be adjusted by controlling the number of activated (e.g., voltage-applied) word line structures. Furthermore, by using the conductive layer and the bit lines, which are simultaneously coupled to multiple programmable cells, it is possible to individually control the programming state (fuse-out or not) and resistance state of each programmable cell.

[0027] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0028] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0029] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 2 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0031] Figure 3 This is a cross-sectional schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0033] Figures 5 to 8 This is a cross-sectional schematic diagram illustrating various intermediate semiconductor elements of an embodiment of the present disclosure.

[0034] Figure 9 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0035] Figures 10 to 15 This is a cross-sectional schematic diagram illustrating various intermediate semiconductor elements of an embodiment of the present disclosure.

[0036] Figure 16 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0037] Figures 17 to 18 This is a cross-sectional schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0038] Figure 19 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0039] Figures 20 to 22 This is a cross-sectional schematic diagram illustrating various intermediate semiconductor elements of an embodiment of the present disclosure.

[0040] Figure 23 This is a cross-sectional schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 10: Preparation method

[0043] 101: Base

[0044] 103: Insulation layer

[0045] 105: First interlayer dielectric layer

[0046] 107: Second interlayer dielectric layer

[0047] 109: First Gap

[0048] 111: Second gap

[0049] 211: Common Source Region

[0050] 213: Common source pole region

[0051] 215: Common Source Region

[0052] 217: Common Source Region

[0053] 221: Common source pole region

[0054] 223: Common source pole region

[0055] 225: Common source pole region

[0056] 227: Common source pole region

[0057] 231: Drain region of the first branch

[0058] 233: Drain region of the first branch

[0059] 235: Drain region of the first branch

[0060] 237: Drain region of the first branch

[0061] 241: Drain region of the first branch

[0062] 243: Drain region of the first branch

[0063] 245: Drain region of the first branch

[0064] 247: Drain region of the first branch

[0065] 251: Second branch drain region

[0066] 253: Second branch drain region

[0067] 255: Second branch drain region

[0068] 257: Second branch drain region

[0069] 261: Second branch drain region

[0070] 263: Second branch drain region

[0071] 265: Second branch drain region

[0072] 267: Second branch drain region

[0073] 271: First dielectric layer

[0074] 311: Upper electrode

[0075] 313: Upper electrode

[0076] 315: Upper electrode

[0077] 317: Upper electrode

[0078] 321: Upper electrode

[0079] 323: Upper electrode

[0080] 325: Upper electrode

[0081] 327: Upper electrode

[0082] 351: Upper contact point

[0083] 353: Upper contact point

[0084] 355: Upper contact point

[0085] 357: Upper contact point

[0086] 361: Upper contact point

[0087] 363: Upper contact point

[0088] 365: Upper contact point

[0089] 367: Upper contact point

[0090] 371: Source contact point

[0091] 373: Source contact point

[0092] 375: Source contact point

[0093] 377: Source contact point

[0094] 381: Source contact point

[0095] 383: Source contact point

[0096] 385: Source contact point

[0097] 387: Source contact point

[0098] 411: Upper conductive layer

[0099] 413: Upper conductive layer

[0100] 421: Bitline

[0101] 423: Bitline

[0102] 511: First character line structure

[0103] 513: First character line structure

[0104] 513L: First long shaft section

[0105] 513LS: First lower short shaft section

[0106] 513US: First upper short shaft section

[0107] 515: First character line structure

[0108] 515L: First long shaft section

[0109] 515LS: First lower short shaft section

[0110] 515US: First upper short shaft section

[0111] 517: First character line structure

[0112] 521: Second character line structure

[0113] 523: Second character line structure

[0114] 523L: Second long shaft section

[0115] 523LS: Second lower short shaft section

[0116] 523US: Second upper short shaft section

[0117] 525: Second character line structure

[0118] 525L: Second long wheelbase section

[0119] 525LS: Second lower short shaft section

[0120] 525US: Second upper short shaft section

[0121] 527: Second character line structure

[0122] 811: Prefabricated Active Zone

[0123] 813: Prefabricated active zone

[0124] 821: Prefabricated Active Zone

[0125] 823: Prefabricated active zone

[0126] 831: Prefabricated Active Zone

[0127] 833: Prefabricated Active Zone

[0128] 841: Prefabricated Active Zone

[0129] 843: Prefabricated active zone

[0130] 851: First masking layer

[0131] 853: First masking layer

[0132] H1: Horizontal distance

[0133] L1: Length

[0134] PU1: Programmable Unit

[0135] PU2: Programmable Unit

[0136] PU3: Programmable Unit

[0137] PU4: Programmable Unit

[0138] PU5: Programmable Unit

[0139] PU6: Programmable Unit

[0140] PU7: Programmable Unit

[0141] PU8: Programmable Unit

[0142] S11: Steps

[0143] S13: Steps

[0144] S15: Steps

[0145] S17: Steps

[0146] W1: Width

[0147] W2: Width

[0148] W3: Width

[0149] W4: Width

[0150] X: Direction

[0151] Y: direction Detailed Implementation

[0152] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0153] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0154] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0155] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0156] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term “substantially” may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0157] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0158] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0159] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element according to an embodiment of the present disclosure. Figure 2 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along... Figure 2 Part of the process for fabricating semiconductor devices using cross-sections A-A' and B-B'.

[0160] Please refer to Figures 1 to 8 In step S11, a plurality of common source regions 211, 213, 215, 217, 221, 223, 225, 227, a plurality of first branch drain regions 231, 233, 235, 237, 241, 243, 245, 247, and a plurality of second branch drain regions 251, 253, 255, 257, 261, 263, 265, 267 may be formed in a substrate 101, and a first dielectric layer 271 may be formed on the substrate 101.

[0161] Please refer to Figure 2 and Figure 3 The substrate 101 may be a bulk semiconductor substrate, a multilayer or gradient substrate, or the like. The substrate 101 may include a semiconductor material, such as an elemental semiconductor, a compound or alloy semiconductor, or a combination thereof, where the elemental semiconductor is such as silicon or germanium, and the chemical or metallic semiconductor is such as silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, aluminum gallium arsenide, gallium indium arsenide, indium arsenide, gallium indium phosphide, indium antimonide, or gallium indium arsenide phosphide. The substrate 101 may be doped or undoped.

[0162] Please refer to Figure 2 and Figure 3 An insulating layer 103 may be formed in the substrate 101. For example, the insulating layer 103 may be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. The insulating layer 103 may define multiple regions of multiple pre-active regions 811, 813, 821, 823, 831, 833, 841, and 843.

[0163] It should be understood that, in this disclosure, silicon oxynitride represents a substance comprising silicon, nitrogen, and oxygen, wherein the oxygen content is greater than the nitrogen content. Silicon nitride oxide represents a substance comprising silicon, oxygen, and nitrogen, wherein the nitrogen content is greater than the oxygen content.

[0164] Please refer to Figure 2 and Figure 3 An implantation process can be performed to form multiple pre-fabricated active regions 811, 813, 821, 823, 831, 833, 841, and 843 in a substrate 101, surrounded by an insulating layer 103. The dopants in the implantation process can include p-type impurities (dopants) or n-type impurities (dopants). These p-type impurities can be added to an intrinsic semiconductor to create defects with multiple valence electrons. Examples of p-type dopants (i.e., impurities) in a silicon-containing substrate include, but are not limited to, boron, aluminum, gallium, and indium. These n-type impurities can be added to an intrinsic semiconductor to contribute multiple free electrons to the intrinsic semiconductor. Examples of n-type dopant (i.e., impurities) in a silicon-containing substrate include, but are not limited to, antimony, arsenic, and phosphorus. After the implantation process, the multiple pre-fabricated active regions 811, 813, 821, 823, 831, 833, 841, and 843 can have an electrical type, such as n-type or p-type. In this embodiment, the electrical type of the multiple prefabricated active zones 811, 813, 821, 823, 831, 833, 841, and 843 can be p-type.

[0165] Multiple prefabricated active zones 811, 813, 821, 823, 831, 833, 841, and 843 can be staggered along direction (or dimension) X and direction (or dimension) Y. That is, along direction X or direction Y, adjacent prefabricated active zones can be spaced approximately the same distance apart. In a top view, the upper column of prefabricated active zones 811, 821, 831, and 841 can have a U-shaped profile. In a top view, the lower column of prefabricated active zones 813, 823, 833, and 843 can have an inverted U-shaped profile.

[0166] Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 and Figure 6 This is a cross-sectional schematic diagram illustrating a portion of the process for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 4 The cross-sections along sections A-A' and B-B', and sections C-C' and D-D'.

[0167] Please refer to Figures 4 to 6Multiple first masking layers 851, 853 may be formed on the substrate 101. The multiple first masking layers 851, 853 may extend along direction X and may be spaced apart from each other. In a top view, the first masking layer 851 may span the upper column of the prefabricated active regions 811, 821, 831, 841 to divide each prefabricated active region 811, 821, 831, 841 into multiple upper portions and multiple lower portions, while covering the portions of the prefabricated active regions 811, 821, 831, 841 below the first masking layer 851. Accordingly, the first masking layer 853 may span the next column of the prefabricated active areas 811, 821, 831, 841 to divide each prefabricated active area 813, 823, 833, 843 into multiple upper portions and multiple lower portions, while covering the portions of the prefabricated active areas 813, 823, 833, 843 below the first masking layer 853.

[0168] Please refer to Figures 4 to 6 An implantation process involving n-type dopant can be performed, wherein the electrical type of the pre-fabricated active regions 811, 813, 821, 823, 831, 833, 841, and 843 is opposite, with the doped pre-fabricated active regions 811, 813, 821, 823, 831, 833, 841, and 843 serving as masking portions. After the implantation process, the upper portions of the pre-fabricated active regions 811, 821, 831, and 841 can be respectively and correspondingly transformed into multiple first branch drain regions 231, 233, 235, and 237 and multiple second drain regions 251, 253, 255, and 257. The lower portions of the pre-fabricated active regions 811, 821, 831, and 841 can be respectively and correspondingly transformed into multiple common source regions 211, 213, 215, and 217. The upper portions of the prefabricated active regions 813, 823, 833, and 843 can be respectively and correspondingly transformed into multiple common source regions 221, 223, 225, and 227. The lower portions of the prefabricated active regions 813, 823, 833, and 843 can be respectively and correspondingly transformed into multiple first branch drain regions 241, 243, 245, and 247 and multiple second branch drain regions 261, 263, 265, and 267. After the implantation process, multiple first masking layers 851 and 853 can be removed.

[0169] For the sake of brevity, clarity, and ease of description, only some common source regions, some first-branch drain regions, and some second-branch drain regions will be described.

[0170] In a top view, the common source region 213 may have a U-shaped profile. The two branches of the U-shaped profile may simultaneously contact the lower side of the first masking layer 851. In a cross-sectional view, the two branches of the U-shaped profile may contact one side of the remaining prefabricated active region 821 below the first masking layer 851.

[0171] In some embodiments, in a top view schematic, the common source region 213 may have a linear profile (or a rod-shaped profile) extending along the X direction. One side of the linear profile may contact the underside of the first masking layer 851.

[0172] In a top view, the common source region 227 may have an inverted U-shaped profile. The two branches of the inverted U-shaped profile may simultaneously contact the upper side of the first masking layer 853. In a cross-sectional view, the two branches of the inverted U-shaped profile may contact one side of the remaining prefabricated active region 843 below the first masking layer 853.

[0173] In some embodiments, in a top view schematic, the common source region 227 may have a linear profile extending along the direction X. One side of the linear profile may contact the upper side of the first masking layer 853.

[0174] In a top view, the first branch drain region 233 and the second branch drain region 253 may each have a linear profile. The first branch drain region 233 and the second branch drain region 253 may extend along the Y direction and may be parallel to each other. The first branch drain region 233 and the second drain region 253 may simultaneously contact the upper side of the first masking layer 851. That is, the first branch drain region 233 and the second drain region 253 may be respectively and correspondingly disposed at the opposite locations of the common source region 213 interposed with the first masking layer 851 (in the top view) or the remaining prefabricated active region 821 (in the cross-sectional view).

[0175] In a top view, the first branch drain region 247 and the second branch drain region 267 may each have a linear profile. The first branch drain region 247 and the second branch drain region 267 may extend along the Y direction and may be parallel to each other. The upper ends of the first branch drain region 247 and the second branch drain region 267 may simultaneously contact the lower side of the first masking layer 853. That is, the first branch drain region 247 and the second branch drain region 267 may be respectively and correspondingly disposed at the opposite position of the common source region 227 in which the first masking layer 853 (in a top view) or the remaining prefabricated active region 843 (in a cross-sectional view) is interposed.

[0176] Other common source regions, other first-branch drain regions, and other second-branch drain regions may have similar or identical structures to those described, and their descriptions will not be repeated in the text.

[0177] Figure 7 and Figure 8 This is a cross-sectional schematic diagram illustrating a portion of the process for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 4 The cross-sections along sections A-A' and B-B', and sections C-C' and D-D'.

[0178] Please refer to Figure 7 and Figure 8 A first dielectric layer 271 may be formed on the substrate 101. For example, the first dielectric layer 271 may comprise oxides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, dielectric materials with high dielectric constants, or combinations thereof. For example, the fabrication technique of the first dielectric layer 271 may include suitable deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, solvent deposition, or other suitable deposition processes. The thickness of the first dielectric layer 271 may vary depending on the deposition process and the composition and amount of the materials used. For example, the thickness of the first dielectric layer 271 may be between approximately... To about In some embodiments, the first dielectric layer 271 may comprise multiple layers. For example, the first dielectric layer 271 may be an oxide-nitride-oxide (ONO) structure. As another example, the first dielectric layer 271 may comprise a lower layer comprising silicon oxide and an upper layer comprising a dielectric material with a high dielectric constant.

[0179] Examples of dielectric materials with high dielectric constants (having a dielectric constant greater than 7.0) include metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but are not limited thereto. For example, dielectric materials with high dielectric constants may also include multiple dopants, such as lanthanum or aluminum.

[0180] Figure 9 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 10 to 12 This is a cross-sectional schematic diagram illustrating a portion of the process for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 9 The cross-sections along lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0181] Please refer to Figure 1 and Figures 9 to 15In step S13, a plurality of first character line structures 511, 513, 515, 517, a plurality of second character line structures 521, 523, 525, 527, and a plurality of upper electrodes 311, 313, 315, 317, 321, 323, 325, 327 may be formed on the first dielectric layer 271.

[0182] Please refer to Figures 9 to 12 Multiple first character line structures 511, 513, 515, and 517 can be arranged alternately along direction X. That is, along direction X, adjacent first character line structures can be spaced apart by approximately the same distance. In a top view schematic diagram, some portions of the multiple first character line structures 511, 513, 515, and 517 can respectively and correspondingly overlap with the remaining prefabricated active areas 811, 813, 821, 823, 831, 833, 841, and 843.

[0183] Please refer to Figures 9 to 12 Multiple second character line structures 521, 523, 525, and 527 can be arranged alternately along direction X. That is, along direction X, adjacent second character line structures can be spaced apart by approximately the same distance. In a top view schematic diagram, some portions of the multiple second character line structures 521, 523, 525, and 527 can respectively and correspondingly overlap with the remaining prefabricated active areas 811, 813, 821, 823, 831, 833, 841, and 843.

[0184] In a top view diagram, multiple first character line structures 511, 513, 515, 517 and multiple second character line structures 521, 523, 525, 527 can be arranged alternately along the direction X.

[0185] For the sake of brevity, clarity, and ease of description, only some first-character line structures and some second-character line structures will be described.

[0186] In a top view, the first character line structure 513 may include a first upper short axis portion 513US, a first lower short axis portion 513LS, and a first long axis portion 513L. The first upper short axis portion 513US may have a linear profile. The first upper short axis portion 513US may extend along the X direction and be disposed between the first branch drain region 233 and the common source region 213. In a cross-sectional view, the first upper short axis portion 513US may be formed on the remaining prefabricated active region 821.

[0187] In a top view, the first lower short axis portion 513LS may have a linear profile. The first lower short axis portion 513LS may be parallel to the first upper short axis portion 513US. The first lower short axis portion 513LS may be disposed between the common source region 223 and the first branch drain region 243. In a cross-sectional view, the first lower short axis portion 513LS may be disposed on the remaining prefabricated active region 823 (not shown).

[0188] In a top-view schematic diagram, the first long axis portion 513L extends along the Y direction and connects to the left ends of the first upper short axis portion 513US and the first lower short axis portion 513LS, respectively. In a cross-sectional schematic diagram, the first long axis portion 513L may not be structurally positioned on the common source region 213, the first branch drain region 233, the common source region 223, and the first branch drain region 243. That is, in a top-view schematic diagram, the first long axis portion 513L may not overlap with the common source region 213, the first branch drain region 233, the common source region 223, and the first branch drain region 243.

[0189] In a top view, the second character line structure 523 may include a second upper short axis portion 523US, a second lower short axis portion 523LS, and a second long axis portion 523L. The second upper short axis portion 523US may have a linear profile. The second upper short axis portion 523US may extend along the direction X. The second upper short axis portion 523US may be disposed between the second branch drain region 253 and the common source region 213. The second upper short axis portion 523US and the first upper short axis portion 513US may be disposed opposite each other along the direction X. In a cross-sectional view, the second upper short axis portion 523US may be disposed on the remaining prefabricated active region 821.

[0190] In a top view, the second lower short axis portion 523LS may have a linear profile. The second lower short axis portion 523LS may be parallel to the second upper short axis portion 523US. The second lower short axis portion 523LS may be disposed between the common source region 223 and the second branch drain region 263. The second lower short axis portion 523LS and the first lower short axis portion 513LS may be disposed opposite each other along the X direction. In a cross-sectional view, the second lower short axis portion 523LS may be disposed on the remaining prefabricated active region 823.

[0191] In a top view, the second long axis portion 523L extends along the Y direction and connects to the right ends of the second upper short axis portion 523US and the second lower short axis portion 523LS, respectively. In a cross-sectional view, the second long axis portion 523L may not be structurally positioned on the common source region 213, the second branch drain region 253, the common source region 223, and the second branch drain region 263. That is, in the top view, the second long axis portion 523L may not overlap with the common source region 213, the second branch drain region 253, the common source region 223, and the second branch drain region 263.

[0192] In a top-view schematic, the first character line structure 515 may be disposed adjacent to the second character line structure 523, and may include a first upper short axis portion 515US, a first lower short axis portion 515LS, and a first long axis portion 515L. The first upper short axis portion 515US may extend along direction X, be disposed opposite to the second upper short axis portion 523US sandwiched therebetween, and be disposed between the first branch drain region 235 and the common source region 215. The first lower short axis portion 515LS may be parallel to the first upper short axis portion 515US, be disposed opposite to the second long axis portion 523L sandwiched therebetween, and be disposed between the common source region 225 and the first branch drain region 245. The first long axis portion 515L may extend along a second direction and connect to the left ends of the first upper short axis portion 515US and the first lower short axis portion 515LS, respectively. The first long shaft portion 515L is located opposite the second long shaft portion 523L.

[0193] In a top-view schematic, the second character line structure 525 may be disposed adjacent to the first character line structure 515, and may include a second upper short axis portion 525US, a second lower short axis portion 525LS, and a second long axis portion 525L. The second upper short axis portion 525US may extend along direction X, be disposed opposite to the first upper short axis portion 515US, and be disposed between the first branch drain region 255 and the common source region 215. The second lower short axis portion 525LS may be parallel to the second upper short axis portion 525US, be disposed opposite to the first lower short axis portion 515LS, and be disposed between the common source region 225 and the first branch drain region 265. The second long axis portion 525L may extend along a second direction and connect to the right ends of the second upper short axis portion 525US and the second lower short axis portion 525LS.

[0194] Please refer to Figures 9 to 12 Multiple upper electrodes 311, 313, 315, and 317 can be arranged alternately along direction X. Multiple upper electrodes 321, 323, 325, and 327 can be arranged alternately along direction X, and are respectively parallel to the multiple upper electrodes 311, 313, 315, and 317.

[0195] For the sake of brevity, clarity, and ease of description, only some of the upper electrodes will be described.

[0196] In a top view, the upper electrode 313 may be formed between the first long axis portion 513L and the second long axis portion 523L. In a cross-sectional view, the upper electrode 313 may be structurally disposed between the first branch drain region 233 and the second branch drain region 253. In a top view, the upper electrode 313 may overlap with the first branch drain region 233 and the second branch drain region 253. The upper electrode 313, the first branch drain region 233, the second branch drain region 253, and the first dielectric layer 271 sandwiched between the upper electrode 313 and the first branch drain region 233 and between the upper electrode 313 and the second branch drain region 253 may be configured together to form a programmable unit PU2 (also referred to as a first programmable unit), such as an antifuse. The first branch drain region 233 or the second branch drain region 253 may individually or simultaneously serve as the lower electrode of the first programmable unit PU2.

[0197] In a top view, the upper electrode 323 may be formed between the first long axis portion 513L and the second long axis portion 523L. In a cross-sectional view (not shown), the upper electrode 323 may be structurally disposed on the first branch drain region 243 and the second branch drain region 263. In a top view, the upper electrode 323 may overlap with the first branch drain region 243 and the second branch drain region 263. The upper electrode 323, the first branch drain region 243, the second branch drain region 263, and the first dielectric layer 271 sandwiched between the upper electrode 323 and the first branch drain region 243 and between the upper electrode 323 and the second branch drain region 263 may be configured together to form another programmable unit PU6, which is located away from the first programmable unit PU2 along the Y direction.

[0198] In a top view, the upper electrode 315 may be formed between the first long axis portion 515L and the second long axis portion 252L. In a cross-sectional view, the upper electrode 315 may be structurally disposed on the first branch drain region 235 and the second branch drain region 255. In a top view, the upper electrode 315 may overlap with the first branch drain region 235 and the second branch drain region 255. The upper electrode 315, the first branch drain region 235, the second branch drain region 255, and the first dielectric layer 271 sandwiched between the upper electrode 315 and the first branch drain region 235 and between the upper electrode 315 and the second branch drain region 255 may be configured together to form another programmable unit PU3, which is located away from the first programmable unit PU2 along the X direction.

[0199] Other first character line structures, other second character line structures, and other upper electrodes may have similar or identical characteristics to those described herein, and their descriptions will not be repeated here. Other programmable units PU1, PU4, PU5, PU7, and PU8 have the same architecture as programmable units PU2, PU3, and PU6, and their descriptions will not be repeated here.

[0200] In some embodiments, for example, a plurality of first character line structures 511, 513, 515, 517, a plurality of second character line structures 521, 523, 525, 527, and a plurality of upper electrodes 311, 313, 315, 317, 321, 323, 325, 327 may comprise polysilicon, doped polysilicon, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0201] In some embodiments, the upper electrodes, the first character line structures, and the second character line structures may be formed simultaneously. In some embodiments, the upper electrodes, the first character line structures, and the second character line structures may be formed separately.

[0202] Figures 13 to 15 This is a cross-sectional schematic diagram illustrating a portion of the process for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 9 The cross-sections along lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0203] Please refer to Figures 13 to 15 A plurality of first spacers 109 may be formed on the sidewalls of the plurality of first character line structures 511, 513, 515, 517 and on the sidewalls of the plurality of second character line structures 521, 523, 525, 527. For example, the plurality of first spacers 109 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or other applicable insulating materials. The plurality of first spacers 109 may provide additional electrical isolation between adjacent character line structures. In some embodiments, for example, the plurality of first spacers 109 may comprise a material with a low dielectric constant to reduce parasitic capacitance between adjacent character line structures.

[0204] Please refer to Figures 13 to 15A first interlayer dielectric layer 105 may be formed on the substrate 101 to cover the character line structures. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a generally flat surface for subsequent processing steps. For example, the first interlayer dielectric layer 105 may comprise silicon nitride, silicon oxide, silicon oxynitride, flowing oxide, tonnen silazen, undoped silicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, plasma-enhanced tetraethyl orthosilicate, fluorosilicate glass, carbon-doped silicon oxide, or combinations thereof. For example, the fabrication techniques for the first interlayer dielectric layer 105 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, similar methods, or other applicable deposition processes.

[0205] Figure 16 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 17 and Figure 18 This is a cross-sectional schematic diagram illustrating a portion of the process for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 16 The cross-sections of sections E-E', F-F', G-G', and H-H'.

[0206] Please refer to Figure 1 and Figures 16 to 18 In step S15, multiple upper contact points 351, 353, 355, 357, 361, 363, 365, and 367 can be formed on multiple upper electrodes 311, 313, 315, 317, 321, 323, 325, and 327, and multiple source contact points 371, 373, 375, 377, 381, 383, 385, and 387 can be formed on multiple common source regions 211, 213, 215, 217, 221, 223, 225, and 227.

[0207] For the sake of brevity, clarity, and ease of description, only one upper contact point and one source contact point will be described.

[0208] Please refer to Figures 16 to 18The upper contact point 355 may be formed along the first interlayer dielectric layer 105 and on the upper electrode 315. In some embodiments, the upper contact point 355 may be structurally disposed on the first branch drain region 235 or the second branch drain region 255. In some embodiments, the upper contact point 355 may not be structurally disposed on the first branch drain region 235 and the second branch drain region 255. In some embodiments, the width W1 of the upper contact point 355 may be less than or equal to the horizontal distance H1 between the first branch drain region 235 and the second branch drain region 255. In some embodiments, the width W1 of the upper contact point 355 may be greater than the horizontal distance H1 between the first branch drain region 235 and the second branch drain region 255. In some embodiments, the length L1 of the upper contact point 355 may be greater than or equal to the width W2 of the upper electrode 315.

[0209] Please refer to Figures 16 to 18 The source contact 371 may be formed along the first interlayer dielectric layer 105 and the first dielectric layer 271, and is formed on the common source region 211. In some embodiments, the width W3 of the source contact 317 may be greater than or equal to the width W1 of the upper contact 351. In some embodiments, the width W3 of the source contact 371 may be greater than or equal to the horizontal distance H1 between the first branch drain region 231 and the second branch drain region 251. In some embodiments, the width W3 of the source contact 371 may be less than or equal to the width W4 of the upper electrode 311.

[0210] In some embodiments, for example, the upper contact 355 and the source contact 371 may comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the upper contact 355 and the source contact 371 may be formed simultaneously. In some embodiments, the upper contact 355 and the source contact 371 may be formed separately.

[0211] Figure 19 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 20 to 22 This is a cross-sectional schematic diagram illustrating a portion of the process for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 19 The cross sections of section E', C-C', D-D', E-E', F-F', and sections G-G' and H-H'.

[0212] Please refer to Figure 1 and Figures 19 to 22In step S17, multiple upper conductive layers 411 and 413 can be formed on multiple upper contact points 351, 353, 355, 357, 361, 363, 365, and 367, and multiple bit lines 421 and 423 are formed on multiple source contact points 371, 373, 375, 377, 381, 383, 385, and 387.

[0213] Please refer to Figures 19 to 22 A second interlayer dielectric layer 107 may be formed on the first interlayer dielectric layer 105. For example, the second interlayer dielectric layer 107 may comprise silicon nitride, silicon oxide, silicon oxynitride, flowing oxide, silazane, undoped silicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, plasma-enhanced tetraethoxysilane, fluorosilicate glass, carbon-doped silicon oxide, or combinations thereof. For example, the fabrication technique of the second interlayer dielectric layer 107 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, similar methods, or other applicable deposition processes. A plurality of common upper conductive layers 411, 413 and a plurality of bit lines 421, 423 may be formed on the second interlayer dielectric layer 107. For example, the multiple common conductive layers 411, 413 and the multiple bit lines 421, 423 may comprise polysilicon, doped polysilicon, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0214] Please refer to Figures 19 to 22 The upper conductive layer 411 can extend along the X direction and be formed simultaneously on multiple upper contact points 351, 353, 355, and 357. The upper conductive layer 413 can be parallel to the upper conductive layer 411 and be formed simultaneously on multiple upper contact points 361, 363, 365, and 367. The bit line 421 can extend along the X direction and be formed simultaneously on multiple source contact points 371, 373, 375, and 377. The bit line 423 can be parallel to the bit line 421 and be formed simultaneously on multiple source contact points 381, 383, 385, and 387.

[0215] The upper conductive layer 411 may be electrically coupled to an external voltage source to simultaneously provide a programmed voltage to the upper part of the programmed units. The upper conductive layer 413 may be electrically coupled to another external voltage source to simultaneously provide a programmed voltage to the lower part of the programmed units. In some embodiments, the same external voltage source may be electrically coupled to multiple upper conductive layers 411, 413 to simultaneously provide a programmed voltage to the upper part and the lower part of the programmed units. The programmed voltage may be between approximately +5.0 volts and +8.0 volts.

[0216] Multiple bit lines 421 and 423 can be set between ground potential and -2.0 volts, respectively. Multiple first word line structures 511, 513, 515, and 517 and multiple second word line structures 521, 523, 525, and 527 can be coupled to different voltage sources to electrically control the access and value of programmed current and correspond to the programmed units PU1, PU2, PU3, PU4, PU5, PU6, PU7, and PU8, respectively.

[0217] For example, when the upper conductive layer 411 is set to +6.0 volts, the bit line 421 is grounded, and both the first word line structure 513 and the second word line structure 523 are set to +0.0 volts, no current path is generated below the first upper short axis portion 513US or the second upper short axis portion 523US. Therefore, no programmed current is generated, and no programmed current can access the first programmable unit. That is, the first dielectric layer 271 of the first programmable unit PU2 remains intact. Therefore, the resistance state of the first programmable unit PU2 in this case is high.

[0218] For another example, when the upper conductive layer 411 is set to +6.0 volts, the bit line 421 is grounded, and only one of the first word line structures 513 or the second word line structure 523 is set to +0.0 volts and the other is set to +1.5 volts, a current path is formed only below the word line structure that is not set to +0.0 volts. That is, the programmed current can be accessed only to the first programmable unit via one of the word line structures 513, 523. Using the first word line structure 513 as an example, when only the first word line structure 513 is set to +1.5 volts and the second word line structure 523 is set to +0.0 volts, the programmed unit (also represented as the first programmed current) can flow through the channel region (or current path) generated below the first upper short axis portion 513US. The first dielectric layer 271, sandwiched between the upper electrode 313 and the first branch drain region 233, can be pressurized below the programmed voltage. Therefore, the clamping portion of the first dielectric layer 271 will break to form a continuous path connecting the upper electrode 313 and the first branch drain region 2330. In other words, the clamping portion of the first dielectric layer 271 can be melted. In this case, the resistance state of the first programmable unit PU2 is medium.

[0219] To give another example, when the upper conductive layer 411 is set to +6.0 volts, the bit line 421 is grounded, and both the first word line structure 513 and the second word line structure 523 are set to +1.5 volts, the programmed current (also referred to as the second programmed current) can flow through the two channel regions generated below the first upper short axis portion 513US and the second upper short axis portion 523US. The first dielectric layer 271, sandwiched between the upper electrode 131 and the first branch drain region 233, and between the upper electrode 313 and the second branch drain region 253, can be pressurized under the programmed voltage. Therefore, the sandwiched portion of the first dielectric layer 271 can be melted. Since the second programmed current is greater than the first programmed current, the resistance state of the first programmable unit PU2 in this case is low.

[0220] In summary, the resistance state of a programmable cell can be adjusted by controlling the voltages applied to the multiple word line structures integrated with the programmable cell. By applying these voltages to more word line structures, the programming current can be increased to obtain a programmable cell with a lower resistance value.

[0221] Furthermore, by utilizing the upper conductive layers 411, 413 and the bit lines 421, 423, and with the upper conductive layers 411, 413 simultaneously coupled to multiple programmable units PU1, PU2, PU3, PU4, PU5, PU6, PU7, PU8, it is possible to individually control the programmable state (fuse-out or not) and resistance state of the programmable units PU1, PU2, PU3, PU4, PU5, PU6, PU7, PU8.

[0222] For example, in order to fuse programmable units PU2 and PU6, the upper conductive layers 411 and 413 can be set to +6.0 volts, the bit lines 421 and 423 can be grounded, the first word line structure 513 and / or the second word line structure 523 can be set to +1.5 volts, and the first word line structures 511, 515, and 517 and the second word line structures 521, 525, and 527 can be set to +0.0 volts.

[0223] For another example, to melt only the programmable unit PU2, the upper conductive layers 411 and 413 can be set to +6.0 volts (also represented as a first voltage), bit line 421 can be grounded, bit line 423 can be set to a voltage between the ground potential and the first voltage (e.g., +2.0 volts), the first word line structure 513 and / or the second word line structure 523 can be set to +1.5 volts, and the first word line structures 511, 515, and 517 and the second word line structures 521, 525, and 527 can be set to +0.0 volts. Because the higher voltage is set on multiple bit lines 421 and 423, the voltage difference between bit line 423 and the upper conductive layer 413 may not be sufficient to melt the first dielectric layer 271. Therefore, the following programmable units PU5, PU6, PU7, and PU8 can be completely undamaged, even if the upper conductive layer 413 is electrically coupled to a high voltage source.

[0224] Figure 23 This is a cross-sectional schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0225] Please refer to Figure 23 Intermediate semiconductor elements may have similar characteristics to, for example: Figure 23 The described structure. In Figure 23 The same as or similar to Figure 20 The components in the diagram are designated as similar reference elements, and their repeated descriptions have been omitted. A plurality of second spacers 111 may be disposed on the sidewalls of the upper conductive layers 411, 413 and on the sidewalls of the plurality of bit lines 421, 423. For example, the plurality of second spacers 111 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or other applicable insulating materials. The plurality of second spacers 111 may provide additional electrical isolation between adjacent upper conductive layers and bit lines. In some embodiments, for example, the plurality of second spacers 111 may comprise a material with a low dielectric constant to reduce parasitic capacitance between adjacent upper conductive layers and bit lines.

[0226] One embodiment of this disclosure provides a semiconductor device including a first dielectric layer disposed on a substrate; a first upper short axis portion and a second upper short axis portion extending along a first direction, spaced apart from each other, and disposed on the first dielectric layer; a first common source region disposed in the substrate and adjacent to the first upper short axis portion and the second upper short axis portion; a first branch drain region disposed in the substrate, adjacent to the first upper short axis portion, and disposed opposite to the first common source region; a second branch drain region disposed in the substrate, adjacent to the second upper short axis portion, and disposed opposite to the first common source region; and an upper electrode disposed on the first dielectric layer and topologically disposed on the first branch drain region and the second branch drain region. The upper electrode, the first dielectric layer, the first branch drain region, and the second branch drain region are configured together to form a first programmable unit.

[0227] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including forming a common source region, a first branch drain region, and a second branch drain region in a substrate; wherein the first branch drain region and the second branch drain region are parallel to each other and are both separated from the common source region; forming a first dielectric layer on the substrate; forming a first upper short axis portion and a second upper short axis portion on the first dielectric layer; wherein the first upper short axis portion and the second upper short axis portion extend along a first direction and are separated from each other; wherein the first upper short axis portion is disposed between the common source region and the first branch drain region, and the second upper short axis portion is disposed between the common source region and the second branch drain region; and forming an upper electrode on the first dielectric layer, and topologically disposed on the first branch drain region and the second branch drain region. The first branch drain region, the second branch drain region, the first dielectric layer, and the upper electrode are configured together to form a programmable unit.

[0228] Due to the design of the semiconductor device disclosed herein, the resistance of the programmable unit can be adjusted by controlling the number of activated (e.g., voltage-applied) word line structures. Furthermore, by using the conductive layers 411, 413 and the bit lines 421, 423, which are simultaneously coupled to multiple programmable units, it is possible to individually control the programming state (fuse-out or not) and resistance state of each programmable unit.

[0229] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0230] It should be understood that in the description of this disclosure, an xyz coordinate system is assumed, where x and y represent the dimensions in the plane parallel to the main surface of the structure, and z represents a dimension perpendicular to the plane. When two features have approximately the same x and y coordinates, those features are aligned on the terrain structure.

[0231] It should be understood that the term "about" modifies an ingredient, a quantity of a component, or a reactant of this disclosure, indicating a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of the components or the implementation of such methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0232] It should be understood that, for clarity, some elements (such as the substrate and the first dielectric layer) may be omitted in the top view diagram in the description of this disclosure.

[0233] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0234] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A first dielectric layer is disposed on a substrate; A first character line structure is disposed on the first dielectric layer, the first character line structure including a first upper short axis portion; A second character line structure is disposed on the first dielectric layer, the second character line structure including a second upper short axis portion; The first upper short axis portion and the second upper short axis portion extend along a first direction, are spaced apart from each other, and are disposed on the first dielectric layer; A first common source region is disposed in the substrate and adjacent to the first upper short axis portion and the second upper short axis portion; A first branch drain region is disposed in the substrate, adjacent to the first upper short axis portion, and opposite to the first common source region; A second branch drain region is disposed in the substrate, adjacent to the second upper short axis portion, and opposite to the first common source region; as well as An upper electrode is disposed on the first dielectric layer and on the first branch drain region and the second branch drain region in terms of topographic structure; The upper electrode, the first dielectric layer, the first branch drain region, and the second branch drain region are configured together to form a first programmable unit; The first branch drain region and the second branch drain region are arranged parallel to each other along a second direction, and the first direction and the second direction are perpendicular to each other.

2. The semiconductor device as claimed in claim 1, wherein, The first character line structure further includes a first long axis portion, and the second character line structure further includes a second long axis portion; wherein the first long axis portion is disposed on the first dielectric layer, extends along the second direction, and is connected to one end of the first upper short axis portion, and one end of the first upper short axis portion is disposed at the opposite position of the second upper short axis portion; wherein the second long axis portion is disposed on the first dielectric layer, extends along the second direction, and is connected to one end of the second upper short axis portion, and one end of the second upper short axis portion is disposed at the opposite position of the first upper short axis portion.

3. The semiconductor device as claimed in claim 2, wherein, The first character line structure further includes a first lower short axis portion, and the second character line structure further includes a second lower short axis portion; the semiconductor device further includes a second common source region and a second programmable unit; wherein the first lower short axis portion is disposed on the first dielectric layer, parallel to the first upper short axis portion, and connected to the first long axis portion; wherein the second lower short axis portion is disposed on the first dielectric layer, parallel to the second upper short axis portion, connected to the second long axis portion, and located opposite to the first lower short axis portion; wherein the second common source region is disposed in the substrate, separated from the first common source region, and adjacent to the first lower short axis portion and the second lower short axis portion; wherein the second programmable unit is separated from the first programmable unit along the second direction and includes: A first branch drain region is disposed in the substrate, adjacent to the first lower short axis portion, and opposite to the second common source region; A second branch drain region is disposed in the substrate, adjacent to the second lower short axis portion, and opposite to the second common source region; and An upper electrode is disposed on the first dielectric layer and on the first branch drain region and the second branch drain region in the topographic structure.

4. The semiconductor device of claim 1 further includes an upper contact point disposed on the upper electrode of the first programmable unit.

5. The semiconductor device of claim 4, wherein the width of the upper contact point is less than a horizontal distance between the first branch drain region and the second branch drain region of the first programmable unit.

6. The semiconductor element of claim 4, wherein a length of the upper contact point is greater than or equal to a width of the upper electrode of the first programmable unit.

7. The semiconductor element of claim 4 further includes an upper conductive layer disposed on the upper contact point and extending along the first direction.

8. The semiconductor device of claim 7 further includes a plurality of second spacers disposed on each sidewall of the upper conductive layer; wherein the plurality of second spacers include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

9. The semiconductor device of claim 1 further includes a source contact point disposed on the first common source region.

10. The semiconductor element of claim 9, further comprising a bit line disposed at the source contact point and extending along the first direction.

11. The semiconductor element of claim 9, wherein the width of the upper electrode is greater than or equal to the width of the source contact.

12. The semiconductor device of claim 2, further comprising a third word line structure and a fourth word line structure; the third word line structure comprising a third upper short axis portion; the fourth word line structure comprising a fourth upper short axis portion; the semiconductor device further comprising a second common source region and a second programmable unit; wherein the third upper short axis portion is disposed on the first dielectric layer, disposed opposite to the second upper short axis portion and the second long axis portion sandwiched therebetween, and extends along the first direction; wherein the fourth upper short axis portion is disposed on the first dielectric layer, spaced apart from the third upper short axis portion, disposed opposite to the second long axis portion, and extends along the first direction; wherein the second common source region is disposed in the substrate and adjacent to the third upper short axis portion and the fourth upper short axis portion; wherein the second programmable unit is disposed along the first direction, separated from the first programmable unit, and comprises: A first branch drain region is disposed in the substrate, adjacent to the third upper short axis portion, and opposite to the second common source region; A second branch drain region is disposed in the substrate, adjacent to the fourth upper short axis portion, and opposite to the second common source region; as well as An upper electrode is disposed on the first dielectric layer and on the first branch drain region and the second branch drain region in the topographic structure.

13. The semiconductor device of claim 12, further comprising a first upper contact, a second upper contact, and an upper conductive layer; wherein the first upper contact is disposed on the upper electrode of the first programmable unit; wherein the second upper contact is disposed on the upper electrode of the second programmable unit; wherein the upper conductive layer extends along the first direction and is disposed on the first upper contact and the second upper contact.

14. The semiconductor device of claim 13, further comprising a first source contact, a second source contact, and a bit line; wherein the first source contact is disposed on the first common source region; wherein the second source contact is disposed on the second common source region; wherein the bit line extends along the first direction and is disposed on the first source contact and the second source contact.

15. The semiconductor element of claim 14, wherein a width of the first source contact is greater than a width of the first upper contact.

16. The semiconductor device of claim 14, wherein a width of the first source contact is greater than or equal to a distance between the first branch drain region and the second branch drain region of the first programmable unit.

17. A method for fabricating a semiconductor device, comprising: A common source region, a first branch drain region, and a second branch drain region are formed in a substrate; The first branch drain region and the second branch drain region are parallel to each other and are both separated from the common source region; A first dielectric layer is formed on the substrate; A first character line structure is formed on the first dielectric layer, the first character line structure including a first upper short axis portion; A second character line structure is formed on the first dielectric layer, the second character line structure including a second upper short axis portion; The first upper short axis portion and the second upper short axis portion are formed on the first dielectric layer; The first upper short axis portion and the second upper short axis portion extend along a first direction and are separated from each other; The first upper short axis portion is disposed between the common source region and the first branch drain region, and the second upper short axis portion is disposed between the common source region and the second branch drain region; and An upper electrode is formed on the first dielectric layer and disposed on the first branch drain region and the second branch drain region in the topographic structure; The first branch drain region, the second branch drain region, the first dielectric layer, and the upper electrode are configured together as a programmable unit. The first branch drain region and the second branch drain region are arranged parallel to each other along a second direction, and the first direction and the second direction are perpendicular to each other.

18. The method for fabricating a semiconductor device as described in claim 17, further comprising: A contact point is formed on the upper electrode; A source contact point is formed along the first direction on the common source region; An upper conductive layer is formed at the upper contact point and extends along the first direction; as well as A bit line is formed at the source contact point and extends along the first direction.

19. The method for fabricating a semiconductor element as claimed in claim 18, wherein the upper electrode and the first upper short axis portion are formed simultaneously.

20. The method for fabricating a semiconductor element as claimed in claim 19, wherein the upper contact point and the source contact point are formed simultaneously.

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