Multistage broadband amplifier with intra- and inter-stage inductive coupling

Abstract

A multi-stage amplifier includes a first stage and a second stage. The first stage includes a first common-source amplifier, a first inductive load network including a first load resistor and a first load inductor connected in series, and a first inter-stage inductor. The first inductive load network includes a first source network for receiving a first signal and outputting a first load signal. The first inter-stage inductor is configured to couple the first load signal to a second signal. The second stage includes a second common-source amplifier, a second inductive load network including a second load resistor and a second load inductor connected in series, and a second inter-stage inductor. The second inductive load network includes a second source network for receiving the second signal and outputting a second load signal. The second inter-stage inductor is configured to couple the second load signal to a third signal. The first load inductor and the second load inductor are arranged to enhance inter-stage inductive coupling.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to multi-stage broadband amplifiers, and more particularly to multi-stage broadband amplifiers with intra-stage and inter-stage inductive coupling. BACKGROUND

[0002] A multi-stage amplifier includes a plurality of stages, including a first stage, a second stage, and so on, configured in a cascade configuration to achieve a high overall gain, where the first stage receives a first signal and outputs a second signal, the second stage receives the second signal and outputs a third signal, and so on. The more stages used, the higher the overall gain that can be achieved, but also the overall bandwidth is reduced, because the bandwidth of each of the plurality of stages is limited, as is the case with any practical circuit. In other words, adding an extra stage can result in an increase in the overall gain, but also causes a reduction in the overall bandwidth, due to the limited bandwidth of the extra stage.

[0003] What is needed in the art is a multi-stage amplifier that allows for an increase in the overall gain when an extra stage is used, without sacrificing the overall bandwidth. SUMMARY

[0004] According to an embodiment of the present disclosure, a multi-stage amplifier includes a first stage including a first cascode amplifier, a first inductive load network, and a first inter-stage inductor, where the first inductive load network includes a first load resistance and a first load inductor connected in series, and includes a first source network to receive a first signal and output a first load signal, the first inter-stage inductor to couple the first load signal to a second signal; and a second stage including a second cascode amplifier, a second inductive load network, and a second inter-stage inductor, where the second inductive load network includes a second load resistance and a second load inductor connected in series, and includes a second source network to receive the second signal and output a second load signal, the second inter-stage inductor to couple the second load signal to a third signal, where: a portion of the first load inductor is topologically adjacent and parallel to a portion of the first inter-stage inductor, a portion of the second load inductor is topologically adjacent and parallel to a portion of the second inter-stage inductor, and a portion of the first load inductor is topologically adjacent and parallel to a portion of the second load inductor.

[0005] According to an embodiment of the present disclosure, a multi-stage amplifier includes a first stage including a first common-source amplifier, a first inductive load network, and a first inter-stage inductor, wherein the first inductive load network includes a first load resistance and a first load inductor connected in series, and includes a first source network for receiving a first signal and outputting a first load signal, and the first inter-stage inductor is used to couple the first load signal to a second signal; and a second stage including a second common-source amplifier, a second inductive load network, and a second inter-stage inductor, wherein the second inductive load network includes a second load resistance and a second load inductor connected in series, and includes a second source network for receiving the second signal and outputting a second load signal, and the second inter-stage inductor is used to couple the second load signal to a third signal, wherein: the first load inductor and the first inter-stage inductor are arranged to enhance a first intra-stage inductive coupling, the second load inductor and the second inter-stage inductor are arranged to enhance a second intra-stage inductive coupling, and the first load inductor and the second load inductor are arranged to enhance an inter-stage inductive coupling.

[0006] As to the features, implementations and technical effects of the present disclosure, preferred embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 According to an embodiment of the present disclosure, a schematic diagram of a multi-stage amplifier is shown;

[0008] Figure 2 According to an embodiment of the present disclosure, a schematic diagram of a source network for a multi-stage amplifier of Figure 1 is shown; and

[0009] Figure 3 According to an embodiment of the present disclosure, a top view of an arrangement of a multi-stage amplifier of Figure 1 is shown.

[0010] LIST OF SYMBOLS

[0011] 100: multi-stage amplifier

[0012] ST1: first stage

[0013] ST2: second stage

[0014] V DD : power supply node

[0015] V 1+ , V1: two voltages of a first signal V1

[0016] V 2+ , V 2- : two voltages of a second signal V2

[0017] V 3+ , V3-: two voltages of the third signal V3

[0018] CS1: first common-source amplifier

[0019] SN1: first source network

[0020] ILN1: first inductive load network

[0021] CS2: second common-source amplifier

[0022] SN2: second source network

[0023] ILN2: second inductive load network

[0024] V L1+ , V L1- : two voltages of the first load signal V L1

[0025] V L2+ , V L2- : two voltages of the second load signal V L2

[0026] M1p, M2p, M1n, M2n: NMOS transistors

[0027] T1p, T1n: first inter-stage inductor pair

[0028] T2p, T2n: second inter-stage inductor pair

[0029] R1p, R1n: first load resistor pair

[0030] R2p, R2n: second load resistor pair

[0031] L1p, L1n: first load inductor pair

[0032] L2p, L2n: first load inductor pair

[0033] k 1p , k 1n , k 2p , k 2n : intra-stage coupling coefficient

[0034] k 12p , k 12n : inter-stage coupling coefficient

[0035] 200: source network

[0036] 210: current source

[0037] 211, 212: NMOS transistors ​​

[0038] 220: source degeneration circuit

[0039] 221: resistor

[0040] 222: capacitor

[0041] V B : bias voltage

[0042] 301: pattern specification block

[0043] 302: symmetry plane

[0044] 313, 314, 323, 324: via

[0045] TM1: first thick metal layer

[0046] TM2: second thick metal layer

[0047] TM1-TM2 via: TM1-TM2 via layer DETAILED DESCRIPTION

[0048] The present disclosure is directed toward multi-stage amplifiers. While the present specification discloses embodiments of the present disclosure that can be viewed as preferred examples of practicing the present invention, it must be noted that the present invention can be practiced in a wide variety of ways, not limited to the specific examples described below, nor to the specific ways of implementing the technical features of the specific examples. In other cases, known details have not been shown or described to avoid obscuring the point of the present disclosure.

[0049] The microelectronics-related terminology and basic concepts used in the present disclosure, such as "voltage," "signal," "differential signal," "gain," "bias," "current source," "impedance," "inductance," "capacitance," "resistance," "inductive coupling," "common-source amplifier," "transconductance," "load," "source degeneration," "parallel connection," "polysilicon," "via," "circuit node," "ground," "power supply," "MOS (metal-oxide-semiconductor)," "CMOS (complementary metal-oxide-semiconductor) technology," "NMOS (n-channel metal-oxide-semiconductor) transistor," and "PMOS (p-channel metal-oxide-semiconductor) transistor," will be understood by those skilled in the art of the present technology. When such terminology and basic concepts are used in articles about microelectronics, they are well known to those skilled in the art, and their details are not described here.

[0050] Units mentioned in this specification, such as nH (nano-Henry), pH (pico-Henry), fF (femto-Farad), nm (nanometer), and pm (micrometer), are well known to those skilled in the art.

[0051] Circuit diagrams are well known to those skilled in the art to contain electronic elements such as inductors, capacitors, resistors, NMOS transistors, PMOS transistors, etc., and it is not necessary to redundantly specify how a certain element in the diagram is connected to another element. Those skilled in the art also recognize a ground symbol, a capacitor symbol, an inductor symbol, a resistor symbol, and symbols for PMOS and NMOS transistors, and are able to recognize the "source terminal", "gate terminal", and "drain terminal" of the above transistors. For brevity, in the following description, the "source terminal" is simply referred to as the "source", the "gate terminal" is simply referred to as the "gate", and the "drain terminal" is simply referred to as the "drain" for MOS transistors.

[0052] A MOS transistor, PMOS transistor, or NMOS transistor has a threshold voltage. When the gate-to-source voltage of a MOS transistor is greater than its threshold voltage (in absolute value), the MOS transistor is turned on. When a MOS transistor is turned on, the absolute value of the difference between the gate-to-source voltage and the threshold voltage is referred to as the "over-drive voltage". When a MOS transistor is turned on and its over-drive voltage is less than its drain-to-source voltage (in absolute value), the MOS transistor is in the "saturation region". A MOS transistor is only an effective gain element when it is in the "saturation region".

[0053] A circuit is a collection of transistors, capacitors, resistors, and / or other electronic elements interconnected in a certain way to perform a certain function.

[0054] In this disclosure, a "circuit node" is often simply referred to as a "node" when the meaning of the "circuit node" is clear from the context.

[0055] A signal is a voltage of variable level that carries certain information and can vary with time. At a certain instant, the level of the signal represents the state of the signal at that instant. In this disclosure, "signal" and "voltage signal" mean the same thing, and the two terms are interchangeable.

[0056] In this disclosure, a differential signal architecture is widely used. When a differential signal architecture is implemented, a signal contains two voltages, denoted by the subscripts "+" and "-", and the value of the signal represents the difference between the two voltages. For example, a signal V1(V2) in a differential signal implementation contains two voltages V 1+ (V 2+ ) and V 1- (V 2- ), and the value of the signal V1(V2) depends on the difference between the two voltages V 1+ (V 2+ ) and V 1- (V 2- ). The voltage V 1+ (V 2+ ) is called a first end signal of the signal V1(V2), and the voltage V 1- (V 2- ) is called a second end signal of the signal V1(V2). The first end signal is also called a positive end signal, and the second end signal is also called a negative end signal. In a differential signal implementation, the average of the first end signal and the second end signal of a signal is called a "common mode" voltage of the signal.

[0057] A common source amplifier contains a MOS transistor (either an NMOS transistor or a PMOS transistor) that receives an input voltage at the gate of the MOS transistor and outputs an output voltage to a load network at the drain of the MOS transistor, where the load network is connected to the drain of the MOS transistor, under a bias condition determined by a source network connected to the source of the MOS transistor. The gain of the common source amplifier is defined as the ratio between the amplitude of the output voltage and the amplitude of the input voltage; the gain is determined by the source network, the load network, the size of the MOS transistor, and the bias condition. Mathematically, we can write the following equation:

[0058]

[0059] In the above equation, G represents the gain of the common source amplifier, g m represents the transconductance of the common source amplifier, Z source represents the impedance of the source network, and Z loadrepresents the impedance of the load network. A larger impedance of the load network can result in a higher gain, while a larger impedance of the source network can result in a lower gain. Similarly, a smaller impedance of the load network can result in a lower gain, while a smaller impedance of the source network can result in a higher gain.

[0060] Figure 1 An embodiment according to the present disclosure shows a schematic diagram of a multi-stage amplifier 100. The multi-stage amplifier 100 comprises a plurality of stages, including a first stage ST1, a second stage ST2, etc., configured in a cascade configuration. For brevity, Figure 2 only two stages are shown (i.e., the first stage ST1 and the second stage ST2), it is apparent to those skilled in the art how to follow the principles described below and extend to more than two stages. Throughout the disclosure, "V DD represents a power supply node. For brevity, the first (second) stage ST1 (ST2) is hereinafter referred to as ST1 (ST2). ST1 receives a first signal V1 (in a differential signal embodiment, the first signal V1 comprises two voltages V 1+ and V1) and outputs a second signal V2 (in a differential signal embodiment, the second signal V2 comprises two voltages V 2+ and V2), while ST2 receives the second signal V2 and outputs a third signal V3 (in a differential signal embodiment, the third signal V3 comprises two voltages V 3+ and V3). ST1 comprises a first cascode amplifier CS1, a first source network SN1, and a first inductive load network ILN1; while ST2 comprises a second cascode amplifier CS2, a second source network SN2, and a second inductive load network ILN2. For brevity, hereinafter: the first (second) cascode amplifier CS1 (CS2) is referred to as CS1 (CS2); the first (second) source network SN1 (SN2) is referred to as SN1 (SN2); the first (second) inductive load network ILN1 (ILN2) is referred to as ILN1 (ILN2); and the first (second, third) signal V1 (V2, V3) is referred to as V1 (V2, V3). CS1 receives V1 and outputs a first load signal V L1 (in a differential signal embodiment, the first load signal V L1 comprises two voltages V L1+ and V L1- across ILN1, while CS2 receives V2 and outputs a second load signal V L2 (in a differential signal embodiment, the second load signal V L2 comprises two voltages V L2+ and V L2-) across ILN2. For simplicity, the first (second) load signal V L1 (V L2 ) is simply referred to as V L1 (V L2 ). CS1 (CS2) comprises two NMOS transistors Mlp (M2p) and Mln (M2n) for receiving V 1+ (V 2+ ) and V 1- (V 2- ), respectively, and outputting V L1+ (V L2+ ) and V L1- (V L2- ), respectively. ST1 further comprises a first inter-stage inductor pair Tlp and Tln for connecting V L1+ and V L1- to V 2+ and V 2- , respectively. ST2 further comprises a second inter-stage inductor pair T2p and T2n for connecting V L2+ and V L2- to V 3+ and V 3- , respectively. ILN1 (ILN2) comprises a first (second) load resistor pair Rlp (R2p) and Rln (R2n) and a first (second) load inductor pair LIp (L2p) and LI n (L2n). It is well understood by those skilled in the art that the impedance of ILN1 (ILN2) and the gain of CS1 (CS2) increase as the frequency of V L1 (V L2 ) increases.

[0061] In one embodiment, multi-stage amplifier 100 is an integrated circuit fabricated on a silicon substrate. Figure 1 The eight inductors: LIp, LI n, Tlp, Tln, L2p, L2n, T2p and T2n are shown. LIp (LI n) and Tlp (Tln) are placed close to each other and hence have a strong intra-stage inductive coupling represented by an intra-stage coupling coefficient k 1p (k 1n ). L2p (L2n) and T2p (T2n) are placed close to each other and hence have a strong intra-stage inductive coupling represented by an intra-stage coupling coefficient k 2p (k 2n ). ST1 and ST2 are placed close to each other and hence LIp (LI n) and L2p (L2n) can have a strong inter-stage inductive coupling represented by an inter-stage coupling coefficient k 12p (k 12n ).

[0062] Figure 2 A schematic diagram of a source network 200 is shown, which can be used as an example for implementing SN1 (SN2). The source network 200 includes a current source 210 including two NMOS transistors 211 and 212 for sourcing current to the source of Mlp (M2p) and the source of Mln (M2n) according to a bias voltage V B respectively, and a source degeneration circuit 220 including a resistor 221 and a capacitor 222 connected in parallel. The current source 210 is used to bias the NMOS transistors Mlp (M2p) and Mln (M2n) in a saturation region, so that CS1 (CS2) can effectively operate as a common source amplifier. The source degeneration circuit 220 is used to establish the impedance of the source network 200, thereby affecting the gain of CS1 (CS2). In a special case, the source network 200 has an impedance approximately equal to zero, and CS1 (CS2) has a maximum gain, the capacitor 222 is removed, and the resistor 221 is replaced by a short circuit. In an embodiment, at least one of the resistor 221 and the capacitor 222 is adjustable, so that the impedance of the source network 200 and the gain of CS1 (CS2) are adjustable. The source network 200 is well known to those skilled in the art, and therefore no further explanation is needed. The concepts of "adjustable resistor" and "adjustable capacitor" are also well known to those skilled in the art, and therefore no further explanation is needed.

[0063] In a non-limiting example, a 12 nm CMOS (complementary metal-oxide-semiconductor) process technology is used to fabricate the multi-stage amplifier 100 on a silicon substrate, which allows a circuit designer to use a multi-layer structure including a first thick metal layer (hereinafter referred to as TM1), a second thick metal layer (hereinafter referred to as TM2), a "TM1-TM2 via" layer for interconnection between TM1 and TM2, a polysilicon layer, thin metal layers with inter-layer connection vias, and active device layers for fabricating active devices (such as NMOS transistors and PMOS transistors). Using a CMOS process technology, it is a well-known concept to those skilled in the art to use a multi-layer structure (including multiple layers (metal and / or polysilicon and / or active devices) with inter-layer connection vias) to integrate multiple circuits on a silicon substrate, the details of which are not described here.V DDThe voltage of the power supply node VDD is 0.9V; the frequency range of interest is between 10MHz and 13GHz; the inductance values of Llp, Lln, L2p and L2n are 13nH; the resistance values of Rlp, Rln, R2p and R2n are 220 Ohm; the inductance values of Tlp, Tln, T2p and T2n are 200pH; the resistance value of resistor 221 is 100 Ohm; the capacitance value of capacitor 222 is 50fF; and the width-to-length ratio W / L (which stands for width / length) is 5μm / 12nm.

[0064] Figure 3 A top view showing the layout of the multi-stage amplifier 100 is shown. Block 301 shows a legend. As shown, the layout of the multi-stage amplifier 100 is symmetric with respect to a symmetry plane 302 (which is perpendicular to the multi-layer structure and is a line from a top view perspective). The inductors Llp, Lln, L2p, L2n, Tlp, Tln, T2p and T2n are all laid out on TMl. With respect to the symmetry plane 302, Llp, L2p, Tlp and T2p are mirror images of Lln, L2n, Tln and T2n, respectively. Llp, Lln, L2p and L2n are all multi-turn spiral inductors. A portion of the outer turn of Llp (Lln, L2p, L2n) is adjacent to and parallel to a portion of Tlp (Tln, T2p, T2n), which results in a strong inductive coupling and makes the intra-stage coupling coefficient k 1p (k 1n , k 2p , k 2n ) large. A portion of the outer turn of Llp (Lln) is adjacent to and parallel to a portion of the outer turn of L2p (L2n), which results in a strong inductive coupling and makes the inter-stage coupling coefficient k 12p (k 12n ) large. Llp, Lln, L2p and L2n are connected to the power supply node VDD via a metal trace laid out on TM2 and vias 313, 314, 323 and 324, respectively. DDCS1(CS2), SN1(SN2), R1p(R2p) and R1n(R2n) are arranged in close proximity for connection. R1p(R1n, R2p, R2n) comprises a polysilicon trace arranged on the polysilicon layer and connected to L1p(L1n, L2p, L2p) through a series of interlayer connection vias. CS1(CS2) is arranged using layers belonging to NMOS transistors and connected to T1p(T2p) and T1n(T2n) through a series of interlayer vias. SN1(SN2) comprises a polysilicon trace arranged on the polysilicon layer (for making a resistor) and a plurality of inter-digitating metal fingers arranged on the plurality of thin metal layers (for making a capacitor) with interlayer connection vias. By using a strong intra-stage inductive coupling at a stage (ST1 or ST2), the frequency bandwidth of the stage can be extended because the effective inductance of the inductive load network (ILN1 or ILN2) can be increased to increase a high frequency gain. By using a strong inter-stage inductive coupling, the effective inductance of the inductive load network (ILN1 or ILN2) can also be increased to further increase a high frequency gain, thereby extending an overall frequency bandwidth. As a result, the reduction in overall frequency bandwidth caused by adding an additional amplification stage can be improved. This allows a designer to add an additional amplification stage to achieve a higher overall gain without sacrificing an overall frequency bandwidth.

[0065] Although the present application has been described in connection with the embodiments thereof, it will occur to those skilled in the art that modifications can be made of the present application, from its teachings, without departing from the spirit and scope of the application, and it is intended to include all such modifications as fall within the scope of the claims.

Claims

1. A multi-stage amplifier, comprising: a first stage including a first cascode amplifier, a first inductive load network, and a first inter-stage inductor, wherein the first inductive load network includes a first load resistor and a first load inductor connected in series, and includes a first source network for receiving a first signal and outputting a first load signal, and the first inter-stage inductor is for coupling the first load signal to a second signal; and a second stage including a second cascode amplifier, a second inductive load network, and a second inter-stage inductor, wherein the second inductive load network includes a second load resistor and a second load inductor connected in series, and includes a second source network for receiving the second signal and outputting a second load signal, and the second inter-stage inductor is for coupling the second load signal to a third signal, wherein: a portion of the first load inductor is adjacent and parallel to a portion of the first inter-stage inductor in layout, a portion of the second load inductor is adjacent and parallel to a portion of the second inter-stage inductor in layout, and a portion of the first load inductor is adjacent and parallel to a portion of the second load inductor in layout; one end of the first inter-stage inductor is coupled between the first inductive load network and the first cascode amplifier, and the other end of the first inter-stage inductor is coupled to the second cascode amplifier.

2. The multi-stage amplifier of claim 1, wherein each of the first stage and the second stage is fabricated as a multi-layer structure in a complementary metal-oxide-semiconductor process technology on a silicon substrate.

3. The multi-stage amplifier of claim 2, wherein the multi-layer structure includes: a first thick metal layer; a second thick metal layer; a polysilicon layer; a plurality of thin metal layers; a plurality of active device layers suitable for fabricating metal-oxide-semiconductor transistors; and a plurality of inter-layer connection vias.

4. The multi-stage amplifier of claim 3, wherein the first cascode amplifier includes a first n-channel metal-oxide-semiconductor transistor, and the second cascode amplifier includes a second n-channel metal-oxide-semiconductor transistor; the first n-channel metal-oxide-semiconductor transistor receives the first signal at its gate and outputs the first load signal at its drain according to a first bias condition established through the first source network via its source; and the second n-channel metal-oxide-semiconductor transistor receives the second signal at its gate and outputs the second load signal at its drain according to a second bias condition established through the second source network via its source.

5. The multi-stage amplifier of claim 3, wherein the first load inductor, the second load inductor, the first inter-stage inductor, and the second inter-stage inductor each include at least a portion of layout on the first thick metal layer.

6. The multi-stage amplifier of claim 5, wherein the portion of the first load inductor is adjacent and parallel to the portion of the first inter-stage inductor, the portion of the first load inductor is disposed on the first thick metal layer.

7. The multi-stage amplifier of claim 5, wherein the portion of the second load inductor is adjacent and parallel to the portion of the second inter-stage inductor, the portion of the second load inductor is disposed on the first thick metal layer.

8. The multi-stage amplifier of claim 5, wherein the portion of the first load inductor is adjacent and parallel to the portion of the second load inductor, the portion of the first load inductor is disposed on the first thick metal layer.

9. The multi-stage amplifier of claim 5, wherein a power supply node is connected to the first load inductor by a first metal trace and a first interlayer connection via, the first metal trace is disposed on the second thick metal layer; the power supply node is connected to the second load inductor by a second metal trace and a second interlayer connection via, the second metal trace is disposed on the second thick metal layer.

10. A multi-stage amplifier, comprising: a first stage comprising a first cascode amplifier, a first inductive load network, and a first inter-stage inductor, wherein the first inductive load network comprises a first load resistor and a first load inductor connected in series, and comprises a first source network for receiving a first signal and outputting a first load signal, the first inter-stage inductor for coupling the first load signal to a second signal; and a second stage comprising a second cascode amplifier, a second inductive load network, and a second inter-stage inductor, wherein the second inductive load network comprises a second load resistor and a second load inductor connected in series, and comprises a second source network for receiving the second signal and outputting a second load signal, the second inter-stage inductor for coupling the second load signal to a third signal, the first load inductor and the first inter-stage inductor are disposed to enhance inductive coupling within a first stage, the second load inductor and the second inter-stage inductor are disposed to enhance inductive coupling within a second stage, the first load inductor and the second load inductor are disposed to enhance inductive coupling between stages; one end of the first inter-stage inductor is coupled between the first inductive load network and the first cascode amplifier, the other end of the first inter-stage inductor is coupled to the second cascode amplifier. ​ ​ wherein: ​

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