transceiver

Abstract

A transceiver includes a first digital-to-analog converter (D / A converter), a second D / A converter, and a timing control module. In calibration mode, the first D / A converter transmits a transmit signal; the second D / A converter transmits an echo cancellation signal; and the timing control module obtains the timing offset between the echo signal and the echo cancellation signal of the transmit signal within the timing control module, and generates a first timing control signal and a second timing control signal to the first D / A converter and the second D / A converter respectively based on the timing offset. The first D / A converter adjusts the transmission delay of the transmit signal according to the first timing control signal, and / or the second D / A converter adjusts the transmission delay of the echo cancellation signal according to the second timing control signal.

Description

Technical Field

[0001] This invention relates to a transceiver, and more particularly to a transceiver capable of adjusting for delay mismatch. Background Technology

[0002] In transceivers, due to non-ideal factors, the transmission delay of the signal path may differ from the expected delay, resulting in signal distortion and increased noise, which in turn reduces the actual usable dynamic range of the analog-to-digital converter. Therefore, how to improve these problems has become one of the issues of concern in this field. Summary of the Invention

[0003] This invention discloses a transceiver comprising a first digital-to-analog converter (D / A converter), a second D / A converter, and a timing control module. In calibration mode, the first D / A converter transmits a transmitted signal; the second D / A converter transmits an echo cancellation signal; and the timing control module obtains the timing offset between the echo signal and the echo cancellation signal in the timing control module based on the echo signal and the echo cancellation signal of the transmitted signal, and generates a first timing control signal and a second timing control signal to the first D / A converter and the second D / A converter respectively based on the timing offset. The first D / A converter adjusts the transmission delay of the transmitted signal according to the first timing control signal, and / or the second D / A converter adjusts the transmission delay of the echo cancellation signal according to the second timing control signal.

[0004] This invention discloses a transceiver comprising a first digital-to-analog converter and a timing control module. In calibration mode, the first digital-to-analog converter transmits a first signal and a second signal. The timing control module comprises a time-to-digital converter and a controller. In calibration mode, the time-to-digital converter obtains a first time-digital signal and a second time-digital signal based on the first signal and the second signal. The controller obtains a first timing offset between the first signal and the second signal in the timing control module based on the first time-digital signal and the second time-digital signal, and adjusts the transmission delay of the first signal and the transmission delay of the second signal transmitted by the first digital-to-analog converter according to the first timing offset to reduce the first timing offset.

[0005] The transceiver of the present invention uses a timing control module to adjust the transmission delay of signals, thereby reducing timing errors between signals and reducing signal noise. Attached Figure Description

[0006] The various forms of this application can be best understood by reading the following embodiments and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0007] Figure 1 This is a schematic diagram of a transceiver in some embodiments of the present invention.

[0008] Figure 2 This is a schematic diagram of a time-to-digital converter in some embodiments of the present invention.

[0009] Figure 3 This is a schematic diagram of a transceiver in another embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of a digital-to-analog converter in another embodiment of the present invention. Detailed Implementation

[0011] Figure 1 This is a schematic diagram of an embodiment of the transceiver 10 of the present invention. The transceiver 10 is in duplex mode and functions as both a transmitter and a receiver. When the transceiver 10 transmits a transmit signal STX and receives an input signal SRX, it also simultaneously receives the echo signal SE of the transmit signal STX. The echo signal SE increases the noise of the input signal SRX, therefore the transceiver 10 internally generates an echo cancellation signal SC to counteract the effect of the echo signal SE.

[0012] However, when the transmission delays of the echo signal SE and the echo cancellation signal SC are different, causing a timing offset between them, it is not only difficult to completely eliminate the echo signal SE, but also impossible to effectively reduce the noise of the input signal SRX. The transceiver 10 of this invention can adjust the transmission delays of the transmitted signal STX and / or the echo cancellation signal SC to adjust the timing offset between the echo signal SE and the echo cancellation signal SC.

[0013] Transceiver 10 includes a digital-to-analog converter DAC1, a digital-to-analog converter DAC2, a programmable gain amplifier PGA, an analog-to-digital converter ADC, and a timing control module TCM.

[0014] The input / output (IO) terminals are used to transmit the transmitted signal STX and receive the input signal SRX. Simultaneously, the IO terminals also receive the echo signal SE of the transmitted signal STX. The digital-to-analog converter (DAC2) is used to generate the echo cancellation signal SC. In the normal mode of transceiver 10, the programmable gain amplifier (PGA) provides a gain value to the input signal SRX to generate the gain input signal SA. The analog-to-digital converter (ADC) performs analog-to-digital conversion on the gain input signal SA to generate the data signal SD. When the timing relationship between the echo signal SE and the echo cancellation signal SC is incorrect due to certain factors, the resulting noise is amplified by the PGA, significantly increasing the noise of the gain input signal SA. To solve this problem, in this invention, transceiver 10 enters a calibration mode before entering the normal mode. In calibration mode, the timing control module (TCM) adjusts the transmission delay of the echo signal SE and the echo cancellation signal SC based on the echo signal SE and the echo cancellation signal SC, thereby reducing the timing offset between the echo signal SE and the echo cancellation signal SC.

[0015] In some embodiments, in calibration mode, transceiver 10 transmits a transmit signal STX to receive an echo signal SE, but does not transmit an echo cancellation signal SC, allowing the timing control module TCM to process the echo signal SE separately first. Then, transceiver 10 transmits only the echo cancellation signal SC, without transmitting the transmit signal STX, allowing the timing control module TCM to process the echo cancellation signal SC separately.

[0016] The timing control module (TCM) includes a gain unit (AMP), a comparator (COM), a time-to-digital converter (TDC), and a controller (CTR).

[0017] The gain unit AMP provides gain values ​​to the echo signal SE and the echo cancellation signal SC to generate the gained echo signal SEA and the gained echo cancellation signal SCA, respectively. The gain unit AMP applies gain to the echo signal SE and the echo cancellation signal SC to enable subsequent signal processing with larger amplitude signals. In some embodiments, the echo signal SE and the echo cancellation signal SC are differential signals, and the gain unit AMP is also used to convert these differential signals into single-ended signals, but this is not a limitation.

[0018] The comparator COM performs a comparison operation on the gain echo signal SEA and the gain echo cancellation signal SCA to generate comparison signals SP1 and SP2, respectively. Comparison signals SP1 and SP2 are digital signals. Specifically, the comparator COM compares the gain echo signal SEA with a reference value to generate comparison signal SP1, and compares the gain echo cancellation signal SCA with the reference value to generate comparison signal SP2. In some embodiments, the comparator COM performs a one-bit resolution analog-to-digital conversion on the gain echo signal SEA and the gain echo cancellation signal SCA to generate comparison signals SP1 and SP2, but this is not a limitation. In a further embodiment, the comparator COM also provides additional gain when performing the comparison operation on the gain echo signal SEA and the gain echo cancellation signal SCA, so that the generated comparison signals SP1 and SP2 have a larger amplitude.

[0019] The Time-to-Digital Converter (TDC) is used to convert the comparison signals SP1 and SP2 into time-to-digital signals ST1 and ST2 respectively, based on the reference signal SR. For instructions on operating the Time-to-Digital Converter (TDC), please refer to [link to relevant documentation]. Figure 2 . Figure 2 This is a schematic diagram of an embodiment of the Time-to-Digital Converter (TDC) of the present invention. The TDC includes a reference input terminal NR, a data input terminal ND, multiple delay units BF1 to BFN, and multiple flip-flops FF1 to FFN. In some embodiments, the flip-flops FF1 to FFN are D-type flip-flops.

[0020] These delay circuits BF1 to BFN are connected in series to the reference input terminal NR. These flip-flops FF1 to FFN are connected in parallel to the data input terminal ND and the output terminals of the corresponding delay circuits BF1 to BFN. The clock terminal CLK of flip-flops FF1 to FFN is coupled to the data input terminal ND, the terminal D of each flip-flop FF1 to FFN is coupled to the output terminal of the corresponding delay circuit BF1 to BFN, and the terminal Q of each flip-flop FF1 to FFN is used to output the data Q1 to QN of each bit in the digital time signals ST1 and ST2. The reference input terminal NR is used to receive the reference signal SR, which is a clock signal. The data input terminal ND is used to receive the comparison signals SP1 and SP2.

[0021] Before the timing offset between the echo signal SE and the echo cancellation signal SC is adjusted, the transmission delays of the echo signal SE and the echo cancellation signal SC are different (i.e., the echo signal SE and the echo cancellation signal SC arrive at the timing control module TCM at different times). Consequently, the arrival times of the comparison signals SP1 and SP2 at the time-to-digital converter TDC are also different. Therefore, when the comparison signals SP1 and SP2 enter the data input terminal ND at different times, they respectively activate two of the flip-flops FF1 to FFN. The corresponding endpoints Q of the activated two then generate data Q1 to QN with different digital values ​​than the endpoints Q of the preceding flip-flops FF1 to FFN, thus forming the time digital signals ST1 and ST2. For example, if the time digital signals ST1 = 00011111 and ST2 = 00000011, it means that the time offset between the comparison signals SP1 and SP2 differs by 3 minimum units of time (referring to the minimum unit of time of the time-to-digital converter TDC). In other words, the time digital signal ST1 and the time digital signal ST2 record the time difference of the transmission delay between the comparison signal SP1 and the comparison signal SP2. In some embodiments, the time difference of the transmission delay between the comparison signal SP1 and the comparison signal SP2 is approximately equal to the timing offset between the echo signal SE and the echo cancellation signal SC.

[0022] The controller CTR receives time digital signals ST1 and ST2, and generates timing control signals STC1 and STC2 respectively based on the time difference recorded by ST1 and ST2, which are then sent to digital-to-analog converters DAC1 and DAC2. DAC1 and DAC2 then adjust the transmission delays of the transmit signal STX and echo cancellation signal SC according to the timing control signals STC1 and STC2 respectively. For example, if the time representation comparison signal SP2 recorded by ST1 and ST2 arrives at the time digital converter TDC 3 minimum units of time earlier than the comparison signal SP1, DAC1 does not adjust the transmission delay of the transmit signal STX according to timing control signal STC1, while DAC2 increases the transmission delay of the echo cancellation signal SC by 3 minimum units of time according to timing control signal STC2 (i.e., transmits the echo cancellation signal SC 3 minimum units of time later).

[0023] After the digital-to-analog converters DAC1 and DAC2 adjust the transmission delays of the transmit signal STX and the echo cancellation signal SC according to timing control signals STC1 and STC2 respectively, the timing between the echo signal SE and the echo cancellation signal SC is corrected back to the correct relationship. In some embodiments, the timing offset between the echo signal SE and the echo cancellation signal SC is corrected to, but not limited to, less than one minimum unit time. Afterward, the transceiver 10 leaves the correction mode and enters the normal mode.

[0024] In other embodiments, the timing control module (TCM) uses a phase detector instead of the time-to-digital converter (TDC). The phase detector detects the phase difference between comparison signals CP1 and CP2, and then uses this phase difference to generate the digital time signal ST.

[0025] In some embodiments, such as Figure 3 As shown, the timing control module (TCM) does not include a gain unit (AMP). The TCM is coupled to the output of the programmable gain amplifier (PGA) to receive the echo signal SE and echo cancellation signal SC, which are amplified by the PGA. Relative to... Figure 1 In the embodiments, Figure 3 The timing control module TCM uses the gain echo signal SE' and echo cancellation signal SC, which are amplified by the programmable gain amplifier PGA, to replace the gain echo signal SEA and gain echo cancellation signal SCA in order to generate timing control signals STC1 and STC2.

[0026] Please also refer to Figure 4 . Figure 4This is a schematic diagram of an embodiment of the digital-to-analog converter DAC3 of the present invention. The digital-to-analog converter DAC3 can be applied to the digital-to-analog converter DAC1 and / or digital-to-analog converter DAC2 of the transceiver 10. The digital-to-analog converter DAC3 internally contains multiple current source paths. For example, the digital-to-analog converter DAC3 has a resolution of 3 bits and has a number of current source paths corresponding to the number of binary 3-bit thermometer codes (7 in this example, but some paths are omitted). Each current source path includes latches 121-127, delayers 131-137, and current generators 141-147 coupled to the binary-to-thermometer codec 110. When the binary-to-thermometer encoder-decoder 110 decodes the binary signal SB and turns on different current generators 141 to 147, the signals S1 to S7 from the different current generators 141 to 147 may have different transmission delays, which in turn worsens the time delay error introduced by the digital-to-analog converter DAC3 in addition to parameters such as integral non-linearity (INL) and differential non-linearity (DNL).

[0027] To reduce the delay mismatch among the current source paths within the digital-to-analog converter (DAC3), the transceiver 10 further obtains the timing offset between signals S1 to S7, and then generates a timing control signal STC1 based on the timing offset between signals S1 to S7. In some embodiments, the DAC3 sequentially activates current generators 141 to 147 at equal intervals, allowing the timing control module TCM to sequentially receive signals S1, the sum of signals S1 to S2, the sum of signals S1 to S3, ..., the sum of signals S1 to S7. Therefore, the timing control module TCM can distinguish the transmission delay of each current source path by each signal change. The timing control signal STC1, comprising timing control signals STC11 to STC17, is transmitted to delay units 131 to 137 respectively. After receiving the timing control signals STC11 to STC17, the DAC3 adjusts the delay units 131 to 137 to ensure that the delays of each current source path are consistent. It is worth noting that when resolving the timing mismatch between digital-to-analog converters DAC1 and DAC2, the timing control signals STC11 to STC17 are equal, meaning the propagation delay adjustment magnitude for each current source path in DAC1 is equal. However, when resolving the timing mismatch between the current source paths within DAC1, the timing control signals STC11 to STC17 can be different.

[0028] The foregoing description briefly outlines the features of certain embodiments of this application, enabling those skilled in the art to more fully understand the various forms of this application. Those skilled in the art should understand that they can readily use this application as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments still fall within the spirit and scope of this application, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this application.

[0029] [Symbol Explanation]

[0030] 10: Transceiver

[0031] 110: Binary to Thermometer Encoder / Decoder

[0032] 121: Latch

[0033] 122: Latch

[0034] 127: Latch

[0035] 131: Delay Unit

[0036] 132: Delay Unit

[0037] 137: Delay Unit

[0038] 141: Current Generator

[0039] 142: Current Generator

[0040] 147: Current Generator

[0041] ADC: Analog-to-Digital Converter

[0042] AMP: Gain Unit

[0043] BF1: Delay Unit

[0044] BF2: Delay Unit

[0045] BF3: Delay Unit

[0046] BFN: Delay Unit

[0047] CLK: Clock endpoint

[0048] COM: Comparator

[0049] CTR: Controller

[0050] D: Endpoint

[0051] DAC1: Digital-to-Analog Converter

[0052] DAC2: Digital-to-Analog Converter

[0053] DAC3: Digital-to-Analog Converter

[0054] FF(N-1): Flip-Flipper

[0055] FF1: Shifter

[0056] FF2: Shifter

[0057] FF3: Shifter

[0058] FFN: Shifter

[0059] IO: Input / Output Terminal

[0060] ND: Data input terminal

[0061] NR: Reference Input

[0062] PGA: Programmable Gain Amplifier

[0063] Q(N-1): Data

[0064] Q: Endpoint

[0065] Q1: Data

[0066] Q2: Data

[0067] Q3: Data

[0068] QN: Data

[0069] S1: Signal

[0070] S2: Signal

[0071] S7: Signal

[0072] SA: Gain Input Signal

[0073] SB: Binary signal

[0074] SC: Echo Cancellation Signal

[0075] SCA: Gain Echo Cancellation Signal

[0076] SD: Data signal

[0077] SE: Echo Signal

[0078] SE': Gain echo signal

[0079] SEA: Gain Echo Signal

[0080] SP1: Comparison signal

[0081] SP2: Comparison signal

[0082] SR: Reference signal

[0083] SRX: Input signal

[0084] ST: Time Digital Signal

[0085] STC1: Timing control signal

[0086] STC1: Timing control signal

[0087] STC12: Timing control signal

[0088] STC17: Timing Control Signal

[0089] STC2: Timing control signal

[0090] STX: Transmit signal

[0091] TCM: Time Control Module

[0092] TDC: Time-to-Digital Converter

Claims

1. A transceiver comprising: The first digital-to-analog converter, in calibration mode, is used to transmit the transmitted signal; A second digital-to-analog converter, in the correction mode, is used to transmit the echo cancellation signal; and In the correction mode, the timing control module is used to obtain the timing offset between the echo signal and the echo cancellation signal in the timing control module based on the echo signal and the echo cancellation signal of the transmitted signal, and to generate a first timing control signal and a second timing control signal respectively to the first digital-to-analog converter and the second digital-to-analog converter based on the timing offset. The first digital-to-analog converter adjusts the transmission delay of the transmitted signal according to the first timing control signal, and / or the second digital-to-analog converter adjusts the transmission delay of the transmitted echo cancellation signal according to the second timing control signal.

2. The transceiver according to claim 1, wherein the timing control module comprises: A comparator is configured to generate a first comparison signal and a second comparison signal based on the echo signal and the echo cancellation signal, respectively; and The controller is configured to generate the first timing control signal and the second timing control signal based on the first comparison signal and the second comparison signal.

3. The transceiver according to claim 2, wherein the timing control module further comprises: A gain unit is used to provide gain values ​​to the echo signal and the echo cancellation signal to generate a gain echo signal and a gain echo cancellation signal, respectively. The comparator is used to perform a comparison operation on the gain echo signal and the gain echo cancellation signal to generate the first comparison signal and the second comparison signal.

4. The transceiver according to claim 3, wherein the timing control module further comprises: A phase detector is used to detect the phase difference between the echo signal and the echo cancellation signal based on the first comparison signal and the second comparison signal. The controller is used to obtain the timing offset based on the phase difference.

5. The transceiver according to claim 3, wherein the timing control module further comprises: A time-to-digital converter is used to convert the first comparison signal and the second comparison signal into a first time digital signal and a second time digital signal, respectively, based on a reference signal. The controller is used to obtain the timing offset based on the digital time signal.

6. A transceiver comprising: A first digital-to-analog converter, in calibration mode, is used to transmit a first signal and a second signal; and The timing control module includes: A time-to-digital converter, in the correction mode, is used to obtain a first time digital signal and a second time digital signal based on the first signal and the second signal; The controller is configured to obtain a first timing offset between the first signal and the second signal in the timing control module based on the first time digital signal and the second time digital signal, and adjust the transmission delay of the first digital-to-analog converter in transmitting the first signal and the transmission delay of the second signal based on the first timing offset to reduce the first timing offset.

7. The transceiver according to claim 6, wherein the timing control module further comprises: Gain unit, used to provide gain values ​​to the first signal and the second signal to generate a first gain signal and a second gain signal, respectively; and A comparator is used to perform a comparison operation on the first gain signal and the second gain signal to generate a first comparison signal and a second comparison signal.

8. The transceiver according to claim 7, wherein the time-to-digital converter is configured to convert the first comparison signal and the second comparison signal into the first time digital signal and the second time digital signal respectively according to the reference signal, wherein the first time digital signal and the second time digital signal record a first time difference.

9. The transceiver of claim 7, wherein the first digital-to-analog converter is further configured to transmit a transmit signal in the correction mode, and wherein the transceiver further comprises: The second digital-to-analog conversion, in the correction mode, is used to transmit the echo cancellation signal. The timing control module is further configured to obtain a second timing offset between the echo signal of the transmitted signal and the echo cancellation signal in the timing control module.

10. The transceiver of claim 9, wherein the gain unit is further configured to provide the gain value to the echo signal and the echo cancellation signal to generate a gain echo signal and a gain echo cancellation signal, respectively, wherein the comparator is further configured to perform the comparison operation on the gain echo signal and the gain echo cancellation signal to generate a third comparison signal and a fourth comparison signal.

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