Display panel and display device

Abstract

Display panel and display device, wherein the display panel includes: a substrate (010), including a notch area (A2), a display area (A1), and a first non-display area (A3), the first non-display area (A3) being located between the notch area (A2) and the display area (A1); a first conductive layer located on the substrate; a target insulating layer located between the first conductive layer and the substrate; a functional layer located between the target insulating layer and the substrate (010); the display area (A1) includes a plurality of sub-pixels (spx), and at least one of the plurality of sub-pixels (spx) includes: a connection through-hole; wherein the connection through-hole penetrates the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connection through-hole; the first non-display area (A3) includes at least one auxiliary through-hole: wherein the auxiliary through-hole penetrates the target insulating layer and the auxiliary through-hole is not filled with a conductive material.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Electroluminescent diodes such as Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), and Micro Light Emitting Diode (Micro LED) have advantages such as self-luminescence and low power consumption, and are one of the hotspots in the field of application research of current electroluminescent display devices. Summary of the Invention

[0003] The display panel provided by the embodiments of the present disclosure includes:

[0004] A substrate, including a notch area, a display area, and a first non-display area, where the first non-display area is located between the notch area and the display area;

[0005] A first conductive layer, located on the substrate;

[0006] A target insulating layer, located between the first conductive layer and the substrate;

[0007] A functional layer, located between the target insulating layer and the substrate;

[0008] The display area includes a plurality of sub-pixels, a plurality of data lines, a plurality of scan lines, and a plurality of light emission control lines; wherein, at least one of the plurality of sub-pixels includes: a connection through-hole; wherein, the connection through-hole penetrates the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connection through-hole;

[0009] The first non-display area includes: at least one auxiliary through-hole, a plurality of data transmission lines, a plurality of scan transmission lines, and a plurality of light emission transmission lines: wherein, at least one of the plurality of data lines is electrically connected to at least one of the plurality of data transmission lines, at least one of the plurality of scan lines is electrically connected to at least one of the plurality of scan transmission lines, and at least one of the plurality of light emission control lines is electrically connected to at least one of the plurality of light emission transmission lines;

[0010] In the first non-display area, at least two of the plurality of data transmission lines, the plurality of scan transmission lines, and the plurality of light emission transmission lines surround to form an auxiliary area, the auxiliary through-hole is located in the auxiliary area, and the auxiliary through-hole penetrates the target insulating layer and the auxiliary through-hole is not filled with a conductive material.

[0011] Optionally, in the embodiments of the present disclosure, the display panel includes:

[0012] A semiconductor layer located between the substrate and the first conductive layer;

[0013] A first gate insulating layer located between the semiconductor layer and the first conductive layer;

[0014] A third conductive layer located between the first gate insulating layer and the first conductive layer;

[0015] A second gate insulating layer located between the third conductive layer and the first conductive layer;

[0016] A fourth conductive layer located between the second gate insulating layer and the first conductive layer;

[0017] An interlayer dielectric layer located between the fourth conductive layer and the first conductive layer;

[0018] At least one of the plurality of sub-pixels includes: a first connection through-hole, a second connection through-hole, and a third connection through-hole; wherein, the first connection through-hole penetrates through the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer; the second connection through-hole penetrates through the second gate insulating layer and the interlayer dielectric layer; the third connection through-hole penetrates through the interlayer dielectric layer;

[0019] The first conductive layer is electrically connected to the semiconductor layer through the first connection through-hole;

[0020] The first conductive layer is electrically connected to the third conductive layer through the second connection through-hole;

[0021] The first conductive layer is electrically connected to the fourth conductive layer through the third connection through-hole;

[0022] The auxiliary through-hole is filled with an insulating material.

[0023] Optionally, in the embodiments of the present disclosure, the display panel further includes:

[0024] An interlayer insulating layer located on a side of the first conductive layer away from the substrate;

[0025] The auxiliary through-hole is filled with the material of the interlayer insulating layer.

[0026] Optionally, in the embodiments of the present disclosure, the functional layer includes the semiconductor layer;

[0027] The target insulating layer includes: the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer;

[0028] The connection through-holes include the first connection through-hole;

[0029] The auxiliary through-holes include a first auxiliary through-hole that penetrates through the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer, and the material filled in the first auxiliary through-hole penetrates through the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer.

[0030] Optionally, in an embodiment of the present disclosure, the distribution density of the first auxiliary through-holes is less than or approximately equal to the distribution density of the first connection through-holes.

[0031] Optionally, in an embodiment of the present disclosure, the orthographic projection of the first auxiliary through-holes on the substrate does not overlap with the orthographic projections of the semiconductor layer, the third conductive layer, the fourth conductive layer, and the first conductive layer on the substrate.

[0032] Optionally, in an embodiment of the present disclosure, the functional layer includes the third conductive layer;

[0033] The target insulating layer includes: the second gate insulating layer and the interlayer dielectric layer;

[0034] The connection through-holes include the second connection through-hole;

[0035] The auxiliary through-holes include a second auxiliary through-hole that penetrates through the second gate insulating layer and the interlayer dielectric layer, and the material filled in the second auxiliary through-hole penetrates through the second gate insulating layer and the interlayer dielectric layer.

[0036] Optionally, in an embodiment of the present disclosure, the distribution density of the second auxiliary through-holes is less than or approximately equal to the distribution density of the second connection through-holes.

[0037] Optionally, in an embodiment of the present disclosure, the orthographic projection of the second auxiliary through-holes on the substrate does not overlap with the orthographic projections of the third conductive layer, the fourth conductive layer, and the first conductive layer on the substrate.

[0038] Optionally, in an embodiment of the present disclosure, the functional layer includes the fourth conductive layer;

[0039] The target insulating layer includes: the interlayer dielectric layer;

[0040] The connection through-holes include the third connection through-hole;

[0041] The auxiliary through-holes include a third auxiliary through-hole that penetrates through the interlayer dielectric layer, and the material filled in the third auxiliary through-hole penetrates through the interlayer dielectric layer.

[0042] Optionally, in the embodiments of the present disclosure, the distribution density of the third auxiliary vias is less than or approximately equal to the distribution density of the third connection vias.

[0043] Optionally, in the embodiments of the present disclosure, the orthographic projection of the third auxiliary vias on the substrate does not overlap with the orthographic projections of the fourth conductive layer and the first conductive layer on the substrate.

[0044] Optionally, in the embodiments of the present disclosure, the plurality of data transmission lines include a plurality of first data transmission lines; the first conductive layer includes the plurality of data lines and the plurality of first data transmission lines; the interlayer insulating layer has a plurality of first data vias.

[0045] The display panel further includes:

[0046] A second conductive layer, located on a side of the interlayer insulating layer away from the substrate, and including a plurality of first data connection portions.

[0047] At least one of the plurality of first data connection portions is electrically connected to at least one of the plurality of data lines and at least one of the plurality of first data transmission lines through the first data vias respectively.

[0048] Optionally, in the embodiments of the present disclosure, the plurality of data transmission lines include a plurality of second data transmission lines.

[0049] The second conductive layer further includes: the plurality of second data transmission lines; the plurality of second data transmission lines are arranged at intervals from the first data connection portions.

[0050] The interlayer insulating layer further includes: a plurality of second data vias.

[0051] The plurality of data lines include a plurality of first data lines and a plurality of second data lines; wherein, one of the first data lines is electrically connected to one of the first data transmission lines through the first data connection portion; one of the second data lines is electrically connected to one of the second data transmission lines through the second data vias.

[0052] Optionally, in the embodiments of the present disclosure, the third conductive layer includes the plurality of scan lines and the plurality of light emission control lines; wherein, the plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines.

[0053] The display area further includes a plurality of sub-pixels; wherein, one row of the sub-pixels corresponds to one of the first scan lines and one of the second scan lines; the second scan line corresponding to the first row of sub-pixels in every two adjacent rows of sub-pixels is electrically connected to the first scan line corresponding to the second row of sub-pixels.

[0054] One row of the sub-pixels corresponds to one of the light-emitting control lines; and the light-emitting control lines corresponding to adjacent rows of sub-pixels are electrically connected.

[0055] Optionally, in the embodiments of the present disclosure, the first conductive layer further includes: a plurality of first scan connection portions that are insulated from and spaced apart from the data line and the first data transmission line; wherein, the second scan line corresponding to the sub-pixels in the (q - 1)-th row is electrically connected to the first scan line corresponding to the sub-pixels in the q-th row through at least one of the first scan connection portions; q is an integer.

[0056] The second insulating layer includes a plurality of first scan through-holes and a plurality of second scan through-holes.

[0057] The first end of the first scan connection portion is electrically connected to the corresponding first scan line through at least one of the plurality of first scan through-holes, and the second end of the first scan connection portion is electrically connected to the corresponding second scan line through at least one of the plurality of second scan through-holes.

[0058] Optionally, in the embodiments of the present disclosure, all the rows of sub-pixels include first-type row sub-pixels; at least one row of sub-pixels in the first-type row sub-pixels corresponds to at least one of the first data connection portions.

[0059] For the first scan line, the second scan line, and the first data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the first data connection portion on the substrate does not overlap with the orthographic projections of the first scan connection portion corresponding to the first scan line and the first scan connection portion corresponding to the second scan line on the substrate.

[0060] Optionally, in the embodiments of the present disclosure, for the first scan line, the second scan line, and the first data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the first data connection portion on the substrate is located between the orthographic projections of the first scan through-hole corresponding to the first scan line and the second scan through-hole corresponding to the second scan line on the substrate.

[0061] Optionally, in the embodiments of the present disclosure, for the first scan line, the second scan line, and the first data connection portion corresponding to the same row of sub-pixels, the line connecting the centers of the orthographic projections of the first scan through-hole corresponding to the first scan line and the second scan through-hole corresponding to the second scan line on the substrate overlaps with the orthographic projection of the first data connection portion on the substrate.

[0062] Optionally, in the embodiments of the present disclosure, for the first scan line, the first data connection part corresponding to the same row of sub-pixels, the first data line and the first data transmission line electrically connected by using the first data connection part, the orthographic projection of the first data connection part on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate, and the orthographic projections of the first data line and the first data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

[0063] Optionally, in the embodiments of the present disclosure, for the first scan line and the first data connection part corresponding to the same row of sub-pixels, the orthographic projection of the edge area of the first data connection part on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate.

[0064] Optionally, in the embodiments of the present disclosure, for the first scan line and the first data connection part corresponding to the same row of sub-pixels, the orthographic projection of the central area of the first data connection part on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate.

[0065] Optionally, in the embodiments of the present disclosure, some of the row sub-pixels in the first type of row sub-pixels correspond to two first data connection parts. For the first scan line, the second scan line, and the two first data connection parts corresponding to the same row of sub-pixels, the orthographic projections of the two first data connection parts on the substrate have an overlapping area with the orthographic projection of the first scan line on the substrate, and the orthographic projections of the two first data connection parts on the substrate do not overlap with the orthographic projection of the second scan line on the substrate.

[0066] Optionally, in the embodiments of the present disclosure, for the first scan line, the second scan line, and the two first data connection parts corresponding to the same row of sub-pixels

[0067] The orthographic projection of the first first data connection part of the two first data connection parts on the substrate is close to the orthographic projection of the first scan through hole corresponding to the first scan line on the substrate; and / or,

[0068] The orthographic projection of the second first data connection part of the two first data connection parts on the substrate is close to the orthographic projection of the second scan through hole corresponding to the second scan line on the substrate.

[0069] Optionally, in the embodiments of the present disclosure, the second conductive layer further includes: a plurality of second data connection parts; wherein, one second data transmission line is directly electrically connected to at least one of the second data connection parts, and the second data connection part is electrically connected to one second data line through the second data through hole.

[0070] Optionally, in the embodiments of the present disclosure, along the first direction, the first data line and the second data line are alternately arranged;

[0071] The projections of the first data connection portion and the second data connection portion on a straight line extending along the first direction are alternately arranged.

[0072] Optionally, in the embodiments of the present disclosure, all the row sub-pixels include second-type row sub-pixels; the second-type row sub-pixels are different from the first-type row sub-pixels;

[0073] At least one row sub-pixel in the second-type row sub-pixels corresponds to at least one of the second data connection portions;

[0074] For the first scan line corresponding to the same row sub-pixel, the second data connection portion, and the second data line and the second data transmission line electrically connected by the second data connection portion, the orthographic projection of the second data connection portion on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate, and the orthographic projections of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

[0075] Optionally, in the embodiments of the present disclosure, for a row sub-pixel corresponding to two of the first data connection portions, the row sub-pixel also corresponds to one of the second data connection portions;

[0076] For the first scan line corresponding to the same row sub-pixel, the second data connection portion, and the second data line and the second data transmission line electrically connected by the second data connection portion, the orthographic projection of the second data connection portion on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate, and the orthographic projections of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

[0077] Optionally, in the embodiments of the present disclosure, the first conductive layer further includes: a plurality of first light-emitting connection portions that are insulated from and spaced apart from the data line and the first data transmission line; wherein, the mutually electrically connected light-emitting control lines correspond to at least one of the first light-emitting connection portions;

[0078] The second insulating layer includes a plurality of first light-emitting through holes and a plurality of second light-emitting through holes;

[0079] The first end of the first light-emitting connection part is electrically connected to a corresponding one of the light-emitting control lines through at least one of the plurality of first light-emitting through-holes, and the second end of the first light-emitting connection part is electrically connected to another corresponding one of the light-emitting control lines through at least one of the plurality of second light-emitting through-holes.

[0080] Optionally, in the embodiments of the present disclosure, the plurality of scan transmission lines include: a plurality of first scan transmission lines and a plurality of second scan transmission lines, and the light-emitting transmission lines include a plurality of first light-emitting transmission lines and a plurality of second light-emitting transmission lines;

[0081] The third conductive layer further includes the plurality of first scan transmission lines and the plurality of first light-emitting transmission lines located in the first non-display area; wherein, the first scan transmission lines and the first light-emitting transmission lines are arranged at intervals;

[0082] Some of the first scan lines and the second scan lines that are electrically connected to each other are directly and correspondingly electrically connected to a first scan transmission line; and some of the light-emitting control lines that are electrically connected to each other are directly electrically connected to a first light-emitting transmission line;

[0083] The fourth conductive layer further includes the plurality of second scan transmission lines and the plurality of second light-emitting transmission lines located in the first non-display area; wherein, the second scan transmission lines and the second light-emitting transmission lines are arranged at intervals;

[0084] The interlayer dielectric layer further includes a plurality of third scan through-holes and a plurality of third light-emitting through-holes;

[0085] The remaining first scan lines and second scan lines that are electrically connected to each other correspond to a second scan transmission line, and the first scan connection part is further electrically connected to the second scan transmission line through the third scan through-hole;

[0086] The remaining light-emitting control lines that are electrically connected to each other correspond to a second light-emitting transmission line, and the first light-emitting connection part is further electrically connected to the second light-emitting transmission line through the third light-emitting through-hole.

[0087] Optionally, in the embodiments of the present disclosure, the plurality of scan transmission lines include: a plurality of third scan transmission lines, and the light-emitting transmission lines include a plurality of third light-emitting transmission lines;

[0088] The fourth conductive layer includes a plurality of third scan transmission lines located in the first non-display area;

[0089] The interlayer dielectric layer includes a plurality of fourth scan through-holes;

[0090] The mutually electrically connected first scan line and second scan line correspond to one third scan transmission line, and the first scan connection portion is also electrically connected to the third scan transmission line through a fourth scan through hole;

[0091] The third conductive layer further includes a third light-emitting transmission line located in the first non-display area; among them, the mutually electrically connected light-emitting control lines are directly electrically connected to one third light-emitting transmission line.

[0092] Optionally, in the embodiment of the present disclosure, the multiple scan transmission lines include: multiple fourth scan transmission lines, and the light-emitting transmission lines include multiple fourth light-emitting transmission lines;

[0093] The fourth conductive layer includes multiple fourth light-emitting transmission lines located in the first non-display area;

[0094] The interlayer dielectric layer includes multiple fourth light-emitting through holes;

[0095] The mutually electrically connected light-emitting control lines correspond to one fourth light-emitting transmission line, and the first light-emitting connection portion is also electrically connected to the fourth light-emitting transmission line through a fourth light-emitting through hole;

[0096] The third conductive layer further includes a fourth scan transmission line located in the first non-display area; among them, the mutually electrically connected first scan line and second scan line are directly electrically connected to one fourth scan transmission line.

[0097] Optionally, in the embodiment of the present disclosure, for the light-emitting control lines, the second scan line, and the second data connection portion corresponding to the sub-pixels in the same row, the orthographic projection of the second data connection portion on the substrate is located between the orthographic projection of the second scan through hole corresponding to the second scan line and the orthographic projection of the first light-emitting through hole corresponding to the light-emitting control line on the substrate.

[0098] The display device further provided in the embodiment of the present disclosure includes the above display panel. Description of the Drawings

[0099] Figure 1 Structural schematic diagrams of some display panels provided in the embodiment of the present disclosure;

[0100] Figure 2 Circuit structural schematic diagrams of some sub-pixels provided in the embodiment of the present disclosure;

[0101] Figure 3 Layout structural schematic diagrams of some sub-pixels provided in the embodiment of the present disclosure;

[0102] Figure 4a Layout structural schematic diagrams of the semiconductor layer in some sub-pixels provided in the embodiment of the present disclosure;

[0103] Figure 4b Schematic diagram of the layout structure of the third conductive layer in some sub-pixels provided by embodiments of the present disclosure;

[0104] Figure 4c Schematic diagram of the layout structure of the fourth conductive layer in some sub-pixels provided by embodiments of the present disclosure;

[0105] Figure 4d Schematic diagram of the layout structure of the first conductive layer in some sub-pixels provided by embodiments of the present disclosure;

[0106] Figure 4e Schematic diagram of the layout structure of the second conductive layer in some sub-pixels provided by embodiments of the present disclosure;

[0107] Figure 5 is Figure 3 Schematic diagram of the cross-sectional structure along the AA' direction in the shown layout structure diagram;

[0108] Figure 6 Schematic diagram of the structure of some display panels provided by embodiments of the present disclosure;

[0109] Figure 7a Schematic diagram of the layout structure of a partial area of some display panels provided by embodiments of the present disclosure;

[0110] Figure 7b Schematic diagram of the layout structure of a partial area of some other display panels provided by embodiments of the present disclosure;

[0111] Figure 8a is Figure 7a Schematic diagram of the cross-sectional structure along the AA' direction in the shown layout structure diagram of the partial area of the display panel;

[0112] Figure 8b is Figure 7a Schematic diagram of the cross-sectional structure along the BB' direction in the shown layout structure diagram of the partial area of the display panel;

[0113] Figure 8c is Figure 7b Schematic diagram of the cross-sectional structure along the BB' direction in the shown layout structure diagram of the partial area of the display panel;

[0114] Figure 9a Schematic diagram of the layout structure of a partial area of some other display panels provided by embodiments of the present disclosure;

[0115] Figure 9b Schematic diagram of the layout structure of a partial area of some other display panels provided by embodiments of the present disclosure;

[0116] Figure 10a The Figure 9a schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of the partial area of the display panel shown;

[0117] Figure 10b The Figure 9a schematic cross-sectional structure diagram along the BB' direction in the layout structure diagram of the partial area of the display panel shown;

[0118] Figure 10c The Figure 9b schematic cross-sectional structure diagram along the BB' direction in the layout structure diagram of the partial area of the display panel shown;

[0119] Figure 11 Some other layout structure diagrams of the partial area of the display panel provided by the embodiments of the present disclosure;

[0120] Figure 12 The Figure 11 schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of the partial area of the display panel shown;

[0121] Figure 13 Some other layout structure diagrams of the partial area of the display panel provided by the embodiments of the present disclosure;

[0122] Figure 14 The Figure 13 schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of the partial area of the display panel shown. Detailed implementation manners

[0123] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0124] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are merely used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0125] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of this disclosure. Throughout the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions.

[0126] With the development of display technology, the full-screen display, with its large screen-to-body ratio and ultra-narrow bezels, can greatly improve the visual effect of viewers compared with ordinary display screens, and thus has received extensive attention. Generally, in a display device such as a mobile phone that adopts a full-screen display, in order to implement functions such as selfies and calls, a front camera, a receiver, etc. are usually provided on the front of the display device. Generally, a notch area A2 for arranging devices such as a front camera and a receiver is provided in the display panel. However, due to the existence of this notch area A2, it is necessary to wind the scan lines and data lines according to the notch area A2, which results in a coupling effect between the scan lines and the data lines, causing signal interference and affecting the display effect.

[0127] In view of this, embodiments of this disclosure provide a display panel that can reduce the coupling effect between scan lines and data lines, reduce signal interference, and improve the display effect.

[0128] As Figure 1As shown in the figure, the display panel provided by the embodiment of the present disclosure may include: a substrate 010. The substrate 010 may include a notch area A2, a display area A1, and a first non-display area A3, and the first non-display area A3 is located between the notch area A2 and the display area A1. Among them, the substrate 010 may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited herein. When the display panel is applied to a display device, devices such as a camera and a receiver are generally also provided. Therefore, in order to provide devices such as a camera and a receiver, the notch area A2 may be a hollowed-out area of the substrate 010. For example, in the actual manufacturing process, the position of the substrate 010 corresponding to the notch area A2 is dug into a hollowed-out area by cutting to be used for providing devices such as a camera and a receiver in the display device. Alternatively, the substrate 010 may not be cut, but the circuit on the substrate 010 is avoided to make the position corresponding to the notch area A2 a transparent area to form the notch area A2.

[0129] In practical applications, the display panel generally may also include a border area surrounding the display area A1. Elements such as an electrostatic discharge circuit and a gate driving circuit may be provided in the border area. Of course, the display panel may also not be provided with a border area, which can be designed and determined according to the requirements of the actual application environment and is not limited herein.

[0130] In specific implementation, in the embodiment of the present disclosure, as Figure 1 shown, the display area A1 may further include a plurality of pixel units PX arranged in an array. Among them, the pixel unit PX may include a plurality of sub-pixels spx. The sub-pixels spx may be arranged in an array in the display area A1. Exemplarily, in combination with Figure 1 and Figure 2 shown, the sub-pixel spx may include: a pixel driving circuit 0121 and a light-emitting device 0120. Among them, the pixel driving circuit 0121 has transistors and capacitors, and generates an electrical signal through the interaction of the transistors and capacitors. The generated electrical signal is input into the first light-emitting electrode of the light-emitting device 0120. And by applying a corresponding voltage to the second light-emitting electrode of the light-emitting device 0120, the light-emitting device 0120 can be driven to emit light.

[0131] In combination with Figure 2 shown, the pixel driving circuit 0121 may include: a driving control circuit 0122, a first light-emitting control circuit 0123, a second light-emitting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129.

[0132] The drive control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the drive control circuit 0122 is configured to provide a drive current for driving the light-emitting device 0120 to emit light. For example, the first light-emitting control circuit 0123 is connected to the first terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the drive control circuit 0122 is configured to connect and conduct or disconnect the connection between the drive control circuit 0122 and the first voltage terminal VDD.

[0133] The second light-emitting control circuit 0124 is electrically connected to the second terminal of the drive control circuit 0122 and the first light-emitting electrode of the light-emitting device 0120. And the second light-emitting control circuit 0124 is configured to connect and conduct or disconnect the connection between the drive control circuit 0122 and the light-emitting device 0120.

[0134] The data writing circuit 0126 is electrically connected to the first terminal of the drive control circuit 0122. And the second light-emitting control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scan line GA2.

[0135] The storage circuit 0127 is electrically connected to the control terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals.

[0136] The threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the drive control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the drive control circuit 0122.

[0137] The reset circuit 0129 is electrically connected to the control terminal of the drive control circuit 0122 and the first light-emitting electrode of the light-emitting device 0120. And the reset circuit 0129 is configured to reset the control terminal of the drive control circuit 0122 and the first light-emitting electrode of the light-emitting device 0120 under the control of the signal on the gate line GA1.

[0138] Wherein, the light-emitting device 0120 may include a first light-emitting electrode, a light-emitting functional layer, and a second light-emitting electrode which are stacked. Exemplarily, the first light-emitting electrode may be an anode, and the second light-emitting electrode may be a cathode. The light-emitting functional layer may include a light-emitting layer. Further, the light-emitting functional layer may further include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light-emitting device 0120 may be designed and determined according to the requirements of the actual application environment, which is not limited herein.

[0139] Exemplarily, in combination with Figure 2As shown, the drive control circuit 0122 includes: a drive transistor T1. The control terminal of the drive control circuit 0122 includes the gate of the drive transistor T1. The first terminal of the drive control circuit 0122 includes the first pole of the drive transistor T1. The second terminal of the drive control circuit 0122 includes the second pole of the drive transistor T1.

[0140] Exemplarily, in combination with Figure 2 As shown, the data writing circuit 0126 includes a data writing transistor T2. The storage circuit 0127 includes a storage capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a first light emission control transistor T4. The second light emission control circuit 0124 includes a second light emission control transistor T5. The reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.

[0141] Specifically, the first pole of the data writing transistor T2 is electrically connected to the first pole of the drive transistor T1. The second pole of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive a data signal. The gate of the data writing transistor T2 is configured to be electrically connected to the second scan line GA2 to receive a scan signal.

[0142] The first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD. The second pole of the storage capacitor CST is electrically connected to the gate of the drive transistor T1.

[0143] The first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the drive transistor T1. The second pole of the threshold compensation transistor T3 is electrically connected to the gate of the drive transistor T1. The gate of the threshold compensation transistor T3 is configured to be electrically connected to the second scan line GA2 to receive a compensation control signal.

[0144] The first pole of the first reset transistor T6 is configured to be electrically connected to the first reset signal line VINIT1 to receive a first reset signal. The second pole of the first reset transistor T6 is electrically connected to the gate of the drive transistor T1. The gate of the first reset transistor T6 is configured to be electrically connected to the first scan line GA1 to receive a control signal.

[0145] The first pole of the second reset transistor T7 is configured to be electrically connected to the second reset signal line VINIT2 to receive a second reset signal. The second pole of the second reset transistor T7 is electrically connected to the first light emitting electrode of the light emitting device 0120. The gate of the second reset transistor T7 is configured to be electrically connected to the first scan line GA1 to receive a control signal.

[0146] The first pole of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD. The second pole of the first light-emitting control transistor T4 is electrically connected to the first pole of the driving transistor T1. The gate of the first light-emitting control transistor T4 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0147] The first pole of the second light-emitting control transistor T5 is electrically connected to the second pole of the driving transistor T1. The second pole of the second light-emitting control transistor T5 is electrically connected to the first light-emitting electrode of the light-emitting device 0120. The gate of the second light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0148] The second light-emitting electrode of the light-emitting device 0120 is electrically connected to the second power supply terminal VSS. Herein, the first pole and the second pole of the above transistors can be determined as the source or the drain according to the actual application, and are not limited herein.

[0149] Exemplarily, one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. For example, in the embodiment shown as Figure 2 shown, the first power supply terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; while the second power supply terminal VSS can be a voltage source to output a constant second voltage, and the second voltage is a negative voltage, etc. For example, in some examples, the second power supply terminal VSS can be grounded.

[0150] It should be noted that in the embodiments of the present disclosure, the pixel driving circuit in the sub-pixel spx can be Figure 2 the structure shown, and can also be a structure including other numbers of transistors, which is not limited in the embodiments of the present disclosure.

[0151] Figure 3 is a schematic layout structure diagram of a pixel driving circuit provided by some embodiments of the present disclosure. Figures 4a to 4e is a schematic diagram of each layer of a pixel driving circuit provided by some embodiments of the present disclosure. Among them, Figures 3 to 4e the example shown takes the pixel driving circuit of one sub-pixel spx as an example. Among them, Figures 3 to 4e it also shows the first scan line GA1, the second scan line GA2, the first reset signal line VINIT1 (if the first reset signal line VINIT1 and the second reset signal line VINIT2 are the same signal line, then the first reset signal line VINIT1 is shown), the light-emitting control line EM, the data line VD, the first power supply signal line VDD1 and the second power supply signal line VDD2 that are electrically connected to the first power supply terminal VDD. The first power supply signal line VDD1 and the second power supply signal line VDD2 are electrically connected to each other.

[0152] Exemplarily, asFigure 3 As shown in Figure 4a , the semiconductor layer 500 of the pixel driving circuit 0121 is shown. The semiconductor layer 500 can be formed by patterning a semiconductor material. The semiconductor layer 500 can be used to fabricate the active layers of the driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, and second reset transistor T7 described above. Each active layer can include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layers of the respective transistors are integrally provided.

[0153] For example, the semiconductor layer 500 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0154] It should be noted that in the display area A1, the semiconductor layer 500 can be patterned using a lithography process. In the first non-display area A3, the unpatterned semiconductor layer 500 is retained. Moreover, the semiconductor layers 500 in the first non-display area A3 and the display area A1 are arranged at intervals. Of course, the present disclosure includes but is not limited to this.

[0155] Exemplarily, a first gate insulating layer 610 (not shown) is formed on the above-mentioned semiconductor layer 500 to protect the above-mentioned semiconductor layer 500. As Figure 3 As shown in Figure 4b , the third conductive layer 300 of the pixel driving circuit 0121 is shown. The third conductive layer 300 is disposed on the first gate insulating layer 610, thereby insulating it from the semiconductor layer 500. The third conductive layer 300 can include the second electrode CC2a of the storage capacitor CST, the first scan line GA1, the second scan line GA2, the light-emitting control line EM, and the gates of the driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, and second reset transistor T7.

[0156] For example, as Figures 3 to 4bAs shown, the gate of the data writing transistor T2 may be the overlapping portion of the second scanning line GA2 and the semiconductor layer 500. The gate of the first light-emitting control transistor T4 may be the first overlapping portion of the light-emitting control line EM and the semiconductor layer 500. The gate of the second light-emitting control transistor T5 may be the second overlapping portion of the light-emitting control line EM and the semiconductor layer 500. The gate of the first reset transistor T6 is the first overlapping portion of the first scanning line GA1 and the semiconductor layer 500. The gate of the second reset transistor T7 is the second overlapping portion of the first scanning line GA1 and the semiconductor layer 500. The threshold compensation transistor T3 may be a thin film transistor with a double-gate structure. The first gate of the threshold compensation transistor T3 may be the first overlapping portion of the second scanning line GA2 and the semiconductor layer 500. The second gate of the threshold compensation transistor T3 may be the second overlapping portion of the protruding portion protruding from the second scanning line GA2 and the semiconductor layer 500. As Figure 3 and 4b shown, the gate of the driving transistor T1 may be the second electrode CC2a of the storage capacitor CST.

[0157] It should be noted that Figure 4a each of the dashed rectangular frames in shows the respective overlapping portions of the third conductive layer 300 and the semiconductor layer 500 in the sub-pixel spx. Among them, the active layer of the threshold compensation transistor T3 has a first channel region overlapping with the first gate of the threshold compensation transistor T3, a second channel region overlapping with the second gate of the threshold compensation transistor T3, and a source-drain region located between the first channel region and the second channel region. The source-drain region is used to electrically connect the first channel region and the second channel region.

[0158] Exemplarily, as Figure 3 and Figure 4b shown, the first scanning line GA1, the second scanning line GA2, and the light-emitting control line EM are arranged along the second direction F2, and the second scanning line GA2 is located between the first scanning line GA1 and the light-emitting control line EM.

[0159] Exemplarily, as Figure 3 and Figure 4b shown, in the second direction F2, the second electrode CC2a of the storage capacitor CST is located between the second scanning line GA2 and the light-emitting control line EM. The protruding portion protruding from the second scanning line GA2 is located on the side of the second scanning line GA2 away from the light-emitting control line EM.

[0160] Exemplarily, as Figure 3 and Figure 4bAs shown, in the second direction F2, the gates of the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are all located on the first side of the gate of the driving transistor T1, and the gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.

[0161] For example, in some embodiments, as Figure 3 with Figure 4b shown, in the first direction F1, the gates of the data writing transistor T2 and the first light-emitting control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the first gate of the threshold compensation transistor T3, the gate of the second light-emitting control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. Among them, the third side and the fourth side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the first direction F1.

[0162] Exemplarily, a second gate insulating layer 620 (not shown) is formed on the above-mentioned third conductive layer 300 to protect the above-mentioned third conductive layer 300. As Figure 3 with Figure 4c shown, the fourth conductive layer 400 of the pixel driving circuit 0121 is shown. The fourth conductive layer 400 is disposed on the second gate insulating layer 620. The fourth conductive layer 400 may include: the first pole CC1a of the storage capacitor CST, the first reset signal line VINIT1, and the light-shielding portion 344a. Exemplarily, the orthographic projection of the first pole CC1a of the storage capacitor CST on the substrate 010 and the orthographic projection of the second pole CC2a of the storage capacitor CST on the substrate 010 at least partially overlap to form the storage capacitor CST. The orthographic projection of the light-shielding portion 344a on the substrate 010 and the source-drain region in the active layer of the threshold compensation transistor T3 have an overlapping region on the substrate 010.

[0163] Exemplarily, an interlayer dielectric layer 630 (not shown) is formed on the above-mentioned fourth conductive layer 400 to protect the above-mentioned fourth conductive layer 400. As Figure 3 with Figure 4d shown, the first conductive layer 100 of the pixel driving circuit 0121 is shown. The first conductive layer 100 is disposed on the interlayer dielectric layer 630. The first conductive layer 100 may include: the data line VD, the first power supply signal line VDD1, and the bridging portions 341a, 342a, and 343a.

[0164] Exemplarily, an interlayer insulating layer 640 (not shown) is formed on the above-mentioned first conductive layer 100 to protect the above-mentioned first conductive layer 100. As Figure 3 withFigure 4e As shown, the second conductive layer 200 of the pixel driving circuit 0121 is shown, and the second conductive layer 200 is disposed on the interlayer insulating layer 640. The second conductive layer 200 includes a second power signal line VDD2 and a transfer portion 351a.

[0165] Figure 5 for Figure 3 The schematic diagram of the layout structure is a schematic diagram of a cross-sectional structure along the AA' direction. A first gate insulating layer 610 is provided between the semiconductor layer 500 and the third conductive layer 300, a second gate insulating layer 620 is provided between the third conductive layer 300 and the fourth conductive layer 400, an interlayer dielectric layer 630 is provided between the fourth conductive layer 400 and the first conductive layer 100, and an interlayer insulating layer 640 is provided between the first conductive layer 100 and the second conductive layer 200.

[0166] Combination Figure 3 and Figure 5 As shown, the sub-pixel spx includes a first connection through hole, a second connection through hole, a third connection through hole and a fourth connection through hole; wherein the first connection through hole passes through the first gate insulation layer 610, the second gate insulation layer 620 and the interlayer dielectric layer 630; the second connection through hole passes through the second gate insulation layer 620 and the interlayer dielectric layer 630; the third connection through hole passes through the interlayer dielectric layer 630; and the fourth connection through hole passes through the interlayer insulation layer 640.

[0167] Exemplarily, the sub-pixel spx may include first connection through holes 381a, 382a, 384a, 387a and 388a. The sub-pixel spx may include a second connection through hole 385a. The sub-pixel spx may include third connection through holes 386a, 3832a and 389a. The sub-pixel spx includes fourth connection through holes 385a and 3831a. The data line VD is electrically connected to the source region of the data writing transistor T2 in the semiconductor layer 500 through at least one first connection through hole 381a. The first power signal line VDD1 is electrically connected to the source region of the corresponding first light emission control transistor T4 in the semiconductor layer 500 through at least one first connection through hole 382a. One end of the bridge portion 341a is electrically connected to the drain region of the corresponding threshold compensation transistor T3 in the semiconductor layer 500 through at least one first connection through hole 384a. The other end of the bridge portion 341a is electrically connected to the gate of the driving transistor T1 in the third conductive layer 300 (i.e., the second electrode CC2a of the storage capacitor CST) through at least one second connection through hole 385a. One end of the bridge portion 342a is electrically connected to the first reset signal line VINIT1 through at least one third connection through hole 386a, and the other end of the bridge portion 342a is electrically connected to the drain region of the second reset transistor T7 in the semiconductor layer 500 through at least one first connection through hole 387a. The bridge portion 343a is electrically connected to the drain region of the second light emission control transistor T5 in the semiconductor layer 500 through at least one first connection through hole 388a. The first power signal line VDD1 is electrically connected to the first electrode CC1a of the storage capacitor CST in the fourth conductive layer 400 through at least one third connection through hole 3832a. The first power signal line VDD1 is also electrically connected to the second power signal line VDD2 in the second conductive layer 200 through at least one fourth connection through hole 3831a. The transfer portion 351a is electrically connected to the bridge portion 343a by penetrating at least one fourth connection through hole 385a. The first power signal line VDD1 is also electrically connected to the light shielding portion 344a through at least one first connection through hole 389a to input a fixed voltage to the light shielding portion 344a.

[0168] For example, the first connection through holes 381a, 382a, 384a, 387a and 388a in the sub-pixel may be provided with one or two, etc. In practical applications, the design may be determined according to the requirements of the actual application environment, and is not limited here.

[0169] For example, one or two second connecting through holes 385a in a sub-pixel may be provided. In practical applications, the design may be determined according to the requirements of the practical application environment, and is not limited here.

[0170] For example, the third connection through holes 386a, 3832a and 389a in the sub-pixel may be provided with one or two, etc. In practical applications, the design may be determined according to the requirements of the practical application environment, and is not limited here.

[0171] For example, one or two fourth connection through holes 385a and 3831a in a sub-pixel may be respectively provided. In practical applications, the design may be determined according to the requirements of the practical application environment, and is not limited here.

[0172] Furthermore, a planarization layer, a first light-emitting electrode layer, a pixel defining layer, a light-emitting function layer, and a second light-emitting electrode layer are sequentially arranged on the side of the second conductive layer 200 away from the base substrate 010. Moreover, the first light-emitting electrode is electrically connected to the transfer portion 351a through a via hole penetrating the planarization layer.

[0173] For example, Figures 3 to 4e As shown, in the second direction F2, the first scan line GA1, the second scan line GA2, and the first reset signal line VINIT1 are all located at a first side of the gate of the driving transistor T1, and the light emitting control line EM is located at a second side of the driving transistor T1.

[0174] In a specific implementation, on the entire display substrate, the first power signal line VDD1 and the second power signal line VDD2 are electrically connected, so that the signal line electrically connected to the first power terminal VDD has a smaller resistance and a lower voltage drop, thereby improving the stability of the power voltage provided by the first power terminal VDD.

[0175] For example, the first scan line GA1, the second scan line GA2, and the light emitting control line EM may be located in the same layer (ie, the third conductive layer 300). The first power signal line VDD1 and the data line VD are located in the same layer (ie, the first conductive layer 100).

[0176] It should be noted that the position arrangement relationship of the transistors in each sub-pixel spx is not limited to Figures 3 to 4e In the example shown, the position of the above transistors can be specifically set according to actual application requirements.

[0177] It should be noted that the first direction F1 may be the row direction of the sub-pixels, and the second direction F2 may be the column direction of the sub-pixels. Alternatively, the first direction F1 may be the column direction of the sub-pixels, and the second direction F2 may be the row direction of the sub-pixels. In practical applications, it can be set according to actual application requirements and is not limited here.

[0178] In specific implementation, in the embodiments of the present disclosure, the display area may include a plurality of data lines, a plurality of scan lines, and a plurality of light emission control lines. The first non-display area may include a plurality of data transmission lines, a plurality of scan transmission lines, and a plurality of light emission transmission lines: wherein, at least one of the plurality of data lines is electrically connected to at least one of the plurality of data transmission lines, at least one of the plurality of scan lines is electrically connected to at least one of the plurality of scan transmission lines, and at least one of the plurality of light emission control lines is electrically connected to at least one of the plurality of light emission transmission lines.

[0179] In specific implementation, in the embodiments of the present disclosure, as Figure 6 shown, the plurality of data lines in the first conductive layer 100 may include a data line VD1 and a data line VD2. Among them, both the data line VD1 and VD2 are located in the display area A1, and the data line VD1 and VD2 are respectively arranged along the first direction F1. The data line VD1 extends from the lower side of the display area A1 to the upper side of the display area A1 along the second direction F2 and is arranged along the first direction F1. The data line VD2 extends along the second direction F2 and is divided by the notch area A2, that is to say, the data line VD2 may extend from the lower side of the display area A1 to the first non-display area A3, or may extend from the upper side of the display area A1 to the first non-display area A3.

[0180] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, the first conductive layer 100 may further include: a plurality of first data transmission lines 711 arranged at intervals. The second conductive layer 200 may further include: a plurality of first data connection portions 211 arranged at intervals. And the interlayer insulating layer 640 has a plurality of first data through holes. And at least one of the plurality of first data connection portions 211 is electrically connected to at least one of the plurality of data lines VD2 and at least one of the plurality of first data transmission lines 711 through the first data through holes respectively. In this way, the data lines in the first conductive layer 100 and the first data transmission lines 711 can be electrically connected to each other through the first data connection portions 211 in the second conductive layer 200. It should be noted that the data lines VD2 corresponding to the same column of sub-pixels spx and divided by the notch area A2 can be electrically connected to each other through the first data transmission lines 711 to form a data line for inputting data signals to this column of sub-pixels spx.

[0181] The above display panel provided by the embodiments of the present disclosure enables the data line VD2 and the first data transmission line 711 in the first conductive layer 100 to be electrically connected to each other through the first data connection portion 211 in the second conductive layer 200 by disposing the first data connection portion 211 in the second conductive layer 200. In this way, not only can the data lines VD2 corresponding to the same column of sub-pixels spx and separated by the notch area A2 be electrically connected, but also the interference of the first data connection portion 211 on the third conductive layer 300 and the fourth conductive layer 400 can be reduced, thereby improving the signal stability and the display effect.

[0182] Moreover, since there are many bridging portions provided in the first conductive layer 100, if the first data connection portion 211 is also disposed in the first conductive layer 100, the area in the first conductive layer 100 for disposing the bridging portions, the data lines, and the first power signal line will be reduced, which may cause a short circuit among the bridging portions, the data lines, the first power signal line, and the first data connection portion 211. Therefore, the above display panel provided by the embodiments of the present disclosure can also reduce the short-circuit risk, further improve the stability of the display panel, and enhance the competitiveness of the display panel.

[0183] In a specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, multiple first data transmission lines 711 are located in the first non-display area A3. Exemplarily, the multiple first data transmission lines 711 may be arranged in an arc around the notch area A2. The interlayer insulating layer 640 may have: a plurality of first data vias 641-1 and a plurality of first data vias 641-2. One first data connection portion 211 corresponds to at least one first data via 641-1 and at least one first data via 641-2. Moreover, one end of the first data connection portion 211 may be electrically connected to the data line VD2 through the corresponding first data via 641-1, and the other end of the first data connection portion 211 may be electrically connected to the first data transmission line 711 through the corresponding first data via 641-2. In practical applications, one first data connection portion 211 may correspond to one, two, three, or more first data vias 641-1. Also, one first data connection portion 211 may correspond to one, two, three, or more first data vias 641-2. These can be designed and determined according to the actual application requirements and are not limited herein.

[0184] In a specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8aAs shown, a plurality of data lines VD2 may include a plurality of first data lines 121 and a plurality of second data lines 122. Exemplarily, along the first direction F1, the first data lines 121 and the second data lines 122 may be alternately arranged. For example, in the direction indicated by the arrow along the first direction F1, the odd-numbered ones among the plurality of data lines VD2 may be used as the first data lines 121, and the even-numbered ones among the plurality of data lines VD2 may be used as the second data lines 122. Of course, the first data lines 121 and the second data lines 122 may also be designed and determined according to the requirements of the actual application environment, which is not limited herein.

[0185] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, one first data line 121 may be electrically connected to one first data transmission line 711 through a first data connection portion 211. Exemplarily, one first data line 121 may correspond to one first data connection portion 211 and one first data transmission line 711. And, the first data line 121 may be electrically connected to the corresponding first data transmission line 711 through the corresponding first data connection portion 211, so that the first data lines 121 corresponding to the same column of sub-pixels spx and separated by the notch region A2 can be electrically connected to the first data transmission line 711 through the corresponding first data connection portions 211.

[0186] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, the second conductive layer 200 may further include: a plurality of second data transmission lines 712 spaced apart from the first data connection portions 211; the interlayer insulating layer 640 may further include: a plurality of second data through holes 642. One second data line 122 is electrically connected to one second data transmission line 712 through the second data through hole 642. Exemplarily, one second data line 122 may correspond to one second data transmission line 712, and one second data transmission line 712 may correspond to at least one second data through hole 642, so that the second data line 122 can be electrically connected to the corresponding second data transmission line through the corresponding second data through hole 642. In actual application, one second data transmission line 712 may correspond to one, two, three or more second data through holes 642. These can be designed and determined according to the requirements of the actual application, which is not limited herein.

[0187] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 7b shown, the plurality of second data transmission lines 712 are located in the first non-display area A3. Exemplarily, the plurality of second data transmission lines 712 may be arranged in an arc around the notch region A2. Further, the orthographic projection of the second data transmission line 712 on the substrate 010 and the orthographic projection of the first data transmission line 711 on the substrate 010 may be spaced apart. Exemplarily, as Figures 6 to 7bAs shown, the orthographic projection of the first data transmission line 711 on the substrate 010 and the orthographic projection of the second data transmission line 712 on the substrate 010 can be alternately arranged. Since the first data transmission line 711 and the second data transmission line 712 are located in different planes, the distance between the first data transmission line 711 and the second data transmission line 712 can be increased, further reducing the signal interference between the first data transmission line 711 and the second data transmission line 712.

[0188] Exemplarily, in order to reduce the occupied area, the orthographic projection of one second data transmission line 712 on the substrate 010 and the orthographic projection of one first data transmission line 711 on the substrate 010 can have an overlapping area. Further, the orthographic projection of one second data transmission line 712 on the substrate 010 and the orthographic projection of one first data transmission line 711 on the substrate 010 can be partially overlapped, so that the occupied area of the first data transmission line 711 and the second data transmission line 712 can be reduced to the greatest extent, and then the occupied area of the first non-display area A3 can be reduced.

[0189] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 7b shown, multiple scan lines can include multiple first scan lines GA1 and multiple second scan lines GA2 located in the display area A1, that is, the third conductive layer 300 can include multiple first scan lines GA1 and multiple second scan lines GA2 located in the display area A1; wherein, one row of sub-pixels spx corresponds to one first scan line GA1 and one second scan line GA2. And, the second scan line GA2 corresponding to the (q - 1)-th row of sub-pixels G(q - 1) in every two adjacent rows of sub-pixels spx is electrically connected to the first scan line GA1 corresponding to the q-th row of sub-pixels G(q). For example, Figure 7a With Figure 7b showing four rows of sub-pixels spx arranged along the second direction F2, along the direction opposite to the arrow of the second direction F2, there can be the (q - 1)-th row of sub-pixels G(q - 1), the q-th row of sub-pixels G(q), the (q + 1)-th row of sub-pixels G(q + 1), and the (q + 2)-th row of sub-pixels G(q + 2). The second scan line GA2 corresponding to the (q - 1)-th row of sub-pixels G(q - 1) is electrically connected to the first scan line GA1 corresponding to the q-th row of sub-pixels G(q), and the second scan line GA2 corresponding to the q-th row of sub-pixels G(q) is electrically connected to the first scan line GA1 corresponding to the (q + 1)-th row of sub-pixels G(q + 1). The rest is the same by analogy, and details are not described here. It should be noted that q is an integer, Figure 7a With Figure 7b only showing a part of the rows of sub-pixels spx in the display panel.

[0190] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8aAs shown, the first conductive layer 100 may further include: a plurality of first scan connection portions 131 that are insulated from and spaced apart from the data lines and the first data transmission lines 711; wherein, the second scan line GA2 corresponding to the sub-pixels G(q - 1) in the (q - 1)-th row is electrically connected to the first scan line GA1 corresponding to the sub-pixels G(q) in the q-th row through at least one first scan connection portion 131. Further, the second insulating layer may further include a plurality of first scan vias 811 and a plurality of second scan vias 812; wherein, a first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through at least one of the plurality of first scan vias 811, and a second end of the first scan connection portion 131 is electrically connected to the corresponding second scan line GA2 through at least one of the plurality of second scan vias 812. Exemplarily, the mutually electrically connected first scan line GA1 and second scan line GA2 may correspond to one first scan connection portion 131. One first scan connection portion 131 may correspond to at least one first scan via 811 and at least one second scan via 812. For example, one first scan connection portion 131 may correspond to one first scan via 811 and one second scan via 812. The second scan line GA2 corresponding to the sub-pixels G(q - 1) in the (q - 1)-th row is electrically connected to the first scan line GA1 corresponding to the sub-pixels G(q) in the q-th row, the electrically connected second scan line GA2 and first scan line GA1 correspond to one first scan connection portion 131, and the first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through the corresponding first scan via 811, and the second end of the first scan connection portion 131 is electrically connected to the corresponding second scan line GA2 through the corresponding second scan via 812. The second scan line GA2 corresponding to the sub-pixels G(q) in the q-th row is electrically connected to the first scan line GA1 corresponding to the sub-pixels G(q + 1) in the (q + 1)-th row, the electrically connected second scan line GA2 and first scan line GA1 correspond to one first scan connection portion 131, and the first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through the corresponding first scan via 811, and the second end of the first scan connection portion 131 is electrically connected to the corresponding second scan line GA2 through the corresponding second scan via 812. The same applies to the rest, and so on, which will not be elaborated here. It should be noted that the second insulating layer may include: a second gate insulating layer 620 and an interlayer dielectric layer 630.

[0191] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8aAs shown, all row sub-pixels spx can include a first type of row sub-pixels spx. At least one row sub-pixel spx in the first type of row sub-pixels spx corresponds to at least one first data connection portion 211. Exemplarily, the first type of row sub-pixels spx can include some rows among all row sub-pixels spx. And, each row sub-pixel spx in the first type of row sub-pixels spx can correspond to at least one first data connection portion 211. For example, each row in some row sub-pixels spx in the first type of row sub-pixels spx can correspond to one first data connection portion 211, and each row in the remaining row sub-pixels spx can correspond to two first data connection portions. Exemplarily, the first type of row sub-pixels spx can include Figure 7a and Figure 7b the q-th row sub-pixel G(q) shown in

[0192] In a specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, for the first scan line GA1, the second scan line GA2, and the first data connection portion 211 corresponding to the same row sub-pixel spx, the orthographic projection of the first data connection portion 211 on the substrate 010 does not overlap with the orthographic projection of the first scan connection portion 131 corresponding to the first scan line GA1 and the orthographic projection of the first scan connection portion 131 corresponding to the second scan line GA2 on the substrate 010. This can make the first data connection portion 211 and the first scan connection portion 131 be spaced apart, reducing the risk of short circuit.

[0193] In a specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, for the first scan line GA1, the second scan line GA2, and the first data connection portion 211 corresponding to the same row sub-pixel spx, the orthographic projection of the first data connection portion 211 on the substrate 010 is located between the orthographic projection of the first scan through hole 811 corresponding to the first scan line GA1 and the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 on the substrate 010. Exemplarily, for the first scan line GA1, the second scan line GA2, and the first data connection portion 211 corresponding to the same row sub-pixel spx, the line connecting the centers of the orthographic projections of the first scan through hole 811 corresponding to the first scan line GA1 and the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 on the substrate overlaps with the orthographic projection of the first data connection portion 211 on the substrate 010.

[0194] It should be noted that the center of the above orthographic projection can be the geometric center of the orthographic projection. However, in actual manufacturing processes, the shapes of the above-described structures generally have certain deviations from the regular shapes designed above. In addition, the shapes of the above-described structures actually manufactured may also have other variations from the designed shapes. Therefore, in the embodiments of the present disclosure, the center of the above orthographic projection can have a certain offset from the geometric center of the above orthographic projection.

[0195] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown, the second conductive layer 200 may further include: a plurality of second data connection portions 212; wherein, one second data transmission line 712 is directly electrically connected to at least one second data connection portion 212, and the second data connection portion 212 is electrically connected to one second data line 122 through a second data through hole 642. Exemplarily, one second data line 122 corresponds to one second data transmission line 712 and one second data connection portion 212, and one second data connection portion 212 corresponds to at least one second data through hole 642. Moreover, the second data connection portion 212 is directly electrically connected to the corresponding second data transmission line 712, and the second data connection portion 212 is electrically connected to the corresponding second data line 122 through the corresponding second data through hole 642. Exemplarily, in practical applications, one second data connection portion 212 can correspond to one, two, three or more second data through holes 642. These can be designed and determined according to the requirements of practical applications and are not limited herein.

[0196] In specific implementation, in the embodiments of the present disclosure, as Figure 7a shown in Figure 7b it is possible to alternately arrange the projections of the first data connection portion 211 and the second data connection portion 212 on a straight line extending in the first direction F1. Since the first data line 121 and the second data line 122 are alternately arranged in the first direction F1, by alternately arranging the projections of the first data connection portion 211 and the second data connection portion 212 on a straight line extending in the first direction F1, the first data connection portion 211 electrically connected to the first data line 121 and the second data connection portion 212 electrically connected to the second data line 122 can be correspondingly arranged, thereby reducing signal interference.

[0197] In specific implementation, in the embodiments of the present disclosure, as Figures 6 to 8a shown in

[0198] it is possible to make the orthographic projections of the first data connection portion 211 and the second data connection portion 212 on the substrate 010 not overlap with the orthographic projections of the first scan connection portion 131, the first scan line GA1, the second scan line GA2, and the light emission control line EM on the substrate 010, respectively. Figure 7a shown inFigure 7b As shown, the light-emitting control lines corresponding to adjacent rows of sub-pixels spx can be electrically connected. Exemplarily, the sub-pixel G(q - 1) in the (q - 1)-th row is electrically connected to the light-emitting control line corresponding to the sub-pixel in the (q - 2)-th row, the sub-pixel G(q) in the q-th row and the light-emitting control line corresponding to the sub-pixel G(q + 1) in the (q + 1)-th row are electrically connected, and the sub-pixel G(q + 2) in the (q + 2)-th row is electrically connected to the light-emitting control line corresponding to the sub-pixel in the (q + 3)-th row. The rest is the same by analogy, and will not be elaborated here.

[0199] In specific implementation, in the embodiments of the present disclosure, as Figure 7a 、 Figure 7b and Figure 8a shown, the first conductive layer 100 may further include: a plurality of first light-emitting connection portions 141 that are insulated from and spaced apart from the data line and the first data transmission line 711; wherein, the mutually electrically connected light-emitting control lines correspond to at least one first light-emitting connection portion 141. The second insulating layer may include a plurality of first light-emitting through holes 821 and a plurality of second light-emitting through holes 822. Moreover, the first end of the first light-emitting connection portion 141 is electrically connected to a corresponding light-emitting control line through at least one of the plurality of first light-emitting through holes 821, and the second end of the first light-emitting connection portion 141 is electrically connected to a corresponding other light-emitting control line through at least one of the plurality of second light-emitting through holes 822. Exemplarily, the mutually electrically connected light-emitting control lines may correspond to one first light-emitting connection portion 141, and one first light-emitting connection portion 141 corresponds to at least one first light-emitting through hole 821 and at least one second light-emitting through hole 822. And, the first end of the first light-emitting connection portion 141 is electrically connected to the corresponding light-emitting control line through the corresponding first light-emitting through hole 821, and the second end of the first light-emitting connection portion 141 is electrically connected to the corresponding other light-emitting control line through the corresponding second light-emitting through hole 822. For example, the first end of the first light-emitting connection portion 141 is electrically connected to the light-emitting control line corresponding to the sub-pixel G(q) in the q-th row through the corresponding first light-emitting through hole 821, and the second end of the first light-emitting connection portion 141 is electrically connected to the light-emitting control line corresponding to the sub-pixel G(q + 1) in the (q + 1)-th row through the corresponding second light-emitting through hole 822. Exemplarily, one first light-emitting connection portion 141 may correspond to one, two, three or more first light-emitting through holes 821. One first light-emitting connection portion 141 may correspond to one, two, three or more second light-emitting through holes 822. These can be designed and determined according to the requirements of actual applications, and are not limited here.

[0200] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8aAs shown, the third conductive layer 300 may further include a plurality of first scan transmission lines 311 and a plurality of first light-emitting transmission lines 321 located in the first non-display area A3; wherein, the first scan transmission lines 311 and the first light-emitting transmission lines 321 are arranged at intervals. Exemplarily, the orthographic projection of the first scan transmission lines 311 on the substrate 010 and the orthographic projection of the first light-emitting transmission lines 321 on the substrate 010 may be arranged at intervals. Further, the orthographic projection of the first scan transmission lines 311 on the substrate 010 and the orthographic projection of the first light-emitting transmission lines 321 on the substrate 010 may be arranged alternately. Further, the first scan transmission lines 311 and the first light-emitting transmission lines 321 may be arranged in an arc around the first non-display area A3. Of course, these can be determined according to the requirements of actual applications and are not limited herein.

[0201] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, some of the first scan lines GA1 and the second scan lines GA2 that are electrically connected to each other are directly electrically connected to a first scan transmission line 311; and some of the light-emitting control lines that are electrically connected to each other are directly electrically connected to a first light-emitting transmission line 321. In this way, the first scan lines GA1 in the third conductive layer 300 can be directly electrically connected to the first scan transmission line 311, and the light-emitting control lines can be directly electrically connected to the first light-emitting transmission line 321, so that the design difficulty of these signal lines can be reduced.

[0202] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, the fourth conductive layer 400 may further include a plurality of second scan transmission lines 411 and a plurality of second light-emitting transmission lines 421 located in the first non-display area A3; wherein, the second scan transmission lines 411 and the second light-emitting transmission lines 421 are arranged at intervals. Exemplarily, the orthographic projection of the second scan transmission lines 411 on the substrate 010 and the orthographic projection of the second light-emitting transmission lines 421 on the substrate 010 may be arranged at intervals. Further, the orthographic projection of the second scan transmission lines 411 on the substrate 010 and the orthographic projection of the second light-emitting transmission lines 421 on the substrate 010 may be arranged alternately. Further, the second scan transmission lines 411 and the second light-emitting transmission lines 421 may be arranged in an arc around the first non-display area A3. Of course, these can be determined according to the requirements of actual applications and are not limited herein.

[0203] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8aAs shown, the interlayer dielectric layer 630 may further include a plurality of third scan vias 813 and a plurality of third light-emitting vias 823. Except for the first scan lines GA1 and the second scan lines GA2 that are electrically connected to each other in the above-mentioned part, the remaining first scan lines GA1 and the second scan lines GA2 that are electrically connected to each other correspond to a second scan transmission line 411, and the first scan connection part 131 corresponding to the remaining first scan lines GA1 that are electrically connected to each other is also electrically connected to the second scan transmission line 411 through the third scan vias 813. In this way, the first scan lines GA1 corresponding to the same row of sub-pixels spx and separated by the notch area A2 can be electrically connected through the second scan transmission line 411. Exemplarily, one second scan transmission line 411 may correspond to one, two, three or more third scan vias 813. These can be determined according to the requirements of actual applications and are not limited herein.

[0204] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, except for the above-mentioned part of the light-emitting control lines that are electrically connected to each other, the remaining light-emitting control lines that are electrically connected to each other correspond to a second light-emitting transmission line 421, and the first light-emitting connection part 141 is also electrically connected to the second light-emitting transmission line 421 through the third light-emitting vias 823. In this way, the light-emitting control lines corresponding to the same row of sub-pixels spx and separated by the notch area A2 can be electrically connected through the second light-emitting transmission line 421. Exemplarily, one second light-emitting transmission line 421 may correspond to one, two, three or more third light-emitting vias 823. These can be determined according to the requirements of actual applications and are not limited herein.

[0205] Moreover, by disposing the first scan transmission line 311, the second scan transmission line 411, the first light-emitting transmission line 321, and the second light-emitting transmission line 421 in the first non-display area A3. And disposing the first scan transmission line 311 and the first light-emitting transmission line 321 in the third conductive layer 300, and disposing the second scan transmission line 411 and the second light-emitting transmission line 421 in the fourth conductive layer 400, the signal interference of the first scan transmission line 311, the second scan transmission line 411, the first light-emitting transmission line 321, and the second light-emitting transmission line 421 can be reduced.

[0206] Exemplarily, the orthographic projection of the first scan transmission line 311 on the substrate 010 may overlap with the orthographic projection of a part of the first data transmission line 711 on the substrate 010. Further, the orthographic projection of one first scan transmission line 311 on the substrate 010 may partially overlap with the orthographic projection of one first data transmission line 711 on the substrate 010. Exemplarily, the orthographic projection of the first light-emitting transmission line 321 on the substrate 010 may overlap with the orthographic projection of the remaining part of the first data transmission line 711 on the substrate 010. Further, the orthographic projection of one first light-emitting transmission line 321 on the substrate 010 may partially overlap with the orthographic projection of one of the remaining part of the first data transmission line 711 on the substrate 010. This can reduce the occupied area of the first non-display area.

[0207] Exemplarily, the orthographic projection of the second scan transmission line 411 on the substrate 010 may overlap with the orthographic projection of a part of the second data transmission line 712 on the substrate 010. Further, the orthographic projection of one second scan transmission line 411 on the substrate 010 may partially overlap with the orthographic projection of one second data transmission line 712 on the substrate 010. Exemplarily, the orthographic projection of the second light-emitting transmission line 421 on the substrate 010 may overlap with the orthographic projection of the remaining part of the second data transmission line 712 on the substrate 010. Further, the orthographic projection of one second light-emitting transmission line 421 on the substrate 010 may partially overlap with the orthographic projection of one of the remaining part of the second data transmission line 712 on the substrate 010. This can reduce the occupied area of the first non-display area.

[0208] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, all row sub-pixels spx may also include second type row sub-pixels spx; the second type row sub-pixels spx are different from the first type row sub-pixels spx. And at least one row sub-pixel spx in the second type row sub-pixels spx corresponds to at least one second data connection part 212. Exemplarily, each row sub-pixel spx in the second type row sub-pixels spx corresponds to at least one second data connection part 212. Exemplarily, each row sub-pixel spx in the second type row sub-pixels spx corresponds to one second data connection part 212. It should be noted that the second type row sub-pixels spx may be part of the rows in the display panel, and its specific position can be designed and determined according to the requirements of the actual application environment, which is not limited herein. Exemplarily, the second type row sub-pixels spx may include Figure 7b the first row sub-pixel and the third row sub-pixel in

[0209] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8aAs shown, for the first scan line GA1, the second scan line GA2, and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the orthographic projection of the second data connection portion 212 on the substrate 010 does not overlap with the orthographic projection of the first scan connection portion 131 corresponding to the first scan line GA1 and the orthographic projection of the first scan connection portion 131 corresponding to the second scan line GA2 on the substrate 010. This can enable the second data connection portion 212 and the first scan connection portion 131 to be arranged at intervals, reducing the risk of short circuit.

[0210] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, for the first scan line GA1, the second scan line GA2, and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the orthographic projection of the second data connection portion 212 on the substrate 010 is located between the orthographic projection of the first scan through hole 811 corresponding to the first scan line GA1 and the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 on the substrate 010. Exemplarily, for the first scan line GA1, the second scan line GA2, and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the connection line between the center of the orthographic projection of the second scan through hole 812 corresponding to the first scan line GA1 on the substrate 010 and the center of the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 on the substrate overlaps with the orthographic projection of the second data connection portion 212 on the substrate 010.

[0211] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, the orthographic projection of the second data connection portion 212 on the substrate 010 does not overlap with the orthographic projection of the first light-emitting connection portion 141 on the substrate 010, the orthographic projection of the first scan connection portion 131 on the substrate 010, the orthographic projection of the first scan line GA1 on the substrate 010, and the orthographic projection of the second scan line GA2 on the substrate 010.

[0212] In specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8a shown, for the light-emitting control line EM, the second scan line GA2, and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the orthographic projection of the second data connection portion 212 on the substrate 010 is located between the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 and the orthographic projection of the first light-emitting through hole 821 corresponding to the light-emitting control line on the substrate 010.

[0213] In practical applications, the transistors in sub-pixel spx generally need to be electrically connected, and the electrical connection of these transistors is related to their transistor characteristics. Therefore, if the electrical connection of the transistors is uniform, the characteristics of the transistors can be made uniform. Generally, a wet etching method is used to prepare a through-hole for electrical connection through an etching solution. However, when etching the through-hole of the sub-pixel spx at the edge of the display area A1, the through-hole outside the edge of the display area A1 does not need to be etched, resulting in different etching degrees of the through-hole of the sub-pixel spx at the edge of the display area A1 and the through-hole of the sub-pixel spx inside the display area A1, and thus causing non-uniform characteristics of the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the internal sub-pixel spx. To improve the uniformity of transistor characteristics, in specific implementation, in the embodiments of the present disclosure, the display panel has a target insulating layer located between the first conductive layer and the substrate, and a functional layer located between the target insulating layer and the substrate. At least one of the multiple sub-pixels may include: a connection through-hole; wherein the connection through-hole penetrates the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connection through-hole. And the first non-display area includes at least one auxiliary through-hole: wherein the auxiliary through-hole penetrates the target insulating layer and the auxiliary through-hole is not filled with a conductive material. And in the first non-display area, at least two of the multiple data transmission lines, multiple scan transmission lines, and multiple light-emitting transmission lines surround to form an auxiliary area, and the auxiliary through-hole is located within the auxiliary area. Further, exemplarily, the distance between two adjacent auxiliary through-holes may also be less than or approximately equal to the distance between two adjacent connection through-holes.

[0214] In practical applications, the first connection through-hole is used to realize the electrical connection of the transistors in sub-pixel spx. The electrical connection of these transistors is related to their transistor characteristics. Therefore, if the electrical connection of the transistors is uniform, the characteristics of the transistors can be made uniform. Generally, a wet etching method is used to prepare the first connection through-hole through an etching solution. However, when etching the first connection through-hole of the sub-pixel spx at the edge of the display area A1, the first connection through-hole outside the edge of the display area A1 does not need to be etched, resulting in different etching degrees of the first connection through-hole of the sub-pixel spx at the edge of the display area A1 and the first connection through-hole of the sub-pixel spx inside the display area A1, and thus causing non-uniform characteristics of the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the internal sub-pixel spx. To improve the uniformity of transistor characteristics, in specific implementation, in the embodiments of the present disclosure, the functional layer may include a semiconductor layer; the target insulating layer may include: a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer; the connection through-hole may include a first connection through-hole; the auxiliary through-hole may include a first auxiliary through-hole, and the first auxiliary through-hole penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer. Exemplarily, such as Figures 7a to 8cAs shown, the display panel may further include at least one first auxiliary through hole 911 located in the first non-display area A3. Among them, the first auxiliary through hole 911 penetrates through the first gate insulating layer 610, the second gate insulating layer 620, and the interlayer dielectric layer 630, and the first auxiliary through hole 911 is not filled with a conductive material. Moreover, in the first non-display area A3, at least two types of transmission lines among multiple data transmission lines, multiple scan transmission lines, and multiple light-emitting transmission lines may surround to form an auxiliary area FB, and the first auxiliary through hole 911 may be located within the auxiliary area FB. In this way, the first auxiliary through hole 911 can be provided outside the edge of the display area A1, that is, in the first non-display area A3, and the first auxiliary through hole 911 has the same insulating layer as that penetrated by the first connection through hole. Thus, the first auxiliary through hole 911 is etched in the first non-display area A3, and further, the etching effects of the first connection through holes etched in the display edge sub-pixels spx and the internal sub-pixels spx can be made uniform, improving the uniformity of the characteristics of the transistors.

[0215] In specific implementation, an insulating material may be filled in the first auxiliary through hole 911. For example, the material of the interlayer insulating layer 640 may be filled in the first auxiliary through hole 911. In this way, when preparing the interlayer insulating layer 640, the first auxiliary through hole 911 can be directly filled, thereby improving the flatness of the interlayer insulating layer 640.

[0216] In specific implementation, which specific transmission lines are used to surround and form the auxiliary area FB can be designed and determined according to actual application requirements, and no limitation is made here.

[0217] It should be noted that since the semiconductor layer in the first non-display area A3 is not etched away when patterning the semiconductor layer, the semiconductor layer remains in the first non-display area A3, as Figure 8b shown Figure 8c As shown. This makes the depth of the first auxiliary through hole 911 in the direction perpendicular to the plane of the substrate substantially the same as the depth of the first connection through hole in the direction perpendicular to the plane of the substrate. In this way, the etching liquid can etch the first auxiliary through hole 911 and the first connection through hole to a substantially the same extent, further improving the uniformity of the characteristics of the transistors.

[0218] Exemplarily, in specific implementation, in the embodiments of the present disclosure, multiple first auxiliary through holes 911 may be provided in the first non-display area A3. For example, the distribution density of the first auxiliary through holes 911 may be made substantially equal to the distribution density of the first connection through holes. In this way, the etching effects of the first connection through holes etched in the display edge sub-pixels spx and the internal sub-pixels spx can be made uniform, improving the uniformity of the characteristics of the transistors.

[0219] Exemplarily, in specific implementation, in the embodiments of the present disclosure, the distribution density of the first auxiliary vias 911 can also be made smaller than that of the first connection vias. Since other traces or connection parts are also provided in the first non-display area A3, reducing the distribution density of the first auxiliary vias 911 can reduce the occupied area of the entire set of first auxiliary vias 911, and reduce the occupied area of the first non-display area A3. Moreover, by providing the first auxiliary vias 911, the etching effects of the first connection vias etched in the display edge sub-pixels spx and the first connection vias etched in the internal sub-pixels spx can be made uniform, improving the uniformity of the transistor characteristics.

[0220] It should be noted that the distribution density of the first auxiliary vias 911 can be the number of the first auxiliary vias 911 per unit area. The distribution density of the first connection vias can be the number of the first connection vias per unit area. In practical applications, the distribution densities of the first auxiliary vias 911 and the first connection vias can be designed and determined according to the requirements of the actual application environment, and are not limited herein.

[0221] Exemplarily, in specific implementation, in the embodiments of the present disclosure, the distance between two adjacent first auxiliary vias can be made approximately equal to the distance between two adjacent first connection vias. In this way, there is no need to design the distance between the first auxiliary vias additionally, and the distance between the first connection vias can be used for design. Of course, the distance between two adjacent first auxiliary vias can also be made smaller than the distance between two adjacent first connection vias. In this way, the first auxiliary vias can be arranged more compactly, reducing the occupied area of the first non-display area.

[0222] Exemplarily, in specific implementation, in the embodiments of the present disclosure, as Figures 7a to 8c shown, the orthographic projection of the first auxiliary vias 911 on the substrate 010 does not overlap with the orthographic projections of the semiconductor layer, the first conductive layer 100, the third conductive layer 300, and the fourth conductive layer 400 on the substrate 010. In this way, the influence on the conductive layer and the semiconductor layer during the etching of the first auxiliary vias 911 can be reduced.

[0223] In practical applications, the second connection via is also used to implement the electrical connection of the transistors in the sub-pixel spx. The electrical connection of these transistors is related to their transistor characteristics. Therefore, if the electrical connection of the transistors is uniform, the characteristics of the transistors can be made uniform. Generally, a wet etching method is used to prepare the second connection via with an etching solution. However, when etching the second connection via of the sub-pixel spx at the edge of the display area A1, the second connection via does not need to be etched outside the edge of the display area A1, resulting in different etching degrees of the second connection via of the sub-pixel spx at the edge of the display area A1 and the second connection via of the sub-pixel spx inside the display area A1. This leads to non-uniform characteristics of the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the internal sub-pixel spx. To improve the uniformity of the transistor characteristics, in a specific implementation, in the embodiments of the present disclosure, the functional layer includes a third conductive layer; the target insulating layer includes: a second gate insulating layer and an interlayer dielectric layer; the connection via includes a second connection via; the auxiliary via includes a second auxiliary via, and the second auxiliary via penetrates through the second gate insulating layer and the interlayer dielectric layer. Exemplarily, as Figure 7b and Figure 8c shown, the display panel may further include at least one second auxiliary via 912 located in the first non-display area A3; wherein, the second auxiliary via 912 penetrates through the second gate insulating layer 620 and the interlayer dielectric layer 630, and the second auxiliary via 912 is not filled with a conductive material. Also, the second auxiliary via 912 may also be located within the auxiliary area FB. In a specific implementation, an insulating material may be filled in the second auxiliary via 912. For example, the material of the interlayer insulating layer 640 may be filled in the second auxiliary via 912. This can directly fill the second auxiliary via 912 when preparing the interlayer insulating layer 640, thereby improving the flatness of the interlayer insulating layer 640.

[0224] Exemplarily, in a specific implementation, in the embodiments of the present disclosure, a plurality of second auxiliary vias 912 may be provided in the first non-display area A3. For example, the distribution density of the second auxiliary vias 912 may be made approximately equal to the distribution density of the second connection vias. This can make the etching effects of the second connection vias etched in the sub-pixel spx at the display edge and the second connection vias etched in the internal sub-pixel spx uniform, and improve the uniformity of the transistor characteristics.

[0225] Exemplarily, in specific implementation, in the embodiments of the present disclosure, the distribution density of the second auxiliary vias 912 can also be made less than that of the second connection vias. Since other traces or connection portions are also provided in the first non-display area A3, reducing the distribution density of the second auxiliary vias 912 can reduce the occupied area of the entire set of second auxiliary vias 912 and thus reduce the occupied area of the first non-display area A3. Moreover, by providing the second auxiliary vias 912, the etching effect of the second connection vias etched in the display edge sub-pixels spx can be made uniform with that of the first connection vias etched in the internal sub-pixels spx, improving the uniformity of the transistor characteristics.

[0226] It should be noted that the distribution density of the second auxiliary vias 912 can be the number of second auxiliary vias 912 per unit area. The distribution density of the second connection vias can be the number of second connection vias per unit area. In practical applications, the distribution densities of the second auxiliary vias 912 and the second connection vias can be designed and determined according to the requirements of the actual application environment, and are not limited herein.

[0227] It should be noted that since the third conductive layer 300 in the first non-display area A3 is etched away when patterning the third conductive layer 300, there will be no third conductive layer 300 remaining in the first non-display area A3, as Figure 8c shown. This makes the depth of the second auxiliary vias 912 in the direction perpendicular to the plane of the substrate be greater than the depth of the second connection vias in the direction perpendicular to the plane of the substrate.

[0228] Exemplarily, in specific implementation, in the embodiments of the present disclosure, the distance between two adjacent second auxiliary vias can be made approximately equal to the distance between two adjacent second connection vias. In this way, there is no need to design the distance between the second auxiliary vias additionally, and the distance between the second connection vias can be used for design. Of course, the distance between two adjacent second auxiliary vias can also be made less than the distance between two adjacent second connection vias. In this way, the second auxiliary vias can be arranged more compactly, reducing the occupied area of the second non-display area.

[0229] Exemplarily, in specific implementation, in the embodiments of the present disclosure, as Figure 7b shown, the orthographic projection of the second auxiliary vias 912 on the substrate 010 does not overlap with the orthographic projections of the first conductive layer 100, the third conductive layer 300, and the fourth conductive layer 400 on the substrate 010. This can reduce the influence on the conductive layer and the semiconductor layer when etching the second auxiliary vias 912.

[0230] In practical applications, the third connection via is also used to implement the electrical connection of transistors in the sub-pixel spx. The electrical connection of these transistors is related to their transistor characteristics. Therefore, if the electrical connection of the transistors is uniform, the characteristics of the transistors can be made uniform. Generally, a wet etching method is used to prepare the third connection via with an etching solution. However, when etching the third connection via of the sub-pixel spx at the edge of the display area A1, the third connection via outside the edge of the display area A1 does not need to be etched, resulting in different etching degrees of the third connection via of the sub-pixel spx at the edge of the display area A1 and the third connection via of the sub-pixel spx inside the display area A1. This leads to non-uniform characteristics of the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the internal sub-pixel spx. To improve the uniformity of transistor characteristics, in a specific implementation, in the embodiments of the present disclosure, the functional layer includes a fourth conductive layer; the target insulating layer includes: an interlayer dielectric layer; the connection via includes a third connection via; the auxiliary via includes a third auxiliary via, and the third auxiliary via penetrates the interlayer dielectric layer. Exemplarily, as Figure 7b as Figure 8c shown, the display panel may further include at least one third auxiliary via 913 located in the first non-display area A3; the third auxiliary via 913 penetrates the interlayer dielectric layer 630, and the third auxiliary via 913 is not filled with a conductive material. Also, the third auxiliary via 913 may also be located within the auxiliary area FB. In a specific implementation, an insulating material may be filled in the third auxiliary via 913. For example, the material of the interlayer insulating layer 640 may be filled in the third auxiliary via 913. This can directly fill the third auxiliary via 913 when preparing the interlayer insulating layer 640, thereby improving the flatness of the interlayer insulating layer 640.

[0231] Exemplarily, in a specific implementation, in the embodiments of the present disclosure, a plurality of third auxiliary vias 913 may be provided in the first non-display area A3. For example, the distribution density of the third auxiliary vias 913 may be made substantially equal to the distribution density of the third connection vias. This can make the etching effects of the etched third connection vias in the sub-pixels spx at the display edge and the etched third connection vias in the internal sub-pixels spx uniform, improving the uniformity of transistor characteristics.

[0232] Exemplarily, in specific implementation, in the embodiments of the present disclosure, the distribution density of the third auxiliary vias 913 may also be made less than the distribution density of the third connection vias. Since other traces or connection portions are also provided in the first non-display area A3, reducing the distribution density of the third auxiliary vias 913 can reduce the occupied area of the entire set of the third auxiliary vias 913 and reduce the occupied area of the first non-display area A3. Moreover, by providing the third auxiliary vias 913, the etching effects of the third connection vias etched in the display edge sub-pixels spx and the first connection vias etched in the internal sub-pixels spx can be made uniform, improving the uniformity of the transistor characteristics.

[0233] It should be noted that the distribution density of the third auxiliary vias 913 may be the number of the third auxiliary vias 913 per unit area. The distribution density of the third connection vias may be the number of the third connection vias per unit area. In practical applications, the distribution densities of the third auxiliary vias 913 and the third connection vias may be designed and determined according to the requirements of the actual application environment, and are not limited herein.

[0234] It should be noted that since the fourth conductive layer 400 in the first non-display area A3 is etched away when patterning the fourth conductive layer 400, there will be no fourth conductive layer 400 remaining in the first non-display area A3, as Figure 8c shown. This makes the depth of the third auxiliary vias 913 in the direction perpendicular to the plane of the substrate base greater than the depth of the third connection vias in the direction perpendicular to the plane of the substrate base.

[0235] Exemplarily, in specific implementation, in the embodiments of the present disclosure, the distance between two adjacent third auxiliary vias may be made approximately equal to the distance between two adjacent third connection vias. In this way, there is no need to design the distance between the third auxiliary vias additionally, and the distance between the third connection vias can be used for design. Of course, the distance between two adjacent third auxiliary vias may also be made less than the distance between two adjacent third connection vias. In this way, the third auxiliary vias can be arranged more compactly, reducing the occupied area of the first non-display area.

[0236] Exemplarily, in specific implementation, in the embodiments of the present disclosure, as Figure 7b shown, the orthographic projection of the third auxiliary vias 913 on the substrate base 010 does not overlap with the orthographic projections of the first conductive layer 100 and the fourth conductive layer 400 on the substrate base 010. This can reduce the influence on the conductive layer and the semiconductor layer when etching the third auxiliary vias 913.

[0237] It should be noted that Figure 8aAs shown, GA1-G(q) represents the first scan line corresponding to the sub-pixels in the q-th row. GA2-G(q) represents the second scan line corresponding to the sub-pixels in the q-th row. GA1-G(q+1) represents the first scan line corresponding to the sub-pixels in the (q+1)-th row. EM-G(q) represents the emission control line corresponding to the sub-pixels in the q-th row. EM-G(q+1) represents the emission control line corresponding to the sub-pixels in the (q+1)-th row. The same applies hereinafter and will not be elaborated further.

[0238] It should be noted that due to process conditions or other factors, the same or equal in the above-mentioned features may not be exactly the same or equal, and there may be some deviations. Therefore, as long as the same or equal relationship between the above-mentioned features generally meets the above conditions, it belongs to the protection scope of the present disclosure. For example, the above-mentioned sameness can be the sameness allowed within the error tolerance range.

[0239] The embodiments of the present disclosure also provide some other display panels, such as Figures 9a to 10c As shown, it is a deformation of some implementation manners in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the same parts will not be elaborated here.

[0240] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10a As shown, for the first scan line GA1 corresponding to the sub-pixels spx in the same row, the first data connection portion 211, the first data line 121 and the first data transmission line 711 electrically connected by using the first data connection portion 211, the orthographic projection of the first data connection portion 211 on the substrate 010 and the orthographic projection of the first scan line GA1 on the substrate 010 have an overlapping area, and the orthographic projections of the first data line 121 and the first data transmission line 711 on the substrate 010 and the orthographic projection of the first scan line GA1 on the substrate 010 do not overlap. This can avoid forming a facing area between the first scan line GA1 and the first data line 121. And, since the first data connection portion 211 is located in the second conductive layer 200, the distance between the first scan line GA1 and the first data connection portion 211 can be made larger, so that the coupling capacitance between the first scan line GA1 and the first data connection portion 211 is reduced less, thereby reducing signal interference and improving the display effect.

[0241] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10aAs shown, for the first scan line GA1 and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the orthographic projection of the edge region of the first data connection portion 211 on the substrate 010 and the orthographic projection of the first scan line GA1 on the substrate 010 have an overlapping region. Alternatively, for the first scan line GA1 and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the orthographic projection of the central region of the first data connection portion 211 on the substrate 010 and the orthographic projection of the first scan line GA1 on the substrate 010 have an overlapping region.

[0242] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10a shown, some of the row sub-pixels spx in the first type of row sub-pixels spx correspond to two first data connection portions. For example, Figure 9a and Figure 9b the (q + 2)-th row sub-pixel G(q + 2) in may correspond to two first data connection portions: 211a and 211b. Among them, for the first scan line GA1, the second scan line GA2, and the two first data connection portions corresponding to the same row of sub-pixels spx, it is possible to make the orthographic projections of these two first data connection portions 211a and 211b on the substrate 010 and the orthographic projection of the first scan line GA1 on the substrate 010 have an overlapping region, and make the orthographic projections of these two first data connection portions 211a and 211b on the substrate 010 and the orthographic projection of the second scan line GA2 on the substrate 010 non-overlapping.

[0243] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10a shown, for the first scan line GA1, the second scan line GA2, and the two first data connection portions a and 211b corresponding to the same row of sub-pixels spx, among them, the orthographic projection of the first of these two first data connection portions 211a on the substrate 010 is close to the orthographic projection of the first scan through hole 811 corresponding to the first scan line GA1 on the substrate 010. Exemplarily, compared with the second first data connection portion 211b of these two first data connection portions, the first first data connection portion 211a can make the orthographic projection of the first first data connection portion 211a on the substrate 010 close to the orthographic projection of the first scan through hole 811 corresponding to the first scan line GA1 on the substrate 010.

[0244] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10aAs shown, for the first scan line GA1, the second scan line GA2, and the two first data connection parts corresponding to the same row of sub-pixels spx, the second first data connection part 211b of the two first data connection parts is close to the positive projection of the second scan through hole 812 corresponding to the second scan line GA2 on the substrate 010. Exemplarily, compared with the first first data connection part 211a, the second first data connection part 211b of the two first data connection parts can make the positive projection of the second first data connection part 211b on the substrate 010 close to the positive projection of the second scan through hole 812 corresponding to the second scan line GA2 on the substrate 010.

[0245] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10a shown, for the first scan line GA1 corresponding to the same row of sub-pixels spx, the second data connection part 212, and the second data line 122 and the second data transmission line 712 electrically connected by the second data connection part 212, the positive projection of the second data connection part 212 on the substrate 010 and the positive projection of the first scan line GA1 on the substrate 010 have an overlapping area, and the positive projections of the second data line 122 and the second data transmission line 712 on the substrate 010 and the positive projection of the first scan line GA1 on the substrate 010 do not overlap.

[0246] In specific implementation, in the embodiments of the present disclosure. As Figures 9a to 10a shown, for a row of sub-pixels corresponding to two first data connection parts, the row of sub-pixels also corresponds to a second data connection part 212. For the first scan line GA1 corresponding to the same row of sub-pixels, the second data connection part 212, and the second data line 122 and the second data transmission line 712 electrically connected by the second data connection part 212, the positive projection of the second data connection part 212 on the substrate 010 and the positive projection of the first scan line GA1 on the substrate 010 have an overlapping area, and the positive projections of the second data line 122 and the second data transmission line 712 on the substrate 010 and the positive projection of the first scan line GA1 on the substrate 010 do not overlap.

[0247] It should be noted that, as Figure 10b shown in Figure 10c the display panel is also provided with a first auxiliary through hole 911, a second auxiliary through hole 912, and a third auxiliary through hole 913. Moreover, the setting manners of the first auxiliary through hole 911, the second auxiliary through hole 912, and the third auxiliary through hole 913 can refer to the above embodiments, which will not be elaborated here.

[0248] The embodiments of the present disclosure also provide some other display panels, such as Figure 11 shown in Figure 12As shown, it is a modification of some of the embodiments in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0249] In specific implementation, in the embodiments of the present disclosure. As Figure 11 and Figure 12 shown, the fourth conductive layer 400 may further include a plurality of third scan transmission lines 413 located in the first non-display area A3. And, the interlayer dielectric layer 630 may further include a plurality of fourth scan vias 814; the first scan line GA1 and the second scan line GA2 that are electrically connected to each other correspond to one third scan transmission line 413, and the first scan connection portion 131 is also electrically connected to the third scan transmission line 413 through the fourth scan via 814. The third conductive layer 300 may further include a third light-emitting transmission line 423 located in the first non-display area A3; among them, the light-emitting control lines that are electrically connected to each other are directly electrically connected to one third light-emitting transmission line 423. In this way, the third light-emitting transmission line 423 can be provided in the third conductive layer 300, and the third scan transmission line 413 can be provided in the fourth conductive layer 400.

[0250] Exemplarily, in order to reduce signal interference, the orthographic projection of the third scan transmission line 413 on the substrate 010 does not overlap with the orthographic projection of the third light-emitting transmission line 423 on the substrate 010. Further, the orthographic projection of the third scan transmission line 413 on the substrate 010 and the orthographic projection of the third light-emitting transmission line 423 on the substrate 010 are spaced apart.

[0251] Further, in order to reduce signal interference, the orthographic projection of the third scan transmission line 413 on the substrate 010 and the orthographic projection of the second data transmission line 712 on the substrate 010 may have an overlapping area. Further, the orthographic projection of the third scan transmission line 413 on the substrate 010 and the orthographic projection of the second data transmission line 712 on the substrate 010 may partially overlap. Since the third scan transmission layer is located in the fourth conductive layer 400 and the second data transmission line 712 is located in the second conductive layer 200, this can not only reduce the coupling capacitance between the third scan transmission line 413 and the second data transmission line 712, but also reduce the occupied area of the first non-display area A3.

[0252] Further, in order to reduce signal interference, the orthographic projection of the third light-emitting transmission line 423 on the substrate 010 and the orthographic projection of the first data transmission line 711 on the substrate 010 may have an overlapping area. Further, the orthographic projection of the third light-emitting transmission line 423 on the substrate 010 and the orthographic projection of the first data transmission line 711 on the substrate 010 may partially overlap. Since the third light-emitting transmission line 423 is located in the third conductive layer 300 and the first data transmission line 711 is located in the first conductive layer 100, this can not only reduce the coupling capacitance between the third light-emitting transmission layer and the first data transmission line 711, but also reduce the occupied area of the first non-display area A3.

[0253] It should be noted that the setting manners of the first auxiliary through hole 911, the second auxiliary through hole 912, and the third auxiliary through hole 913 can be referred to the above embodiments, and will not be elaborated herein.

[0254] The embodiments of the present disclosure also provide some display panels, such as Figure 13 and Figure 14 As shown, some of the embodiments in the above embodiments are deformed. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated herein.

[0255] In specific implementation, in the embodiments of the present disclosure. As Figure 13 and Figure 14 As shown, the fourth conductive layer 400 may further include a plurality of fourth light-emitting transmission lines 424 located in the first non-display area A3; the interlayer dielectric layer 630 may further include a plurality of fourth light-emitting through holes 824; a mutually electrically connected light control line EM corresponds to one fourth light-emitting transmission line 424. And, the first light-emitting connection portion 141 is also electrically connected to the fourth light-emitting transmission line 424 through the fourth light-emitting through hole 824; the third conductive layer 300 may further include a fourth scan transmission line 414 located in the first non-display area A3; wherein, the mutually electrically connected first scan line GA1 and the second scan line GA2 are directly electrically connected to one fourth scan transmission line 414. In this way, the fourth scan transmission line 414 can be provided in the third conductive layer 300, and the fourth light-emitting transmission line 424 can be provided in the fourth conductive layer 400.

[0256] Exemplarily, in order to reduce signal interference, as Figure 13 and Figure 14 As shown, the orthographic projection of the fourth scan transmission line 414 on the substrate 010 and the orthographic projection of the fourth light-emitting transmission line 424 on the substrate 010 may not overlap. Exemplarily, the orthographic projection of the fourth scan transmission line 414 on the substrate 010 and the orthographic projection of the fourth light-emitting transmission line 424 on the substrate 010 may be arranged at intervals.

[0257] Further, in order to reduce signal interference, the orthographic projection of the fourth scan transmission line 414 on the substrate 010 may have an overlapping area with the orthographic projection of the first data transmission line 711 on the substrate 010. Further, the orthographic projection of the fourth scan transmission line 414 on the substrate 010 may partially overlap with the orthographic projection of the first data transmission line 711 on the substrate 010. Since the fourth scan transmission layer is located in the third conductive layer 300 and the first data transmission line 711 is located in the first conductive layer 100, this can not only reduce the coupling capacitance between the fourth scan transmission layer and the first data transmission line 711, but also reduce the occupied area of the first non-display area A3.

[0258] Further, in order to reduce signal interference, the orthographic projection of the fourth light-emitting transmission line 424 on the substrate 010 may have an overlapping area with the orthographic projection of the second data transmission line 712 on the substrate 010. Further, the orthographic projection of the fourth light-emitting transmission line 424 on the substrate 010 may partially overlap with the orthographic projection of the second data transmission line 712 on the substrate 010. Since the fourth light-emitting transmission line 424 is located in the fourth conductive layer 400 and the second data transmission line 712 is located in the second conductive layer 200, this can not only increase the coupling capacitance between the fourth light-emitting transmission layer and the second data transmission line 712, but also reduce the occupied area of the first non-display area A3.

[0259] It should be noted that the setting manners of the first auxiliary via 911, the second auxiliary via 912, and the third auxiliary via 913 can be referred to the above embodiments and will not be elaborated here.

[0260] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure. The principle of the display device for solving problems is similar to that of the foregoing display panel. Therefore, the implementation of the display device can refer to the implementation of the foregoing display panel, and the repeated parts will not be elaborated here.

[0261] In specific implementation, in the embodiments of the present disclosure, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated here, nor should it be regarded as a limitation to the present disclosure.

[0262] The display panel and the display device provided by the embodiments of the present disclosure can electrically connect the data lines and the first data transmission lines in the first conductive layer to each other through the first data connection part in the second conductive layer by arranging the first data connection part in the second conductive layer. In this way, not only can the data lines corresponding to the same column of sub-pixels and separated by the notch be electrically connected, but also the interference of the first data connection part on the third conductive layer and the fourth conductive layer can be reduced, thereby improving the signal stability and the display effect.

[0263] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0264] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, Comprising: A substrate, including a notch region, a display region, and a first non-display region, the first non-display region being located between the notch region and the display region; A first conductive layer, located on the substrate; A target insulating layer, located between the first conductive layer and the substrate; A functional layer, located between the target insulating layer and the substrate; The display region includes a plurality of sub-pixels, a plurality of data lines, a plurality of scan lines, and a plurality of light emission control lines; wherein, at least one of the plurality of sub-pixels includes: a connection through-hole; wherein, the connection through-hole penetrates the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connection through-hole; The first non-display region includes: at least one auxiliary through-hole, a plurality of data transmission lines, a plurality of scan transmission lines, and a plurality of light emission transmission lines: wherein, at least one of the plurality of data lines is electrically connected to at least one of the plurality of data transmission lines, at least one of the plurality of scan lines is electrically connected to at least one of the plurality of scan transmission lines, and at least one of the plurality of light emission control lines is electrically connected to at least one of the plurality of light emission transmission lines; In the first non-display region, at least two of the plurality of data transmission lines, the plurality of scan transmission lines, and the plurality of light emission transmission lines surround to form an auxiliary region, the auxiliary through-hole is located in the auxiliary region, and the auxiliary through-hole penetrates the target insulating layer and the auxiliary through-hole is not filled with a conductive material; Wherein, the display panel includes: A semiconductor layer, located between the substrate and the first conductive layer; A first gate insulating layer, located between the semiconductor layer and the first conductive layer; A third conductive layer, located between the first gate insulating layer and the first conductive layer; A second gate insulating layer, located between the third conductive layer and the first conductive layer; A fourth conductive layer, located between the second gate insulating layer and the first conductive layer; An interlayer dielectric layer, located between the fourth conductive layer and the first conductive layer; At least one of the plurality of sub-pixels includes: a first connection through-hole, a second connection through-hole, and a third connection through-hole; wherein, the first connection through-hole penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer; the second connection through-hole penetrates the second gate insulating layer and the interlayer dielectric layer; the third connection through-hole penetrates the interlayer dielectric layer; The first conductive layer is electrically connected to the semiconductor layer through the first connection through-hole; The first conductive layer is electrically connected to the third conductive layer through the second connection through-hole; The first conductive layer is electrically connected to the fourth conductive layer through the third connection through-hole; The auxiliary through-hole is filled with an insulating material.

2. The display panel according to claim 1, wherein, The display panel further includes: An interlayer insulating layer, located on a side of the first conductive layer facing away from the substrate; The auxiliary through-hole is filled with the material of the interlayer insulating layer.

3. The display panel according to claim 2, wherein, The functional layer includes the semiconductor layer; The target insulating layer includes: the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer; The connection through-hole includes the first connection through-hole; The auxiliary through hole includes a first auxiliary through hole that penetrates through the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer, and the material filled in the first auxiliary through hole penetrates through the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer.

4. The display panel according to claim 3, wherein, The distribution density of the first auxiliary through hole is less than or approximately equal to the distribution density of the first connection through hole.

5. The display panel according to claim 3 or 4, wherein, The orthographic projection of the first auxiliary through hole on the substrate does not overlap with the orthographic projections of the semiconductor layer, the third conductive layer, the fourth conductive layer, and the first conductive layer on the substrate.

6. The display panel according to claim 2, wherein, The functional layer includes the third conductive layer; The target insulating layer includes: the second gate insulating layer and the interlayer dielectric layer; The connection through hole includes the second connection through hole; The auxiliary through hole includes a second auxiliary through hole that penetrates through the second gate insulating layer and the interlayer dielectric layer, and the material filled in the second auxiliary through hole penetrates through the second gate insulating layer and the interlayer dielectric layer.

7. The display panel according to claim 6, wherein, The distribution density of the second auxiliary through hole is less than or approximately equal to the distribution density of the second connection through hole.

8. The display panel according to claim 6 or 7, wherein The orthographic projection of the second auxiliary through hole on the substrate does not overlap with the orthographic projections of the third conductive layer, the fourth conductive layer, and the first conductive layer on the substrate.

9. The display panel according to claim 2, wherein The functional layer includes the fourth conductive layer; The target insulating layer includes: the interlayer dielectric layer; The connection through hole includes the third connection through hole; The auxiliary through hole includes a third auxiliary through hole that penetrates through the interlayer dielectric layer, and the material filled in the third auxiliary through hole penetrates through the interlayer dielectric layer.

10. The display panel according to claim 9, wherein The distribution density of the third auxiliary through hole is less than or approximately equal to the distribution density of the third connection through hole.

11. The display panel according to claim 9 or 10, wherein The orthographic projection of the third auxiliary through hole on the substrate does not overlap with the orthographic projections of the fourth conductive layer and the first conductive layer on the substrate.

12. The display panel according to claim 1, wherein The multiple data transmission lines include multiple first data transmission lines; the first conductive layer includes the multiple data lines and the multiple first data transmission lines; The interlayer insulating layer has multiple first data through holes; The display panel further includes: A second conductive layer located on a side of the interlayer insulating layer away from the substrate and including multiple first data connection portions; At least one of the multiple first data connection portions is electrically connected to at least one of the multiple data lines and at least one of the multiple first data transmission lines through the first data through holes respectively.

13. The display panel according to claim 12, wherein The multiple data transmission lines include multiple second data transmission lines; The second conductive layer further includes: the multiple second data transmission lines; the multiple second data transmission lines are arranged at intervals from the first data connection portions; The interlayer insulating layer further includes: multiple second data through holes; The multiple data lines include multiple first data lines and multiple second data lines; wherein, one of the first data lines is electrically connected to one of the first data transmission lines through the first data connection portion; one of the second data lines is electrically connected to one of the second data transmission lines through the second data through holes.

14. The display panel according to claim 13, wherein The third conductive layer includes the plurality of scan lines and the plurality of light emission control lines; wherein, the plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines; The display area further includes a plurality of sub-pixels; wherein, one row of the sub-pixels corresponds to one of the first scan lines and one of the second scan lines; the second scan line corresponding to the first row of sub-pixels in each adjacent two rows of sub-pixels is electrically connected to the first scan line corresponding to the second row of sub-pixels; One row of the sub-pixels corresponds to one of the light emission control lines; and the light emission control lines corresponding to adjacent two rows of sub-pixels are electrically connected.

15. The display panel according to claim 14, wherein The first conductive layer further includes: a plurality of first scan connection portions that are insulated from and spaced apart from the data lines and the first data transmission lines; wherein, the second scan line corresponding to the (q - 1)-th row of sub-pixels is electrically connected to the first scan line corresponding to the q-th row of sub-pixels through at least one of the first scan connection portions; q is an integer; The second insulating layer includes a plurality of first scan through-holes and a plurality of second scan through-holes; The first end of the first scan connection portion is electrically connected to the corresponding first scan line through at least one of the plurality of first scan through-holes, and the second end of the first scan connection portion is electrically connected to the corresponding second scan line through at least one of the plurality of second scan through-holes.

16. The display panel according to claim 15, wherein All rows of the sub-pixels include first type rows of sub-pixels; at least one row of sub-pixels in the first type rows of sub-pixels corresponds to at least one of the first data connection portions; For the first scan line, the second scan line, and the first data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the first data connection portion on the substrate does not overlap with the orthographic projections of the first scan connection portion corresponding to the first scan line and the first scan connection portion corresponding to the second scan line on the substrate.

17. The display panel according to claim 16, wherein For the first scan line, the second scan line, and the first data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the first data connection portion on the substrate is located between the orthographic projections of the first scan through-hole corresponding to the first scan line and the second scan through-hole corresponding to the second scan line on the substrate.

18. The display panel according to claim 17, wherein For the first scan line, the second scan line, and the first data connection portion corresponding to the same row of sub-pixels, the line connecting the centers of the orthographic projections of the first scan through-hole corresponding to the first scan line and the second scan through-hole corresponding to the second scan line on the substrate overlaps with the orthographic projection of the first data connection portion on the substrate.

19. The display panel according to any one of claims 16 - 18, wherein For the first scan line and the first data connection portion corresponding to the same row of sub-pixels, and the first data line and the first data transmission line electrically connected by using the first data connection portion, the orthographic projection of the first data connection portion on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate, and the orthographic projections of the first data line and the first data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

20. The display panel according to claim 19, wherein For the first scan line and the first data connection portion corresponding to the same row of sub-pixels, an overlapping region exists between the orthographic projection of the edge region of the first data connection portion on the substrate and the orthographic projection of the first scan line on the substrate.

21. The display panel according to claim 19, wherein, For the first scan line and the first data connection portion corresponding to the same row of sub-pixels, an overlapping region exists between the orthographic projection of the central region of the first data connection portion on the substrate and the orthographic projection of the first scan line on the substrate.

22. The display panel according to claim 16, wherein, Some row sub-pixels in the first type of row sub-pixels correspond to two first data connection portions. For the first scan line, the second scan line, and the two first data connection portions corresponding to the same row of sub-pixels, an overlapping region exists between the orthographic projection of the two first data connection portions on the substrate and the orthographic projection of the first scan line on the substrate, and the orthographic projection of the two first data connection portions on the substrate does not overlap with the orthographic projection of the second scan line on the substrate.

23. The display panel according to claim 22, wherein, For the first scan line, the second scan line, and the two first data connection portions corresponding to the same row of sub-pixels The orthographic projection of the first of the two first data connection portions on the substrate is close to the orthographic projection of the first scan through hole corresponding to the first scan line on the substrate; and / or The orthographic projection of the second of the two first data connection portions on the substrate is close to the orthographic projection of the second scan through hole corresponding to the second scan line on the substrate.

24. The display panel according to claim 16, wherein, The second conductive layer further includes: a plurality of second data connection portions; wherein, one second data transmission line is directly electrically connected to at least one of the second data connection portions, and the second data connection portion is electrically connected to one second data line through the second data through hole.

25. The display panel according to claim 24, wherein, Along the first direction, the first data line and the second data line are alternately arranged; The orthographic projections of the first data connection portion and the second data connection portion on a straight line extending along the first direction are alternately arranged.

26. The display panel according to claim 25, wherein, All the row sub-pixels include a second type of row sub-pixels; the second type of row sub-pixels is different from the first type of row sub-pixels; At least one row sub-pixel in the second type of row sub-pixels corresponds to at least one of the second data connection portions; For the first scan line and the second data connection portion corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected by the second data connection portion, an overlapping region exists between the orthographic projection of the second data connection portion on the substrate and the orthographic projection of the first scan line on the substrate, and the orthographic projections of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

27. The display panel according to claim 26, wherein, For a row of sub-pixels corresponding to two first data connection portions, the row of sub-pixels also corresponds to one second data connection portion; For the first scan line, the second data connection part corresponding to the same row of sub-pixels, the second data line and the second data transmission line electrically connected by using the second data connection part, the orthographic projection of the second data connection part on the substrate has an overlapping area with the orthographic projection of the first scan line on the substrate, and the orthographic projections of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

28. The display panel according to claim 14, wherein, The first conductive layer further includes: a plurality of first light-emitting connection parts that are insulated from and spaced apart from the data line and the first data transmission line; wherein, the mutually electrically connected light-emitting control lines correspond to at least one of the first light-emitting connection parts; The second insulating layer includes a plurality of first light-emitting through holes and a plurality of second light-emitting through holes; The first end of the first light-emitting connection part is electrically connected to a corresponding one of the light-emitting control lines through at least one of the plurality of first light-emitting through holes, and the second end of the first light-emitting connection part is electrically connected to another corresponding one of the light-emitting control lines through at least one of the plurality of second light-emitting through holes.

29. The display panel according to claim 28, wherein, The plurality of scan transmission lines include: a plurality of first scan transmission lines and a plurality of second scan transmission lines, and the light-emitting transmission lines include a plurality of first light-emitting transmission lines and a plurality of second light-emitting transmission lines; The third conductive layer further includes the plurality of first scan transmission lines and the plurality of first light-emitting transmission lines located in the first non-display area; wherein, the first scan transmission lines and the first light-emitting transmission lines are spaced apart; Part of the mutually electrically connected first scan lines and second scan lines are directly electrically connected to a corresponding one of the first scan transmission lines; and part of the mutually electrically connected light-emitting control lines are directly electrically connected to a corresponding one of the first light-emitting transmission lines; The fourth conductive layer further includes the plurality of second scan transmission lines and the plurality of second light-emitting transmission lines located in the first non-display area; wherein, the second scan transmission lines and the second light-emitting transmission lines are spaced apart; The interlayer dielectric layer further includes a plurality of third scan through holes and a plurality of third light-emitting through holes; The remaining mutually electrically connected first scan lines and second scan lines correspond to a corresponding one of the second scan transmission lines, and the first scan connection part is further electrically connected to the second scan transmission line through the third scan through hole; The remaining mutually electrically connected light-emitting control lines correspond to a corresponding one of the second light-emitting transmission lines, and the first light-emitting connection part is further electrically connected to the second light-emitting transmission line through the third light-emitting through hole.

30. The display panel according to claim 28, wherein, The plurality of scan transmission lines include: a plurality of third scan transmission lines, and the light-emitting transmission lines include a plurality of third light-emitting transmission lines; The fourth conductive layer includes a plurality of third scan transmission lines located in the first non-display area; The interlayer dielectric layer includes a plurality of fourth scan through holes; The mutually electrically connected first scan lines and second scan lines correspond to a corresponding one of the third scan transmission lines, and the first scan connection part is further electrically connected to the third scan transmission line through the fourth scan through hole; The third conductive layer further includes a third light-emitting transmission line located in the first non-display area; among them, the mutually electrically connected light-emitting control lines are directly electrically connected to one of the third light-emitting transmission lines.

31. The display panel according to claim 28, wherein, The multiple scanning transmission lines include: multiple fourth scanning transmission lines, and the light-emitting transmission lines include multiple fourth light-emitting transmission lines; The fourth conductive layer includes multiple fourth light-emitting transmission lines located in the first non-display area; The interlayer dielectric layer includes multiple fourth light-emitting vias; The mutually electrically connected light-emitting control lines correspond to one of the fourth light-emitting transmission lines, and the first light-emitting connection portion is further electrically connected to the fourth light-emitting transmission line through the fourth light-emitting via; The third conductive layer further includes a fourth scanning transmission line located in the first non-display area; among them, the mutually electrically connected first scanning line and the second scanning line are directly electrically connected to one of the fourth scanning transmission lines.

32. The display panel according to any one of claims 28 - 31, wherein, For the light-emitting control line, the second scanning line, and the second data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the second data connection portion on the substrate is located between the orthographic projection of the second scanning via corresponding to the second scanning line and the orthographic projection of the first light-emitting via corresponding to the light-emitting control line on the substrate.

33. A display device, wherein, Comprising a display panel according to any one of claims 1-32.

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