A multi-path clock detection, switching and reporting device

Abstract

The application provides a multi-path clock detection, switching and reporting device, comprising a clock detection module and a clock switching and reporting module. The application uses a low-frequency clock and a detected clock to jointly drive a detection circuit. The detected clock is used as a driving clock of a counter. If the counter does not reach a target value within a certain period of time, it is judged that the clock stops. This method does not need to introduce an additional high-frequency clock. The detection circuit can still work in a low-power mode. The core detection counter is driven by the detected clock. The detection time is shortened with the increase of the frequency of the detected clock. The clock switching module can automatically select a standby clock with the closest frequency to the detected clock to replace the detected clock, so that the influence on the chip is minimized. The clock convergence frequency is considered. The customer can configure the frequency increase limit value, and the flexibility is improved.

Description

Technical Field

[0001] This invention relates to an in-chip clock device, and more particularly to a multi-channel clock detection, switching and reporting device. Background Technology

[0002] As chip internal clock designs become increasingly complex and the demands on clock signal quality rise, the risk of clock stoppage also increases. Clock stoppage can lead to serious consequences, such as chip restarts or even complete malfunction. Therefore, detecting clock stoppages, switching to a valid clock, and reporting the system clock switch status are crucial for the normal operation of chips. Simultaneously, short clock stop detection times, flexible configuration, glitches-free switching, and accurate reporting information are also becoming increasingly important goals for designers.

[0003] Existing clock stop detection methods use a low-frequency clock as the driving clock for the detection circuit. The clock being detected is used as a signal, and changes in its high and low levels are detected to determine if the clock has stopped. This detection circuit uses a low-frequency clock, resulting in low power consumption, making it suitable for low-power modes of chips. However, the detection time is relatively long, typically on the order of milliseconds, to determine if the clock has stopped. Some methods, in pursuit of faster detection, use a high-frequency clock to drive the detection circuit. While this significantly shortens the detection time, high-frequency clocks increase power consumption and cannot be enabled in some low-power modes where high-frequency clocks need to be disabled. Other methods, upon detecting a clock stop, simply report it to the system and wait for the stopped clock to restart, without performing any clock switching operations. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to provide a multi-channel clock detection, switching and reporting device to address the shortcomings of the prior art.

[0005] To address the aforementioned technical problems, this invention discloses a multi-channel clock detection, switching, and reporting device, comprising: a clock detection module and a clock switching and reporting module; wherein, the clock detection module includes: a detection cycle control module and a clock counting module; and the clock switching and reporting module includes: a clock switching control signal generation module and a clock switching module.

[0006] The input of the detection cycle control module is connected to a normally open clock signal clk_freerun; the clear signal clr output of the detection cycle control module is connected to one input of the clock counting module; the other input of the clock counting module is connected to the clock signal to be detected, Clk_det_source, and the alternative clock signal; one of the two outputs of the clock counting module is connected to the clock active clk_active input of the clock switching control signal generation module, and the other is connected to the clock cycle count clk_cnt_value input of the clock switching control signal generation module; one output of the clock switching control signal generation module is connected to the clock switching module, and the other two outputs output the clock selection signal clk_sel and the frequency difference signal Freq_gap, respectively; the inputs of the clock switching module are also connected to the clock signals to be detected; the output of the clock switching module is the selected clock signal Clk_det from the clock signals to be detected.

[0007] The device has one or more clock counting modules. For each additional alternative clock, one more clock counting module is added. The number of clock switching reporting modules is determined by the clock signals to be detected and switched as needed.

[0008] The detection cycle control module uses a normally open clock signal clk_freerun to generate the detection cycle by counting. After the detection cycle ends, a clear signal clr is generated to reset the counter of the clock counting module and update the frequency difference signal Freq_gap.

[0009] The clock counting module includes a counter. The counter is driven by the clock signal to be detected. When the count reaches a preset value, a clock active signal clk_active is generated to indicate whether the clock being detected is toggling normally. The counter continues to count until a clear signal clr is received from the detection cycle control module. At this time, the current count value clk_cnt_value is temporarily stored and the counter is cleared to zero. If the counter has not reached the preset value when the clear signal is active, it is determined that the clock has stopped oscillating and the counter is cleared to zero.

[0010] The clock switching control signal generation module is enabled when it receives an invalid clock valid signal clk_active from the clock counting module. After being enabled, it first determines the clock valid signals clk_active in other clock counting modules. Among the other valid clock counting modules, it compares the count value clk_cnt_value with the count value recorded in the previous clock detection cycle. The clock signal input by the clock counting module with the smaller difference is determined to be the clock signal with the closest frequency. The corresponding clock selection signal is generated based on the clock signal with the closest frequency and sent to the clock switching module.

[0011] The clock switching module, upon receiving the clock selection signal, seamlessly switches to the clock signal corresponding to the clock selection signal and outputs it.

[0012] The clock detection module is used for clock signal detection, and its workflow is as follows:

[0013] Step A1: Within one detection cycle, if the counter counts to the preset value and the clock valid signal clk_active outputs a valid level, then the clock switching control signal generation module and the clock switching module will not work, and the clock signal clk_det_source to be detected will be maintained to drive the subsequent logic; if the counter does not count to the preset value, the clock valid signal clk_active will output an invalid level, and the clock switching control signal generation module and the clock switching module will be turned on.

[0014] In step A2, the clock counting module continues to accumulate the count. When the clear signal clr generated by the detection cycle control module becomes valid, it checks the clock validity signal clk_active. If the clock validity signal clk_active is valid, the count value clk_cnt_val of the clock counting module is updated. If the clock validity signal clk_active is invalid, the count value clk_cnt_val is not updated in this clock cycle, and the count value clk_cnt_val temporarily stored from the previous detection cycle is output to the clock switching control signal generation module. At the same time, the clear signal clr resets the counter in the clock counting module to zero, and the counting of the next cycle begins again.

[0015] The clock switching reporting module operates as follows:

[0016] Step B1: After the clock valid signal clk_active in the clock counting module connected to the clock signal to be detected becomes invalid, the switching and reporting process is started. At the same time, the clock valid signal clk_active is output to the register for the processor to query, or an interrupt is triggered to report that the detected clock has stopped oscillating. If the clock valid signal clk_active is valid, no operation is performed.

[0017] Step B2: Determine the clock validity signal clk_active in the clock counting module connected to the alternative clock signal. If the clock validity signal clk_active is valid, the alternative clock signal is determined to be normal and can be used to replace the clock signal under test that has stopped oscillating. If the clock validity signal clk_active is invalid, the alternative clock signal is determined to be stopped oscillating and cannot be used.

[0018] Step B3: Calculate the difference (clk_gap) between the count values ​​clk_cnt_val in the clock counting modules connected to each candidate clock signal and the clock signal being tested. The candidate clock signal with the smallest clk_gap is identified as the one with the closest frequency to the clock signal being tested. Then, compare the clk_cnt_val corresponding to the clock signal being tested and the candidate clock signals. If the count value corresponding to the clock signal being tested is greater than the count value corresponding to the candidate clock signal, it indicates that the frequency will decrease after replacement, and replacement is deemed acceptable. Otherwise, it indicates that the frequency will increase after replacement. By comparing the difference clk_gap with a user-preset threshold, determine whether to perform replacement. If replacement is not performed, an interrupt notification is sent to the processor, indicating that no clock signal switching has been performed. If replacement is performed, the control signal clk_sel is set to the value representing this clock signal. Simultaneously, the difference clk_gap and the control signal clk_sel are output to a register for storage.

[0019] Step B4: After the control signal clk_sel is input to the clock switching module, a glitch-free switching is performed; at this point, the clock signal switching of the entire device is completed.

[0020] In step B3, the difference clk_gap and the control signal clk_sel are output to the register for storage. The processor uses this information to query the information of the replaced clock signal and to evaluate the impact of clock oscillation stoppage and switching.

[0021] The glitch-free switching mentioned in step B4, i.e., the glitch-free switching in the clock switching module, is performed as follows:

[0022] First, the control signal clk_sel is converted into Gray code, then synchronized to the selected alternative clock signal, and output using the falling edge of the selected clock signal. Finally, this synchronized signal is used to switch the clock signal to be detected to the selected alternative clock signal, thus completing the glitch-free switching of the clock signal.

[0023] Beneficial effects:

[0024] The clock detection module in this invention uses the detected clock and a low-frequency clock, eliminating the need for a high-frequency clock, thus significantly reducing power consumption. It can also function normally in low-power modes where the high-frequency clock is disabled. The clock counter is driven by the detected clock; therefore, the faster the detected clock, the shorter the detection time. For high-frequency clocks, the detection time can be greatly shortened. Furthermore, the target value and detection period of the clock counter module are user-configurable. Users can flexibly configure them according to their needs, as long as the detection period is longer than the time it takes for the counter to reach the target value. For example, if the user prioritizes rapid detection, both parameters can be configured to their minimum values; if the detected clock experiences a permissible brief pause, the two parameters can be appropriately increased based on the duration of this pause to ensure the accuracy of the detection indication signal.

[0025] The clock switching module can automatically select a backup clock with the closest frequency to the detected clock for replacement, minimizing the impact on the chip. It also considers the clock convergence frequency issue, allowing customers to configure extreme frequency increases, thus increasing flexibility. This invention can report clock oscillation stop information, replacement clock selection information, and replacement clock frequency difference information for the processor to query, enabling users to evaluate and correct errors caused by clock oscillation stoppage. Attached Figure Description

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0027] Figure 1 This is a schematic diagram illustrating the overall principle of the present invention.

[0028] Figure 2 This is a schematic diagram illustrating the workflow of the clock detection module of the present invention.

[0029] Figure 3 This is a schematic diagram of the workflow of the clock switching reporting module of the present invention. Detailed Implementation

[0030] This invention utilizes both a low-frequency clock and the detected clock to jointly drive the detection circuit. The detected clock is no longer detected as a regular signal for whether it toggles, but rather as the driving clock for a counter. If the counter fails to reach a target value within a certain time period, the clock is considered to have stopped. This method does not require an additional high-frequency clock and can still operate in low-power mode. Furthermore, the core detection counter is driven by the detected clock, and the detection time shortens as the frequency of the detected clock increases. The target value of the detection counter used to determine clock stop is user-configurable, allowing for flexible application in various scenarios. For example, if the detection circuit is used for clock detection after a glitch-free switching circuit, depending on the circuit design, there will be varying durations of clock-free states during the clock switching process. This invention allows for flexible configuration of a corresponding counter target value, ensuring that the brief clock-free states during clock switching are not incorrectly identified as clock stop.

[0031] This invention can simultaneously detect multiple clock channels. When a clock channel is detected to have stopped oscillating, the system can select the closest clock channel from the remaining valid clocks for switching. Simultaneously, the approximate range of frequency difference between the switched and previous clock channels is reported to the system. This facilitates system evaluation and processing of current tasks, minimizing the impact of clock oscillation interruptions.

[0032] The overall schematic diagram of this invention is as follows: Figure 1 As shown:

[0033] This multi-channel clock detection, switching and reporting device mainly includes a detection cycle control module, a clock counting module, a clock switching control signal generation module, and a clock switching module. Figure 1 The diagram shown illustrates the module block diagram required to detect the clk_detect_source clock. If clk1_source also needs to be detected, then... Figure 1 Based on this, a clock switching control signal generation module and a clock switching module for clk1_source need to be added. Similarly, for multi-channel clock detection, each channel needs to use... Figure 1 The device can be used, but the detection cycle control module and the clock counting module do not need to be reused.

[0034] The detection cycle control module mainly uses a normally open clock to generate the detection cycle by counting. When the cycle ends, a clear signal is generated.

[0035] The clock counting module primarily uses the detected clock to drive a counter. When it counts to a user-configured value, it generates a clock valid signal, and the counter continues counting until it receives a clear signal from the detection cycle control module. At this point, the current count value is temporarily stored, and the counter is reset to zero. If the counter has not counted to the configured value when the clear signal is valid, it is determined that the clock has stopped oscillating, and the clear signal resets the counter to zero.

[0036] The detection cycle control module and the clock counting module are collectively referred to as the clock detection module. The workflow is as follows: Figure 2 As shown:

[0037] After the detection circuit is enabled, the detection cycle control module and the clock counting module start counting.

[0038] Step 1: If the detection counter reaches the configured value within a detection cycle, the clock active signal (clk_active) is enabled. The clock switching control signal generation module and the clock switching module will not be enabled after the detection, and clk_det_source will be maintained to drive the subsequent logic. If the detection counter does not reach the configured value, the clk_active signal outputs an invalid level, and the clock switching control signal generation module and the clock switching module are enabled.

[0039] Step 2: The clock counting module continues to accumulate the count. When the clear (clr) signal generated by the detection cycle control module becomes valid, it checks whether clk_active is valid. If valid, the count value (clk_cnt_val) of the clock counting module is updated. If invalid, the count value of the previous detection cycle is retained, and the temporarily stored count value is output to the clock switching control signal generation module. At the same time, the clr signal clears the clock counting module to zero, and counting continues for the next cycle.

[0040] After the clock detection is completed, the clock switching and reporting process begins.

[0041] The clock switching control signal generation module is enabled when it receives an invalid clk_active signal from the clock being detected. Once enabled, it first checks the clk_active signals of other candidate clocks. Among the valid candidate clocks, it compares the count value (clk_cnt_val) from the clock counting module with the count value of the clock being detected recorded in the previous clock detection cycle. The clock with the smaller difference is considered to have the closest frequency, and a clock selection signal is output to the clock switching module.

[0042] The clock switching module is mainly responsible for receiving the clock selection signal, switching to the alternative clock without glitches, and outputting the clock.

[0043] The clock switching control signal generation module and the clock switching module are collectively referred to as the clock switching reporting module. The workflow is as follows: Figure 3 As shown:

[0044] Step 1: When the clk_active value of the clock being monitored becomes invalid, the system will switch and report the process. Simultaneously, clk_active will be output to a register for the processor to query, or an interrupt will be triggered to report that the monitored clock has stopped oscillating. If clk_active is valid, no action will be taken.

[0045] Step 2: Check the clk_active signal of the alternative clock. When this signal is valid, it means that the alternative clock is normal and can replace the clock under test that has stopped oscillating. If this signal is invalid, it means that the alternative clock has also stopped oscillating and cannot be used.

[0046] Step 3: Calculate the clk_cnt_val difference between each candidate clock and the clock under test. The candidate clock with the smallest difference is the one whose frequency is closest to the clock under test. Then compare the clock under test with its count value (clk_cnt_val). If the count value of the clock under test is greater than that of the candidate clock, it means the frequency will decrease after replacement, and replacement is possible. If the count value of the clock under test is less than that of the candidate clock, it means the frequency will increase after replacement. Since the frequency increase may not meet the clock frequency convergence condition, an additional judgment is added: the user configures an increase limit value. If the increase value is less than the user-configured value, replacement can be performed; if it is greater than the user-configured value, clock switching is stopped, and an interrupt notification is sent to the processor, and clock switching is not performed. If it is finally determined that the candidate clock can be used to replace the clock under test that has stopped oscillating, the clk_sel control signal is set to the value representing this clock. At the same time, the difference value clk_gap and the clk_sel signal are output to the register for storage so that the processor can query the information of the replaced clk, and the software can evaluate the impact of clock oscillation stopping and switching.

[0047] Step 4: After clk_sel is input to the clock switching module, since it is a multi-bit signal, it is first converted to Gray code, then synchronized to the selected alternative clock, and emitted with the falling edge of the clock. Finally, this synchronized signal is used to switch the detected clock to the selected alternative clock, thus achieving a glitch-free clock switching. At this point, the clock that actually drives the logic is switched to the selected alternative clock.

[0048] The key points of this invention are as follows:

[0049] 1. This multi-channel clock detection, switching, and reporting device mainly includes a detection cycle control module, a clock counting module, a clock switching control signal generation module, and a clock switching module.

[0050] 2. This device can simultaneously detect multiple clocks that require oscillation detection and switching, and can automatically select the clock with the smallest frequency difference for replacement, minimizing the impact of clock oscillation stoppage.

[0051] 3. This device can use various clocks used in the chip system as backup clocks for each other, ensuring that the logic driven by any clock will not stop working if any clock stops oscillating.

[0052] 4. This device can store clock oscillation stop information, replacement clock selection information, and replacement clock frequency difference information for the processor to query, allowing users to evaluate and correct errors caused by clock oscillation stop.

[0053] 5. In the detection cycle control module, the cycle is configurable by the user. The longer the detection cycle, the longer the detection time, but the more accurate the calculation of the frequency difference between the clocks before and after the switch. Users can adjust it according to their actual needs.

[0054] 6. In the clock counting module, a valid clock signal is generated when a certain value is reached. This value is configurable by the user and can be applied to different scenarios. For example, some clocks being detected have passed through a glitch-free clock switching circuit. This circuit will briefly stop during switching. In this case, appropriately lengthening the detection period of the timer counter will prevent the erroneous generation of a clock stop indication signal.

[0055] 7. In addition to the detected clock and the backup clock, the entire device only requires one additional always-on low-frequency clock, which can greatly reduce power consumption and can be applied to low-power mode.

[0056] 8. During a clock detection cycle, the clock timing module can be used to count the values ​​of different backup clocks. Subtracting the count value of the backup clock from the count value of the clock being detected will yield the difference between the two. The smaller the difference, the closer the frequency of the backup clock is to that of the clock being detected. Replacing the clock being detected with the backup clock will cause the least impact.

[0057] 9. If the selected backup clock frequency is higher than the clock being monitored, it may exceed the clock convergence frequency, causing errors in the logic circuits subsequently driven by it. Therefore, the user can configure a register to specify the limit value for increasing the clock frequency. If this limit value is exceeded, the clock will not switch, and the system will report a switching failure.

[0058] 10. The valid clock signal of the monitored clock, if indicating that the clock has stopped oscillating, can trigger an interrupt or be stored in a register for the processor to query. The selection signal for the alternative clock, as well as the difference in counts between the replacement clock and the monitored clock, can also be stored in a register for the processor to query. When the processor receives a clock stop interrupt, it then determines which clock replaced the stopped clock, calculates the clock frequency difference before and after the switch using the count difference, and can assess the impact of this clock stop / switch on system tasks, allowing for timely adjustments and corrections.

[0059] 11. To avoid glitches when switching clocks, the clock selection signal needs to be synchronized with the replacement clock and output on the falling edge of the clock.

[0060] 12. Since there are multiple alternative clocks, the clock selection is a multi-bit signal. When performing synchronization, it needs to be converted to Gray code first to prevent intermediate states from occurring during synchronization, which could cause incorrect clock switching.

[0061] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's content regarding a multi-channel clock detection, switching, and reporting device, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0062] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MUU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0063] This invention provides a concept and method for a multi-channel clock detection, switching, and reporting device. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A multi-channel clock detection device, characterized in that, include: The system includes a clock detection module and a clock switching reporting module; wherein the clock detection module includes a detection cycle control module and a clock counting module; and the clock switching reporting module includes a clock switching control signal generation module and a clock switching module. The input of the detection cycle control module is connected to a normally open clock signal clk_freerun; the clear signal clr output of the detection cycle control module is connected to one input of the clock counting module; the other input of the clock counting module is connected to the clock signal to be detected, Clk_det_source, and the alternative clock signal; one of the two outputs of the clock counting module is connected to the clock valid input Clk_det_active in the clock switching control signal generation module, and the other is connected to the clock cycle count input Clk_det_cnt_value in the clock switching control signal generation module; one output of the clock switching control signal generation module is connected to the clock switching module, and the other two outputs output the clock selection signal Clk_sel and the frequency difference signal Freq_gap, respectively; the inputs of the clock switching module are also connected to the clock signals to be detected; the output of the clock switching module is the selected clock signal Clk_det from the clock signals to be detected. The clock counting module includes a counter. The counter is driven by the clock signal to be detected. When it counts to a preset value, a clock active signal clk_active is generated to indicate whether the detected clock is toggling normally. The counter continues counting until it receives a clear signal clr from the detection cycle control module. At this point, the current count value clk_cnt_value is temporarily stored, and the counter is cleared. If the counter has not counted to the preset value when the clear signal is active, the clock is determined to have stopped oscillating, and the counter is cleared. The clock switching control signal generation module is enabled when it receives an invalid clock valid signal clk_active from the clock counting module. After being enabled, it first determines the clock valid signals clk_active in other clock counting modules. Among the other valid clock counting modules, it compares the count value clk_cnt_value with the count value recorded in the previous clock detection cycle. The clock signal input by the clock counting module with the smaller difference is determined to be the clock signal with the closest frequency. The corresponding clock selection signal is generated based on the clock signal with the closest frequency and sent to the clock switching module.

2. The multi-channel clock detection device according to claim 1, characterized in that, The device has one or more clock counting modules. For each additional alternative clock, one more clock counting module is added. The number of clock switching reporting modules is determined by the clock signals to be detected and switched as needed.

3. The multi-channel clock detection device according to claim 2, characterized in that, The detection cycle control module uses a normally open clock signal clk_freerun to generate the detection cycle by counting. After the detection cycle ends, a clear signal clr is generated to reset the counter of the clock counting module and update the frequency difference signal Freq_gap.

4. The multi-channel clock detection device according to claim 3, characterized in that, The clock switching module, upon receiving the clock selection signal, seamlessly switches to the clock signal corresponding to the clock selection signal and outputs it.

5. A multi-channel clock detection device according to claim 4, characterized in that, The clock detection module is used for clock signal detection, and its workflow is as follows: Step A1: Within one detection cycle, if the counter counts to the preset value and the clock valid signal clk_active outputs a valid level, then the clock switching control signal generation module and the clock switching module will not work, and the clock signal to be detected Clk_det_source will be maintained to drive the subsequent logic; if the counter does not count to the preset value, the clock valid signal clk_active will output an invalid level, and the clock switching control signal generation module and the clock switching module will be enabled. In step A2, the clock counting module continues to accumulate the count. When the clear signal clr generated by the detection cycle control module becomes valid, it checks the clock validity signal clk_active. If the clock validity signal clk_active is valid, the count value clk_cnt_val of the clock counting module is updated. If the clock validity signal clk_active is invalid, the count value clk_cnt_val is not updated in this clock cycle, and the count value clk_cnt_val temporarily stored from the previous detection cycle is output to the clock switching control signal generation module. At the same time, the clear signal clr resets the counter in the clock counting module to zero, and the counting of the next cycle begins again.

6. The multi-channel clock detection device according to claim 5, characterized in that, The clock switching reporting module operates as follows: Step B1: After the clock valid signal clk_active in the clock counting module connected to the clock signal to be detected becomes invalid, the switching and reporting process is started. At the same time, the clock valid signal clk_active is output to the register for the processor to query, or an interrupt is triggered to report that the detected clock has stopped oscillating. If the clock valid signal clk_active is valid, no operation is performed. Step B2: Determine the clock validity signal clk_active in the clock counting module connected to the alternative clock signal. If the clock validity signal clk_active is valid, then the alternative clock signal is determined to be normal and can be used to replace the clock signal to be detected that has stopped oscillating. If the clock active signal clk_active is invalid, then the alternative clock signal is also determined to be stopped and cannot be used; Step B3: Calculate the difference Freq_gap between the count values ​​clk_cnt_val in the clock counting modules connected to each candidate clock signal and the clock signal being tested. The candidate clock signal with the smallest Freq_gap is identified as the one with the closest frequency to the clock signal being tested. Then, compare the count values ​​clk_cnt_val corresponding to the clock signal being tested and those of the candidate clock signals. If the count value of the clock signal being tested is greater than that of the candidate clock signal, it indicates that the frequency will decrease after replacement, and replacement is deemed acceptable. Otherwise, it indicates that the frequency will increase after replacement. By comparing the difference Freq_gap with a user-preset threshold, determine whether to perform replacement. If replacement is not performed, an interrupt notification is sent to the processor, indicating that no clock signal switching has been performed. If replacement is performed, the control signal Clk_sel is set to the value representing this clock signal. Simultaneously, the difference Freq_gap and the control signal Clk_sel are output to a register for storage. Step B4: After the control signal clk_sel is input to the clock switching module, a glitch-free switching process is performed. This completes the clock signal switching for the entire device.

7. A multi-channel clock detection device according to claim 6, characterized in that, In step B3, the difference value Freq_gap and the control signal Clk_sel are output to a register for storage. The processor uses this information to query the information of the replaced clock signal and to evaluate the impact of clock oscillation stoppage and switching.

8. A multi-channel clock detection device according to claim 7, characterized in that, The glitch-free switching mentioned in step B4, i.e., the glitch-free switching in the clock switching module, is performed as follows: First, the control signal Clk_sel is converted into Gray code, then synchronized to the selected alternative clock signal, and output using the falling edge of the selected clock signal. Finally, this synchronized signal is used to switch the clock signal to be detected to the selected alternative clock signal, thus completing the glitch-free switching of the clock signal.

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