Method for hardware implementation of ntt based on folded transform r2-mdc architecture

By improving the R2-MDC architecture and adopting folding transformation and Barrett modular reduction algorithm, the data read and write control logic is simplified, achieving efficient NTT hardware computing. This solves the problems of excessive resource consumption and low computing efficiency in existing technologies, and improves hardware performance and resource utilization.

CN115756387BActive Publication Date: 2026-06-26HANGZHOU DIANZI UNIV
View PDF 2 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HANGZHOU DIANZI UNIV
Filing Date
2022-09-20
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

The existing NTT hardware implementation has complex control logic and excessive resource consumption, making it difficult to optimize circuit area and computing efficiency under high computing power requirements.

Method used

The R2-MDC architecture based on folding transformation is adopted to simplify the data read and write control logic. By improving the design of BFU unit and multiplexer, resource consumption is reduced by 50%. The Barrett modular reduction algorithm is used to optimize the modular multiplication circuit. Combined with the alternating operation of odd and even cycles and mode configuration, three operation modes, NTT, INTT and CWM, are realized.

Benefits of technology

It improves computing performance, achieves 100% resource utilization, reduces hardware resource consumption by 50%, increases computing speed, reduces circuit area, and adapts to various computing needs.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN115756387B_ABST
    Figure CN115756387B_ABST
Patent Text Reader

Abstract

The application discloses an NTT hardware implementation method based on a folding transformation R2-MDC architecture, improves the existing R2-MDC architecture, simplifies data read-write control logic, reduces 50% of resource consumption, and efficiently realizes polynomial multiplication operation on a ring. Specifically, each BFU unit contains a module such as a module addition, a module subtraction and a module multiplication, one-level BFU unit is used to realize two-layer butterfly operation, input of the circuit is distinguished according to odd and even clock, and alternately performed, each BFU unit inputs odd-layer butterfly operation data in an odd period and inputs even-layer butterfly operation data in an even period. And through cooperation of a mode register and a multiplexer, three operations of NTT, INTT and CWM are dynamically realized, and the generality is obviously improved. And a Barrett modular reduction algorithm is used to optimize the module multiplication circuit, and the operation speed is improved.
Need to check novelty before this filing date? Find Prior Art