IFF pulse signal detection method based on FPGA

Abstract

The present invention discloses an FPGA-based IFF pulse signal detection method, comprising the following steps: acquiring a baseband envelope signal; if a rising edge of a pulse of the baseband envelope signal is detected, calculating a pulse detection threshold based on baseband envelope data in a first sliding window and baseband envelope data in a second sliding window; counting the number of sampling points at which the baseband envelope signal exceeds the pulse detection threshold; if the number of sampling points exceeds a preset threshold, repeatedly acquiring the baseband envelope signal until the number of pulse detections reaches a preset number; measuring pulse parameters; and caching the intermediate frequency waveform corresponding to the pulse; performing corresponding signal detection on the pulse based on the pulse width among the pulse parameters; arranging the detection results of each pulse in chronological order according to the arrival time of the corresponding pulse parameter, combining the detection results with the corresponding intermediate frequency waveform into a data frame, and outputting the data. The present invention reduces FPGA resource consumption and improves signal detection speed.

Description

Technical Field

[0001] The present invention relates to the field of information recognition, and in particular to an IFF pulse signal detection method based on FPGA. Background Art

[0002] IFF signal (Chinese name is Identification Friend or Foe signal) is a signal for identification and information exchange between aircraft and ground stations, mainly used in electronic reconnaissance, electronic countermeasures and other fields. Traditional IFF pulse signal detection solutions such as Figure 1 As shown, the intermediate frequency signal is input into the FPGA, and after digital down-conversion, envelope detection and pulse detection are performed, and parameter measurement is performed, and the corresponding intermediate frequency data is stored at the same time; then, this data is sent to the DSP for sorting, identification, demodulation and decoding, and finally combined for output.

[0003] The main feature of DSP is its ability to easily handle complex logical operations. However, its inherent serial operation mode means that when the data rate is too high, the overall operation speed cannot meet the real-time requirements and the ever-increasing signal processing speed requirements. While using FPGA for sorting, recognition, demodulation, and decoding can increase the operation speed, it also has the problem of high resource consumption and complexity and difficulty in implementation. Summary of the Invention

[0004] The technical problem to be solved by the present invention is: in response to the technical problems existing in the prior art, the present invention provides an IFF pulse signal detection method based on FPGA, which can reduce the resource consumption of FPGA and improve the processing speed of signal detection.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0006] An FPGA-based IFF pulse signal detection method includes the following steps:

[0007] Acquire a baseband envelope signal, and if a rising edge of a pulse of the baseband envelope signal is detected, calculate a pulse detection threshold based on the baseband envelope data of the first sliding window and the baseband envelope data in the second sliding window;

[0008] Counting the number of sampling points at which the baseband envelope signal is greater than a pulse detection threshold, detecting a pulse if the number of sampling points is greater than a preset threshold, calculating the parameters of the pulse, and caching the intermediate frequency waveform corresponding to the pulse;

[0009] According to the pulse width in the pulse parameters, the pulse is subjected to corresponding signal detection, and the detection result of each pulse is arranged in chronological order according to the arrival time of the corresponding pulse parameter, combined with the corresponding intermediate frequency waveform into a data frame and output.

[0010] Furthermore, the length of the first sliding window is 90, the length of the second sliding window is 1024, and the pulse detection threshold is calculated as follows:

[0011] thd = avg_1024+avg_90-0.5*std_1024

[0012] Wherein, avg_90 is the mean of the baseband envelope data in the first sliding window, avg_1024 is the mean of the baseband envelope data in the second sliding window, and std_1024 is the standard deviation of the baseband envelope data in the second sliding window.

[0013] Furthermore, after obtaining the baseband envelope signal, the method also includes a step of detecting the rising edge of the pulse, specifically including: respectively calculating the mean of the baseband envelope data and the delay value of the mean in the first sliding window; if the comparison result of the size of the mean and the corresponding delay value meets the first condition, the rising edge of the pulse is detected.

[0014] Furthermore, the first condition is that the size of the mean and the corresponding delay value meet the pulse rising edge characteristics for 50 consecutive times, and the pulse rising edge characteristics are: (x(n) - x(n-90))>0.5* x(n) and x(n)>3* x(n-90), where x(n) is the mean of the baseband envelope data, and x(n-90) is the delay value of the mean.

[0015] Furthermore, measuring the pulse parameters specifically includes: sampling the real-time GPS time by using a clock cognate to the ADC sampling clock to obtain the arrival time of the pulse.

[0016] Furthermore, performing corresponding signal detection on the pulse according to the pulse width in the pulse parameter specifically includes:

[0017] The comparator determines whether the pulse width of the current pulse is within the target pulse width range. If so, the current pulse is cached in the target cache area corresponding to each target signal to prepare for signal detection. Otherwise, the current pulse is discarded and the corresponding intermediate frequency waveform is deleted.

[0018] Furthermore, the specific steps of caching the current pulse in the target buffer area corresponding to each target signal in preparation for signal detection include: obtaining a corresponding number of continuous pulses at the head of the target buffer area corresponding to the current target signal, judging whether the time interval and pulse width error between these pulses are within the range of the current target signal, and if so, demodulating the first pulse therein to obtain the corresponding detection result, and shifting all pulses in the target buffer area forward by one position, and caching the current pulse to the tail of the target buffer area.

[0019] Furthermore, when the target signal is a Mark X signal, the corresponding number is two, when the target signal is an S-mode signal, the corresponding number is four, and when the target signal is a 4-mode signal, the corresponding number is three.

[0020] Furthermore, when the target signal is an S-mode signal, a mask instruction is generated before demodulating the first pulse therein to obtain the corresponding detection result, and a release instruction is generated after demodulating the first pulse therein to obtain the corresponding detection result; when the target signal is a Mark X signal or a 4-mode signal, an instruction is received before obtaining a corresponding number of consecutive pulses at the head of the target buffer area, and if it is a mask instruction, waiting is performed until a release instruction is received.

[0021] Furthermore, when the target signal is a 4-mode signal, before demodulating the first pulse therein to obtain the corresponding detection result, an amplitude consistency test is performed on the corresponding number of continuous pulses in the head. If the consistency does not meet the requirements, the preset threshold is modified, and the number of sampling points where the baseband envelope signal is greater than the pulse detection threshold is returned to be counted, all pulses in the target buffer area are discarded, and the corresponding intermediate frequency waveform is deleted until the consistency meets the requirements.

[0022] Compared with the prior art, the advantages of the present invention are:

[0023] The present invention adopts pipeline processing, which can reduce the block RAM usage and reduce the resource requirements for FPGA;

[0024] The present invention adopts two sliding windows of different lengths to update the pulse detection threshold, which has the advantages of good real-time performance and low resource occupation;

[0025] The present invention uses a series connection method to compare the baseband envelope amplitude and the corresponding pulse detection threshold multiple times, so as to obtain a more accurate pulse parameter measurement result.

[0026] The present invention adopts a shift register method to cache and discard pulse signals generated in real time, thereby realizing high-speed processing of pulse information. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a flow chart of traditional IFF pulse signal detection.

[0028] Figure 2 This is a flow chart of IFF pulse signal detection according to an embodiment of the present invention.

[0029] Figure 3 A schematic diagram of calculating a pulse detection threshold according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the scope of protection of the present invention is not limited thereby.

[0031] To use only the FPGA for IFF pulse signal detection and reduce FPGA resource consumption, we first considered down-converting the input ADC data to baseband; secondly, synchronizing the baseband data with the delayed original IF data; thirdly, performing pulse detection threshold calculation and pulse detection on the baseband data, while simultaneously buffering the pulse information and the associated original IF data; thirdly, performing signal frame detection based on the pulse information, while simultaneously buffering the signal frame information and the associated pulse information; and finally, sequentially searching for the relevant pulse information and the associated original IF data based on the signal frame information, thus forming a framed data stream. This approach provides a clear connection between each layer and the next, facilitating expansion or reduction in scale; and achieves strong real-time performance. The shift register method used to process pulse information is simple in structure and easy to implement.

[0032] like Figure 2 As shown, this embodiment considers implementing the above concept through the following steps:

[0033] 1. First, calculate the first-level pulse detection threshold for the baseband envelope data after down-conversion. Update the pulse detection threshold in real time through the pulse discovery method to adapt to the changing external input. Currently, it is usually necessary to calculate the first-level detection threshold by counting a long period of baseband envelope data (for example, 10,000 sampling points). This not only makes resources very tight, but also affects the calculation speed. In this embodiment, the method for calculating the pulse detection threshold is as follows: Figure 3 As shown, two sliding windows are used: one with a length of 90, called the first sliding window, and the other with a length of 1024, called the second sliding window. These lengths offer the advantages of good real-time performance and low resource usage within the FPGA, conforming to the pulse timing characteristics of the input signal and performing well in actual testing. First, a rough estimate of the rising edge is made. The mean value x(n) of the baseband envelope data within the first sliding window is delayed by 90 sampling points using a first-in, first-out buffer. The delay value of this mean value is x(n-90). Then, by calculating x(n) – x(n-90), if the pulse rising edge characteristics are met 50 times in a row, the pulse rising edge is detected, and the calculation of the first-level pulse detection threshold can begin.

[0034] The aforementioned rising edge characteristic conditions are: (x(n) - x(n-90))>0.5* x(n) and x(n)>3* x(n-90);

[0035] The calculation formula for the first-level pulse detection threshold is: thd = avg_1024+avg_90-0.5*std_1024;

[0036] Where thd is the first-level pulse detection threshold, avg_1024 is the mean of the baseband envelope data in the large window, avg_90 is the mean of the baseband envelope data in the small window, and std_1024 is the standard deviation of the baseband envelope data in the large window.

[0037] 2. Pulse detection is performed based on the pulse detection threshold. If the baseband envelope data amplitude exceeds the pulse detection threshold for more than 16 sampling points, a rising pulse edge is detected. Conversely, if the baseband envelope data amplitude is less than the pulse detection threshold for more than 16 sampling points, a falling pulse edge is detected. Upon pulse detection, pulse parameters (such as pulse width, pulse amplitude, and arrival time) are calculated, and the corresponding intermediate frequency waveform of the detected pulse is cached. In the FPGA, real-time GPS time is sampled using the same clock as the ADC sampling clock, allowing for very precise (nanosecond-level) arrival time determination for each pulse. This is very helpful for pulse timing calculation within the signal framework.

[0038] 3. Pulse information sorting: Pulses are primarily screened based on pulse width. Since the pulse width of the IFF pulse signal is fixed, the upper limit a and lower limit b of the pulse width are set based on the pulse width calculated in the second step. If the pulse width is greater than the upper limit a or less than the lower limit b, the pulse is considered a false detection. Based on this, inappropriate pulse information is eliminated, and pulse information that meets the pulse width conditions is sent to each signal detection module. Each signal detection module performs detection on different types of signals. In the FPGA, real-time pulse width detection allows each signal frame detection module to obtain pulse information within the required pulse width range. The comparator-based design has the advantage of fast processing speed.

[0039] 4. Mark X signal detection: Detection is performed according to the Mark X signal format. Similar to the pulse width screening method used in step 3, the correct pulse is further selected based on the pulse interval and pulse width information. Then, demodulation is performed based on the relative position of the data pulse to generate Mark X information. The shift register method is used to cache and detect the pulse information, which has a fast calculation speed.

[0040] 5. S-mode signal detection: Detection is performed according to the S-mode signal format. A method similar to step 4 is used to screen the pulse interval and pulse width. If the time interval and pulse width of four consecutive pulses meet the S-mode signal format definition within the error range, it is considered that an S-mode signal is detected. At the same time, demodulation is performed based on the relative position of the data pulses. A shift register method is used to cache and detect pulse information, which has a fast calculation speed.

[0041] 6. 4-mode signal detection: Detection is performed according to the 4-mode signal format definition. A method similar to step 4 is used to screen the pulse interval and pulse width. If the time interval and pulse width of three consecutive pulses meet the 4-mode signal format definition, it is considered that a 4-mode signal is detected. On the other hand, amplitude consistency detection is performed on the three pulses of the 4-mode to avoid most crosstalk situations. This amplitude consistency detection can be naturally added to the 4-mode signal detection and only adds a delay of tens of nanoseconds, thus also having the advantage of strong real-time performance.

[0042] 7. Data combination: Pack the detection information of the three signals and the cached intermediate frequency information into a data frame, put the detection information in the frame header, and send this data frame;

[0043] 8. Implement each module according to the idea of stream processing, so that this design can cope with high-speed data processing and meet the increasing signal processing speed requirements;

[0044] In the above steps, the first step adopts the method of sliding window mean and variance estimation of the area near the pulse, which can be changed to other methods such as background noise estimation; the second step is accompanied by pulse amplitude screening in actual implementation, which can effectively reduce the false alarm rate; in steps 4 and 5, the pulse intervals in the signal frame are monitored in real time. If unexpected intervals appear, the frame is considered to be wrong and the detection will be restarted; in step 6, the pulses in the signal frame are tested for amplitude consistency. If the consistency is poor, the frame is considered to be wrong and the detection will be restarted; through the above measures, the recognition and decoding of the three signals have extremely high accuracy and are suitable for actual application environments where the input signal amplitude is constantly changing.

[0045] Based on the above steps, this embodiment proposes an FPGA-based IFF pulse signal detection method, including the following steps:

[0046] Acquire a baseband envelope signal, and if a rising edge of a pulse of the baseband envelope signal is detected, calculate a pulse detection threshold based on the baseband envelope data of the first sliding window and the baseband envelope data in the second sliding window;

[0047] Counting the number of sampling points at which the baseband envelope signal is greater than a pulse detection threshold, detecting a pulse if the number of sampling points is greater than a preset threshold, calculating the parameters of the pulse, and caching the intermediate frequency waveform corresponding to the pulse;

[0048] According to the pulse width in the pulse parameters, the pulse is subjected to corresponding signal detection, and the detection result of each pulse is arranged in chronological order according to the arrival time of the corresponding pulse parameter, combined with the corresponding intermediate frequency waveform into a data frame and output.

[0049] In the method of this embodiment, the length of the first sliding window is 90, the length of the second sliding window is 1024, and the pulse detection threshold is calculated as follows:

[0050] thd = avg_1024+avg_90-0.5*std_1024

[0051] Wherein, avg_90 is the mean of the baseband envelope data in the first sliding window, avg_1024 is the mean of the baseband envelope data in the second sliding window, and std_1024 is the standard deviation of the baseband envelope data in the second sliding window.

[0052] In the method of this embodiment, after obtaining the baseband envelope signal, the method also includes the step of detecting the rising edge of the pulse, which specifically includes: respectively calculating the mean of the baseband envelope data in the first sliding window and the delay value of the mean, and if the comparison result of the size of the mean and the corresponding delay value meets the first condition, the rising edge of the pulse is detected.

[0053] The first condition is that the size of the mean and the corresponding delay value meet the pulse rising edge characteristics for 50 consecutive times, and the pulse rising edge characteristics are: (x(n) - x(n-90))>0.5* x(n) and x(n)>3* x(n-90), where x(n) is the mean of the baseband envelope data, and x(n-90) is the delay value of the mean.

[0054] In the method of this embodiment, measuring the parameters of the pulse specifically includes: sampling the real-time GPS time by using the same clock as the ADC sampling clock to obtain the arrival time of the pulse.

[0055] In the method of this embodiment, performing corresponding signal detection on the pulse according to the pulse width in the pulse parameter specifically includes:

[0056] The comparator determines whether the pulse width of the current pulse is within the target pulse width range. If so, the current pulse is cached in the target cache area corresponding to each target signal to prepare for signal detection. Otherwise, the current pulse is discarded and the corresponding intermediate frequency waveform is deleted.

[0057] In the method of this embodiment, the specific steps of caching the current pulse in the target buffer area corresponding to each target signal in preparation for signal detection include: obtaining a corresponding number of continuous pulses at the head of the target buffer area corresponding to the current target signal, judging whether the time interval and pulse width error between these pulses are within the range of the current target signal, and if so, demodulating the first pulse therein to obtain the corresponding detection result, and shifting all the pulses in the target buffer area forward by one position, and caching the current pulse to the tail of the target buffer area; otherwise, directly shifting all the pulses in the target buffer area forward by one position, and caching the current pulse to the tail of the target buffer area.

[0058] In the case that there are multiple target signals, the above steps are performed in parallel for the target buffer areas of the target signals to ensure that each frame of the final output signal contains the detection result.

[0059] In the method of this embodiment, when the target signal is a Mark X signal, the corresponding number is two, when the target signal is an S-mode signal, the corresponding number is four, and when the target signal is a 4-mode signal, the corresponding number is three.

[0060] In the method of this embodiment, when the target signal is an S-mode signal, a mask instruction is generated before demodulating the first pulse therein to obtain a corresponding detection result, and a release instruction is generated after demodulating the first pulse therein to obtain a corresponding detection result. When the target signal is a Mark X signal or a 4-mode signal, an instruction is received before obtaining a corresponding number of consecutive pulses at the head of the target buffer area. If the instruction is a mask instruction, the method waits until a release instruction is received.

[0061] In the method of this embodiment, when the target signal is a 4-mode signal, before demodulating the first pulse therein to obtain the corresponding detection result, an amplitude consistency test is performed on the corresponding number of continuous pulses in the head. If the consistency does not meet the requirements, the preset threshold is modified, and the number of sampling points where the baseband envelope signal is greater than the pulse detection threshold is returned to be counted, all pulses in the target buffer area are discarded, and the corresponding intermediate frequency waveform is deleted until the consistency meets the requirements.

[0062] This solution implements pulse sorting, identification, and signal frame demodulation within the FPGA. This not only eliminates the high-latency process of transferring pulse information from the FPGA to the DSP, but also uses a shift register approach to cache and discard real-time pulse information, enabling high-speed processing of pulse information. Furthermore, upon identifying the signal frame, demodulation is performed based on the pulse timing characteristics, rapidly obtaining the demodulation result. Furthermore, this solution also preserves the original intermediate frequency waveform corresponding to each signal frame, which is very useful for further research into pulse characteristics.

[0063] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed above with reference to the preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modifications, equivalent variations, and modifications to the above embodiment that do not depart from the technical solution of the present invention and are based on the technical essence of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. An IFF pulse signal detection method based on FPGA, characterized in that: The following steps are involved: Obtain a baseband envelope signal, and calculate the mean of the baseband envelope data and the delay value of the mean within a first sliding window. If a comparison result of the mean and the corresponding delay value meets a first condition, a pulse rising edge is detected. The first condition is that the mean and the corresponding delay value meet a pulse rising edge characteristic for 50 consecutive times, and the pulse rising edge characteristic is: (x(n) - x(n-90))> 0.5* x(n) and x(n)> 3* x(n-90), where x(n) is the mean of the baseband envelope data, and x(n-90) is the delay value of the mean; If a rising edge of the baseband envelope signal is detected, a pulse detection threshold is calculated based on the baseband envelope data of the first sliding window and the baseband envelope data in the second sliding window. The length of the first sliding window is 90, and the length of the second sliding window is 1024. The pulse detection threshold is calculated as follows: thd = avg_1024+avg_90-0.5*std_1024 Wherein, avg_90 is the mean of the baseband envelope data within the first sliding window, avg_1024 is the mean of the baseband envelope data within the second sliding window, and std_1024 is the standard deviation of the baseband envelope data within the second sliding window; Counting the number of sampling points at which the baseband envelope signal is greater than a pulse detection threshold, detecting a pulse if the number of sampling points is greater than a preset threshold, calculating the parameters of the pulse, and caching the intermediate frequency waveform corresponding to the pulse; According to the pulse width in the pulse parameters, the pulse is subjected to corresponding signal detection, and the detection result of each pulse is arranged in chronological order according to the arrival time of the corresponding pulse parameter, combined with the corresponding intermediate frequency waveform into a data frame and output.

2. The FPGA-based IFF pulse signal detection method according to claim 1, wherein: Measuring the parameters of the pulse specifically includes: sampling the real-time GPS time by using the same clock as the ADC sampling clock to obtain the arrival time of the pulse.

3. The FPGA-based IFF pulse signal detection method according to claim 1, wherein: According to the pulse width in the pulse parameter, performing corresponding signal detection on the pulse specifically includes: The comparator determines whether the pulse width of the current pulse is within the target pulse width range. If so, the current pulse is cached in the target cache area corresponding to each target signal to prepare for signal detection. Otherwise, the current pulse is discarded and the corresponding intermediate frequency waveform is deleted.

4. The FPGA-based IFF pulse signal detection method according to claim 3, wherein: The specific steps of caching the current pulse in the target buffer area corresponding to each target signal in preparation for signal detection include: obtaining a corresponding number of continuous pulses at the head of the target buffer area corresponding to the current target signal, judging whether the time interval and pulse width error between these pulses are within the range of the current target signal, and if so, demodulating the first pulse to obtain the corresponding detection result and then discarding it, and shifting all pulses in the target buffer area forward by one position, and caching the current pulse to the tail of the target buffer area.

5. The FPGA-based IFF pulse signal detection method according to claim 4, wherein: When the target signal is a Mark X signal, the corresponding number is two; when the target signal is an S-mode signal, the corresponding number is four; and when the target signal is a 4-mode signal, the corresponding number is three.

6. The FPGA-based IFF pulse signal detection method according to claim 4, wherein: When the target signal is an S-mode signal, a mask instruction is generated before demodulating the first pulse therein to obtain a corresponding detection result, and a release instruction is generated after demodulating the first pulse therein to obtain a corresponding detection result. When the target signal is a Mark X signal or a 4-mode signal, an instruction is received before obtaining a corresponding number of consecutive pulses at the head of the target buffer area. If the instruction is a mask instruction, the system waits until a release instruction is received.

7. The FPGA-based IFF pulse signal detection method according to claim 4, wherein: When the target signal is a 4-mode signal, before demodulating the first pulse therein to obtain the corresponding detection result, an amplitude consistency test is performed on the corresponding number of continuous pulses in the head. If the consistency does not meet the requirements, the preset threshold is modified, and the number of sampling points where the baseband envelope signal is greater than the pulse detection threshold is returned to be counted. All pulses in the target buffer area are discarded and the corresponding intermediate frequency waveform is deleted until the consistency meets the requirements.

Images