A compiling method for realizing dynamic reconfiguration function of FPGA EDA software
By designing reconfigurable and static modules separately in the FPGA design, generating independent code streams, and using the connecting CLB to realize the interface function between modules, the problems of long compilation time and unstable connection in the existing technology are solved, and a fast and stable dynamic reconfigurable function is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- EHIWAY MICROELECTRONIC SCI & TECH (SUZHOU) CO LTD
- Filing Date
- 2022-12-29
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies require the use of special bus macros when implementing dynamically reconfigurable functions in FPGA systems, resulting in long compilation times and unstable connections, making it impossible to directly load new function streams without changing the wiring channels between modules.
By designing reconfigurable modules and static modules separately in FPGA design, marking dynamic and static areas, and performing synthesis, placement, and routing separately, independent code streams are generated. The interface function between modules is implemented by connecting CLBs, avoiding the use of special bus macros.
It enables the rapid loading of new feature streams without changing the wiring channels between modules, reducing compilation time and ensuring the correctness and stability of the connections.
Smart Images
Figure CN115758957B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuits, and in particular relates to a compilation method for implementing the dynamic reconfigurable function of FPGA EDA software. Background Technology
[0002] FPGA EDA software is used to convert system functions written in hardware description languages into downloadable files through compilation modules such as synthesis, placement, routing, and code stream generation. These files are then downloaded to the FPGA to implement the system functions. If other circuit functions are required, the source code needs to be modified, the compilation process re-executed, and the files downloaded to the FPGA again to achieve the intended functionality. With technological advancements, FPGAs are becoming increasingly larger, and digital logic systems are becoming more complex. FPGA chips are developing towards ultra-large scale and high density, resulting in increasingly complex achievable logic functions and user designs, and consequently, longer compilation times when using FPGA EDA software.
[0003] Dynamic reconfigurability refers to dynamically changing the circuit structure while the FPGA system is operating. This is mainly achieved by reconfiguring or partially reconfiguring the programmable logic devices in the system, and the code stream content of the reconfiguration or partial reconfiguration depends on EDA software technology. By defining certain special regions, these regions can be reconfigured while other parts of the device are still running. Dynamic reconfigurability reduces the scope and number of units to be reconfigured, greatly shortening the reconfiguration time, and completing the function conversion without system restart or device power interruption. This allows for reduced functionality, improved board utilization, and faster compilation and download speeds.
[0004] The commonly used EDA dynamic reconfigurable technology is based on partial dynamic reconfiguration of modules. Its implementation requires a special bus macro to ensure that the wiring path between modules has not changed, thus guaranteeing the correct connection. Summary of the Invention
[0005] The technical problem to be solved by this invention is how to directly load the new function code stream of the reconfiguration area without using special bus macros and without changing the wiring channels between modules. A compilation method and device for realizing the dynamic reconfigurable function of FPGAEDA software is proposed.
[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0007] A compilation method for implementing dynamically reconfigurable FPGA EDA software includes the following steps when designing a fully functional FPGA with dynamic reconfigurability:
[0008] Step 1: Mark the reconfigurable modules and specify the physical area of the reconfigurable modules in the chip, which is called the dynamic area. Other areas are static areas. Record the reconfigurable modules and their corresponding location information in the user constraint file.
[0009] Step 2: During synthesis, the logic on reconfigurable and non-reconfigurable modules is not merged or optimized;
[0010] Step 3: During the preprocessing of the generated netlist file, the logical units of the reconfigurable module are marked as reconfigurable logical units;
[0011] Step 4: During packaging, reconfigurable logic units are packaged separately from unmarked logic units. Logic clusters (CLBs) packaged by reconfigurable logic units are marked as reconfigurable CLBs. Signals generated by reconfigurable logic units are marked as reconfigurable signals. Signals that cross the dynamic and static regions are split into two segments: one segment in the static region and one segment in the dynamic region, both marked as reconfigurable signals.
[0012] Step 5: After laying out and routing the static and dynamic areas respectively, generate the bitstreams for the full-function module and the reconfigurable module respectively.
[0013] Furthermore, the method for splitting the signal that crosses the dynamic and static regions into two segments is:
[0014] Find the start and end points of the signal. Divide the signal into two segments from the point where it passes through the dynamic and static regions. Set a virtual start point (start_virtual) and a virtual end point (end_virtual) for each of the two segments. Connect the start point (start) to the virtual end point (end_virtual) and connect the virtual start point (start_virtual) to the end point (end). If the start point (start) is within the dynamic reconfigurable region, mark the signal segment connected to the start point (start) and the virtual end point (end_virtual) as a reconfigurable signal. If the end point (end) is within the dynamic reconfigurable region, mark the signal segment connected to the virtual start point (start_virtual) and the end point (end) as a reconfigurable signal.
[0015] Furthermore, step 2 also includes a resource matching check between the reconfigurable module and the designated physical area after integration. If the physical resources contained in the designated physical area for the implementation of the module's logical functions cannot meet the resources required for the implementation of the reconfigurable module's functions, a prompt indicating insufficient resources in the physical area is given, and a new physical area is designated.
[0016] Furthermore, during placement, the placement range of the reconfigurable CLB is constrained within the physical constraint area corresponding to the dynamic area; during routing, the signal set is traversed, and if a signal has a reconfigurable marker, the routing search range for that signal is constrained to the dynamic area; if a signal does not have a reconfigurable marker, the routing search range for that signal is the static area.
[0017] Furthermore, during packaging, logic units configured as I / O functions with reconfigurable tags are packaged into connection CLBs according to the size of logic clusters (CLBs), and the connection CLBs are placed at the boundaries of the physical constraint regions of the dynamic area.
[0018] Furthermore, when designing and compiling the replacement module, the number and type of I / O in the top-level design of the netlist cannot exceed the number and type of I / O in the reconfigurable module of the full-function module. The replacement module refers to the user-designed module used to replace the functionality of the reconfigurable module.
[0019] Furthermore, when compiling the replacement module, the I / O packaging of the netlist needs to match the connection attributes of the CLB connected in the full-featured design, and the signal types need to be consistent with those of the full-featured module.
[0020] Furthermore, when replacing module layout and routing, the layout and routing range is constrained within the corresponding physical constraint area.
[0021] By adopting the above technical solution, the present invention has the following beneficial effects:
[0022] This invention provides a compilation method for implementing dynamic reconfigurability in FPGA EDA software. This method achieves FPGA reconfigurability through software compilation by separating and independently designing, synthesizing, placing, and routing reconfigurable modules and full-function modules during the design phase, generating separate code streams. This ensures that dynamic reconfigurability is independent from the design stage. When loading the code stream of a new replacement module, since the modules are designed independently, the dynamic area functions independently. The bus interface function is implemented by connecting to the CLB, eliminating the need for a special bus macro to ensure that the routing path between modules remains unchanged, thus guaranteeing correct connections. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the logic unit layout and signal connection of the present invention. Detailed Implementation
[0024] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0025] Figure 1 This invention illustrates a specific embodiment of a compilation method for implementing dynamically reconfigurable FPGA EDA software, comprising the following steps when designing a fully functional FPGA with dynamically reconfigurable capabilities:
[0026] Step 1: Mark the reconfigurable modules and specify their physical regions within the chip, referred to as the dynamic region. Other regions are designated as static regions. Record the reconfigurable modules and their corresponding location information in the user constraint file. In this embodiment, the reconfigurable modules are marked, and their physical regions within the chip are specified, referred to as the dynamic region. Other regions are designated as static regions. The reconfigurable modules and their corresponding location information are recorded in the user constraint file. Because the dynamic and static regions reside on the same chip, during full-function design, the modules to be reconfigured are marked, allowing the marked portions to be processed independently during the synthesis, placement, and routing process for module replacement.
[0027] Step 2: During synthesis, the logic on reconfigurable and non-reconfigurable modules is not merged or optimized. In this embodiment, this logic merging and optimization process needs to be avoided, ensuring that the internal logic functions of the reconfigurable module are independent of those of the non-reconfigurable module. Logic merging and optimization can be performed within either the reconfigurable or non-reconfigurable module. After synthesis, a resource matching check is performed between the reconfigurable module and the designated physical region. If the physical resources within the designated physical region for implementing the module's logic functions do not meet the resource requirements for the reconfigurable module's functionality, a resource shortage warning is given, and a new physical region is designated.
[0028] Step 3: During the preprocessing of the generated netlist file, the logical units of the reconfigurable module are marked as reconfigurable logical units.
[0029] Step 4: During packaging, reconfigurable logic units are packaged separately from unmarked logic units. Logic clusters (CLBs) packaged by reconfigurable logic units are marked as reconfigurable CLBs. Signals generated by reconfigurable logic units are marked as reconfigurable signals. Signals that cross the dynamic and static regions are split into two segments: one segment in the static region and one segment in the dynamic region, both marked as reconfigurable signals.
[0030] In this embodiment, the method for splitting the signal traversing the dynamic and static regions into two segments is as follows:
[0031] Identify the start and end points of the signal. Divide the signal into two segments at the point where it crosses the dynamic / static region. Set a virtual start point (start_virtual) and a virtual end point (end_virtual) for each of the two segments. Connect the start point to the virtual end point (end_virtual) and vice versa. If the start point (start) is within the dynamic reconfigurable region, mark the segment connected to the start point (start_virtual) and the end point (end_virtual) as a reconfigurable signal. Similarly, if the end point (end) is within the dynamic reconfigurable region, mark the segment connected to the end point (start_virtual) as a reconfigurable signal. In this embodiment, by dividing the signal across the dynamic / static region into two segments at the breakpoint and setting virtual start and virtual end points, the dynamic / static regions can be functionally completely separated, making separate packaging possible.
[0032] In this embodiment, during packaging, logic units configured as I / O functions with reconfigurable tags are packaged into connection CLBs according to the size of logic clusters (CLBs). The connection CLBs are then placed at the boundaries of the physical constraint area of the dynamic zone. In this embodiment, packaging logic units configured as I / O functions into connection CLBs according to the requirements of the packaging CLBs is equivalent to a bus interface connecting the dynamic and static zones. With this bus interface, it is possible to connect to the static zone. Through the connection CLBs, the routing of interface signals in the replacement module design continues the routing results from the full-function module design, eliminating the need for redesigning the routing. Therefore, by setting the connection CLBs in the dynamic zone, a special bus macro is not needed to determine that the routing path between modules has not changed, ensuring correct connection. Logic units configured as I / O functions refer to those whose internal logic functions are set to direct connection, meaning signals can enter and exit directly. Signals that need to be connected to logic units configured as I / O functions are divided into two categories. The first category: signals that use dynamic zone I / O for communication are directly interconnected using logic units configured as I / O functions, such as... Figure 1 The signal from start point 6 to end point 6 in the static zone communicates with the signal from start point 9 to end point 9 in the dynamic zone through the connection CLB. The signal from start point 10 to end point 10 in the dynamic zone communicates with the signal from start point 9 to end point 9 in the static zone through the connection CLB. The second type: the signal directly crosses the dynamic and static zones, and their virtual points are interconnected. For example, the signal from start point 1 in the static zone to end point 3 in the dynamic zone is connected by the connection CLB to connect the virtual start point and end point.
[0033] Step 5: After laying out and routing the static and dynamic areas respectively, generate the bitstreams for the full-function module and the reconfigurable module respectively.
[0034] The idea behind this invention is to design the dynamic and static areas separately from the very beginning. Although they are on the same chip, they are treated as two independent parts. Thus, when loading a new replacement module bitstream, i.e. a new dynamic area bitstream, the dynamic area function is independent because it is designed to be separate. It can be as convenient and quick as plugging and unplugging a new functional module, without affecting the use of the static area, and can also quickly load the bitstream of the new replacement module.
[0035] In this embodiment, during separate layout, the layout range of the reconfigurable CLB is constrained within the physical constraint region corresponding to the dynamic region. Only by constraining the reconfigurable CLB within the physical region corresponding to the dynamic region can the function of the dynamic region be realized. During separate routing, the signal set is traversed. If a signal carries a reconfigurable marker, the routing search range for that signal is constrained to the dynamic region; if a signal does not carry a reconfigurable marker, the routing search range for that signal is the static region.
[0036] In this embodiment, during the design and compilation of the replacement module, the number and type of I / O in the top-level design of the netlist cannot exceed the number and type of I / O in the reconfigurable module of the full-function module. The replacement module refers to the user-designed module used to replace the functionality of the reconfigurable module. Furthermore, during compilation, when packaging the netlist I / O, the replacement module needs to match the connection attributes of the CLBs connected in the full-function design, and the signal types must be consistent with those of the full-function module. During the placement and routing of the replacement module, the placement and routing range is constrained within the corresponding physical constraint area. For the replacement dynamic bitstream, its configuration design needs to be tailored to the interfaces used in the full-function design to match the characteristics of the static area, ensuring that its configuration does not affect the static area while still allowing for the reconfiguration of the dynamic area.
[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A compilation method for implementing dynamically reconfigurable FPGA EDA software, characterized in that, When designing a fully modular FPGA with dynamic reconfigurability, the following steps are included: Step 1: Mark the reconfigurable modules and specify the physical area of the reconfigurable modules in the chip, which is called the dynamic area. Other areas are static areas. Record the reconfigurable modules and their corresponding location information in the user constraint file. Step 2: During synthesis, the logic on reconfigurable and non-reconfigurable modules is not merged or optimized; Step 3: During the preprocessing of the generated netlist file, the logical units of the reconfigurable module are marked as reconfigurable logical units; Step 4: During packaging, reconfigurable logic units are packaged separately from unmarked logic units. Logic clusters CLBs packaged by reconfigurable logic units are marked as reconfigurable CLBs. Signals generated by reconfigurable logic units are marked as reconfigurable signals. Signals crossing the dynamic and static regions are split into two segments: one segment in the static region and one segment in the dynamic region, both marked as reconfigurable signals. Logic units configured for I / O functions with reconfigurable markings are packaged into connection CLBs according to the size of logic clusters CLBs, serving as the bus interface connecting the dynamic and static regions. Connection CLBs are placed at the boundary of the physical constraint area of the dynamic region. Logic units configured for I / O functions refer to those whose internal logic functions are set to direct connection functions. Step 5: After laying out and routing the static and dynamic areas respectively, generate the bitstreams for the full-function module and the reconfigurable module respectively.
2. The compilation method according to claim 1, characterized in that, The method to split a signal that crosses the dynamic and static regions into two segments is: Find the start and end points of the signal. Divide the signal into two segments from the point where it passes through the dynamic and static regions. Set a virtual start point (start_virtual) and a virtual end point (end_virtual) for each of the two segments. Connect the start point (start) to the virtual end point (end_virtual) and connect the virtual start point (start_virtual) to the end point (end). If the start point (start) is within the dynamic reconfigurable region, mark the signal segment connected to the start point (start) and the virtual end point (end_virtual) as a reconfigurable signal. If the end point (end) is within the dynamic reconfigurable region, mark the signal segment connected to the virtual start point (start_virtual) and the end point (end) as a reconfigurable signal.
3. The compilation method according to claim 1, characterized in that, Step 2 also includes checking the resource matching between the reconfigurable module and the designated physical area after integration. If the physical resources contained in the designated physical area for the implementation of the module's logical functions cannot meet the resources required for the implementation of the reconfigurable module's functions, a prompt indicating insufficient resources in the physical area will be given, and a new physical area will be designated.
4. The compilation method according to claim 3, characterized in that, During placement, the placement range of the reconfigurable CLB is constrained within the physical constraint area corresponding to the dynamic area; during routing, the signal set is traversed. If a signal has a reconfigurable marker, the routing search range for that signal is constrained to the dynamic area; if a signal does not have a reconfigurable marker, the routing search range for that signal is the static area.
5. The compilation method according to claim 4, characterized in that, When designing and compiling a replacement module, the number and type of I / O in the top-level design of the netlist cannot exceed the number and type of I / O in the reconfigurable module of the full-function module. The replacement module refers to a user-designed module used to replace the functionality of the reconfigurable module.
6. The compilation method according to claim 5, characterized in that, When compiling the replacement module, the I / O packaging of the netlist needs to match the connection attributes of the CLBs connected in the full-featured design, and the signal types need to be consistent with those of the full-featured module.
7. The compilation method according to claim 6, characterized in that, When replacing module placement and routing, constrain the placement and routing range within the corresponding physical constraint area.