A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: firstly, depositing a stack formed by alternately stacking silicon dioxide and silicon nitride on a first silicon substrate, and etching a line trench pattern in the stack; then, filling a germanium-silicon material, and epitaxially growing a first germanium-silicon layer above the stack, so that defects generated during the epitaxial growth of the first germanium-silicon layer are limited in the line trench pattern as much as possible, and lattice defects in the finally prepared first germanium-silicon layer are reduced. Then, forming a silicon dioxide layer or a silicon nitride layer above the first germanium-silicon layer, and performing annealing treatment on the first silicon substrate, the stack, the first germanium-silicon layer and the silicon dioxide layer or the silicon nitride layer, so that tensile stress is generated in the first germanium-silicon layer, and then the silicon dioxide layer or the silicon nitride layer above the first germanium-silicon layer is removed, thereby realizing high-quality Si x Ge 1‑x Preparation of OI substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] High-quality tensile or compressive stress transistors are a widely used technology in the semiconductor industry. Compared to traditional silicon substrates, transistors and other devices fabricated using this technology exhibit lower leakage current, lower power consumption, and higher mobility. Furthermore, transistor characteristics are influenced by the material itself; lower defect density reduces scattering mechanisms, significantly improving transistor mobility. However, current methods for fabricating tensile stress transistor substrates often result in significant lattice defects within the transistor, failing to meet the required specifications. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor structure and the semiconductor structure itself, achieving high-quality Si. x Ge 1-x Preparation of OI substrate.

[0004] In a first aspect, the present invention provides a method for fabricating a semiconductor structure, the method comprising: depositing a stack of alternating layers of silicon dioxide and silicon nitride on a first silicon substrate; etching the stack from top to bottom to form a line trench pattern within the stack, the line trench pattern comprising a plurality of line trenches, each line trench penetrating the upper and lower surfaces of the stack; filling the line trench pattern with germanium-silicon material and forming a first germanium-silicon layer above the stack; forming a silicon dioxide layer or a silicon nitride layer above the first germanium-silicon layer; annealing the first silicon substrate, the stack, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer to generate tensile stress within the first germanium-silicon layer; and removing the silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer.

[0005] In the above scheme, a stack of alternating layers of silicon dioxide and silicon nitride is first deposited on a first silicon substrate, and a trench pattern is etched within the stack. Then, germanium-silicon material is filled in, and a first germanium-silicon layer is epitaxially grown on top of the stack. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer as possible within the trench pattern, reducing lattice defects within the final first germanium-silicon layer. Subsequently, a silicon dioxide or silicon nitride layer is formed on top of the first germanium-silicon layer. The first silicon substrate, the stack, the first germanium-silicon layer, and the silicon dioxide or silicon nitride layer are then annealed to generate tensile stress within the first germanium-silicon layer. Finally, the silicon dioxide or silicon nitride layer above the first germanium-silicon layer is removed. During this process, the presence of silicon nitride in the stack or silicon nitride layer generates more tensile stress within the first germanium-silicon layer during annealing. Simultaneously, due to the confinement of the trench pattern, excessive tensile stress prevents large defects from forming in the first germanium-silicon layer, achieving high-quality Si. x Ge 1-x Preparation of OI substrate.

[0006] In one specific embodiment, before depositing a stack of alternating layers of silicon dioxide and silicon nitride on the first silicon substrate, the fabrication method further includes: growing a second germanium-silicon layer on the first silicon substrate, with the stack of alternating layers of silicon dioxide and silicon nitride deposited above the second germanium-silicon layer; and simultaneously annealing the first silicon substrate, the stack, the first germanium-silicon layer, and the silicon dioxide or silicon nitride layer, annealing the second germanium-silicon layer to generate tensile stress within the second germanium-silicon layer. This further reduces Si... x Ge 1-x Lattice defects in the OI substrate make the tensile stress distribution in the first germanium-silicon layer more uniform, improving the fabrication of Si x Ge 1-x The quality of the OI substrate.

[0007] In one specific embodiment, the first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer are annealed, including: holding the first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer in an annealing environment of 300°C to 850°C for 1 minute to 3 hours, thereby completing the annealing treatment of the first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer. This generates more and more uniformly distributed tensile stress within the first germanium-silicon layer.

[0008] In one specific embodiment, the fabrication method further includes: depositing a dielectric layer on a second silicon substrate; after removing a silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer, bonding the first germanium-silicon layer on the first silicon substrate to the dielectric layer of the second silicon substrate; removing the first silicon substrate and the material between the first silicon substrate and the first germanium-silicon layer, and thinning the first germanium-silicon layer to a predetermined thickness. By first fabricating a first germanium-silicon layer that meets the defect and tensile stress requirements in the first silicon substrate, and then bonding the first germanium-silicon layer to the dielectric layer of the second silicon substrate, contamination of the second silicon substrate during the fabrication of the first germanium-silicon layer is prevented. Simultaneously, when thinning the first germanium-silicon layer, thinning begins from the portion of the first germanium-silicon layer closest to the first silicon substrate, thereby reducing lattice defects within the retained predetermined thickness of the first germanium-silicon layer, enabling the fabrication of a thinner first germanium-silicon layer with a more uniform tensile stress distribution and fewer lattice defects.

[0009] In one specific embodiment, the material of the first germanium-silicon layer is Ge. x Si 1-x , where 0≤x≤1.

[0010] In one specific embodiment, when the thickness of the first germanium-silicon layer above the stack is less than a threshold thickness, x in the first germanium-silicon layer is a fixed value; when the thickness of the first germanium-silicon layer above the stack is not less than the threshold thickness, x in the first germanium-silicon layer is a gradually changing value. In this case, the value of x starts from 1 at a position adjacent to the first germanium-silicon layer and the stack, gradually decreases, and reaches a minimum value min on the upper surface of the first germanium-silicon layer. Adjusting the germanium and silicon content in the first germanium-silicon layer according to the thickness of the first germanium-silicon layer deposited above the stack simplifies the fabrication process and facilitates the fabrication of a higher quality tensile stress first germanium-silicon layer.

[0011] In one specific implementation, when x is a fixed value, 0.5 ≤ x < 1; when x is a gradually changing value, 0.5 ≤ min < 1. This facilitates the fabrication of a higher quality tensile stress first germanium-silicon layer.

[0012] In one specific embodiment, the fabrication method further includes: fabricating a back-gate field-effect transistor on the first germanium-silicon layer, wherein the channel in the back-gate field-effect transistor is a tensile-stressed germanium-silicon channel formed by etching the first germanium-silicon layer. Alternatively, fabricating a fin field-effect transistor on the first germanium-silicon layer, wherein the channel in the fin field-effect transistor is a tensile-stressed germanium-silicon channel formed by etching the first germanium-silicon layer. Alternatively, fabricating a full-around-gate transistor on the first germanium-silicon layer, wherein the channel in the full-around-gate transistor is a tensile-stressed germanium-silicon channel formed by etching the first germanium-silicon layer. This facilitates fabrication on high-quality Si... x Ge 1-xBack-gate field-effect transistors, fin field-effect transistors, or all-around gate transistors are further fabricated on the OI substrate, resulting in back-gate field-effect transistors, fin field-effect transistors, or all-around gate transistors with lower leakage current, lower power consumption, and higher mobility.

[0013] Secondly, the present invention also provides a semiconductor structure comprising a first silicon substrate and a stacked layer deposited on the first silicon substrate, the stacked layer being formed by alternating layers of silicon dioxide and silicon nitride, wherein a trench pattern is etched in the stacked layer; the trench pattern includes a plurality of trenches, each trench penetrating the upper and lower surfaces of the stacked layer. The semiconductor structure further includes a germanium-silicon material filling the trench pattern and forming a first germanium-silicon layer above the stacked layer. The first germanium-silicon layer is further treated to generate tensile stress within it by: forming a silicon dioxide layer or a silicon nitride layer above the first germanium-silicon layer; annealing the first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide or silicon nitride layer; and removing the silicon dioxide or silicon nitride layer located above the first germanium-silicon layer.

[0014] In the above scheme, a stack of alternating layers of silicon dioxide and silicon nitride is first deposited on a first silicon substrate, and a trench pattern is etched within the stack. Then, germanium-silicon material is filled in, and a first germanium-silicon layer is epitaxially grown on top of the stack. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer as possible within the trench pattern, reducing lattice defects within the final first germanium-silicon layer. Subsequently, a silicon dioxide or silicon nitride layer is formed on top of the first germanium-silicon layer. The first silicon substrate, the stack, the first germanium-silicon layer, and the silicon dioxide or silicon nitride layer are then annealed to generate tensile stress within the first germanium-silicon layer. Finally, the silicon dioxide or silicon nitride layer above the first germanium-silicon layer is removed. During this process, the presence of silicon nitride in the stack or silicon nitride layer generates more tensile stress within the first germanium-silicon layer during annealing. Simultaneously, due to the confinement of the trench pattern, excessive tensile stress prevents large defects from forming in the first germanium-silicon layer, achieving high-quality Si. x Ge 1-x Preparation of OI substrate.

[0015] Thirdly, the present invention also provides a semiconductor structure comprising: a second silicon substrate, a dielectric layer deposited on the second silicon substrate, and a first germanium-silicon layer bonded to the dielectric layer. The first germanium-silicon layer is prepared as follows: a stack of alternating layers of silicon dioxide and silicon nitride is deposited on a first silicon substrate; the stack is etched from top to bottom to form a line trench pattern within the stack, the line trench pattern containing multiple line trenches, each line trench penetrating the upper and lower surfaces of the stack; germanium-silicon material is filled into the line trench pattern, and a first germanium-silicon layer is formed above the stack; a silicon dioxide layer or a silicon nitride layer is formed above the first germanium-silicon layer; the first silicon substrate, the stack, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer are annealed to generate tensile stress within the first germanium-silicon layer; the silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer is removed; the first germanium-silicon layer on the first silicon substrate is bonded to a dielectric layer on a second silicon substrate; the first silicon substrate and the material between the first silicon substrate and the first germanium-silicon layer are removed, and the first germanium-silicon layer is thinned to a predetermined thickness.

[0016] In the above scheme, a stack of alternating layers of silicon dioxide and silicon nitride is first deposited on a first silicon substrate, and a trench pattern is etched within the stack. Then, germanium-silicon material is filled in, and a first germanium-silicon layer is epitaxially grown on top of the stack. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer as possible within the trench pattern, reducing lattice defects within the final first germanium-silicon layer. Subsequently, a silicon dioxide or silicon nitride layer is formed on top of the first germanium-silicon layer. The first silicon substrate, the stack, the first germanium-silicon layer, and the silicon dioxide or silicon nitride layer are then annealed to generate tensile stress within the first germanium-silicon layer. Finally, the silicon dioxide or silicon nitride layer above the first germanium-silicon layer is removed. During this process, the presence of silicon nitride in the stack or silicon nitride layer generates more tensile stress within the first germanium-silicon layer during annealing. Simultaneously, due to the confinement of the trench pattern, excessive tensile stress prevents large defects from forming in the first germanium-silicon layer, achieving high-quality Si. x Ge 1-x The fabrication of OI substrates involves first fabricating a first germanium-silicon layer in a first silicon substrate that meets the defect and tensile stress requirements, and then bonding the first germanium-silicon layer to the dielectric layer of a second silicon substrate. This prevents contamination of the second silicon substrate during the fabrication of the first germanium-silicon layer. Furthermore, when thinning the first germanium-silicon layer, thinning begins from the portion closest to the first silicon substrate, resulting in fewer lattice defects within the retained first germanium-silicon layer of the set thickness. This allows for the fabrication of a thinner first germanium-silicon layer with a more uniform tensile stress distribution and fewer lattice defects. Attached Figure Description

[0017] Figure 1A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0018] Figures 2a-2e These are schematic cross-sectional views of each step in the semiconductor structure fabrication process provided in an embodiment of the present invention.

[0019] Figures 3a-3e These are schematic cross-sectional views of each step in the fabrication process of another semiconductor structure provided in an embodiment of the present invention.

[0020] Figures 4a-4e These are schematic cross-sectional views of each step in the fabrication process of another semiconductor structure provided in an embodiment of the present invention.

[0021] Figures 5a-5e These are schematic cross-sectional views of each step in the semiconductor structure fabrication process provided in an embodiment of the present invention.

[0022] Figure 6 This is a three-dimensional schematic diagram of a semiconductor structure prepared according to an embodiment of the present invention;

[0023] Figure 7 Provided for embodiments of the present invention Figure 6 A three-dimensional schematic diagram of a back-gate field-effect transistor fabricated on a semiconductor structure is shown.

[0024] Figure 8 Provided for embodiments of the present invention Figure 6 A three-dimensional schematic diagram of a fin field-effect transistor fabricated on a semiconductor structure is shown.

[0025] Figure 9 Provided for embodiments of the present invention Figure 6 A three-dimensional schematic diagram of a gate-all-around transistor fabricated on a semiconductor structure is shown.

[0026] Figure label:

[0027] 11-First silicon substrate; 12-Second silicon substrate; 13-Dielectric layer; 20-Stacked layer

[0028] 30 - Line trench; 41 - First germanium-silicon layer; 42 - Second germanium-silicon layer; 50 - Silicon dioxide layer or silicon nitride layer

[0029] 60 - Bonding layer; 70 - Tensile stress germanium-silicon channel; 71 - Source; 72 - Drain Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] To facilitate understanding of the semiconductor structure fabrication method provided in the embodiments of the present invention, the application scenario of the semiconductor structure fabrication method provided in the embodiments of the present invention will be described first. This semiconductor structure fabrication method is applied in the fabrication process of tensile stress germanium-silicon layers. The semiconductor structure fabrication method will then be described in detail below with reference to the accompanying drawings.

[0032] refer to Figure 1 , Figures 2a-2e The method for preparing the semiconductor structure provided in this embodiment of the invention includes:

[0033] Step 10: Deposit a stack 20 formed by alternating layers of silicon dioxide and silicon nitride on the first silicon substrate 11;

[0034] Step 20: Etch the stack 20 from top to bottom to form a line groove pattern in the stack 20. The line groove pattern contains multiple line grooves 30, and each line groove 30 penetrates the upper and lower surfaces of the stack 20.

[0035] Step 30: Fill the groove pattern with germanium-silicon material and form a first germanium-silicon layer 41 on top of the stack 20;

[0036] Step 40: Form a silicon dioxide layer or a silicon nitride layer 50 on top of the first germanium-silicon layer 41;

[0037] Step 50: Anneal the first silicon substrate 11, the stack 20, the first germanium-silicon layer 41 and the silicon dioxide layer or silicon nitride layer 50 to generate tensile stress inside the first germanium-silicon layer 41.

[0038] Step 60: Remove the silicon dioxide layer or silicon nitride layer 50 located above the first germanium silicon layer 41.

[0039] In the above scheme, a stack 20 formed by alternating layers of silicon dioxide and silicon nitride is first deposited on a first silicon substrate 11, and a line trench pattern is etched in the stack 20. Then, germanium-silicon material is filled, and a first germanium-silicon layer 41 is epitaxially grown on top of the stack 20. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer 41 as possible within the line trench pattern, reducing lattice defects inside the final first germanium-silicon layer 41. Subsequently, a silicon dioxide layer or a silicon nitride layer 50 is formed on top of the first germanium-silicon layer 41. The first silicon substrate 11, the stack 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50 are annealed to generate tensile stress inside the first germanium-silicon layer 41. Finally, the silicon dioxide or silicon nitride layer 50 located on top of the first germanium-silicon layer 41 is removed. During this process, due to the presence of silicon nitride material in the stacked layer 20 or the silicon nitride layer, more tensile stress is generated inside the first germanium-silicon layer 41 during the annealing of the semiconductor structure. At the same time, due to the limitation of the line trench pattern, large defects will not be generated in the first germanium-silicon layer 41 due to excessive tensile stress, thus achieving high-quality Si. x Ge 1-x Fabrication of OI substrates. The following section describes each step in detail with reference to the accompanying drawings.

[0040] First, refer to Figure 1 , Figure 2a and Figure 2b A stacked layer 20 of alternating layers of silicon dioxide and silicon nitride is deposited on a first silicon substrate 11. The shape of the first silicon substrate 11 can be any shape, such as circular, rectangular, or elliptical. Specifically, when depositing the stacked layer 20 of alternating layers of silicon dioxide and silicon nitride on the first silicon substrate 11, as follows... Figure 2b As shown, a silicon dioxide layer can be deposited on the first silicon substrate 11 first, followed by silicon nitride deposition on the silicon dioxide layer, then silicon dioxide deposition again, and so on, forming a stack 20. Alternatively, a silicon nitride layer can be deposited on the first silicon substrate 11 first, followed by silicon dioxide deposition on the silicon nitride layer, then silicon nitride deposition again, and so on, forming the stack 20. It should be noted that the number of times silicon dioxide and silicon nitride are deposited in the stack 20 can be equal or unequal. For example, in the method shown in 2b, silicon dioxide is deposited twice, while silicon nitride is deposited once.

[0041] Next, refer to Figure 1 , Figure 2b and Figure 2cThe stack 20 is etched from top to bottom to form a line trench pattern within it. The line trench pattern contains multiple line trenches 30, each penetrating both the upper and lower surfaces of the stack 20. Specifically, the area of ​​the line trench pattern can be larger than the area of ​​the active region, thus forming a larger, high-quality first germanium-silicon layer 41. The line trench pattern can be etched into the stack 20 using dry etching, wet etching, or photolithography. The shape of each line trench 30 can be a straight trench, a curved trench, etc. The multiple line trenches 30 in the pattern can be arranged uniformly or non-uniformly. Each line trench 30 penetrates from the upper surface to the lower surface of the stack 20, meaning it traverses both the upper and lower surfaces of the stack 20.

[0042] Next, refer to Figure 1 , Figure 2c and Figure 2d Germanium-silicon material is filled into the groove pattern, and a first germanium-silicon layer 41 is formed on top of the stack 20. Specifically, the grooves 30 in the groove pattern are first filled with germanium-silicon material, and then germanium-silicon material is deposited further to form the first germanium-silicon layer 41 on top of the stack 20. The material of the first germanium-silicon layer 41 can be Ge. x Si 1-xWhere 0 ≤ x ≤ 1. Furthermore, the thickness of the first germanium-silicon layer 41 can be related to x in the material of the first germanium-silicon layer 41. For example, when the thickness of the first germanium-silicon layer 41 above the stack 20 is thinner—specifically, when the thickness of the first germanium-silicon layer 41 above the stack 20 is less than a threshold thickness—x in the first germanium-silicon layer 41 can be a fixed value. When the thickness of the first germanium-silicon layer 41 above the stack 20 is thicker—specifically, when the thickness of the first germanium-silicon layer 41 above the stack 20 is not less than a threshold thickness—x in the first germanium-silicon layer 41 can be a gradually changing value. In this case, the value of x can start from 1 at a position adjacent to the first germanium-silicon layer 41 and the stack 20, gradually decrease, and reach a minimum value min on the upper surface of the first germanium-silicon layer 41. Adjusting the germanium and silicon content within the first germanium-silicon layer 41 according to the thickness of the first germanium-silicon layer 41 deposited above the stack 20 simplifies the fabrication process and facilitates the fabrication of a higher quality tensile stress first germanium-silicon layer 41. When determining the specific value of x, if x is a fixed value, 0.5 ≤ x < 1 can be used, meaning x can be any value greater than or equal to 0.5 but less than 1, such as 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc. If x is a gradually changing value, 0.5 ≤ min < 1 can be used, meaning that as the value of x gradually decreases from 1 to min, the value of min can be any value greater than or equal to 0.5 but less than 1, such as 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc. This facilitates the fabrication of a higher quality tensile stress first germanium-silicon layer 41.

[0043] Next, refer to Figure 1 and Figure 2d A silicon dioxide layer or a silicon nitride layer 50 is formed above the first germanium-silicon layer 41. Either a silicon dioxide layer or a silicon nitride layer can be deposited above the first germanium-silicon layer 41.

[0044] Next, as Figure 1 As shown, the first silicon substrate 11, the stacked layer 20, the first germanium-silicon layer 41, and the silicon dioxide layer or silicon nitride layer 50 are annealed to generate tensile stress within the first germanium-silicon layer 41. Specifically, during annealing, Figure 2c The entire semiconductor device shown undergoes annealing to generate tensile stress within the first germanium-silicon layer 41. During this process, the presence of silicon nitride material in the stack 20 or silicon nitride layer increases the tensile stress within the first germanium-silicon layer 41 during annealing. Simultaneously, due to the constraints of the trench pattern, excessive tensile stress prevents large defects from forming in the first germanium-silicon layer 41, thus achieving high-quality silicon. x Ge 1-x Preparation of OI substrate.

[0045] When annealing the first silicon substrate 11, the stacked layer 20, the first germanium-silicon layer 41, and the silicon dioxide layer or silicon nitride layer 50, the annealing process can be completed by holding the first silicon substrate 11, the stacked layer 20, the first germanium-silicon layer 41, and the silicon dioxide layer or silicon nitride layer 50 in an annealing environment of 300℃ to 850℃ for 1 minute to 3 hours. The annealing environment temperature can be any temperature between 300℃ and 850℃, such as 300℃, 400℃, 500℃, 600℃, 700℃, 800℃, and 850℃. The annealing time can be any duration between 1min and 3h, such as 1min, 10min, 30min, 50min, 70min, 90min, 110min, 130min, 150min, 170min, and 180min, so that more and more uniformly distributed tensile stress is generated inside the first germanium-silicon layer 41.

[0046] Next, refer to Figure 1 , Figure 2d and Figure 2e The silicon dioxide layer or silicon nitride layer 50 located above the first germanium-silicon layer 41 is removed. Specifically, this can be achieved by etching or polishing to remove the silicon dioxide layer or silicon nitride layer 50 above the first germanium-silicon layer 41, thus achieving high-quality Si. x Ge 1-x Preparation of OI substrate.

[0047] In addition, such as Figures 3a-3e In another method for fabricating a semiconductor structure, before depositing a stack 20 formed by alternating layers of silicon dioxide and silicon nitride on the first silicon substrate 11, the method may further include: growing a second germanium-silicon layer 42 on the first silicon substrate 11, and depositing the stack 20 formed by alternating layers of silicon dioxide and silicon nitride on top of the second germanium-silicon layer 42. The material of the second germanium-silicon layer 42 can also be Ge. x Si 1-x Where 0 ≤ x ≤ 1. The method for determining x can be the same as that for x in the first germanium-silicon layer 41, and will not be repeated here. At this time, as... Figures 3b-3e As shown, the subsequent steps of forming the line trench pattern, depositing the first germanium-silicon layer 41, and the silicon dioxide or nitride layer are similar to those described above. Figures 2a-2e The method shown is the same and will not be repeated here. It should be noted that while annealing the first silicon substrate 11, the stacked layer 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50, the second germanium-silicon layer 42 also needs to be annealed to generate tensile stress within the second germanium-silicon layer 42. This further reduces Si... x Ge 1-xLattice defects in the OI substrate make the tensile stress distribution in the first germanium-silicon layer 41 more uniform, improving the fabrication of Si x Ge 1-x The quality of the OI substrate.

[0048] like Figures 4a-4e As shown, the preparation method may further include: Figure 4a As shown, a dielectric layer 13 is deposited on the second silicon substrate 12. The material of the dielectric layer 13 can specifically be an oxide insulating layer composed of nitrides or oxides, etc. Figure 4b , Figure 4c As shown, after removing the silicon dioxide layer or silicon nitride layer 50 located above the first germanium-silicon layer 41, the first germanium-silicon layer 41 on the first silicon substrate 11 is bonded to the dielectric layer 13 of the second silicon substrate 12. The specific bonding method can be as follows: Figure 4b As shown, a bonding layer 60 is deposited on the first germanium-silicon layer 41. The material of the bonding layer 60 can be alumina. Then, as... Figure 4c As shown, the first germanium-silicon layer 41 on the first silicon substrate 11 is bonded to the dielectric layer 13 of the second silicon substrate 12 via a bonding layer 60. Then, as... Figure 4d , Figure 4e As shown, the material between the first silicon substrate 11 and the first germanium-silicon layer 41 is removed. Specifically, in Figures 4a-4e In the illustrated method, it is necessary to remove the remaining material in the first silicon substrate 11, the stacked layer 20, and the germanium-silicon material filling the line trench pattern. Then, as... Figure 4e As shown, the first germanium-silicon layer 41 is thinned to a predetermined thickness, which can be achieved through methods such as grinding. By first fabricating a first germanium-silicon layer 41 that meets the defect and tensile stress requirements in the first silicon substrate 11, and then bonding the first germanium-silicon layer 41 to the dielectric layer 13 of the second silicon substrate 12, contamination of the second silicon substrate 12 during the fabrication of the first germanium-silicon layer 41 is prevented. Simultaneously, when thinning the first germanium-silicon layer 41, the thinning begins from the portion of the first germanium-silicon layer 41 closest to the first silicon substrate 11, thereby reducing lattice defects within the retained predetermined thickness of the first germanium-silicon layer 41. This results in a thinner first germanium-silicon layer 41 with a more uniform tensile stress distribution and fewer lattice defects.

[0049] like Figures 5a-5e Another method for fabricating a semiconductor structure is shown, which is similar to... Figures 4a-4e The method is basically the same, except that a second germanium-silicon layer 42 is grown on the first silicon substrate 11, and a stack 20 formed by alternating layers of silicon dioxide and silicon nitride is deposited on top of the second germanium-silicon layer 42. At this time, as... Figure 5d , Figure 5eAs shown, when removing the first silicon substrate 11 and the material between the first silicon substrate 11 and the first germanium-silicon layer 41, in addition to removing the remaining material in the first silicon substrate 11, the stacked layer 20, and the germanium-silicon material filling the trench pattern, it is also necessary to remove the second germanium-silicon layer 42. By first preparing a first germanium-silicon layer 41 that meets the defect and tensile stress requirements in the first silicon substrate 11, and then bonding the first germanium-silicon layer 41 to the dielectric layer 13 of the second silicon substrate 12, contamination of the second silicon substrate 12 during the preparation of the first germanium-silicon layer 41 is prevented. At the same time, when thinning the first germanium-silicon layer 41, the thinning starts from the portion of the first germanium-silicon layer 41 closest to the first silicon substrate 11, thereby reducing the number of lattice defects in the first germanium-silicon layer 41 of the set thickness, and enabling the preparation of a thinner first germanium-silicon layer 41 with a more uniform tensile stress distribution and fewer lattice defects.

[0050] In addition, such as Figure 6 A semiconductor structure fabricated using the above method includes a second silicon substrate 12, a dielectric layer 13, and a thinned first germanium-silicon layer 41. Further processing can then be performed... Figure 6 Transistor devices are fabricated from the semiconductor structure shown. For details, refer to... Figure 7 A back-gate field-effect transistor can be fabricated on the first germanium-silicon layer 41. The back-gate field-effect transistor includes a source 71 and a drain 72, wherein both the source 71 and the drain 72 are formed by backfilling source and drain materials after etching the first germanium-silicon layer 41. Figure 7 As shown, the channel in the back-gate field-effect transistor is a tensile-stressed germanium-silicon channel 70 formed by etching the first germanium-silicon layer 41. It should be noted, however, that the subsequent fabrication of the transistor on the first germanium-silicon layer 41 is not limited to... Figure 7 Besides the method shown, other methods can also be used. For example, refer to... Figure 8 A finned field-effect transistor can be fabricated on the first germanium-silicon layer 41. The finned field-effect transistor includes a source 71 and a drain 72, wherein both the source 71 and drain 72 are formed by backfilling source and drain materials after etching the first germanium-silicon layer 41. For example... Figure 8 As shown, the channel in the fin field-effect transistor is a tensile-stressed germanium-silicon channel 70 formed by etching the first germanium-silicon layer 41. (Reference) Figure 9 Furthermore, a fully all-around gate transistor can be fabricated on the first germanium-silicon layer 41. The fully all-around gate transistor includes a source 71 and a drain 72, wherein both the source 71 and drain 72 are formed by backfilling source / drain material after etching the first germanium-silicon layer 41. For example... Figure 9 As shown, the channel in the all-around gate transistor is a tensile-stressed germanium-silicon channel 70 formed by etching the first germanium-silicon layer 41. This facilitates the fabrication of high-quality silicon wafers. x Ge 1-xBack-gate field-effect transistors, fin field-effect transistors, or all-around gate transistors are further fabricated on the OI substrate, resulting in back-gate field-effect transistors, fin field-effect transistors, or all-around gate transistors with lower leakage current, lower power consumption, and higher mobility.

[0051] Of course, it should be noted that the methods for fabricating back-gate field-effect transistors, fin field-effect transistors, or all-around gate transistors on the first germanium-silicon layer 41 are not limited to those shown above. Figure 6 The semiconductor structure shown is fabricated using methods other than those described. For example, it can be directly fabricated on... Figure 2e , Figure 3e , Figure 4e , Figure 5e The semiconductor structure shown in the figure is further fabricated with transistors, and the gate channels in the transistors are all tensile germanium-silicon channels 70 formed by etching the first germanium-silicon layer 41.

[0052] In the various embodiments shown above, a stack 20 formed by alternating layers of silicon dioxide and silicon nitride is first deposited on a first silicon substrate 11, and a line trench pattern is etched in the stack 20. Then, germanium-silicon material is filled in, and a first germanium-silicon layer 41 is epitaxially grown above the stack 20. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer 41 as possible within the line trench pattern, reducing lattice defects within the final first germanium-silicon layer 41. A silicon dioxide layer or a silicon nitride layer 50 is then formed above the first germanium-silicon layer 41. The first silicon substrate 11, the stack 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50 are then annealed to generate tensile stress within the first germanium-silicon layer 41. Finally, the silicon dioxide or silicon nitride layer 50 located above the first germanium-silicon layer 41 is removed. During this process, due to the presence of silicon nitride material in the stacked layer 20 or the silicon nitride layer, more tensile stress is generated inside the first germanium-silicon layer 41 during the annealing of the semiconductor structure. At the same time, due to the limitation of the line trench pattern, large defects will not be generated in the first germanium-silicon layer 41 due to excessive tensile stress, thus achieving high-quality Si. x Ge 1-x Preparation of OI substrate.

[0053] Furthermore, embodiments of the present invention also provide a semiconductor structure, with reference to... Figures 2a-2eThe semiconductor structure includes a first silicon substrate 11 and a stack 20 deposited on the first silicon substrate 11. The stack 20 is formed by alternating layers of silicon dioxide and silicon nitride. A trench pattern is etched into the stack 20. The trench pattern includes multiple trenches 30, each trench 30 penetrating the upper and lower surfaces of the stack 20. The semiconductor structure also includes a germanium-silicon material filling the trench pattern and a first germanium-silicon layer 41 formed above the stack 20. The first germanium-silicon layer 41 is further treated to generate tensile stress within it by: forming a silicon dioxide layer or a silicon nitride layer 50 above the first germanium-silicon layer 41; annealing the first silicon substrate 11, the stack 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50; and removing the silicon dioxide or silicon nitride layer 50 located above the first germanium-silicon layer 41.

[0054] First, a stack 20 of alternating layers of silicon dioxide and silicon nitride is deposited on a first silicon substrate 11, and a trench pattern is etched in the stack 20. Then, germanium-silicon material is filled in, and a first germanium-silicon layer 41 is epitaxially grown on top of the stack 20. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer 41 as possible within the trench pattern, reducing lattice defects inside the final first germanium-silicon layer 41. Then, a silicon dioxide layer or a silicon nitride layer 50 is formed on top of the first germanium-silicon layer 41. The first silicon substrate 11, the stack 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50 are annealed to generate tensile stress inside the first germanium-silicon layer 41. Finally, the silicon dioxide or silicon nitride layer 50 located on top of the first germanium-silicon layer 41 is removed. During this process, due to the presence of silicon nitride material in the stacked layer 20 or the silicon nitride layer, more tensile stress is generated inside the first germanium-silicon layer 41 during the annealing of the semiconductor structure. At the same time, due to the limitation of the line trench pattern, large defects will not be generated in the first germanium-silicon layer 41 due to excessive tensile stress, thus achieving high-quality Si. x Ge 1-x Preparation of OI substrate.

[0055] refer to Figures 3a-3e Furthermore, before depositing a stack 20 formed by alternating layers of silicon dioxide and silicon nitride on the first silicon substrate 11, a second germanium-silicon layer 42 can be grown on the first silicon substrate 11, with the stack 20 formed by alternating layers of silicon dioxide and silicon nitride deposited above the second germanium-silicon layer 42. The material of the second germanium-silicon layer 42 can also be Ge. x Si 1-x Where 0 ≤ x ≤ 1. The method for determining x can be the same as that for x in the first germanium-silicon layer 41, and will not be repeated here. At this time, as... Figures 3b-3e As shown, the subsequent steps of forming the line trench pattern, depositing the first germanium-silicon layer 41, and the silicon dioxide or nitride layer are similar to those described above. Figures 2a-2e The method shown is the same and will not be repeated here. It should be noted that while annealing the first silicon substrate 11, the stacked layer 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50, the second germanium-silicon layer 42 also needs to be annealed to generate tensile stress within the second germanium-silicon layer 42. This further reduces Si... x Ge 1-x Lattice defects in the OI substrate make the tensile stress distribution in the first germanium-silicon layer 41 more uniform, improving the fabrication of Si x Ge 1-x The quality of the OI substrate.

[0056] In addition, embodiments of the present invention also provide another semiconductor structure, see reference. Figures 4a-4e The semiconductor structure includes: a second silicon substrate 12, a dielectric layer 13 deposited on the second silicon substrate 12, and a first germanium-silicon layer 41 bonded to the dielectric layer 13. The first germanium-silicon layer 41 is prepared as follows: a stack 20 of alternating layers of silicon dioxide and silicon nitride is deposited on the first silicon substrate 11; the stack 20 is etched from top to bottom to form a trench pattern within the stack 20, the trench pattern containing multiple trenches 30, each trench 30 penetrating the upper and lower surfaces of the stack 20; germanium-silicon material is filled into the trench pattern, and the first germanium-silicon layer 41 is formed above the stack 20; a silicon dioxide layer or a silicon nitride layer is formed above the first germanium-silicon layer 41. Silicon layer 50; Annealing the first silicon substrate 11, stack 20, first germanium-silicon layer 41 and silicon dioxide layer or silicon nitride layer 50 to generate tensile stress inside the first germanium-silicon layer 41; Removing the silicon dioxide layer or silicon nitride layer 50 located above the first germanium-silicon layer 41; Bonding the first germanium-silicon layer 41 on the first silicon substrate 11 to the dielectric layer 13 of the second silicon substrate 12; Removing the first silicon substrate 11 and the material between the first silicon substrate 11 and the first germanium-silicon layer 41, and thinning the first germanium-silicon layer 41 to a set thickness.

[0057] First, a stack 20 of alternating layers of silicon dioxide and silicon nitride is deposited on a first silicon substrate 11, and a trench pattern is etched in the stack 20. Then, germanium-silicon material is filled in, and a first germanium-silicon layer 41 is epitaxially grown on top of the stack 20. This confines as many defects generated during the epitaxial growth of the first germanium-silicon layer 41 as possible within the trench pattern, reducing lattice defects inside the final first germanium-silicon layer 41. Then, a silicon dioxide layer or a silicon nitride layer 50 is formed on top of the first germanium-silicon layer 41. The first silicon substrate 11, the stack 20, the first germanium-silicon layer 41, and the silicon dioxide or silicon nitride layer 50 are annealed to generate tensile stress inside the first germanium-silicon layer 41. Finally, the silicon dioxide or silicon nitride layer 50 located on top of the first germanium-silicon layer 41 is removed. During this process, due to the presence of silicon nitride material in the stacked layer 20 or the silicon nitride layer, more tensile stress is generated inside the first germanium-silicon layer 41 during the annealing of the semiconductor structure. At the same time, due to the limitation of the line trench pattern, large defects will not be generated in the first germanium-silicon layer 41 due to excessive tensile stress, thus achieving high-quality Si. x Ge 1-x The fabrication of the OI substrate involves first fabricating a first germanium-silicon layer 41 that meets the defect and tensile stress requirements in the first silicon substrate 11, and then bonding the first germanium-silicon layer 41 to the dielectric layer 13 of the second silicon substrate 12. This prevents contamination of the second silicon substrate 12 during the fabrication of the first germanium-silicon layer 41. Furthermore, when thinning the first germanium-silicon layer 41, the thinning begins from the portion of the first germanium-silicon layer 41 closest to the first silicon substrate 11, thereby reducing lattice defects within the retained first germanium-silicon layer 41 of the set thickness. This results in a thinner first germanium-silicon layer 41 with a more uniform tensile stress distribution and fewer lattice defects.

[0058] like Figures 5a-5e As shown, the semiconductor structure in this preparation method is similar to... Figures 4a-4e The method is basically the same, except that a second germanium-silicon layer 42 is grown on the first silicon substrate 11, and a stack 20 formed by alternating layers of silicon dioxide and silicon nitride is deposited on top of the second germanium-silicon layer 42. At this time, as... Figure 5d , Figure 5eAs shown, when removing the first silicon substrate 11 and the material between the first silicon substrate 11 and the first germanium-silicon layer 41, in addition to removing the remaining material in the first silicon substrate 11, the stacked layer 20, and the germanium-silicon material filling the trench pattern, it is also necessary to remove the second germanium-silicon layer 42. By first preparing a first germanium-silicon layer 41 that meets the defect and tensile stress requirements in the first silicon substrate 11, and then bonding the first germanium-silicon layer 41 to the dielectric layer 13 of the second silicon substrate 12, contamination of the second silicon substrate 12 during the preparation of the first germanium-silicon layer 41 is prevented. At the same time, when thinning the first germanium-silicon layer 41, the thinning starts from the portion of the first germanium-silicon layer 41 closest to the first silicon substrate 11, thereby reducing the number of lattice defects in the first germanium-silicon layer 41 of the set thickness, and enabling the preparation of a thinner first germanium-silicon layer 41 with a more uniform tensile stress distribution and fewer lattice defects.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A stack of alternating layers of silicon dioxide and silicon nitride is deposited on a first silicon substrate; The stack is etched from top to bottom to form a line groove pattern within the stack; The groove pattern contains multiple grooves, each groove penetrating the upper and lower surfaces of the stack. Germanium-silicon material is filled into the groove pattern, and a first germanium-silicon layer is formed on top of the stack; A silicon dioxide layer or a silicon nitride layer is formed above the first germanium-silicon layer; The first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer are annealed to generate tensile stress inside the first germanium-silicon layer. Remove the silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer.

2. The preparation method according to claim 1, characterized in that, Before depositing a stack of alternating layers of silicon dioxide and silicon nitride on the first silicon substrate, the fabrication method further includes: A second germanium-silicon layer is grown on the first silicon substrate, wherein the stacked layer formed by alternating layers of silicon dioxide and silicon nitride is deposited on top of the second germanium-silicon layer; Furthermore, while annealing the first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer, the second germanium-silicon layer is also annealed to generate tensile stress inside the second germanium-silicon layer.

3. The preparation method according to claim 1, characterized in that, The annealing treatment of the first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer includes: The annealing process of the first silicon substrate, stack, first germanium silicon layer and silicon dioxide layer or silicon nitride layer is completed after annealing in an annealing environment of 300℃~850℃ for 1min~3h.

4. The preparation method according to any one of claims 1 to 3, characterized in that, Also includes: A dielectric layer is deposited on a second silicon substrate; After removing the silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer, the first germanium-silicon layer on the first silicon substrate is bonded to the dielectric layer of the second silicon substrate. Remove the first silicon substrate and the material between the first silicon substrate and the first germanium-silicon layer, and thin the first germanium-silicon layer to a set thickness.

5. The preparation method according to claim 1, characterized in that, The material of the first germanium-silicon layer is Ge x Si 1-x , where 0≤x≤1.

6. The preparation method according to claim 5, characterized in that, When the thickness of the first germanium-silicon layer above the stack is less than the threshold thickness, x in the first germanium-silicon layer is a fixed value; When the thickness of the first germanium-silicon layer above the stack is not less than the threshold thickness, x in the first germanium-silicon layer is a gradual value; at this time, the value of x starts from 1 at the position adjacent to the first germanium-silicon layer and the stack, gradually decreases, and decreases to the minimum value min on the upper surface of the first germanium-silicon layer.

7. The preparation method according to claim 6, characterized in that, When x is a fixed value, 0.5 ≤ x < 1; When x is a gradually changing value, 0.5 ≤ min < 1.

8. The preparation method according to any one of claims 1 to 3, characterized in that, Also includes: A back-gate field-effect transistor is fabricated on the first germanium-silicon layer, wherein the channel in the back-gate field-effect transistor is a tensile-stressed germanium-silicon channel formed by etching the first germanium-silicon layer; or, A finned field-effect transistor is fabricated on the first germanium-silicon layer, wherein the channel in the finned field-effect transistor is a tensile-stressed germanium-silicon channel formed by etching the first germanium-silicon layer; or, A gate-all-around transistor is fabricated on the first germanium-silicon layer, wherein the channel in the gate-all-around transistor is a tensile-stressed germanium-silicon channel formed by etching the first germanium-silicon layer.

9. A semiconductor structure, characterized in that, include: First silicon substrate; A stack deposited on a first silicon substrate, the stack being formed by alternating layers of silicon dioxide and silicon nitride; wherein, a line trench pattern is etched in the stack; the line trench pattern includes a plurality of line trenches, each line trench penetrating the upper and lower surfaces of the stack; Germanium-silicon material filling the groove pattern and forming a first germanium-silicon layer on top of the stack; The first germanium-silicon layer is further treated in the following way to generate tensile stress within it: A silicon dioxide layer or a silicon nitride layer is formed above the first germanium-silicon layer; The first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer are subjected to annealing treatment; Remove the silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer.

10. A semiconductor structure, characterized in that, include: Second silicon substrate; A dielectric layer deposited on a second silicon substrate; A first germanium-silicon layer is bonded to the dielectric layer; wherein the first germanium-silicon layer is prepared in the following manner: A stack of alternating layers of silicon dioxide and silicon nitride is deposited on a first silicon substrate; The stack is etched from top to bottom to form a line groove pattern within the stack; the line groove pattern includes multiple line grooves, each line groove penetrating the upper and lower surfaces of the stack; Germanium-silicon material is filled into the groove pattern, and a first germanium-silicon layer is formed on top of the stack; A silicon dioxide layer or a silicon nitride layer is formed above the first germanium-silicon layer; The first silicon substrate, the stacked layer, the first germanium-silicon layer, and the silicon dioxide layer or silicon nitride layer are annealed to generate tensile stress inside the first germanium-silicon layer. Remove the silicon dioxide layer or silicon nitride layer located above the first germanium-silicon layer; The first germanium-silicon layer on the first silicon substrate is bonded to the dielectric layer of the second silicon substrate; Remove the first silicon substrate and the material between the first silicon substrate and the first germanium-silicon layer, and thin the first germanium-silicon layer to a set thickness.

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