Conversion device and conversion method of jtag interface to cjtag interface

Abstract

Provided is a conversion device and a conversion method of a JTAG interface to a cJTAG interface, wherein the conversion device comprises: an enabling device configured to use a TMS signal output by the JTAG interface as an enabling signal to enable a TDI signal output by the JTAG interface to be input to a TMSC pin of the cJTAG interface; and an output device configured to use a signal output by the TMSC pin of the cJTAG interface to be output to a TDO pin of the JTAG interface. In this way, the JTAG interface TMS signal and the TDI signal can be combined into a signal input to the TMSC pin of the cJTAG interface by using a simple circuit, and then the signal output by the TMSC pin of the cJTAG interface is obtained to be output to the TDO pin of the JTAG interface, thereby realizing the conversion of the JTAG interface to the cJTAG interface.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically to a JTAG interface to cJTAG interface conversion apparatus and conversion method. Background Technology

[0002] The IEEE 1149.1 standard defines a boundary scan technique called the Joint Test Action Group (JTAG). This standard requires at least four signal lines for debugging: TCK, TMS, TDI, and TDO (Test Clock, Test Mode Select, Test Data Input, and Test Data Output). To reduce the number of test pins and power consumption in modern chips, the IEEE 1149.7 standard introduced the compact boundary scan technique, compact JTAG (cJTAG), in 2009. This standard uses only two signals for boundary scanning: TMSC (Test Mode Select Counter, a type of test serial data) and TCK (Test Clock). However, currently, only a few commercially available JTAG debuggers, such as J-LINK, implement the cJTAG interface, resulting in high debugging costs.

[0003] There is a need for a low-cost solution for the conversion between JTAG and cJTAG interfaces, especially the conversion from JTAG to cJTAG. Summary of the Invention

[0004] According to one aspect of this application, a JTAG interface to cJTAG interface conversion device is provided, comprising: an enabling device configured to use a TMS signal output from the JTAG interface as an enabling signal to enable a TDI signal output from the JTAG interface, so as to input the TMSC pin of the cJTAG interface; and an output device configured to use a signal output from the TMSC pin of the cJTAG interface to output the signal to the TDO pin of the JTAG interface.

[0005] According to another aspect of this application, a method for converting a JTAG interface to a cJTAG interface is provided, comprising: enabling a TDI signal output by the JTAG interface by using the TMS signal output by the JTAG interface as an enable signal through an enabling device, so as to input the TMSC pin of the cJTAG interface; and outputting the signal output by the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface through an output device.

[0006] In this way, a simple circuit can be used to combine the TMS and TDI signals of the JTAG interface into a signal input to the TMSC pin of the cJTAG interface, and then obtain the signal output from the TMSC pin of the cJTAG interface to output to the TDO pin of the JTAG interface, thereby realizing the conversion from JTAG interface to cJTAG interface. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 An example block diagram of a debugging system is shown, including a JTAG interface to cJTAG interface conversion device according to an embodiment of this application.

[0009] Figure 2 An example block diagram of a JTAG interface to cJTAG interface conversion device according to an embodiment of this application is shown.

[0010] Figure 3 This is an example block diagram of a JTAG interface to cJTAG interface conversion device according to another embodiment of this application.

[0011] Figure 4 Example signal waveforms of four pin signals TCK, TMS, TDI, and TDO according to an embodiment of this application are shown.

[0012] Figure 5 A schematic flowchart of a method for converting a JTAG interface to a cJTAG interface according to an embodiment of this application is shown.

[0013] Figure 6 A schematic flowchart illustrating a method for converting a JTAG interface to a cJTAG interface according to a further embodiment of this application is shown.

[0014] Figure 7 This illustrates the typical structure of a JTAG interface. Detailed Implementation

[0015] Specific embodiments of this application will now be described in detail, with examples of the application illustrated in the accompanying drawings. Although this application will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit this application to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of this application as defined by the appended claims. It should be noted that the method steps described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0016] Figure 7 The typical structure of a JTAG interface 700 is shown.

[0017] The JTAG signals of the JTAG interface 700 include: TMS (Test Mode Select): This signal selects the test mode and controls the state of the JTAG state machine. TCK (Test Clock): The JTAG clock signal. TDI (Test Data Input): The test data input signal. TDO (Test Data Output): The test data output signal. nTRST (n Test Rest): The JTAG reset signal, used to reset the JTAG state machine and internal macrocells.

[0018] like Figure 7As shown, the Test Access Port (TAP) is a general-purpose port that provides access to all data registers (DR) 710 and instruction registers (IR) 720 provided by the chip. To configure devices in the JTAG chain, the programming software sets other devices to bypass mode. Devices in bypass mode transfer programming data from the TDI pin to the TDO pin through a single bypass register 730. When the chip is in debug mode, the boundary scan register (scan unit) 750 isolates the chip from the external input / output pins 760. The boundary scan register unit 750 allows for observation and control of the chip's external input / output pins. For the chip's output pins, signals (data) can be loaded into the pin through the connected boundary scan register unit; for the chip's input pins, the output signal on the pin can also be "captured" through the connected boundary scan register. Boundary scan (shift) register units on the chip pins can be interconnected to form a boundary scan chain around the chip. This chain can serially input and output, allowing for convenient observation and control of the chip during debugging using appropriate clock and control signals. When multiple boundary scan cells (BSCs) exist within the chip, a corresponding mechanism is needed to control access. Control of the entire TAP (Touch Shift Register) is accomplished through the TAP controller 740.

[0019] During testing, each JTAG unit can send test data input signals to the pins of the IC being debugged / tested via the TDI pin, and listen to the bit status output from the corresponding pin of the IC being debugged / tested via the TDO pin of the JTAG unit.

[0020] The TAP controller has 16 synchronization states: Test-Logic-Reset, Run-Test-Idle, Select-DR-Scan, Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, Update-DR, Select-IR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR. The next state of the controller is determined by the TMS signal, which is sampled and activated on the rising edge of the TCK.

[0021] During the instruction register access process, the system powers on, and the TAP controller enters the Test-Logic Reset state. The sequence is: Run-Test / Idle -> Select-DR-Scan -> Select-IR-Scan -> Capture-IR -> Shift-IR -> Exit1-IR -> Update-IR, finally returning to the Run-Test / Idle state. In the Capture-IR state, a specific logic sequence is loaded into the instruction register; then it enters the Shift-IR state.

[0022] In the data register access process, the currently accessible data registers are determined by the current instruction in the instruction register. Starting from Run-Test / Idle, the process sequentially enters Select-DR-Scan->Capture-DR->Shift-DR->Exit1-DR->Update-DR, finally returning to the Run-Test / Idle state.

[0023] Existing JTAG boundary scan testing methods are struggling to meet the challenges from multiple aspects, including testing, debugging, and functionality: during testing, multiple test access ports (TAPs) need to be controlled and scanned simultaneously; during debugging, the scan chain length needs to be shortened and debugging data transmission needs to be supported; and functionally, the number of test pins needs to be reduced and lower power consumption needs to be achieved.

[0024] Against this backdrop, the Bus Testability Standards Committee approved the IEEE 1149.7 standard in 2009, proposing the compact boundary scan technology cJTAG. CTAG uses the TCK and TMS pins to control the state process of the TAP controller (supporting the IEEE 1149.x standard), and the TDI and TDO pins to transmit test data. cJTAG, on the other hand, uses the Test Clock Counter (TCKC) and Test Mode Select Counter (TMSC) pins to not only control the TAP state process but also to transmit test data. The Test Data Input Counter (TDIC) and Test Data Output Counter (TDOC) pins can be left idle or used for other functions (not used in this paper).

[0025] Currently, various circuit chips supporting cJTAG testing have been designed. However, many debuggers using JTAG interfaces still do not support direct debugging / testing of circuit chips with cJTAG interfaces, and only a few commercially available JTAG debuggers, such as J-LINK, support debugging the cJTAG interface, resulting in high debugging costs.

[0026] Therefore, a low-cost solution is needed for the conversion between JTAG and cJTAG interfaces, especially the conversion from JTAG to cJTAG.

[0027] This application designs a low-cost connection scheme between JTAG and cJTAG interfaces. It utilizes the commonly used chip debugger from FTDI (Fittec Inc.), making full use of FTDI's existing standard JTAG interface, and thus combining it with OpenOCD (Open On-Chip Debugger) to debug fifth-generation reduced instruction set (RISC-V) central processing units (CPUs).

[0028] Figure 1 An example block diagram of a debugging system 100 including a JTAG interface to cJTAG interface conversion device 130 according to an embodiment of this application is shown.

[0029] like Figure 1 As shown, the FDTI chip is used as a JTAG debugger, combined with the OpenOCD on-chip debugger to perform debugging, system programming and boundary scan functions on the RISC-V CPU.

[0030] The FDTI chip uses a JTAG interface, while the RISC-V CPU uses a cJTAG interface.

[0031] Figure 1The debugging system 100 includes: a computer PC 110, which includes an OpenOCD on-chip debugger and an FDTI driver; a JTAG debugger 120 utilizing an FDTI chip; a JTAG interface to cJTAG interface converter 130 (or cJTAG adapter for short); and a RISC-V CPU, including a cJTAG to JTAG converter 140 and a RISC-V debugging module 150.

[0032] The JTAG interface to cJTAG interface conversion device 130 includes: an enable device 131 configured to use the TMS signal output from the JTAG interface as an enable signal to enable the TDI signal output from the JTAG interface, so as to input it to the TMSC pin of the cJTAG interface; and an output device 132 configured to use the signal output from the TMSC pin of the cJTAG interface to output it to the TDO pin of the JTAG interface.

[0033] In this way, the TMS and TDI signals of the JTAG interface can be combined into a signal input to the TMSC pin of the cJTAG interface using a simple circuit. Then, the signal output from the TMSC pin of the cJTAG interface can be obtained and output to the TDO pin of the JTAG interface, thereby realizing the conversion from JTAG interface to cJTAG interface.

[0034] Figure 2 An example block diagram of a JTAG interface to cJTAG interface conversion device 130 according to an embodiment of this application is shown.

[0035] like Figure 2 As shown, the enabling device 131 includes a first tri-state buffer 1311, wherein the TMS pin of the JTAG interface is connected to the high-level active enable terminal of the first tri-state buffer 1311, the TDI pin of the JTAG interface is connected to the input terminal of the first tri-state buffer 1311, and the output terminal of the first tri-state buffer 1311 is connected to the TMSC pin of the cJTAG interface.

[0036] In one embodiment, the enable terminal of the first tri-state buffer 1311 is also connected to the ground voltage.

[0037] A three-state buffer, also known as a three-state gate or three-state driver, has its output controlled by an enable input. When the enable input is active, the device outputs in its normal logic state (logic 0, logic 1), performing no operations on the input value; the output value is the same as the input value. When the enable input is inactive, the output of the three-state buffer is in a high-impedance state, equivalent to being disconnected from the connected circuit.

[0038] Therefore, in Figure 2In this configuration, the TMS pin of the JTAG interface is connected to the high-level enabled terminal of the first tri-state buffer 1311, making the TMS signal of the JTAG interface's TMS pin the enable signal for enabling the output of the tri-state buffer. For example, when the TMS signal of the JTAG interface's TMS pin is high, the TDI signal of the JTAG interface's TDI pin is output from the input terminal to the output terminal of the first tri-state buffer 1311, and thus output to the TMSC pin of the cJTAG interface. When the TMS signal of the JTAG interface's TMS pin is low, the output of the tri-state buffer is in a high-impedance state, which is equivalent to disconnecting the TDI pin of the JTAG interface from the TMSC pin of the cJTAG interface.

[0039] In one embodiment, the enable terminal of the first tri-state buffer 1311 is connected to ground via a first resistor, wherein the resistance of the first resistor is greater than a first predetermined threshold. The resistance of the first resistor can be, for example, 10K ohms. Of course, this value is merely an example and not a limitation. Setting the resistance of the first resistor to a higher level makes the signal level output by the TMS pin higher, preventing it from quickly returning to zero, which is more beneficial for the enable signal of the first tri-state buffer.

[0040] In one embodiment, the enabling device 131 further includes a resistor between the output of the first tri-state buffer 1311 and the TMSC pin. For example, the resistor has a resistance of 27 ohms.

[0041] In one embodiment, the output device 132 may be a signal line that directly connects the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface.

[0042] However, at this time, there is no delay in the signal transmission from the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface, which may cause it to be out of sync with the signal from the TDI pin of the JTAG interface to the TMSC pin of the cJTAG interface. Therefore, as follows, the output device 132 may include a second tri-state buffer 1321 to make the signals on both sides more synchronized.

[0043] In one embodiment, the output device 132 includes a second tri-state buffer 1321, wherein the TMSC pin of the cJTAG interface is connected to the input terminal of the second tri-state buffer 1321, the high-level active enable terminal of the second tri-state buffer 1321 is connected to the power supply voltage VCC, and the output terminal of the second tri-state buffer 1321 is connected to the TDO pin of the JTAG interface.

[0044] In one embodiment, the enable terminal of the second tri-state buffer 1321 is connected to the power supply voltage VCC via a second resistor, wherein the resistance of the second resistor is greater than a second predetermined threshold. For example, the resistance of the second resistor is 4.7K ohms. This value is merely an example and not a limitation; setting the resistance of the second resistor to be larger is mainly for current limiting.

[0045] By connecting the power supply voltage VCC to the high-level enable pin of the second tri-state buffer 1321, the second tri-state buffer 1321 is always enabled. That is, the TMSC signal of the TMSC pin of the cJTAG interface can be output from the input to the output of the second tri-state buffer 1321, and thus output to the TDO pin of the JTAG interface. Since the power supply voltage VCC is always high, the TMSC signal of the TMSC pin of the cJTAG interface can be directly output to the TDO pin of the JTAG interface.

[0046] In one embodiment, the output device further includes a resistor between the output terminal of the second tri-state buffer 1321 and the TDO pin of the JTAG interface, and a resistor between the input terminal of the second tri-state buffer 1321 and the TMSC pin of the cJTAG interface. For example, the resistance of the resistor is 27 ohms.

[0047] In one embodiment, the TCK pin of the JTAG interface is connected to the TCKC pin of the cJTAG interface via a resistor. For example, the resistor has a resistance of 27 ohms.

[0048] In one embodiment, the tri-state buffer is a general-purpose tri-state buffer or a dual-gate tri-state buffer.

[0049] The main function of the 27-ohm resistors in these peripheral circuits is impedance matching.

[0050] In one embodiment, the above-mentioned tri-state buffer can be a general-purpose tri-state buffer chip 74LVT126D or a dual-gate tri-state buffer chip SN74LVC2G126.

[0051] Figure 3 This is an example block diagram of a JTAG interface to cJTAG interface conversion device 130 according to another embodiment of this application.

[0052] In this embodiment, the enabling device 131 includes a third tri-state buffer 1311', wherein the TMS pin of the JTAG interface is connected to the low-level active enable terminal of the third tri-state buffer 1311' via an inverter 1312, the TDI pin of the JTAG interface is connected to the input terminal of the third tri-state buffer 1311', and the output terminal of the third tri-state buffer 1311' is connected to the TMSC pin of the cJTAG interface.

[0053] Thus, for example, when the TMS signal on the TMS pin of the JTAG interface is high, it is changed to low by the inverter 1312. This enables the low-level active enable terminal of the third tri-state buffer 1311', allowing the TDI signal of the TDI pin of the JTAG interface to be output from the input terminal to the output terminal of the third tri-state buffer 1311', and thus output to the TMSC pin of the cJTAG interface. Conversely, when the TMS signal on the TMS pin of the JTAG interface is low, it is changed to high by the inverter 1312. This disables the low-level active enable terminal of the third tri-state buffer 1311', resulting in a high-impedance output of the tri-state buffer, which is equivalent to disconnecting the TDI pin of the JTAG interface from the TMSC pin of the cJTAG interface.

[0054] In one embodiment, the enabling device 131 further includes a resistor between the output of a third tri-state buffer 1311' and the TMSC pin. For example, the resistor has a resistance of 27 ohms.

[0055] In one embodiment, the output device 132 includes a fourth tri-state buffer 1321', wherein the TMSC pin of the cJTAG interface is connected to the input of the fourth tri-state buffer 1321', the low-level active enable pin of the fourth tri-state buffer 1321' is connected to ground voltage GND, and the output of the fourth tri-state buffer 1321' is connected to the TDO pin of the JTAG interface.

[0056] By connecting the ground voltage GND to the low-level active enable pin of the fourth tri-state buffer 1321', the fourth tri-state buffer 1321' is always enabled. That is, the TMSC signal of the TMSC pin of the cJTAG interface can be output from the input of the second tri-state buffer 1321 to the output of the fourth tri-state buffer 1321', and thus to the TDO pin of the JTAG interface. Since the ground voltage GND is always low, the TMSC signal of the TMSC pin of the cJTAG interface can be directly output to the TDO pin of the JTAG interface.

[0057] In one embodiment, the output device 132 further includes a resistor between the output terminal of the fourth tri-state buffer 1321' and the TDO pin of the JTAG interface, and a resistor between the input terminal of the fourth tri-state buffer 1321' and the TMSC pin of the cJTAG interface. For example, the resistance of the resistor is 27 ohms.

[0058] Figure 2 and Figure 3 The use of a tri-state buffer is merely a specific implementation method for enabling and output devices, but it is not a limitation. Other methods can actually be used, such as direct signal line connection or other enabling circuits. Furthermore, Figure 2 and Figure 3 The tri-state buffers in the enable and output devices can be interchanged and combined. For example, the enable device can use a high-level active tri-state buffer, while the output device can use a low-level active tri-state buffer, and so on.

[0059] return Figure 1 The RISC-V CPU being debugged, for example, may include a cJTAG to JTAG converter 140 and a RISC-V debug module 150. Internally, the RISC-V CPU being debugged still uses the four signals of the JTAG interface: TCK, TMS, TDI, and TDO. Therefore, the RISC-V CPU internally needs to use the cJTAG to JTAG converter 140 (cjtag2jtag) to convert the two cJTAG signals, TCKC and TMSC, back to the four JTAG signals: TCK, TMS, TDI, and TDO, before transmitting them to the RISC-V debug module for debugging.

[0060] like Figure 1 As shown, the specific debugging operation method is as follows:

[0061] (1) The FTDI driver 110 communicates with the FTDI chip 120 through the Universal Serial Bus (USB) interface and transmits JTAG signals / instructions to the cJTAG adapter 130;

[0062] (2) The FTDI driver 110 transmits the received JTAG signal / instruction to the cJTAG adapter 130, and the cJTAG adapter 130 converts the JTAG signal / instruction into the corresponding cJTAG signal / instruction.

[0063] (3) The cJTAG adapter 130 merges the JTAG signal from the host computer into a cJTAG signal and transmits it (through the TCKC pin and the TMSC pin) to the device under test (RISC-V) for debugging.

[0064] (4) The cJTAG adapter 130 will also convert the cJTAG output signal (via the TMSC pin) of the device being debugged (RISC-V) into a JTAG signal (via the TDO pin) and transmit it to the FTDI driver.

[0065] During JTAG signal / command transmission, OpenOCD uses the TDI pin to send data and the TDO pin to receive data sent back by the device being debugged. The TMS pin signal is used to control whether data is sent via the TDI pin, and the TCK pin is used for clock synchronization between devices.

[0066] Specifically, during the data transmission process from the host computer, OpenOCD first pulls the TMS signal high to enable the output of the tri-state buffer, uses the TDI pin to send data, and outputs a signal to the device under test through the TMSC pin.

[0067] During the data reception process of the host computer, the tri-state buffer of the TDO pin on the host computer receiving side is enabled by default. The device under test directly uses the TMSC pin to send output data to the TDO pin through the tri-state buffer, such as the chip 74LVT126D.

[0068] Figure 4 Example signal waveforms of four pin signals TCK, TMS, TDI, and TDO according to an embodiment of this application are shown.

[0069] like Figure 4 As shown, when the signal on the TMS pin is high, the test data input signal on the TDI pin is valid due to the tri-state buffer being enabled, and can be output to the TMSC pin of the cJTAG interface by the tri-state buffer. However, when the signal on the TMS pin is low, the test data input signal on the TDI pin is invalid due to the tri-state buffer being disabled.

[0070] The output signal of the device under test, which is output from the TMSC pin of the cJTAG interface, can be continuously output to the TDO pin of the JTAG interface.

[0071] Of course, the TMSC pin of the cJTAG interface is bidirectional. Because the tri-state buffer isolates the input and output signals, there will be no conflict between the input and output signals during the entire transmission process. Figure 4 As shown, the test input signal transmitted from the TDI pin to the device under test is only valid when the signal on the TMS pin is high, while the test output signal transmitted from the device under test to the host computer is valid at all times. This test output signal can be transmitted even when the TMSC pin of the cJTAG interface is not transmitting a test input signal.

[0072] Of course, this is just an example of enabling the TMS pin when the signal is high and disabling it when the signal is low. However, this application is not limited to this example. In fact, it is also possible to specify that the TMS pin is enabled when the signal is low. This can be achieved simply by adding an inverter or other circuitry or operation.

[0073] Thus, using a tri-state buffer allows the signal output from the TCK pin of the JTAG interface to be transmitted as a TCKC signal to the TCKC pin of the cJTAG interface of the device being debugged, such as a RISC-V CPU. Similarly, the TDI signal output from the TDI pin of the JTAG interface, after being enabled by the TMS signal output from the TMS pin of the JTAG interface, is transmitted as a TMSC signal to the TMSC pin of the cJTAG interface of the device being debugged, such as a RISC-V CPU. By using a tri-state buffer and external circuitry such as resistors, the JTAG signal is converted into a cJTAG signal for communication with the device being debugged, simplifying both software and hardware design. Therefore, by adding a simple conversion circuit to the currently used FTDI JTAG debugging circuit at extremely low cost, the full functionality of current JTAG debuggers can be fully utilized to achieve all the functions of cJTAG debugging.

[0074] Figure 5 A schematic flowchart of a method for converting a JTAG interface to a cJTAG interface according to an embodiment of this application is shown.

[0075] like Figure 5 As shown, the JTAG interface to cJTAG interface conversion method 500 includes: step 510, using the TMS signal output by the JTAG interface as an enable signal through an enable device to enable the TDI signal output by the JTAG interface, so as to input it to the TMSC pin of the cJTAG interface; step 520, using the signal output by the TMSC pin of the cJTAG interface through an output device to output it to the TDO pin of the JTAG interface.

[0076] In this way, the TMS and TDI signals of the JTAG interface can be combined into a signal input to the TMSC pin of the cJTAG interface using a simple circuit. Then, the signal output from the TMSC pin of the cJTAG interface can be obtained and output to the TDO pin of the JTAG interface, thereby realizing the conversion from JTAG interface to cJTAG interface.

[0077] Figure 6 A schematic flowchart of a JTAG interface to cJTAG interface conversion method 600 according to a further embodiment of this application is shown.

[0078] In one embodiment, the enabling device includes a first tri-state buffer, wherein the TMS pin of the JTAG interface is connected to the high-active enable pin of the first tri-state buffer, the TDI pin of the JTAG interface is connected to the input pin of the first tri-state buffer, and the output pin of the first tri-state buffer is connected to the TMSC pin of the cJTAG interface. In this embodiment, the output device includes a second tri-state buffer, wherein the TMSC pin of the cJTAG interface is connected to the input pin of the second tri-state buffer, the high-active enable pin of the second tri-state buffer is connected to the power supply voltage, and the output pin of the second tri-state buffer is connected to the TDO pin of the JTAG interface.

[0079] Using the enabling device and output device in this embodiment, the method 600 includes: step 610, using the enabling device to use the TMS signal output from the TMS pin of the JTAG interface as an enabling signal, to: enable the output of the TDI signal from the TDI pin of the JTAG interface to the TMSC pin of the cJTAG interface when the TMS signal is at a first level, and disconnect the TDI pin of the JTAG interface and the TMSC pin of the cJTAG interface when the TMS signal is at a second level; step 620, using the output device to output the TMSC signal output from the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface. The first level can be a high level, and the second level can be a low level.

[0080] In another embodiment, the enabling device includes a third tri-state buffer, wherein the TMS pin of the JTAG interface is connected to the low-active enable pin of the third tri-state buffer via an inverter, the TDI pin of the JTAG interface is connected to the input pin of the third tri-state buffer, and the output pin of the third tri-state buffer is connected to the TMSC pin of the cJTAG interface. The output device includes a fourth tri-state buffer, wherein the TMSC pin of the cJTAG interface is connected to the input pin of the fourth tri-state buffer, the low-active enable pin of the fourth tri-state buffer is connected to ground, and the output pin of the fourth tri-state buffer is connected to the TDO pin of the JTAG interface.

[0081] Using the enabling device and output device in this other embodiment, the method 600 includes: step 610, using the enabling device to use the TMS signal output from the TMS pin of the JTAG interface as an enabling signal, to: enable the output of the TDI signal from the TDI pin of the JTAG interface to the TMSC pin of the cJTAG interface when the TMS signal is at a first level, and disconnect the TDI pin of the JTAG interface and the TMSC pin of the cJTAG interface when the TMS signal is at a second level; step 620, using the output device to output the TMSC signal output from the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface. The first level can be a high level, and the second level can be a low level.

[0082] The aforementioned tri-state buffer can be a general-purpose tri-state buffer or a dual-gate tri-state buffer.

[0083] Thus, using a tri-state buffer allows the signal output from the TCK pin of the JTAG interface to be transmitted as a TCKC signal to the TCKC pin of the cJTAG interface of the device being debugged, such as a RISC-V CPU. Similarly, the TDI signal output from the TDI pin of the JTAG interface, after being enabled by the TMS signal output from the TMS pin of the JTAG interface, is transmitted as a TMSC signal to the TMSC pin of the cJTAG interface of the device being debugged, such as a RISC-V CPU. By using a tri-state buffer and external circuitry such as resistors, the JTAG signal is converted into a cJTAG signal for communication with the device being debugged, simplifying both software and hardware design. Therefore, by adding a simple conversion circuit to the currently used FTDI JTAG debugging circuit at extremely low cost, the full functionality of current JTAG debuggers can be fully utilized to achieve all the functions of cJTAG debugging.

[0084] Of course, the specific embodiments described above are merely examples and not limitations. Those skilled in the art can combine and integrate some steps and devices from the various embodiments described separately above to achieve the effects of this application based on the concept of this application. Such combined and integrated embodiments are also included in this application, but will not be described one by one here.

[0085] Note that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of the various embodiments of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations; these details do not restrict this application from being implemented using the aforementioned specific details.

[0086] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0087] The flowcharts and method descriptions in this disclosure are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the given order. As those skilled in the art will recognize, the steps in the above embodiments can be performed in any order. Words such as "then," "next," etc., are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. Furthermore, any reference to a singular element, such as the use of the articles "a," "one," or "the," is not to be construed as limiting that element to the singular.

[0088] Furthermore, the steps and apparatus in the various embodiments herein are not limited to any one embodiment. In fact, new embodiments can be conceived by combining relevant steps and apparatus in the various embodiments herein based on the concepts of this application, and these new embodiments are also included within the scope of this application.

[0089] The various operations of the methods described above can be performed by any suitable means capable of performing the corresponding functions. Such means may include various hardware and / or software components and / or modules, including but not limited to hardware circuits, application-specific integrated circuits (ASICs), or processors.

[0090] The various exemplified logic blocks, modules, and circuits described herein can be implemented or performed using a general-purpose processor, digital signal processor (DSP), ASIC, field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor, but alternatively, it can be any commercially available processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a microprocessor cooperating with a DSP core, or any other such configuration.

[0091] The steps of the methods or algorithms described in this disclosure can be directly embedded in hardware, in a software module executed by a processor, or a combination of both. The software module can reside in any form of tangible storage medium. Some examples of storage media that can be used include random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, etc. The storage medium can be coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integral with the processor. The software module can be a single instruction or many instructions, and can be distributed across several different code segments, different programs, and across multiple storage media.

[0092] The methods disclosed herein include actions for implementing the described methods. The methods and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions may be modified without departing from the scope of the claims.

[0093] The above functions can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as instructions on a tangible computer-readable medium. The storage medium can be any available tangible medium that can be accessed by a computer. By way of example and not limitation, such a computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital universal disc (DVD), floppy disk, and Blu-ray disc, wherein a disc typically magnetically reproduces data, while a disc optically reproduces data using lasers.

[0094] Therefore, a computer program product can perform the operations given herein. For example, such a computer program product can be a computer-readable tangible medium having instructions tangibly stored (and / or encoded) thereon, which can be executed by a processor to perform the operations described herein. The computer program product may include packaging materials.

[0095] Software or instructions can also be transmitted via a transmission medium. For example, software can be transmitted from a website, server, or other remote source using transmission media such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave.

[0096] Furthermore, modules and / or other suitable means for carrying out the methods and techniques described herein can be downloaded and / or obtained by user terminals and / or base stations as appropriate. For example, such a device can be coupled to a server to facilitate the transmission of means for carrying out the methods described herein. Alternatively, the various methods described herein can be provided via storage components (e.g., RAM, ROM, physical storage media such as CDs or floppy disks) so that user terminals and / or base stations can obtain the various methods when coupled to the device or when storage components are provided to the device. Furthermore, any other suitable techniques for providing the methods and techniques described herein to the device can be utilized.

[0097] Other examples and implementations are within the scope and spirit of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various places, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein, including as used in the claims, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not mean that the described examples are preferred or better than other examples.

[0098] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0099] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0100] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A conversion device for the Joint Test Workgroup JTAG interface to the Compact Joint Test Workgroup cJTAG interface, comprising: The enabling device is configured to use the test mode selection TMS signal output from the JTAG interface as an enable signal to enable the test data input TDI signal output from the JTAG interface, so as to input the test mode selection counter TMSC pin of the cJTAG interface. The output device is configured to use the signal output from the TMSC pin of the cJTAG interface to output the test data output TDO pin of the JTAG interface.

2. The conversion device according to claim 1, wherein, The enabling device includes a first tri-state buffer, wherein the TMS pin of the JTAG interface is connected to the high-level active enable terminal of the first tri-state buffer, the TDI pin of the JTAG interface is connected to the input terminal of the first tri-state buffer, and the output terminal of the first tri-state buffer is connected to the TMSC pin of the cJTAG interface.

3. The conversion device according to claim 2, wherein, The enable terminal of the first tri-state buffer is also connected to the ground voltage.

4. The conversion device according to claim 3, wherein, The enable terminal of the first tri-state buffer is connected to the ground voltage through a first resistor, wherein the resistance of the first resistor is greater than a first predetermined threshold.

5. The conversion device according to claim 2, wherein, The enabling device also includes a resistor between the output of the first tri-state buffer and the TMSC pin.

6. The conversion device according to claim 3, wherein, The output device includes a second tri-state buffer, wherein the TMSC pin of the cJTAG interface is connected to the input terminal of the second tri-state buffer, the high-level active enable terminal of the second tri-state buffer is connected to the power supply voltage, and the output terminal of the second tri-state buffer is connected to the TDO pin of the JTAG interface.

7. The conversion device according to claim 6, wherein, The enable terminal of the second tri-state buffer is connected to the power supply voltage through a second resistor, wherein the resistance of the second resistor is greater than a second predetermined threshold.

8. The conversion device according to claim 6, wherein, The output device further includes a resistor between the output terminal of the second tri-state buffer and the TDO pin of the JTAG interface, and a resistor between the input terminal of the second tri-state buffer and the TMSC pin of the cJTAG interface.

9. The conversion device according to claim 1, wherein, The enabling device includes a third tri-state buffer, wherein the TMS pin of the JTAG interface is connected to the low-level active enable terminal of the third tri-state buffer via an inverter, the TDI pin of the JTAG interface is connected to the input terminal of the third tri-state buffer, and the output terminal of the third tri-state buffer is connected to the TMSC pin of the cJTAG interface.

10. The conversion device according to claim 9, wherein, The enabling device also includes a resistor between the output of the third tri-state buffer and the TMSC pin.

11. The conversion device according to claim 1, wherein, The output device includes a fourth tri-state buffer, wherein the TMSC pin of the cJTAG interface is connected to the input of the fourth tri-state buffer, the low-level active enable pin of the fourth tri-state buffer is connected to ground, and the output of the fourth tri-state buffer is connected to the TDO pin of the JTAG interface.

12. The conversion device according to claim 11, wherein, The output device further includes a resistor between the output terminal of the fourth tri-state buffer and the TDO pin of the JTAG interface, and a resistor between the input terminal of the fourth tri-state buffer and the TMSC pin of the cJTAG interface.

13. The conversion device according to claim 1, wherein, The test clock TCK pin of the JTAG interface is connected to the test clock counter TCKC pin of the cJTAG interface through a resistor.

14. The conversion device according to any one of claims 2-12, wherein, The tri-state buffer is a general-purpose tri-state buffer or a dual-gate tri-state buffer.

15. A method for converting a Joint Test Workgroup JTAG interface to a Compact Joint Test Workgroup cJTAG interface, comprising: The test mode selection (TMS) signal output by the JTAG interface is used as the enable signal to enable the test data input (TDI) signal output by the JTAG interface, which is then input to the test mode selection counter (TMSC) pin of the cJTAG interface. The signal output from the TMSC pin of the cJTAG interface is used by the output device to output the test data output TDO pin of the JTAG interface.

16. The conversion method according to claim 15, wherein, The enabling device includes a first tri-state buffer, wherein the TMS pin of the JTAG interface is connected to the high-active enable pin of the first tri-state buffer, the TDI pin of the JTAG interface is connected to the input pin of the first tri-state buffer, and the output pin of the first tri-state buffer is connected to the TMSC pin of the cJTAG interface. The method includes: using the TMS signal output from the TMS pin of the JTAG interface as an enable signal through the enabling device, to: When the TMS signal is at the first level, the TDI signal output from the TDI pin of the JTAG interface is enabled to be output to the TMSC pin of the cJTAG interface, and When the TMS signal is at the second level, disconnect the TDI pin of the JTAG interface and the TMSC pin of the cJTAG interface.

17. The conversion method according to claim 15, wherein, The output device includes a second tri-state buffer, wherein the TMSC pin of the cJTAG interface is connected to the input terminal of the second tri-state buffer, the high-level active enable terminal of the second tri-state buffer is connected to the power supply voltage, and the output terminal of the second tri-state buffer is connected to the TDO pin of the JTAG interface. The method includes: outputting the TMSC signal from the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface through the output device.

18. The conversion method according to claim 15, wherein, The enabling device includes a third tri-state buffer, wherein the TMS pin of the JTAG interface is connected to the low-active enable pin of the third tri-state buffer via an inverter, the TDI pin of the JTAG interface is connected to the input pin of the third tri-state buffer, and the output pin of the third tri-state buffer is connected to the TMSC pin of the cJTAG interface. The method includes: using the TMS signal output from the TMS pin of the JTAG interface as an enable signal through the enabling device, to: When the TMS signal is at the first level, the TDI signal output from the TDI pin of the JTAG interface is enabled to be output to the TMSC pin of the cJTAG interface, and When the TMS signal is at the second level, disconnect the TDI pin of the JTAG interface and the TMSC pin of the cJTAG interface.

19. The conversion method according to claim 15, wherein, The output device includes a fourth tri-state buffer, wherein the TMSC pin of the cJTAG interface is connected to the input terminal of the fourth tri-state buffer, the low-level active enable terminal of the fourth tri-state buffer is connected to ground, and the output terminal of the fourth tri-state buffer is connected to the TDO pin of the JTAG interface. The method includes: outputting the TMSC signal from the TMSC pin of the cJTAG interface to the TDO pin of the JTAG interface through the output device.

20. The conversion method according to any one of claims 16-19, wherein, The tri-state buffer is a general-purpose tri-state buffer or a dual-gate tri-state buffer.

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