Display panel and display device

Abstract

Embodiments of the present disclosure provide a display panel and a display device, relating to the technical field of display, for improving the quality of image display. The display panel comprises a display area, at least one aperture area, and a hole edge area between the aperture area and the display area, and the hole edge area surrounds the aperture area. The hole edge area comprises a wiring area and a packaging area arranged in sequence along a first direction, and the first direction is the direction of the display area pointing to the aperture area. The display panel further comprises a substrate, a first semiconductor layer and at least one layer of silicon nitride layer arranged in sequence. Wherein, in the packaging area, a plurality of first exhaust holes are arranged on the display panel, and each of the plurality of first exhaust holes penetrates each of the at least one layer of silicon nitride layer. Each of the plurality of first exhaust holes penetrates from the side opposite to the substrate of the display panel to the first semiconductor layer. The above-mentioned display panel is used for displaying images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, high contrast, and flexible display. Summary of the Invention

[0003] The purpose of the embodiments disclosed herein is to provide a display panel and display device for improving the problem of uneven brightness at low gray levels during image display and improving the image quality of the display.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display panel is provided, comprising: a display area, at least one aperture area, and an aperture edge area located between the aperture area and the display area, wherein the aperture edge area surrounds the aperture area. The aperture edge area includes: a trace area and a packaging area sequentially disposed along a first direction, wherein the first direction is the direction from the display area to the aperture area. The display panel further includes: a substrate, a first semiconductor layer, and at least one silicon nitride layer sequentially stacked. In the packaging area, the display panel has a plurality of first vent holes, each of the plurality of first vent holes penetrating each of the at least one silicon nitride layer. Each of the plurality of first vent holes penetrates from the side of the display panel opposite to the substrate to the first semiconductor layer.

[0006] In the aforementioned display panel, the first vent hole, which penetrates all the silicon nitride layers in the inorganic film layer, allows a large amount of hydrogen gas present in the silicon nitride layer to be discharged from the display panel, preventing bright spots from appearing at the edge of the hole and solving the problem of uneven brightness at the edge of the hole in the display panel.

[0007] In some embodiments, the plurality of first vent holes are arranged at intervals around the opening area.

[0008] In some embodiments, the arrangement density of the first exhaust holes gradually decreases along the first direction.

[0009] In some embodiments, the cross-sectional shape of the first vent is any one of square, triangular, pentagonal, hexagonal, and circular, wherein the plane containing the cross-section is parallel to the plane containing the substrate.

[0010] In some embodiments, the display panel further includes: a first gate insulating layer, a second gate insulating layer, a first inorganic insulating layer, a second inorganic insulating layer, a third gate insulating layer, an interlayer dielectric layer, and a passivation layer disposed on the side of the first semiconductor layer away from the substrate. The at least one silicon nitride layer includes: the second gate insulating layer, the first inorganic insulating layer, and the passivation layer. The first vent hole penetrates the passivation layer, the interlayer dielectric layer, the third gate insulating layer, the second inorganic insulating layer, the first inorganic insulating layer, the second gate insulating layer, and the first gate insulating layer.

[0011] In some embodiments, in the wiring area, the display panel further includes a second semiconductor layer disposed between the second inorganic insulating layer and the third gate insulating layer. In the wiring area, the display panel is provided with a plurality of second vent holes, each of the plurality of second vent holes extending from a side opposite to the substrate of the display panel through to the second semiconductor layer.

[0012] In some embodiments, in the wiring area, the display panel is provided with a plurality of third vent holes, each of the plurality of third vent holes penetrating each of the at least one silicon nitride layer, and each of the plurality of third vent holes penetrating from the side opposite to the substrate of the display panel to the first semiconductor layer.

[0013] In some embodiments, the display panel includes a first vent, a second vent, and a third vent, wherein the size of the first vent, the second vent, and the third vent ranges from 0.5 μm to 3 μm.

[0014] In some embodiments, the display panel includes: a plurality of pixel driving circuits and a plurality of light-emitting devices, wherein one of the plurality of pixel driving circuits is used to drive one of the plurality of light-emitting devices to emit light; the pixel driving circuit includes a second light-emitting control transistor. The first semiconductor layer includes a first electrode region and a second electrode region of the second light-emitting control transistor.

[0015] The display panel further includes: a first gate conductive layer disposed on the side of the first semiconductor layer away from the substrate; the first gate conductive layer includes: a light emission control signal line and a gate pattern of the second light emission control transistor, wherein the gate pattern of the second light emission control transistor is electrically connected to the light emission control signal line.

[0016] The display panel further includes: a first source / drain metal layer disposed on the side of the first gate conductive layer away from the substrate. The first source / drain metal layer includes a first pattern, and the first pattern is electrically connected to the second electrode region of the second light-emitting control transistor. The display panel further includes: an anode layer disposed on the side of the first source / drain metal layer away from the substrate, the anode layer including the anode pattern of the light-emitting device. The first pattern is electrically connected to the anode pattern. The overlapping area of ​​the first pattern and the light-emitting control signal line projected orthographically onto the substrate is greater than 10% of the area of ​​the first pattern projected orthographically onto the substrate.

[0017] In some embodiments, the ratio of the overlapping area of ​​the first pattern and the orthographic projection of the light-emitting control signal line on the substrate to the area of ​​the orthographic projection of the first pattern on the substrate is 25%.

[0018] In some embodiments, the display panel includes a plurality of light-emitting devices, including a plurality of red light-emitting devices, a plurality of green light-emitting devices, and a plurality of blue light-emitting devices. The display panel further includes a second source / drain metal layer disposed on the side of the first semiconductor layer away from the substrate, the second source / drain metal layer including a plurality of data signal lines and a plurality of power signal lines. Both the plurality of data signal lines and the plurality of power signal lines extend along a second direction. Specifically, along a third direction, every two data signal lines and every two power signal lines are alternately arranged, and the second direction and the third direction intersect.

[0019] In the third direction, adjacent power signal lines, data signal lines, and power signal lines constitute a signal line group. The display panel further includes an anode layer disposed on the side of the second source / drain metal layer away from the substrate, the anode layer comprising a third anode pattern for each of the plurality of blue light-emitting devices. One of the third anode patterns overlaps with the orthographic projection of one of the signal line groups onto the substrate.

[0020] In some embodiments, the anode layer further includes: a first anode pattern for each of the plurality of red light-emitting devices and a second anode pattern for each of the plurality of green light-emitting devices. The area ratio of the orthographic projections of the first anode pattern, the second anode pattern, and the third anode pattern onto the substrate is 30:21:70. The ratio of the overlapping area of ​​the first anode pattern, the second anode pattern, and the third anode pattern with the orthographic projections of the second source / drain metal layer onto the substrate is 14:11:27.

[0021] In some embodiments, a plurality of second patterns are connected between two adjacent signal line groups and between two adjacent power signal lines, and one of the second anode patterns overlaps with the orthographic projection of one of the plurality of second patterns on the substrate.

[0022] In some embodiments, one of the first anode patterns overlaps with the orthographic projection of one of the signal line groups onto the substrate.

[0023] In some embodiments, the display panel includes a plurality of pixel driving circuits, each of the plurality of pixel driving circuits including a plurality of transistors and a capacitor, the plurality of transistors including a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor.

[0024] Wherein, the first reset transistor and the compensation transistor are oxide thin-film transistors; the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are low-temperature polycrystalline silicon thin-film transistors.

[0025] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments.

[0026] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 This is a structural diagram of a display panel provided according to some embodiments;

[0029] Figure 2 According to Figure 1 A magnified view of section B of the provided display panel;

[0030] Figure 3 According to Figure 2 The provided cross-sectional structural diagram of the display panel obtained along the section line CC;

[0031] Figure 4 This is a structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0032] Figure 5 According to Figure 4 The provided cross-sectional structural diagram of the display panel obtained along the cutting line DD;

[0033] Figure 6 According to Figure 4 A magnified view of point E on the provided display panel;

[0034] Figure 7 This is a structural diagram of a pixel driving circuit provided according to some embodiments of the present disclosure;

[0035] Figure 8 This is a diagram illustrating the charging process of the fourth node of a pixel driving circuit provided according to some embodiments of the present disclosure;

[0036] Figure 9 This is a cross-sectional structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0037] Figure 10A This is a structural diagram of a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer, a third gate conductive layer, and a first source / drain metal layer stacked together according to some embodiments of this disclosure;

[0038] Figure 10B This is a structural diagram of a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer, a third gate conductive layer, and a first source / drain metal layer stacked together according to some embodiments;

[0039] Figure 11 This is a structural diagram of the first semiconductor layer and the first gate conductive layer stacked according to some embodiments of the present disclosure;

[0040] Figure 12 This is a structural diagram of the stacked first semiconductor layer, first gate conductive layer and second gate conductive layer according to some embodiments of the present disclosure;

[0041] Figure 13 This is a structural diagram of a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer, and a third gate conductive layer stacked according to some embodiments of this disclosure;

[0042] Figure 14 This is a structural diagram of the stacked second source / drain metal layer, transition electrode layer, and anode layer provided according to some embodiments of this disclosure;

[0043] Figure 15This is a structural diagram of the stacked second source / drain metal layer and anode layer according to some embodiments of this disclosure;

[0044] Figure 16 This is a structural diagram of the superimposed second source / drain metal layer, transition electrode layer, and anode layer according to some embodiments;

[0045] Figure 17 This is a structural diagram of the stacked second source / drain metal layer and anode layer according to some embodiments;

[0046] Figure 18 This is a structural diagram of a display device provided according to some embodiments of the present disclosure. Detailed Implementation

[0047] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0050] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0051] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0052] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0054] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0055] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0056] like Figure 1 As shown, the display device 1000' includes a display panel 100', and the display area (Active Area, AA) array of the display panel 100' is provided with multiple pixels P, which emit light to achieve image display. Among these, uneven low-grayscale brightness display is a key issue that urgently needs to be addressed in image quality control during the display process.

[0057] For example, a display brightness of 2 nits and 32 grayscale results in a current draw of less than 50 pA, making the display relatively dark and more prone to uneven image display.

[0058] It should be noted that grayscale refers to the tonal levels of electromagnetic radiation intensity of ground features in a black-and-white image, and is a scale for classifying the spectral characteristics of ground features. Nit is a unit of brightness, which refers to the physical quantity of the intensity of light (reflection) emitted by the surface of a luminous (reflective) object.

[0059] In related technologies, in order to solve the problem of uneven brightness at low gray levels, the pixel P design of the display area AA of the display panel 100' is improved.

[0060] Normally, such as Figure 1 As shown, the display device 1000' also includes other electronic components, such as cameras. Generally, an opening area H is set in the display area AA of the display panel 100', and the electronic components are placed in the holes of the opening area H.

[0061] To ensure that the setting of the opening area H does not affect the display of the display panel 100', such as Figure 1 and Figure 2 As shown, a hole edge area F is set between the hole area H and the display area AA, so that there is a certain distance between the pixel P and the hole area H. This is called the preset distance. The existence of this preset distance avoids the setting of the hole area H from affecting the image display quality.

[0062] However, in order to solve the problem of uneven low grayscale brightness display, when improving the design of pixel P in the display area AA of display panel 100', there is a situation where pixel P is close to the opening area H, making the distance between pixel P and the opening area H less than the preset distance, thus affecting the image display quality. Examples of improvements to the pixel P design in the display area AA of display panel 100' can be found in later content and will not be repeated here.

[0063] One reason why the aperture of pixel P near the aperture area H can affect the image display quality is as follows.

[0064] In the film layer structure of the display panel 100', such as Figure 3 As shown, the F-layer at the perimeter of the hole has a number of inorganic film layers stacked on it, including silicon nitride (SiN). x Inorganic films require high-temperature processes during their formation. This is because silicon nitride (SiN)... x The inorganic film contains a large amount of hydrogen (H), which reacts with silicon nitride (SiN). x The inorganic film exists in the form of silicon-hydrogen bonds (Si-H). These Si-H bonds break at high temperatures to form hydrogen gas (H2), which then forms a bond in silicon nitride (SiN). x The inorganic film layer contains hydrogen gas (H2). If pixel P is close to the aperture area H, the large amount of hydrogen gas (H2) present in the aperture edge area F will cause bright spots in the aperture edge area F, resulting in uneven brightness of the display panel 100'.

[0065] Based on this, such as Figure 4 As shown, some embodiments of this disclosure provide a display panel 100, which includes: a display area AA, at least one opening area H, and an edge area F located between the opening area H and the display area AA, wherein the edge area F surrounds the opening area H.

[0066] See again in some examples Figure 4 The display panel 100 includes an opening area H, which may be circular in shape, for example. The area between the opening area H and the display area AA is called the edge area F. The edge area F surrounds the opening area H in a ring, and the display area AA surrounds the edge area F and the opening area H. There can be multiple opening areas H, and each opening area H is surrounded by an edge area F. The number of opening areas H can be set as needed and is not limited here.

[0067] For example, the opening in the opening area H is used to install other electronic components, such as cameras.

[0068] like Figure 5As shown, the aperture region F includes a trace region F1 and a packaging region F2 sequentially arranged along a first direction X, where the first direction X is the direction from the display region AA to the aperture region H. The display panel 100 also includes a substrate 101, and a first semiconductor layer 202 and at least one silicon nitride layer sequentially stacked on the substrate 101. In the packaging region F2, the display panel 100 has a plurality of first vent holes K1, each of the plurality of first vent holes K1 penetrating each of the at least one silicon nitride layer. Furthermore, each of the plurality of first vent holes K1 penetrates from the side opposite to the substrate 101 of the display panel 100 to the first semiconductor layer 202.

[0069] For example, substrate 101 may be a flexible substrate. The flexible substrate may include a film substrate and a plastic substrate, wherein the film substrate includes a polymeric organic material. Substrate 101 may also be a rigid substrate, which may be any one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0070] For example, the display panel 100 includes multiple inorganic film layers, including at least one silicon nitride layer, wherein the silicon nitride layer refers to an inorganic film layer comprising silicon nitride material.

[0071] For example, such as Figure 5 As shown, the multilayer inorganic film includes a first gate insulating layer 201, a second gate insulating layer 203, a first inorganic insulating layer 205, a second inorganic insulating layer 207, a third gate insulating layer 209, an interlayer dielectric layer 211, and a passivation layer 213 disposed on the side of the first semiconductor layer 202 away from the substrate 101. At least one silicon nitride layer includes at least one of the second gate insulating layer 203, the first inorganic insulating layer 205, and the passivation layer 213.

[0072] Then, the first vent hole K1 penetrates the passivation layer 213, the interlayer dielectric layer 211, the third gate insulating layer 209, the second inorganic insulating layer 207, the first inorganic insulating layer 205, the second gate insulating layer 203, and the first gate insulating layer 201.

[0073] It should be noted that, as Figure 5 As shown, a first planarization layer 214 can also be disposed on the side of the passivation layer 213 away from the substrate 101 (e.g., Figure 9 As shown), the second planarization layer 215 (as shown) Figure 9 (As shown), inorganic encapsulation layers and organic encapsulation layers, etc., are not limited here. The first vent hole K1 also penetrates other film layers on the side of the passivation layer 213 away from the substrate 101, ensuring that hydrogen gas entering the first vent hole K1 can be smoothly discharged.

[0074] By setting the first exhaust hole K1, which penetrates all the silicon nitride layers in the inorganic film layer, a large amount of hydrogen gas in the silicon nitride layer can be discharged from the display panel 100. When the pixel P is designed to be close to the opening area H, bright spots are avoided in the hole edge area F, thus solving the problem of uneven brightness in the hole edge area F of the display panel 100.

[0075] In some embodiments, such as Figure 6 As shown, multiple first exhaust holes K1 are arranged at intervals around the opening area H.

[0076] For example, such as Figure 6 As shown, multiple first exhaust holes K1 are arranged in a ring around the opening area H. For example, the ring can be square. Alternatively, the ring can also be circular; there is no limitation here.

[0077] By using multiple first exhaust holes K1 arranged in a ring around the opening area H, hydrogen gas in the silicon nitride layer can be effectively discharged, ensuring the hydrogen gas discharge effect and avoiding the impact of hydrogen gas on the image quality of the display panel 100.

[0078] In some embodiments, such as Figure 6 As shown, along the first direction X, the arrangement density of the first exhaust port K1 gradually decreases.

[0079] For example, such as Figure 6 As shown, the density of the first vent holes K1 is relatively low near the opening area H. For example, the distance U1 between two adjacent first vent holes K1 is relatively large in the direction perpendicular to the first direction X. The density of the first vent holes K1 is relatively high relatively far from the opening area H. For example, the distance U2 between two adjacent first vent holes K1 is relatively small in the direction perpendicular to the first direction X, i.e., U1>U2.

[0080] By designing the first exhaust vents K1 with a gradually decreasing density along the first direction X, it is beneficial to completely expel hydrogen (H2) from the inorganic film layer near the display area AA. The closer to the opening area H, the less impact hydrogen (H2) in the inorganic film layer has on the image display. Therefore, a relatively low density of the first exhaust vents K can be set in the area near the opening area H to achieve a better exhaust effect.

[0081] In some embodiments, such as Figure 6 As shown, the cross-sectional shape of the first exhaust port K1 is any one of square, triangular, pentagonal, hexagonal, and circular. The plane containing the cross-section is parallel to the plane containing the substrate 101.

[0082] In other words, the shape of the first exhaust port K1 in the direction perpendicular to its axis can be square, rectangle, triangle, pentagon, hexagon or circle, etc. There are no restrictions here, and it can be set as needed.

[0083] In some embodiments, such as Figure 5 As shown, in the wiring area F1, the display panel 100 further includes a second semiconductor layer 208 disposed between the second inorganic insulating layer 207 and the third gate insulating layer 209. In the wiring area F1, the display panel 100 is provided with a plurality of second vent holes K2, each of the plurality of second vent holes K2 extending from the side opposite to the substrate 101 of the display panel 100 to the second semiconductor layer 208.

[0084] For example, multiple second vent holes K2 are arranged in a ring around the opening area H. The second vent holes K2 can discharge hydrogen (H2) in the inorganic film layer of the wiring area F1, thus avoiding the impact of hydrogen (H2) on the display quality of the display panel 100.

[0085] In some embodiments, such as Figure 5 As shown, in the wiring area F1, the display panel 100 is provided with a plurality of third vent holes K3, each of the plurality of third vent holes K3 penetrating each of at least one silicon nitride layer. And each of the plurality of third vent holes K3 extends from the side opposite to the substrate 101 of the display panel 100 to the first semiconductor layer 202.

[0086] For example, multiple third vent holes K3 are arranged in a ring around the opening area H. The arrangement of the third vent holes K3 can discharge hydrogen (H2) in the inorganic film layer of the wiring area F1, thus avoiding the impact of hydrogen (H2) on the display quality of the display panel 100.

[0087] In some embodiments, such as Figure 6 As shown, the display panel 100 includes: a first vent K1 and a second vent K2 (as shown). Figure 5 (as shown) and the third exhaust port K3 (as shown) Figure 5 As shown, the dimensions U3 of the first exhaust port K1, the second exhaust port K2, and the third exhaust port K3 range from 0.5μm to 3μm.

[0088] For example, the first vent K1, the second vent K2, and the third vent K3 are all square holes, and the side length U3 of the first vent K1, the second vent K2, and the third vent K3 is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, or 3μm, etc., without limitation. Alternatively, the first vent K1, the second vent K2, and the third vent K3 are all circular, and the diameter U3 of the first vent K1, the second vent K2, and the third vent K3 is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, or 3μm, etc., without limitation.

[0089] For example, the first vent hole K1, the second vent hole K2 and the third vent hole K3 are formed by a dry etching process.

[0090] In order to further solve the problem of uneven brightness at low gray levels in the display panel 100, the technical solutions of some embodiments of this disclosure have adjusted the design of pixel P.

[0091] To better understand the causes of uneven low grayscale brightness in the display panel 100 and the solutions provided by some embodiments of this disclosure, some embodiments of this disclosure first introduce the structure of a pixel driving circuit 10 for the display panel 100, the structure of which is as follows: Figure 7 As shown. It should be noted that the structure of the pixel driving circuit 10 is only an example of the structure of a pixel driving circuit 10 provided in some embodiments of this disclosure, and is not a limitation on the structure of the pixel driving circuit 10.

[0092] In some examples, such as Figure 7 As shown, the pixel driving circuit 10 includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7.

[0093] For example, the first reset transistor T1 and the compensation transistor T2 can be oxide thin-film transistors, i.e., LTPO (Low Temperature Polycrystalline Oxide) transistors, which are turned on at a high level. The driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type low-temperature polysilicon thin-film transistors, which are turned on at a low level.

[0094] For example, such as Figure 7As shown, the first reset transistor T1 includes a gate g1, a first terminal s1, and a second terminal d1. The gate g1 of the first reset transistor T1 is electrically connected to the reset signal terminal, the first terminal s1 of the first reset transistor T1 is electrically connected to the first initial signal terminal, and the second terminal d1 of the first reset transistor T1 is electrically connected to the first node N1. The reset signal terminal is used to receive the reset signal transmitted by the reset signal line Reset. The first initial signal terminal is used to receive the first initial signal transmitted by the first initial signal line Vinit1. The first reset transistor T1 is configured to: in response to the reset signal received at the reset signal line Reset, transmit the first initial signal received at the first initial signal line Vinit1 to the first node N1 to reset the gate g3 of the driving transistor T3.

[0095] It should be noted that the first electrode of the transistor in this disclosure is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first electrode and the second electrode of the transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0096] It should be noted that in the circuits provided in the embodiments of this disclosure, nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0097] For example, such as Figure 7 As shown, the compensation transistor T2 includes a gate g2, a first electrode s2, and a second electrode d2. The gate g2 of the compensation transistor T2 is electrically connected to the first scan signal terminal, the first electrode s2 of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode d2 of the compensation transistor T2 is electrically connected to the third node N3. The first scan signal terminal is used to receive the first scan signal transmitted by the first scan signal line Gate1. The compensation transistor T2 is configured to perform threshold compensation on the driving transistor T3 in response to the first scan signal received at the first scan signal line Gate1.

[0098] For example, such as Figure 7As shown, the driving transistor T3 includes a gate g3, a first terminal s3, and a second terminal d3. The gate g3 of the driving transistor T3 is electrically connected to the first node N1, the first terminal s3 of the driving transistor T3 is electrically connected to the second node N2, and the second terminal d3 of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0099] For example, such as Figure 7 As shown, the data writing transistor T4 includes a gate g4, a first terminal s4, and a second terminal d4. The gate g4 of the data writing transistor T4 is electrically connected to the second scan signal terminal, the first terminal s4 of the data writing transistor T4 is electrically connected to the data signal terminal, and the second terminal d4 of the data writing transistor T4 is electrically connected to the second node N2. The data signal terminal is used to receive the data signal transmitted by the data signal line Vdata. The data writing transistor T4 is configured to transmit the data signal received at the data signal line Vdata to the driving transistor T3 in response to the second scan signal received at the second scan signal line Gate2.

[0100] For example, such as Figure 7 As shown, the first light-emitting control transistor T5 includes a gate g5, a first electrode g5, and a second electrode d5. The gate g5 of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal, the first electrode g5 of the first light-emitting control transistor T5 is electrically connected to the power supply signal terminal, and the second electrode d5 of the first light-emitting control transistor T5 is electrically connected to the second node N2. The light-emitting control signal terminal is used to receive the light-emitting control signal transmitted by the light-emitting control signal line EM. The power supply signal terminal is used to receive the power supply signal transmitted by the power supply signal line Vdd. The first light-emitting control transistor T5 is configured to transmit the power supply signal received at the power supply signal line Vdd to the driving transistor T3 in response to the light-emitting control signal received at the light-emitting control signal line EM.

[0101] For example, such as Figure 7 As shown, the second light-emitting control transistor T6 includes a gate g6, a first electrode s6, and a second electrode d6. The gate g6 of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal terminal, the first electrode s6 of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The second light-emitting control transistor T6 is configured to transmit a drive current signal to the light-emitting device L in response to the light-emitting control signal received at the light-emitting control signal line EM, for driving the light-emitting device L to emit light.

[0102] For example, such as Figure 7As shown, the second reset transistor T7 includes a gate g7, a first terminal s7, and a second terminal d7. The gate g7 of the second reset transistor T7 is electrically connected to the second scan signal terminal, the first terminal s7 of the second reset transistor T7 is electrically connected to the second initial signal terminal, and the second terminal d7 of the second reset transistor T7 is electrically connected to the fourth node N4. The second reset transistor T7 is configured to: in response to the second scan signal received at the second scan signal line Gate2, transmit the second initial signal received at the second initial signal line Vinit2 to the light-emitting device L to reset the light-emitting device L.

[0103] For example, the anode of the light-emitting device L is electrically connected to the fourth node N4, and the cathode of the light-emitting device L is electrically connected to the reference voltage line Vss.

[0104] For example, such as Figure 7 As shown, the pixel driving circuit 10 further includes a capacitor Cst, which includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal terminal.

[0105] The above embodiments describe the structure of the 7T1C circuit. The pixel driving circuit 10 in this embodiment may also include 3T1C, 8T1C, or 9T1C circuits, etc., and there is no limitation here. Wherein, T represents a transistor, and the number before T indicates the number of transistors. C represents a capacitor, and the number before C indicates the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor.

[0106] The following section uses the structure of the 7T1C circuit mentioned above as an example to introduce a solution to the problem of uneven brightness at low gray levels in the display panel.

[0107] The inventor discovered that, such as Figure 7 and Figure 8 As shown, low grayscale brightness unevenness is related to the start-up speed of the light-emitting device L. The faster the start-up speed of the light-emitting device L, the smaller the problem of low grayscale brightness unevenness. Therefore, the problem of low grayscale brightness unevenness during image display can be improved by increasing the start-up speed of the light-emitting device L.

[0108] Furthermore, the ignition speed of the light-emitting device L can be improved in the following three ways: (1) improve the efficiency of the light-emitting device L; (2) improve the charging speed of the anode (fourth node N4) of the light-emitting device L; (3) improve the jump variable of the fourth node N4.

[0109] For example, such as Figure 8As shown, the ignition of the light-emitting device L means that the light-emitting device L starts to emit light. That is, when the voltage of the fourth node N4 reaches a certain value, the current flowing through the light-emitting device L meets the requirements for the light-emitting device L to emit light, so that the light-emitting device L emits light.

[0110] Specifically, the relationship between the jump variable of the fourth node N4 and the ignition of the light-emitting device L is as follows: Figure 8 As shown, the light-emitting process of the light-emitting device L is actually the charging process of the fourth node N4, and the charging process of the fourth node N4 includes: the charging of the fourth node N4 and the switching of the fourth node N4.

[0111] For example, such as Figure 8 As shown, R1 represents the voltage curve R1 of the fourth node N4 when the signal voltage transmitted through the second initial signal line Vinit2 is -2.7V. R2 represents the current curve R2 showing the change of the current flowing through the light-emitting device L with the voltage curve R1. R3 represents the timing line of the light-emitting control signal line EM. R10 is a partial magnified view of the voltage curve R1, and EM on and EM off represent the conduction and cutoff of the second light-emitting control transistor T6 under the control of the light-emitting control signal transmitted through the light-emitting control signal line EM, respectively.

[0112] As can be seen from R1 and R10, during the charging process of the fourth node N4, when EM switches from on to off, the voltage of the fourth node N4 jumps to a higher voltage due to coupling. When EM switches from off to on, the voltage of the fourth node N4 jumps to a lower voltage due to coupling. Through repeated cycles of EM switching on and off, the voltage of the fourth node N4 is ultimately increased, thus enabling the light-emitting device L to emit light. Furthermore, the voltage of the fourth node N4 after the jump has a decisive effect on the ignition voltage of the light-emitting device L, thereby affecting its normal light emission. Therefore, it can be seen that the larger the jump value of the fourth node N4, the more it helps to increase the ignition voltage of the light-emitting device L.

[0113] It should be noted that a voltage jump to a higher voltage at node N4 means that the voltage value after the jump is higher than the voltage value before the jump. A voltage jump to a lower voltage at node N4 means that the voltage value after the jump is lower than the voltage value before the jump.

[0114] Based on this, in some embodiments provided in this disclosure, such as Figure 9 As shown, the display panel 100 includes: a plurality of pixel driving circuits 10 and a plurality of light-emitting devices L, wherein one of the pixel driving circuits 10 is used to drive one of the light-emitting devices L to emit light. Figure 10A and Figure 11As shown, the pixel driving circuit 10 includes a second light-emitting control transistor T6, and the first semiconductor layer 202 includes a first electrode region S6 and a second electrode region D6 of the second light-emitting control transistor T6.

[0115] It can be understood that in the first semiconductor layer 202, the first electrode region S6 of the second light-emitting control transistor T6 corresponds to the first electrode s6 in the pixel driving circuit 10, and the second electrode region D6 of the second light-emitting control transistor T6 corresponds to the second electrode d6 in the pixel driving circuit 10. Alternatively, it can be understood that the first electrode region S6 of the second light-emitting control transistor T6 has the same function as the first electrode s6, and the second electrode region D6 of the second light-emitting control transistor T6 has the same function as the second electrode d6. The understanding of other transistors is similar, and will not be elaborated here.

[0116] like Figure 10A As shown, the display panel 100 further includes: a first semiconductor layer 202 disposed away from the substrate 101 (e.g., Figure 9 As shown below, the same applies below) on one side of the first gate conductive layer 204, the first gate conductive layer 204 includes: a light emission control signal line EM and a gate pattern G6 of a second light emission control transistor T6, the gate pattern G6 of the second light emission control transistor T6 is electrically connected to the light emission control signal line EM.

[0117] like Figure 10A As shown, the display panel 100 further includes a first source / drain metal layer 212 disposed on the side of the first gate conductive layer 204 away from the substrate 101. The first source / drain metal layer 212 includes a first pattern M1, and the first pattern M1 is electrically connected to the second electrode region D6 of the second light-emitting control transistor T6.

[0118] It should be noted that, as Figure 9 As shown, an insulating layer is disposed between the functional film layers, and the insulating layer includes the aforementioned inorganic film layers. The functional film layers include: a first semiconductor layer 202 and a first gate conductive layer 204, as well as a second gate conductive layer 206, a second semiconductor layer 208, a third gate conductive layer 210, a first source / drain metal layer 212, a second source / drain metal layer 216, and an anode layer 301. For example, the second electrode region D6 of the first pattern M1 and the second light-emitting control transistor T6 is connected through a via penetrating the insulating layer between them.

[0119] For example, the material of the insulating layer may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiN) x O y (or other suitable materials.)

[0120] like Figure 9As shown, the display panel 100 further includes an anode layer 301 disposed on the side of the first source / drain metal layer 212 away from the substrate 101. The anode layer 301 includes an anode pattern M31 of the light-emitting device L, and the first pattern M1 is electrically connected to the anode pattern M31.

[0121] For example, the first pattern M1 and the anode pattern M31 are connected by a through-hole through the insulating layer between them.

[0122] Among them, such as Figure 10A As shown, the ratio of the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101 to the area SS2 of the first pattern M1 projected onto the substrate 101 is greater than 10%.

[0123] It should be noted that since the first pattern M1 is electrically connected to the second pole region D6 of the second light-emitting control transistor T6, and the first pattern M1 is electrically connected to the anode pattern M31, the first pattern M1 has the same function as the fourth node N4 in the pixel driving circuit 10. That is, the first pattern M1 can be understood as the fourth node N4 in the pixel driving circuit 10.

[0124] The inventors discovered that the magnitude of the jump variable at the fourth node N4 is determined by the magnitude of the parasitic capacitance at the fourth node N4. The term "parasitic" refers to capacitance that exists between wirings even though no actual capacitance was designed at that location. This mutual capacitance can be considered parasitic within the wiring, hence the name "parasitic capacitance," also known as stray capacitance. The larger the parasitic capacitance at the fourth node N4, the larger the jump variable at the fourth node N4. The parasitic capacitance at the fourth node N4 is related to the overlap area SS1 of the orthographic projections of the first pattern M1 and the light-emitting control signal line EM onto the substrate 101. The larger the overlap area SS1 of the orthographic projections of the first pattern M1 and the light-emitting control signal line EM onto the substrate 101, the larger the parasitic capacitance at the fourth node N4.

[0125] Therefore, in order to increase the jump variable of the fourth node N4, the embodiments of this disclosure make the ratio of the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101 to the area SS2 of the first pattern M1 projected onto the substrate 101 greater than 10%. By increasing the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101, the jump variable of the fourth node N4 is increased, thereby improving the start-up speed of the light-emitting device L and improving the problem of uneven low grayscale brightness during image display.

[0126] For example, in related technologies, such as Figure 10BAs shown, the ratio of the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101 to the area SS2 of the first pattern M1 projected onto the substrate 101 is less than 10%. The smaller the parasitic capacitance at the fourth node N4, the smaller the jump variable at the fourth node N4, which can easily lead to uneven low-grayscale brightness during image display.

[0127] In some embodiments, such as Figure 10A As shown, the ratio of the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101 to the area SS2 of the first pattern M1 projected onto the substrate 101 is 25%.

[0128] By setting the ratio of the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101 to the area SS2 of the first pattern M1 projected onto the substrate 101 to 25%, the overlapping area SS1 of the first pattern M1 and the light-emitting control signal line EM projected onto the substrate 101 can be effectively increased, thereby increasing the jump variable of the fourth node N4, thus improving the start-up speed of the light-emitting device L, and effectively improving the problem of uneven low grayscale brightness during image display.

[0129] To better understand the technical solution provided by the embodiments of this disclosure for solving the problem of uneven brightness at low gray levels during image display, the following example illustrates the design of a film layer structure for a display panel 100. It should be noted that this design of the film layer structure for the display panel 100 is merely an example and is not intended to limit the technical solutions provided by the embodiments of this disclosure.

[0130] In some examples, such as Figure 9 As shown, the display panel 100 includes: a first gate insulating layer 201, a first gate conductive layer 204, a second gate insulating layer 203, a second gate conductive layer 206, a first inorganic insulating layer 205, a second inorganic insulating layer 207, a second semiconductor layer 208, a third gate insulating layer 209, a third gate conductive layer 210, an interlayer dielectric layer 211, a first source / drain metal layer 212, a passivation layer 213, a first planarization layer 214, a second source / drain metal layer 216, and a second planarization layer 215, disposed on the side of the first semiconductor layer 202 away from the substrate 101 and stacked sequentially.

[0131] For example, such as Figure 11 As shown, the first semiconductor layer 202 includes an active layer pattern of a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7.

[0132] For example, each transistor includes a first electrode region and a second electrode region, and the active layer pattern of the transistor includes the first electrode region and the second electrode region of the transistor. For instance, the first electrode region S6 of the second light-emitting control transistor T6 and the second electrode region of the driving transistor T3 are electrically connected. Similarly, in the layout design, the first electrode region of the transistor corresponds to the first electrode of the transistor in the pixel driving circuit 10, and the second electrode region of the transistor corresponds to the second electrode of the transistor in the pixel driving circuit 10, which will not be elaborated further here.

[0133] For example, such as Figure 11 As shown, the first gate conductive layer 204 includes the gate patterns of a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7.

[0134] For example, such as Figure 11 As shown, the first gate conductive layer 204 further includes: a first plate Cst1 of capacitor Cst, a second scan signal line Gate2, and a light emission control signal line EM. The gate pattern of the data writing transistor T4 and the gate pattern of the second reset transistor T7 are electrically connected to the second scan signal line Gate2, and the gate patterns of the first light emission control transistor T5 and the second light emission control transistor T6 are electrically connected to the light emission control signal line EM.

[0135] For example, such as Figure 12 As shown, the second gate conductive layer 206 includes: the second plate Cst2 of capacitor Cst, the first initial signal line Vinit1, the first sub-reset signal line Reset1, and the first sub-scan signal line G1.

[0136] For example, such as Figure 13 As shown, the second semiconductor layer 208 includes an active layer pattern of a first reset transistor T1 and a compensation transistor T2.

[0137] For example, such as Figure 13 As shown, the third gate conductive layer 210 includes the gate patterns of the first reset transistor T1 and the compensation transistor T2.

[0138] For example, such as Figure 13 As shown, the third gate conductive layer 210 further includes a second sub-reset signal line Reset2 and a second sub-scan signal line G2. Furthermore, the second sub-reset signal line Reset2 of the third gate conductive layer 210 and the first sub-reset signal line Reset1 of the second gate conductive layer 206 are electrically connected vias to form the reset signal line Reset. The second sub-scan signal line G2 of the third gate conductive layer 210 and the first sub-scan signal line G1 of the second gate conductive layer 206 are electrically connected vias to form the first scan signal line Gate1.

[0139] The gate pattern of the first reset transistor T1 is electrically connected to the reset signal line Reset, and the gate pattern of the compensation transistor T2 is electrically connected to the first scan signal line Gate1.

[0140] For example, such as Figure 10A As shown, the first source / drain metal layer 212 also includes a second initial signal line Vinit2.

[0141] In some embodiments, such as Figure 10A As shown, the material of the second semiconductor layer 208 includes indium gallium zinc oxide.

[0142] As described above, the ignition speed of the light-emitting device L can be increased by improving the charging speed of the anode (fourth node N4) of the light-emitting device L. The following describes an embodiment for improving the charging speed of the anode (fourth node N4) of the light-emitting device L.

[0143] like Figure 14 and Figure 16 As shown, the display panel 100 includes: a plurality of light-emitting devices L, and the plurality of light-emitting devices L includes: a plurality of red light-emitting devices L R Multiple green light-emitting devices L G and multiple blue light-emitting devices L B .like Figure 9 As shown, the display panel 100 further includes: a second source / drain metal layer 216 disposed on the side of the first semiconductor layer 202 away from the substrate 101, and an anode layer 301 disposed on the side of the second source / drain metal layer 216 away from the substrate 101. Figure 14 and Figure 16 As shown, the anode layer 301 includes: a plurality of blue light-emitting devices L B Each blue light-emitting device L B The third anode pattern is M313.

[0144] For example, the anode layer 301 also includes: a plurality of red light-emitting devices L R Each red light-emitting device L R The first anode pattern M311 and multiple green light-emitting devices L G Each green light-emitting device L G The second anode pattern is M312.

[0145] For example, the red light-emitting device L R Configured to emit red light, green light-emitting device L G Configured to emit green light, blue light-emitting device L B Configured to emit blue light, multiple red light-emitting devices L R Multiple green light-emitting devices L G and multiple blue light-emitting devices L BThe settings allow for full-color display on the display panel 100. For example, a pixel P mentioned above can include: a red light-emitting device L. R Two green light-emitting devices L G and a blue light-emitting device L B .

[0146] For example, such as Figure 14 and Figure 16 As shown, a transition electrode layer 218 can be disposed between the second source / drain metal layer 216 and the anode layer 301. The transition electrode layer 218 includes multiple transition electrodes, which are used to realize the electrical connection between the anode pattern M31 in the anode layer 301 and the pixel driving circuit 10. The anode pattern M31 includes: a first anode pattern M311, a second anode pattern M312, and a third anode pattern M313.

[0147] It should be noted that, in order to more clearly illustrate the layout design relationship between the anode layer 301 and the second source / drain metal layer 216, Figures 14-16 The film layer configuration between the second source / drain metal layer 216 and the substrate 101 is not shown. For details on the film layer configuration between the second source / drain metal layer 216 and the substrate 101, please refer to the above content, which will not be repeated here.

[0148] In related technologies, such as Figure 16 and Figure 17 As shown, a relatively large second pattern M2 is usually designed in the second source / drain metal layer 216. The orthographic projection of the second pattern M2 on the substrate 101 covers part of the functional film layer in the pixel driving circuit 10. For example, the orthographic projection of the second pattern M2 on the substrate 101 can cover the orthographic projection of the active layer patterns of the first reset transistor T1 and the compensation transistor T2 on the substrate 101. The setting of the second pattern M2 is related to the optics and power consumption of the display panel 100, which is beneficial to improving the performance of the display panel 100. For the position and connection relationship of the second pattern M2, please refer to the following content, which will not be repeated here.

[0149] For example, such as Figure 16 and Figure 17 As shown, in related technologies, due to the blue light-emitting device L... B The projected area of ​​the third anode pattern M313 on the substrate 101 is significantly larger than the projected area of ​​the first anode pattern M311 on the substrate 101 and larger than the projected area of ​​the second anode pattern M312 on the substrate 101. Each blue light-emitting device L... B The orthographic projection of the third anode pattern M313 onto the substrate 101 overlaps with the orthographic projection of the second pattern M2 onto the substrate 101. This arrangement will make the blue light-emitting device L... BThe parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 is relatively large.

[0150] However, the inventors discovered that reducing the blue light-emitting device L... B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 can improve the overall charging speed of the display panel 100 during image display, which is beneficial to improving the optical performance of the display panel 100.

[0151] Based on this, in some embodiments, such as Figure 14 As shown, the second source / drain metal layer 216 includes multiple data signal lines Vdata and multiple power signal lines Vdd. Both the multiple data signal lines Vdata and the multiple power signal lines Vdd extend along the second direction I.

[0152] It should be noted that the extension of multiple data signal lines Vdata and multiple power signal lines Vdd along the second direction I means that the data signal lines Vdata and power signal lines Vdd as a whole have a tendency to extend along the second direction I.

[0153] In this configuration, along the third direction J, every two data signal lines Vdata from the multiple data signal lines Vdata are alternately set with every two power signal lines Vdd from the multiple power signal lines Vdd. The second direction I intersects with the third direction J.

[0154] For example, the second direction I and the third direction J are perpendicular.

[0155] On the third anode J, adjacent power signal lines Vdd, data signal lines Vdata, and power signal lines Vdd form a signal line group VV. A third anode pattern M313 overlaps with the orthographic projection of a signal line group VV onto the substrate 101.

[0156] like Figure 14 As shown, since every two data signal lines Vdata and every two power signal lines Vdd are alternately set, the two data signal lines Vdata and the power signal lines Vdd on both sides of the two data signal lines Vdata along the third direction J are divided into a signal line group VV.

[0157] In related technologies, due to the blue light-emitting device L B The projected area of ​​the third anode pattern M313 on the substrate 101 is significantly larger than the projected area of ​​the first anode pattern M311 on the substrate 101 and larger than the projected area of ​​the second anode pattern M312 on the substrate 101. Each blue light-emitting device L... BThe orthographic projection of the third anode pattern M313 onto the substrate 101 overlaps with the orthographic projection of the second pattern M2 onto the substrate 101. This arrangement will make the blue light-emitting device L... B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 is relatively large. Blue light-emitting device L B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 is relatively large, which is not conducive to improving the charging speed of the display panel 100.

[0158] In the layout design of the anode layer 301, the arrangement of overlapping a third anode pattern M313 with the orthographic projection of a signal line group VV onto the substrate 101 can reduce the light emission of the blue light-emitting device L. B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 is increased, thereby improving the performance of the blue light-emitting device L. B The purpose of this is to improve the charging speed, thereby increasing the overall charging speed of the display panel 100 during image display, which is beneficial to improving the optical performance of the display panel 100.

[0159] Therefore, the technical solution provided by the above embodiments avoids the blue light-emitting device L B The arrangement where the orthographic projection of the third anode pattern M313 on the substrate 101 overlaps with the orthographic projection of the second pattern M2 on the substrate 101 reduces the light emission of the blue light-emitting device L. B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216.

[0160] In some embodiments, such as Figure 14 As shown, the area ratio of the orthographic projections of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 onto the substrate 101 is 30:21:70. The ratio of the overlapping area of ​​the orthographic projections of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 onto the substrate 101 and the second source / drain metal layer 216 is 14:11:27.

[0161] For example, by designing the area ratio of the orthographic projections of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 on the substrate 101 to be 30:21:70, and the ratio of the overlapping area of ​​the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 and the orthographic projections of the second source / drain metal layer 216 on the substrate 101 to be 14:11:27, a rational layout of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 is achieved, thereby solving the problem of uneven low grayscale brightness display and improving the image quality of the display.

[0162] With a design where the ratio of the overlapping areas of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 to the orthogonal projections of the second source / drain metal layer 216 onto the substrate 101 is 14:11:27, as shown... Figure 14 As shown, this can effectively reduce the L of blue light-emitting devices. B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 improves the blue light-emitting device L B The improved charging speed enhances the image display performance of the display panel 100, effectively solving the problem of uneven low grayscale brightness display during image display.

[0163] To improve the blue light-emitting device L B To improve charging speed, adjustments need to be made to the overall layout design of the anode layer 301 to reduce the amount of blue light emitting elements (L). B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216. An embodiment of adjusting the layout design of the anode layer 301 is described below.

[0164] In some embodiments, such as Figure 14 As shown, there are multiple second patterns M2 connected between two adjacent signal line groups VV and between two adjacent power signal lines Vdd. A second anode pattern M312 overlaps with the orthographic projection of one of the multiple second patterns M2 on the substrate 101.

[0165] It is understandable that the two adjacent power signal lines Vdd here refer to two power signal lines Vdd that do not have a data signal line Vdata between them. In other words, one of the two adjacent power signal lines Vdd is located in a signal line group VV, and the other power signal line Vdd is located in an adjacent signal line group VV.

[0166] For example, such as Figure 14 As shown, two adjacent power signal lines Vdd are connected to form a second pattern M2 with a larger area, so that the second pattern M2 and the power signal line Vdd transmit the same voltage signal. The design of the second pattern M2 is related to the optics and power consumption of the display panel 100, which is beneficial to improving the performance of the display panel 100.

[0167] A green light-emitting device L G The second anode pattern M312 overlaps with the orthographic projection of a second pattern M2 on the substrate 101, that is, during the film stacking process, the second anode pattern M312 is placed on the second pattern M2.

[0168] In some embodiments, such as Figure 14As shown, a first anode pattern M311 overlaps with the orthographic projection of a signal line group VV onto the substrate 101.

[0169] That is, by setting the first anode pattern M311 and the third anode pattern M313 to be stacked on the signal line group VV, and the second anode pattern M312 to be set on the second pattern M2, the rational design of the first anode pattern M311, the second anode pattern M312 and the third anode pattern M313 is realized, and the ratio of the overlapping area of ​​the first anode pattern M311, the second anode pattern M312 and the third anode pattern M313 and the orthogonal projection of the second source drain metal layer 216 on the substrate 101 is 14:11:27.

[0170] For example, such as Figure 14 As shown, the first anode pattern M311 and the third anode pattern M313 are alternately set on the third direction J.

[0171] For example, such as Figure 14 As shown, the first anode pattern M311 and the third anode pattern M313 are alternately set on the third direction J, and the second anode pattern M312 is set on the second pattern M2, so that the first anode pattern M311, the second anode pattern M312 and the third anode pattern M313 are arranged in a regular array.

[0172] For example, during the formation of the anode layer 301, the relative positions of the anode layer 301 and the second source / drain metal layer 216 can be adjusted to achieve a design where the ratio of the overlapping areas of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 and the second source / drain metal layer 216 on the substrate 101 is 14:11:27.

[0173] For example, in related technologies, such as Figure 16 As shown, an array of first anode patterns M311, second anode patterns M312, and third anode patterns M313 is arranged, wherein the orthographic projection of one first anode pattern M311 on substrate 101 overlaps with the orthographic projection of one second pattern M2 on substrate 101, and the orthographic projection of one third anode pattern M313 on substrate 101 overlaps with the orthographic projection of one second pattern M2 on substrate 101. Since the orthographic projection area of ​​the third anode pattern M313 of the blue light-emitting device LB on substrate 101 is significantly larger than the orthographic projection area of ​​the first anode pattern M311 on substrate 101 and larger than the orthographic projection area of ​​the second anode pattern M312 on substrate 101, the blue light-emitting device LB... B The parasitic capacitance between the third anode pattern M313 and the second source / drain metal layer 216 is relatively large.

[0174] Will Figure 14 and Figure 16As can be seen from the comparison, the overall arrangement of the array of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 remains unchanged. By adjusting the relative positional relationship between the anode layer 301 and the second source / drain metal layer 216, the size of the overlapping area of ​​the orthogonal projection of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 and the second source / drain metal layer 216 on the substrate 101 can be adjusted.

[0175] For example, the overall moving design of the first anode pattern M311, the second anode pattern M312, and the third anode pattern M313 arranged in an array, such as... Figure 14 As shown, the adjusted green light-emitting device L can be realized. G The design of the second anode pattern M312 overlapping the orthogonal projection on the substrate 101 with the orthogonal projection of the second pattern M2 on the substrate changes the relative position of the anode layer 301 and the second source / drain metal layer 216.

[0176] like Figure 14 As shown, during the adjustment of the layout design of the anode layer 301, the light-emitting device L may become relatively close to the aperture edge region F, causing bright spots to appear around the aperture region H, resulting in uneven brightness in the image display. In this case, multiple first vent holes K1 need to be set in the encapsulation area F2 of the aperture edge region F to solve the problem of bright spots appearing around the aperture region H. For details on setting vent holes in the aperture edge region F, please refer to the above content; it will not be repeated here.

[0177] On the other hand, such as Figure 18 As shown, some embodiments of this disclosure also provide a display device 1000, which includes a display panel 100 as described in any of the above embodiments.

[0178] In some examples, the display device 1000 also includes a frame, a circuit board, a display driver IC (Integrated Circuit), and other electronic components, with the display panel 100 disposed within the frame.

[0179] The display device 1000 provided in the embodiments of this disclosure can be any device that displays text or images, whether in motion (e.g., video) or still (e.g., image). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: The display area, at least one opening area, and an edge area of ​​the opening area and the display area, wherein the edge area of ​​the opening area surrounds the opening area; The hole edge area includes: a wiring area and a packaging area arranged sequentially along a first direction, wherein the first direction is the direction from the display area to the hole area; The display panel further includes: a substrate, and a first semiconductor layer and at least one silicon nitride layer sequentially stacked on the substrate; In the encapsulation area, the display panel is provided with a plurality of first vent holes, each of the plurality of first vent holes penetrating each of the at least one silicon nitride layer, and each of the plurality of first vent holes penetrating from the side opposite to the substrate of the display panel to the first semiconductor layer.

2. The display panel according to claim 1, characterized in that, The plurality of first exhaust holes are arranged at intervals around the opening area.

3. The display panel according to claim 1 or 2, characterized in that, Along the first direction, the arrangement density of the first exhaust holes gradually decreases.

4. The display panel according to claim 1 or 2, characterized in that, The cross-sectional shape of the first vent is any one of square, triangle, pentagon, hexagon and circle; wherein the plane of the cross-section is parallel to the plane of the substrate.

5. The display panel according to claim 1 or 2, characterized in that, Also includes: A first gate insulating layer, a second gate insulating layer, a first inorganic insulating layer, a second inorganic insulating layer, a third gate insulating layer, an interlayer dielectric layer, and a passivation layer are disposed on the side of the first semiconductor layer away from the substrate. The at least one silicon nitride layer includes: a second gate insulating layer, a first inorganic insulating layer, and a passivation layer; the first vent hole penetrates the passivation layer, the interlayer dielectric layer, the third gate insulating layer, the second inorganic insulating layer, the first inorganic insulating layer, the second gate insulating layer, and the first gate insulating layer.

6. The display panel according to claim 5, characterized in that, In the wiring area, the display panel further includes: a second semiconductor layer disposed between the second inorganic insulating layer and the third gate insulating layer; In the wiring area, the display panel is provided with a plurality of second vent holes, each of the plurality of second vent holes extending from the side opposite to the substrate of the display panel to the second semiconductor layer.

7. The display panel according to claim 6, characterized in that, The size of the second exhaust port ranges from 0.5μm to 3μm.

8. The display panel according to claim 1 or 2, characterized in that, In the wiring area, the display panel is provided with a plurality of third vent holes, each of the plurality of third vent holes penetrating each of the at least one silicon nitride layer, and each of the plurality of third vent holes penetrating from the side opposite to the substrate of the display panel to the first semiconductor layer.

9. The display panel according to claim 8, characterized in that, The display panel includes a first vent and a third vent, the size of which ranges from 0.5μm to 3μm.

10. The display panel according to claim 1 or 2, Its features are, It includes: multiple pixel driving circuits and multiple light-emitting devices, wherein one of the multiple pixel driving circuits is used to drive one of the multiple light-emitting devices to emit light; the pixel driving circuit includes a second light-emitting control transistor; the first semiconductor layer includes a first electrode region and a second electrode region of the second light-emitting control transistor; It also includes: a first gate conductive layer disposed on the side of the first semiconductor layer away from the substrate; the first gate conductive layer includes: a light emission control signal line and a gate pattern of the second light emission control transistor, wherein the gate pattern of the second light emission control transistor is electrically connected to the light emission control signal line; It also includes: a first source / drain metal layer disposed on the side of the first gate conductive layer away from the substrate; the first source / drain metal layer includes a first pattern, and the first pattern is electrically connected to the second electrode region of the second light-emitting control transistor; It also includes: an anode layer disposed on the side of the first source / drain metal layer away from the substrate, the anode layer including the anode pattern of the light-emitting device; the first pattern is electrically connected to the anode pattern; Wherein, the ratio of the overlapping area of ​​the first pattern and the light-emitting control signal line projected onto the substrate to the area of ​​the first pattern projected onto the substrate is greater than 10%.

11. The display panel according to claim 10, characterized in that, The ratio of the overlapping area of ​​the first pattern and the orthographic projection of the light-emitting control signal line on the substrate to the area of ​​the orthographic projection of the first pattern on the substrate is 25%.

12. The display panel according to claim 1 or 2, characterized in that, include: Multiple light-emitting devices, including: multiple red light-emitting devices, multiple green light-emitting devices, and multiple blue light-emitting devices; It also includes: a second source / drain metal layer disposed on the side of the first semiconductor layer away from the substrate, the second source / drain metal layer including: multiple data signal lines and multiple power signal lines; the multiple data signal lines and the multiple power signal lines all extend along a second direction; Wherein, along the third direction, every two data signal lines and every two power signal lines among the plurality of data signal lines are alternately arranged; the second direction and the third direction intersect; In the third direction, adjacent power signal lines, data signal lines, and power signal lines form a signal line group; The display panel further includes: an anode layer disposed on the side of the second source / drain metal layer away from the substrate; the anode layer includes: a third anode pattern for each of the plurality of blue light-emitting devices; one of the third anode patterns overlaps with the orthographic projection of one of the signal line groups on the substrate.

13. The display panel according to claim 12, characterized in that, The anode layer further includes: a first anode pattern for each of the plurality of red light-emitting devices and a second anode pattern for each of the plurality of green light-emitting devices; The area ratio of the orthographic projections of the first anode pattern, the second anode pattern, and the third anode pattern on the substrate is 30:21:70; the ratio of the overlapping areas of the first anode pattern, the second anode pattern, and the third anode pattern with the orthographic projections of the second source / drain metal layer on the substrate is 14:11:

27.

14. The display panel according to claim 13, characterized in that, Between two adjacent signal line groups, and between two adjacent power signal lines, there are multiple second patterns; one second anode pattern overlaps with the orthographic projection of one of the multiple second patterns onto the substrate.

15. The display panel according to claim 13 or 14, characterized in that, One of the first anode patterns overlaps with the orthographic projection of one of the signal line groups on the substrate.

16. The display panel according to claim 1 or 2, characterized in that, It includes multiple pixel driving circuits, each of which includes: a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor. Wherein, the first reset transistor and the compensation transistor are oxide thin-film transistors; the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor and the second reset transistor are low-temperature polycrystalline silicon thin-film transistors.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 16.

Images