A processing system and processing method for re-routing circuit patterns

Abstract

A processing system and a processing method for a re-wiring circuit pattern, the processing system comprising a position detection system, an image generation system and a projection system, the position detection system acquires actual position information of a bare chip located on a wafer reconstruction member, the image generation system adjusts a standard re-wiring pattern according to the actual position information of the bare chip to obtain a projection image, and the projection system forms a re-wiring circuit pattern on the wafer reconstruction member according to the projection image, the image generation system judges whether the offset of the bare chip relative to the wafer reconstruction member exceeds an offset threshold according to the actual position information of the bare chip, and corrects a unit standard re-wiring pattern corresponding to the bare chip exceeding the offset threshold. The processing system and the processing method for the re-wiring circuit pattern reduce the number of offset bare chips that need to be processed by setting the offset threshold, which helps to improve the processing speed of the image generation system.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging, and in particular to a processing system and method for processing rewiring circuit patterns in advanced packaging. Background Technology

[0002] Integrated circuit chips need to have circuits formed on wafers and be applied to circuit boards through processing steps such as packaging. Packaging integrated circuits serves to protect the chip, provide electrical connections, and facilitate assembly. Traditional packaging typically involves first dicing the wafer into individual chips and then packaging them. However, with the increasing demand for miniaturization, thinning, and densification of integrated circuit chips, wafer-level packaging (WLP) is becoming more and more common. Unlike traditional packaging, most of the process in wafer-level packaging involves manipulating the wafer itself; that is, the entire chip is packaged on the wafer, and then it is diced after packaging. For chips with small area and few pins, fan-in packaging (FIWLP) is usually used. However, for chips with small area and many pins, the chip area cannot accommodate enough pins, thus fan-out packaging (FOWLP) was developed. To achieve a greater number of pins outside the chip area, a redistribution layer (RDL) is typically used to connect the internal and external solder joints of the chip. For fan-out packaging, the actual process involves first dicing the bare wafers, then reconfiguring the individual bare chips onto the wafer or carrier board. Based on this, the final packaged chip is formed through batch processing and metallized wiring interconnection. During the bare chip reconfiguration process, positional deviations may occur, leading to connection errors between internal and external solder joints. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a processing system and method for accurately connecting the internal and external solder joints of the bare chip in the form of a rewiring circuit pattern.

[0004] Compared with the prior art, the present invention provides a processing system for redistribution circuit patterns. The processing system includes an alignment detection system, an image generation system, and a projection system. The alignment detection system acquires the actual position information of the bare chip located on the wafer rework component. The image generation system adjusts the standard redistribution pattern according to the actual position information of the bare chip to obtain a projected image. The projection system forms a redistribution circuit pattern on the wafer rework component based on the projected image. The image generation system determines whether the offset of the bare chip relative to the wafer rework component exceeds an offset threshold based on the actual position information of the bare chip. For bare chips that exceed the offset threshold, the standard redistribution pattern of the corresponding cell is corrected.

[0005] Furthermore, the offset threshold is set according to the design of the standard redistribution layer. When setting the bare chip offset threshold, it is determined based on the area of ​​the external solder joint connection area, or based on the area of ​​the internal solder joint connection area and the external solder joint connection area.

[0006] Furthermore, the offset threshold includes a displacement threshold, a expansion / contraction threshold, and a rotation threshold.

[0007] Furthermore, the processing system also includes an image detection system to determine the accuracy of the projected image, wherein the image detection system obtains detection information through the alignment detection system.

[0008] Furthermore, the alignment detection system includes a first alignment detection system and a second alignment detection system, and the image generation system includes a first image generation system and a second image generation system. The first alignment detection system communicates with the first image generation system. The first image generation system determines whether the offset of the bare chip relative to the wafer rework component exceeds an offset threshold based on the actual position information of the bare chip. For bare chips that exceed the offset threshold, the standard redistribution pattern of the corresponding cell is corrected to obtain a corrected redistribution image. The second image generation system receives the redistribution image output by the first image generation system and the alignment information from the second alignment detection system to obtain a projection image. The projection image of the second image generation system is output to the projection system.

[0009] Furthermore, the processing system also includes an image detection system to determine the accuracy of the projected image, wherein the image detection system obtains detection information through the second alignment detection system.

[0010] Furthermore, the pattern detection system also includes a detection component, and when the projection system projects the wafer component, it simultaneously projects the detection pattern onto the detection component.

[0011] A method for processing redistribution circuit patterns includes: a alignment detection system obtaining actual position information of a bare chip in a wafer rework component; obtaining offset information of the bare chip based on its actual position information; transmitting the offset information of the bare chip to an image generation system; generating a corrected redistribution circuit image based on the offset information of the bare chip; and determining whether the offset of the bare chip relative to the wafer rework component exceeds an offset threshold based on the actual position information of the bare chip, thereby determining whether to correct the standard redistribution pattern.

[0012] Furthermore, the image generation system generates an initial projection image based on the actual position information of the bare chip and the standard redistribution image. Based on whether the offset of the bare chip relative to the wafer re-component exceeds a threshold range, it determines whether to correct the corresponding cell redistribution image to obtain a corrected redistribution image.

[0013] Furthermore, the correction of the cell projection image corresponding to the bare chip exceeding the threshold range includes: correcting the external solder joint area in the initial projection image according to the external solder joint connection area in the standard redistribution image; connecting the internal solder joint connection area and its corrected external solder joint connection area; and checking whether there are erroneous connections in the updated redistribution structure.

[0014] Furthermore, the image generation system obtains an initial projection image based on the actual position of the wafer rework component and a standard redistribution image. Based on the offset information of the bare chip, it determines whether the offset of the bare chip relative to the wafer rework component exceeds a threshold range. The redistribution image of the cell corresponding to the bare chip whose offset exceeds the threshold range is corrected to obtain a corrected redistribution image.

[0015] Furthermore, the actual position of the internal solder joint is determined based on the offset information of the bare chip, and the internal solder joint connection area in the initial projection image is corrected; the corrected internal solder joint connection area is connected to the corresponding external solder joint connection area; and the redistribution structure in the corrected projection image is checked for erroneous connections.

[0016] Compared to existing technologies, the rewiring circuit pattern processing system and method, by setting an offset threshold, reduces the number of offset bare chips that need to be processed, thus improving the processing speed of the image generation system. Simultaneously, the projected image obtained based on the actual position of the bare chip includes both the deviation information of the wafer rewiring component and the deviation information of the bare chip itself, allowing for more precise connection between internal and external solder joints in the rewiring layer. The pattern detection system can promptly identify problems in the processing system, preventing the projection of wafer rewiring components using a faulty processing system, which could lead to the scrapping of wafer rewiring components and unnecessary losses. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an embodiment of a circuit pattern processing system for rewiring layers.

[0018] Figure 2 This is a schematic diagram of the first embodiment of the image generation system generating a corrected rewiring image.

[0019] Figure 3 This is a schematic diagram of a second embodiment of the image generation system generating a corrected rewiring image.

[0020] Figure 4 This is a schematic diagram of a first embodiment of the image generation system for the rewiring image method of the offset bare chip correction unit.

[0021] Figure 5 This is a schematic diagram of a second embodiment of the image generation system for the rewiring image method of the offset bare chip correction unit.

[0022] Figure 6 This is a schematic diagram of the first embodiment of the circuit pattern processing method for rewiring layers.

[0023] Figure 7 This is a block diagram of another embodiment of a circuit pattern processing system for rewiring layers.

[0024] Figure 8 This is a schematic diagram of another embodiment of the circuit image processing system for rewiring layers.

[0025] Figure 9 This is a block diagram of an embodiment of a circuit pattern processing system that includes a rewiring layer of a pattern detection system.

[0026] Figure 10 This is a block diagram of another embodiment of a circuit pattern processing system that includes a rewiring layer of a pattern detection system.

[0027] Figure 11 This is a schematic diagram of the first embodiment of the circuit pattern processing device for rewiring layers.

[0028] Figure 12 This is a schematic diagram of a second embodiment of a circuit pattern processing device for rewiring layers. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described below with reference to specific embodiments shown in the accompanying drawings.

[0030] For fan-out wafer-level packaging (FOWLP), wafer reconfiguration technology is required to rearrange the fabricated dies to obtain a wafer reassembly. This wafer reassembly utilizes a carrier board to rearrange the fabricated dies; the carrier board can be a wafer or a circuit board. The fabrication process of the wafer reassembly includes attaching surface mount tape to the carrier board, placing a tested die with its active side down on the surface mount tape, fixing the die position with the tape, then using molding compound to cover and fill the gaps between the die and the die, and finally gradually separating the carrier board and the surface mount tape to obtain the wafer reassembly. The wafer reassembly contains multiple arrayed dies to be further packaged, each die including internal solder joints for electrical connection to external solder joints.

[0031] During the fabrication of the wafer reassembly, the bare die needs to be placed on a carrier board for rearrangement. This placement process is affected by factors such as placement accuracy, resulting in discrepancies between the die's intended placement position and its actual position, including horizontal and rotational shifts, which impact subsequent processing. In particular, after obtaining the wafer reassembly, a redistribution layer, Under Bump Metal (UBM), and external solder joints need to be further fabricated on it to complete the bare chip packaging structure. The circuit structure of the redistribution layer connects the internal and external solder joints of the bare chip. Changes in the die's placement position will prevent the standard redistribution circuit structure from effectively connecting the internal and external solder joints.

[0032] This invention relates to a system and method for processing circuit patterns of redistribution layers. The method for processing redistribution layers performs redistribution layer processing based on the actual location of the bare chip.

[0033] like Figure 1 As shown, the fabrication system for the redistribution layer includes an alignment detection system, an image generation system, a projection system, and a carrier system. The carrier system is used to place the wafer rework component. The alignment detection system is used to align the positions of the bare chips in the wafer rework component. The image generation system generates a projection image based on the position information of the bare chips obtained by the alignment detection system. The projection system exposes the wafer rework component based on the projection image.

[0034] The wafer reassembly assembly comprises multiple regularly arranged bare chips. Each bare chip has a marker point, or existing point information within the bare chip can be used as the marker point information, such as the position information of internal solder joints formed in previous processes. The actual position information of the bare chip is determined based on the position information of the marker points, including translation, expansion, and rotation of the bare chip. The wafer reassembly assembly may also include alignment points corresponding to the entire wafer reassembly assembly. The actual position information of the entire wafer reassembly assembly, including translation, expansion, and rotation, is obtained through these alignment points.

[0035] The alignment detection system includes an image acquisition device that acquires marker points on the bare chip to determine its actual position; the image acquisition device also acquires alignment points on the wafer reassembly to determine its actual position. The image acquisition device is compatible with both area scan and line scan cameras to achieve accurate acquisition of marker points on the bare chip and alignment points on the wafer reassembly.

[0036] The image generation system adjusts the standard redistribution image to obtain a projected image based on the actual position information of each bare chip in the wafer rework assembly.

[0037] The projection system forms a rewiring circuit pattern on the wafer reassembly based on the projected image.

[0038] The standard redistribution image corresponds to the image of the redistribution layer when, under ideal conditions, the bare die is located at a predetermined position in the wafer re-component. Each bare die in the standard redistribution image corresponds to one unit of standard redistribution image.

[0039] The alignment detection system obtains the position information of the marker points on the bare chip, and simultaneously obtains the position information of the alignment points on the wafer reassembly, thus obtaining the actual position information of the bare chip and its offset information relative to the wafer reassembly. Alternatively, the alignment detection system obtains the position information of the marker points on the bare chip, records the position information of the marker points, and obtains the actual position information of the bare chip and its offset information relative to the projection system based on the position information of the marker points. The alignment detection system transmits the offset information of the bare chip to the image generation system.

[0040] The image generation system determines whether the offset of the bare chip relative to the wafer rewiring component exceeds a threshold range based on the actual position information of the bare chip, and determines whether to correct the cell redistribution pattern. The image generation system obtains the corrected redistribution image in the following way.

[0041] like Figure 2 As shown, in the first method: the image generation system generates an initial projection image based on the actual position information of the bare chip and the standard redistribution image, and determines whether to correct the corresponding cell redistribution image based on whether the offset of the bare chip relative to the wafer rework component exceeds a threshold range, thereby obtaining a corrected redistribution image.

[0042] like Figure 3 As shown, in the second method: the image generation system obtains an initial projection image based on the actual position of the wafer rework component and the standard redistribution image, determines whether the offset of the bare chip relative to the wafer rework component exceeds a threshold range based on the offset information of the bare chip, and corrects the corresponding cell redistribution image for bare chips that exceed the threshold range to obtain a corrected redistribution image.

[0043] like Figure 4As shown, in the first method, the image generation system obtains an initial projection image based on the actual position information of the bare chip. In the initial projection image, the external solder joint connection area changes, causing the external solder joint connection area to be unable to connect to the external solder joint area that is subsequently manufactured. The unit image in the initial projection image is corrected in the following ways, including the correction of the external solder joint connection area and the connection line.

[0044] S1 corrects the external solder joint connection area in the initial projection image based on the external solder joint connection area in the standard redistribution image.

[0045] S2 connects the internal solder joint connection area and the modified external solder joint connection area.

[0046] S3 checks the corrected rewiring image for incorrect connections.

[0047] In step S1, the external solder joint connection area in the standard rewiring image corresponds to the position of the external solder joint connection point in the subsequent standard.

[0048] In step S2, the corrected external solder joint area differs from the position of the external solder joint in the initial redistribution pattern. Based on the actual positions of the corrected external solder joint connection area and the internal solder joint connection area, the corrected external solder joint connection area is connected to the internal solder joint connection area. In step S3, the corrected redistribution image is checked for problems such as crossovers or insufficient spacing between connecting lines that prevent the redistribution layer from performing its function. Based on the detected problems, the redistribution image is further corrected, fixing the problematic connecting lines.

[0049] like Figure 5 As shown, for the second method, the image generation system obtains an initial projection image based on the actual position information of the wafer component. In the initial projection image, the internal solder joint area changes, causing the internal solder joint area to be unable to connect to the internal solder joint of the bare chip. The cell image in the initial projection image is corrected in the following ways, including the correction of the internal solder joint area and the connection line.

[0050] S1 determines the actual position of the internal solder joints based on the offset information of the bare chip, and corrects the internal solder joint connection area in the initial projection image.

[0051] After S2 correction, the internal solder joint connection area is connected to the corresponding external solder joint connection area.

[0052] S3 checks whether there are erroneous connections in the rewiring structure in the corrected projected image.

[0053] In step S1, the actual position of the internal solder joint connection area is determined based on the actual position information of the bare chip, and the external solder joint connection area corresponds to the position of the external solder joint connection point in the subsequent standard.

[0054] In step S2, the external solder joint connection area and the corrected internal solder joint connection area are connected according to the wiring rules based on the actual position of the corrected internal solder joint connection area.

[0055] In step S3, the corrected redistribution image is checked to see if there are any problems such as crossovers or insufficient spacing between connecting lines that prevent the redistribution layer from performing its corresponding functions. Based on the detected problems, the redistribution image is further corrected to change the direction of the problematic connecting lines.

[0056] like Figure 6 As shown, the circuit pattern processing system for the redistribution layer of the wafer rewiring component realizes the circuit pattern processing of the redistribution layer through the following steps.

[0057] S11 Detect the actual position of each bare chip in the wafer reassembly: Using the image acquisition device, sequentially detect the marker point of each bare chip in the wafer reassembly and the alignment point of the wafer reassembly, and record the position information of the marker point and the alignment point.

[0058] S12 Determines whether the bare chip has shifted based on its actual position: Sets an offset threshold, determines the offset information of the bare chip relative to the wafer reassembly based on the information of the marker point and the alignment point, compares it with the offset threshold, and determines that the bare chip has not shifted within the offset threshold range, and that the bare chip has shifted if it exceeds the offset threshold.

[0059] S13 Generates a projection image based on the determination result of whether the bare chip in the wafer reassembly is offset: Adjusts the standard redistribution image according to the position information of the marker point or the position information of the alignment point to obtain an initial image, and corrects the cell image corresponding to the offset bare chip in the initial projection image to obtain a projection image corresponding to the actual position of the bare chip in the wafer reassembly.

[0060] S14 performs a projection operation on the wafer rework component based on the projection image to form a rewiring pattern.

[0061] The position information of the marker point and the alignment point in step S11 includes coordinate values ​​and rotation values. The offset value, rotation value and expansion / contraction value of the bare chip are obtained based on the position information of the marker point. The offset value, rotation value and expansion / contraction value of the wafer reassembly are obtained based on the position information of the alignment point.

[0062] The offset threshold in step S12 is set according to the design of the redistribution layer. When setting the bare die offset threshold, the displacement threshold, expansion threshold, and rotation threshold of the bare die relative to the wafer rework components can be set based on the area of ​​the internal solder joint connection area and the area of ​​the external solder joint connection area. Within the threshold range, even if the bare die has a certain offset relative to the predetermined position, the wiring structure can still connect the internal solder joint and the external solder joint. Bare dies that do not exceed the offset threshold range are considered as bare dies without offset, and bare dies that exceed the offset threshold range are considered as bare dies with positional offset.

[0063] In step S13, the unit image is corrected according to the method of correcting the unit image corresponding to the acquisition method of the initial image, so as to obtain a projection image corresponding to the actual position of the bare chip in the wafer reassembly.

[0064] In step S14, the carrier system and the projection system move relative to each other, so that the projection area of ​​the wafer re-component can receive the light emitted by the light source to form a redistribution pattern.

[0065] By setting an offset threshold, the number of offset bare chips that need to be processed is reduced, which helps to improve the processing speed of the image generation system. Simultaneously, the projected image obtained based on the actual position of the bare chip includes both the offset information of the wafer reassembly and the offset information of the bare chip itself, allowing the redistribution layer to more accurately connect internal and external solder joints.

[0066] The image generation system receives the position information of the bare chip and the wafer rewiring component detected by the alignment detection system, first determines whether the bare chip has shifted, and then generates an initial projection image based on the standard redistribution image; or generates an initial projection image based on the standard redistribution image and then determines whether the bare chip has shifted; or performs both simultaneously.

[0067] like Figure 7As shown, another embodiment of the redistribution layer processing system includes a first alignment detection system, a first image generation system, a second alignment detection system, a second image generation system, and a projection system. The first alignment detection system communicates with the first image generation system, and the first image generation system communicates with the second image generation system. The first image generation system obtains the position information of the bare chip and the wafer rework component through the first alignment detection system. The second image generation system obtains the position information of the wafer rework component through the second alignment detection system. The first image generation system determines whether the offset of the bare chip relative to the wafer rework component exceeds an offset threshold based on the actual position information of the bare chip. For bare chips exceeding the offset threshold, the standard redistribution pattern of the corresponding cell is corrected to obtain a corrected projection image. The second image generation system receives the corrected projection image output by the first image generation system and the alignment information from the second alignment detection system to obtain a projection image. The projection image from the second image generation system is output to the projection system, which projects the redistribution image onto the wafer rework component.

[0068] like Figure 8 As shown, the specific steps of the processing method of the rewiring layer processing system are as follows:

[0069] S21 The first alignment detection system detects the actual position of each bare die in the wafer reassembly component and obtains an initial projection image: Using the first alignment detection system, the alignment points of the wafer reassembly component and the marker points of each bare die are detected, and the position information of the alignment points and the marker points is recorded. Based on the position information of the marker points and the alignment points, the positional relationship of the bare die relative to the wafer reassembly component is obtained. Based on the information of the marker points and the standard redistribution image of the unit corresponding to each bare die in the standard redistribution image, alignment adjustment is performed to generate an initial projection image.

[0070] S22 determines whether the bare chip has shifted based on the marker point information and the alignment point information: according to the set offset threshold, the offset information of the bare chip relative to the wafer reassembly determined by the marker point and the alignment point information is compared with the offset threshold. If the offset threshold is within the range, the bare chip is determined not to have shifted; if the offset threshold is exceeded, the bare chip is determined to have shifted.

[0071] S23 Generates a corrected projection image based on the determination result of whether the bare chip in the wafer reassembly is offset: corrects the cell image corresponding to the bare chip whose position is offset in the initial projection image to obtain a corrected projection image corresponding to the actual position of the bare chip in the wafer reassembly.

[0072] S24 Repositions the wafer reassembly component and forms a projection pattern on it: The second alignment detection system obtains the position information of the wafer reassembly component again; the first image generation system transmits the corrected projection image to the second image generation system, the second image generation system obtains a projection image based on the position information of the wafer reassembly component obtained by the second alignment detection system and the corrected projection image, the projection image is output to the projection system, and the projection system projects the wafer reassembly component based on the projection image.

[0073] The alignment point location information in step S21 includes coordinate values ​​and rotation values, obtaining the offset, expansion, and rotation information of the wafer re-component. The marker point location information includes the marker point's coordinate values ​​and rotation values, obtaining the offset, expansion, and rotation information of the bare die relative to the wafer re-component based on the alignment point information of the wafer re-component. The standard redistribution image corresponds to the image of the redistribution layer when the bare die is located at a predetermined position on the wafer re-component under ideal conditions, and each bare die in the standard redistribution image corresponds to one unit standard redistribution image. The initial projection image can also be generated based on the alignment point information and the standard redistribution image.

[0074] The offset threshold in step S22 is set according to the design of the redistribution layer in the bare chip. When setting the bare chip offset threshold, the displacement threshold, expansion threshold, and rotation threshold of the bare chip relative to a predetermined position can be set based on the area of ​​the external solder joint connection area. A bare chip that does not exceed the offset threshold range is considered a bare chip that has not been offset; a bare chip that exceeds the offset threshold range is considered a bare chip with a positional offset. Within the threshold range, even if the bare chip has a certain offset relative to the predetermined position, the wiring structure adjusted according to the actual position of the bare chip can still connect the internal solder joint and the external solder joint.

[0075] In step S23, the unit image is corrected according to the method of correcting the unit image corresponding to the acquisition method of the initial image, so as to obtain a projection image corresponding to the actual position of the bare chip in the wafer reassembly.

[0076] In step S24, the carrier system and the projection system move relative to each other, so that the projection area of ​​the wafer re-component can receive the light emitted by the light source to form a redistribution pattern.

[0077] The wafer reassembly component is transferred from the first alignment detection system to the second alignment detection system via a transfer mechanism, or the wafer reassembly component is transferred from the first alignment detection system to the second alignment detection system via a transfer device.

[0078] The first alignment detection system and the first image generation system first correct the standard redistribution image according to the actual position of the bare chip, and then transfer the wafer re-component to the second alignment detection system and the projection system, thereby reducing the waiting time of the projection system, improving the fabrication time of the wafer re-component redistribution layer, and increasing efficiency.

[0079] like Figure 9-10 As shown, the circuit pattern processing system of the rewiring layer further includes a pattern detection system to detect major defects related to the device after projection.

[0080] A detection pattern is added to the projection pattern, and the detection pattern is projected simultaneously when the projection system projects an image onto the wafer component. The detection pattern is directly projected onto the wafer component, or, for cases where it is not suitable to form a detection pattern on the wafer component, a detection element is provided on at least one side of the wafer component. Preferably, detection elements are provided on two adjacent edges of the wafer component to facilitate the accuracy of detecting the detection pattern in two directions.

[0081] The alignment detection system acquires information about the detection pattern projected onto the wafer rework component or inspection piece, and outputs it to the pattern detection system. The pattern detection system judges the accuracy of the projected pattern based on the detection pattern, thereby obtaining the reliability of the exposure mechanism. In a second embodiment of the circuit pattern processing system for the redistribution layer, the second alignment detection system acquires information about the detection pattern and transmits it to the pattern detection system.

[0082] The preferred selection of the detection pattern is a regular pattern, such as parallel lines, squares, or circles.

[0083] The graphic detection system can promptly detect problems with the projection system, preventing the projection of critical wafer components using a faulty system, thus avoiding the scrapping of these components and unnecessary losses.

[0084] Corresponding to the circuit pattern processing system of the above-mentioned redistribution layer, a circuit pattern processing apparatus for the redistribution layer is provided. The circuit pattern processing apparatus for the redistribution layer includes a alignment detection system, an image generation system, a projection system, a pattern detection system, and a carrier system. The carrier system moves in the areas corresponding to the alignment detection system and the projection system. The alignment detection system communicates with the pattern generation system, the image generation system communicates with the projection system, and the alignment detection system communicates with the pattern detection system.

[0085] like Figure 11As shown, the support system 1 includes a support platform 10 and a driving mechanism, the driving mechanism drives the support platform to move, and the alignment detection system 2 includes at least one image acquisition device 20, the image acquisition device 20 is used to acquire alignment information and detection information.

[0086] The projection system 3 includes a light source assembly, a spatial light modulation element, and a projection assembly. Light emitted from the light source assembly is modulated by the spatial light modulation element to form a projected image, which is then projected onto the wafer reassembly component via the projection assembly. The spatial light modulation element is controlled based on the projected image obtained by the image generation system to obtain a modulated image, which is then projected onto the wafer reassembly component. The spatial light modulation element can be a digital micromirror array, a galvanometer, or other rotating polygon scanner with the same function for controlling the projection position of the light source.

[0087] The wafer re-component is placed on the carrier system 1. The carrier system 1 drives the wafer re-component sequentially through the alignment detection system 2 and the projection system 3. The alignment detection system 2 obtains the marker point information on the wafer re-component. The marker point information includes alignment point information corresponding to the wafer re-component's position information and marker point information corresponding to the bare chip's position information. The alignment detection system 2 transmits the obtained marker point information to the image generation system. The image generation system corrects the standard redistribution image based on the marker point information. Simultaneously, it adds a detection pattern to the corrected redistribution image to obtain a projection image. The projection image is projected onto the wafer re-component by the projection system, forming a redistribution pattern and a detection pattern. The alignment detection system 2 scans the wafer re-component again to obtain an image of the detection pattern. The reliability of the circuit pattern processing device for the redistribution layer is monitored based on the detection pattern.

[0088] Preferably, at least one side of the support platform is provided with a detection element 11, which forms a detection pattern after being projected by a projection system. The projection pattern is formed on the detection element 11 while the wafer component is being projected. The detection element includes a photosensitive layer that forms the detection pattern after receiving light from the projection system. Preferably, the photosensitive layer can return to its initial state after a period of time and can be reused. Alternatively, the photosensitive layer can be replaced with a thermally sensitive layer, which forms the detection pattern by utilizing the temperature change generated by the light beam.

[0089] Preferably, detection elements 11 are provided on two adjacent sides of the support platform 10 to monitor the reliability of the processing device for the circuit pattern of the redistribution layer in two directions.

[0090] like Figure 12As shown in another embodiment of the circuit pattern processing device for the redistribution layer, the carrier system 1 includes a first carrier platform 100 and a second carrier platform 200, the alignment detection system 2 includes a first alignment detection mechanism 300 and a second alignment detection mechanism 400, and the projection system 3 is disposed between the first alignment detection mechanism 300 and the second alignment detection mechanism 400. The first carrier platform 100 moves in the corresponding area of ​​the first alignment detection mechanism 300 and the projection system 3, and the second carrier platform 200 moves in the corresponding area of ​​the second alignment detection mechanism 400 and the projection system 3. The first carrier platform 100 and the second carrier platform 200 move sequentially to the corresponding area of ​​the projection system 3, making full use of the projection system 3, reducing the idle time of the projection system 3, and improving the efficiency of the circuit pattern processing device for the redistribution layer.

Claims

1. A system for processing rewiring circuit patterns, characterized in that: The processing system includes an alignment detection system, an image generation system, and a projection system. The alignment detection system acquires the position information of the alignment point on the wafer rework component and the position information of the marker point on the bare chip to obtain the actual position information of the bare chip. The image generation system determines whether the offset of the bare chip relative to the wafer rework component exceeds an offset threshold based on the actual position information of the bare chip. If the offset threshold is within the range, the bare chip is considered to have not been offset; if it exceeds the offset threshold, the bare chip is considered to have been offset. The standard redistribution image is adjusted according to the position information of the marker point or the position information of the alignment point to obtain an initial projection image. The cell projection image corresponding to the bare chip that is identified as having been offset in the initial projection image is corrected to obtain a projection image corresponding to the actual position of the bare chip in the wafer rework component. The projection system forms a redistribution circuit pattern on the wafer rework component based on the projection image. The rewiring circuit pattern processing system also includes a pattern detection system. When the projection system projects an image onto the wafer rewiring component, it simultaneously projects and detects the pattern. The alignment detection system acquires the information of the detected pattern and outputs it to the pattern detection system. The pattern detection system determines the reliability of the projection system by judging the accuracy of the detected pattern.

2. The processing system according to claim 1, characterized in that: The offset threshold is set according to the design of the standard redistribution layer. When setting the bare chip offset threshold, it is determined based on the area of ​​the external solder joint connection area, or based on the area of ​​the internal solder joint connection area and the external solder joint connection area.

3. The processing system according to claim 1, characterized in that: The offset thresholds include displacement thresholds, expansion / contraction thresholds, and rotation thresholds.

4. The processing system according to claim 1, characterized in that: The alignment detection system includes a first alignment detection system and a second alignment detection system. The image generation system includes a first image generation system and a second image generation system. The first alignment detection system communicates with the first image generation system. The first image generation system determines whether the offset of the bare chip relative to the wafer rework component exceeds an offset threshold based on the actual position information of the bare chip. For bare chips that exceed the offset threshold, the standard redistribution pattern of the corresponding cell is corrected to obtain a corrected redistribution image. The second image generation system receives the redistribution image output by the first image generation system and the alignment information from the second alignment detection system to obtain a projection image. The projection image from the second image generation system is output to the projection system.

5. The processing system according to claim 1, characterized in that: The pattern detection system also includes a detection component. When the projection system projects the wafer component, it simultaneously projects a detection pattern onto the detection component. The alignment detection system acquires information about the detection pattern on the detection component and outputs it to the pattern detection system.

6. A method for processing rewiring circuit patterns using any one of the processing systems of claims 1-5, characterized in that: The alignment detection system obtains the position information of the alignment points of the wafer reassembly and the position information of the marker points of the bare die, thereby obtaining the actual position information of the bare die. Based on the actual position information of the bare die, the system obtains the offset information of the bare die. The alignment detection system transmits the offset information of the bare die to the image generation system. The image generation system determines whether the offset of the bare die relative to the wafer reassembly exceeds an offset threshold based on the actual position information of the bare die. If the offset is within the threshold range, the bare die is considered not to have shifted; if it exceeds the threshold, the bare die is considered to have shifted. The system then uses the position information of the marker points... Alternatively, the position information of the alignment point is adjusted to obtain an initial projection image from the standard redistribution image. The projection image of the cell corresponding to the bare chip that is identified as having shifted in the initial projection image is corrected to obtain a projection image corresponding to the actual position of the bare chip in the wafer rework component. The projection system forms a redistribution circuit pattern on the wafer rework component based on the projection image. When the projection system projects an image onto the wafer rework component, it simultaneously projects a detection pattern. The alignment detection system acquires the information of the detection pattern and outputs it to the pattern detection system. The pattern detection system obtains the reliability of the projection system by judging the accuracy of the detection pattern.

7. The processing method according to claim 6, characterized in that: The correction of the cell projection image corresponding to the bare chip exceeding the threshold range includes: correcting the external solder joint area in the initial projection image according to the external solder joint connection area in the standard redistribution image; connecting the internal solder joint connection area and its corrected external solder joint connection area; and checking whether there are erroneous connections in the updated redistribution structure.

8. The processing method according to claim 6, characterized in that: The actual position of the internal solder joints is determined based on the offset information of the bare chip, and the internal solder joint connection area in the initial projection image is corrected; the corrected internal solder joint connection area is connected to the corresponding external solder joint connection area; the redistribution structure in the corrected projection image is checked for incorrect connections.

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