Display panel and its data driving circuit, driving method and electronic equipment

Abstract

This application discloses a display panel and its data driving circuit, driving method, and electronic device. The data driving circuit includes a signal input module, a signal processing module, and a signal output module electrically connected to a pixel circuit. The signal input module is used to acquire image data, which includes a first set of metadata and a second set of metadata serially connected to it. The signal processing module is electrically connected to the signal input module and is used to acquire the second set of metadata from the signal input module and process the second set of metadata to obtain a first data signal when a first enable signal is received. The enable period of the first enable signal is within a first time period, which is a delay period during which the signal output module outputs the second data signal to the pixel circuit. The second data signal is the data signal obtained by the signal processing module processing the first set of metadata.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display panel and its data driving circuit, driving method and electronic device. Background Technology

[0002] With the rapid development of display technology, Organic Light-Emitting Diode (OLED) display panels are gradually becoming mainstream. Existing OLED panels incorporate pixel circuits and data driving circuits. The data signal output by the data driving circuit provides a charging signal for the storage capacitors in the pixel circuits. However, due to the operating delay of the gamma module in the driving circuit and the panel's RC (resistor-capacitor) circuitry, the charging time of the storage capacitors is insufficient, thus affecting the display panel's performance. Summary of the Invention

[0003] This application aims to provide a display panel and its data driving circuit, driving method and electronic device, which are intended to improve the problem of insufficient charging time of storage capacitors caused by delay and improve the display effect of the panel.

[0004] In a first aspect, embodiments of this application propose a data driving circuit, including a signal input module, a signal processing module, and a signal output module electrically connected to the pixel circuit; wherein...

[0005] The signal input module can be used to acquire image data, which may include a first set of metadata and a second set of metadata in serial form.

[0006] The signal processing module can be electrically connected to the signal input module. When the first enable signal is received, the signal processing module can obtain a second set of metadata from the signal input module and process the second set of metadata to obtain a first data signal. The enable period of the first enable signal is located within a first time period. The first time period is the delay period during which the signal output module outputs the second data signal to the pixel circuit. The second data signal is the data signal obtained by the signal processing module after processing the first set of metadata.

[0007] Secondly, embodiments of this application provide a display panel, which includes the data driving circuit described in the first aspect above.

[0008] Thirdly, embodiments of this application provide an electronic device, which includes a data driving circuit as described in the first aspect or a display panel as described in the second aspect.

[0009] Fourthly, embodiments of this application also propose a method for driving a display panel, the method comprising:

[0010] Within a first time period after processing the first set of metadata and upon receiving the first enable signal, the second set of metadata is obtained from the image data, and the second set of metadata is processed to obtain the first data signal.

[0011] The first time period is a delay period for outputting the second data signal to the pixel circuit. The second data signal is the data signal obtained by processing the first set of metadata. The image data includes the first set of metadata and the second set of metadata in sequence.

[0012] In the embodiments of this application, a signal input module, a signal processing module, and a signal output module electrically connected to the pixel circuit are provided in the data driving circuit. The signal input module is capable of acquiring image data, which may include a first set of metadata and a second set of metadata serially connected. The signal processing module, electrically connected to the signal input module, is capable of acquiring the second set of metadata from the signal input module upon receiving a first enable signal, and processing the second set of metadata to obtain a first data signal. Since the enabling period of the first enable signal is within the delay period of the signal output module outputting the second data signal to the pixel circuit, and this second data signal is the data signal obtained by the signal processing module processing the first set of metadata serially connected to the second set of metadata, the signal processing module can be triggered to acquire the next set of data signals within the delay period of outputting the second data signal to the pixel circuit. This takes into account the delay effect when the data driving circuit outputs data signals, and by processing the signal in advance, increases the charging time of the storage capacitor, thus helping to improve the display effect of the display panel.

[0013] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0014] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0015] Figure 1 This is a schematic diagram of a pixel circuit involved in the data driving circuit according to an embodiment of this application;

[0016] Figure 2 This is a signal timing diagram of a pixel circuit involved in the data driving circuit according to an embodiment of this application;

[0017] Figure 3 This is a schematic diagram of a module structure of a data driving circuit according to an embodiment of this application;

[0018] Figure 4This is a signal timing diagram of the data driving circuit according to an embodiment of this application;

[0019] Figure 5 This is a schematic diagram of another module structure of the data driving circuit according to an embodiment of this application.

[0020] Figure label:

[0021] Pixel circuit 10; driving module 11; light emission control module 12; initialization module 13; data writing module 14; compensation module 15; reset module 16;

[0022] Light-emitting element 20;

[0023] Signal input module 31; signal processing module 32; signal output module 33; switch module 34; buffer 311; main logic processor 312; shift register 313;

[0024] First enable signal 1st-Latch-EN; Second enable signal 2nd-Latch-EN;

[0025] Drive transistor T0; First transistor T1;

[0026] Data signal Source; First scan signal S1;

[0027] Reset / set trigger latch; Analog-to-digital converter (DAC); Operational amplifier (AMP). Detailed Implementation

[0028] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] In the description of this application, it should be understood that the terms "center", "depth", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0031] With the development of display technology, display panels are widely used in electronic devices such as mobile phones, televisions, laptops, and computers. These display panels can be OLED display panels. For example, the OLED display panel can be an Active Matrix Organic Light Emitting Diode (AMOLED) panel. The display panel can include pixel circuits, light-emitting elements, and driving circuits that provide various signals to the pixel circuits.

[0032] The pixel circuit can be a 2T1C, 7T1C, 8T1C, or 8T2C circuit structure. The light-emitting element can be a light-emitting diode (LED), OLED, or others. The driving circuit can include at least one of a gate driving circuit, a light-emitting control driving circuit, and a data driving circuit.

[0033] Please refer to Figure 1 To illustrate the pixel circuit, we take the common 7T1C structure as an example. That is, the pixel circuit 10 consists of 7 thin film transistors (TFTs) and 1 capacitor (C).

[0034] The pixel circuit 10 can be used to provide driving current to the light-emitting element 20 of the display panel. The pixel circuit 10 can also be connected to a data signal line (not shown). The data signal line can transmit the data signal Source output by the data driving circuit to the pixel circuit 10.

[0035] The pixel circuit 10 described above may include a driving module 11, a light emission control module 12, an initialization module 13, a data writing module 14, a compensation module 15, and a reset module 16. The driving module 11 may include a driving transistor T0, whose gate can receive the data signal Source written by the data driving circuit.

[0036] The data writing module 14 can be used to selectively provide a data signal Source to the driving transistor T0; the data writing module 14 may include a first transistor T1. The drain of the first transistor T1 can be connected to the source of the driving transistor T0, the source of the first transistor T1 can be connected to the data signal line, and it can receive the data signal Source. The control terminal of the first transistor T1 can be connected to the first scan signal line (not shown), and it can be used to receive the first scan signal S1. The first scan signal S1 can control the first transistor T1 to turn on and off.

[0037] It should be noted that, based on Figure 1 The optional circuit structure of the pixel circuit 10 and the light-emitting element 20 of the display panel shown requires precise control of each signal, especially the data signal, in order for the pixel circuit 10 to provide driving current to the light-emitting element 20 in an orderly manner, so as to ensure the display effect of the display panel.

[0038] However, during the actual operation of the display panel, due to the influence of manufacturing process and thin-film transistor characteristics, the display panel is prone to display abnormalities such as uneven display and image retention.

[0039] Special combination Figure 1 and Figure 2 It can be observed that only one line of time is reserved as charging time for the storage capacitor in the pixel circuit. This line time is related to the frame rate and refresh rate of the display panel, and the calculation method for this line time can be referred to the following formula (1).

[0040] Line time = 1 ÷ frame rate ÷ (number of valid lines + number of blank lines) (1)

[0041] In practical applications, the gamma module in the data driver circuit has a high bit depth (for example, a 10-bit gamma module). Higher bit depth leads to greater latency, resulting in higher latency during analog signal processing. Furthermore, increased panel area and pixel count also introduce latency in the panel's RC circuit, causing insufficient charging time for the storage capacitor within a single line. This is particularly pronounced in higher resolution and frame rate solutions, such as a 3200x1440 pixel resolution display panel with a 120Hz refresh rate, where the deterioration in display quality due to various latency issues becomes increasingly apparent.

[0042] To address the aforementioned technical problems, this application provides a display panel and its data driving circuit, driving method, and electronic device. The data driving circuit provided in this application will be described first below.

[0043] Please refer to Figure 3 and Figure 4 ,in Figure 3The diagram shows an optional circuit structure schematic of the data driving circuit according to an embodiment of this application. Figure 4 It shows Figure 3 The timing diagram of each module and signal processing in the data driving circuit.

[0044] The data driving circuit can be a driver chip for the display panel. The data driving circuit may include a signal input module 31, a signal processing module 32, and a signal output module 33 electrically connected to the pixel circuit 10. The signal processing module 32 can be disposed between the signal input module 31 and the signal output module 33.

[0045] The signal input module 31 can be used to acquire image data. The image data may include a first set of metadata and a second set of metadata in serial form.

[0046] For example, please refer to the following: Figures 3 to 5 The signal input module 31 may include a buffer 311, a main logic processor 312, and a shift register 313. The buffer 311 can be used to buffer image data; for example, the buffer 311 can buffer one frame of image data at a time. The buffer 311 can be random access memory (RAM), such as static random access memory (SRAM). The main logic processor 312 can process the image data to form m sets of serial metadata. These m sets of metadata can be shifted line by line via the shift register 313.

[0047] The signal output module 33 can be the output pin of the driver chip, which can be electrically connected to the data signal line to provide a data signal source for each pixel circuit 10.

[0048] Please continue reading. Figure 3 and Figure 4 The signal processing module 32 can be used to obtain a second set of metadata from the signal input module 31 when a first enable signal 1st-Latch-EN is received.

[0049] The second set of metadata can be a set of metadata used to generate data signals. It should be noted that the first set of metadata and the second set of metadata are relative concepts. For example, when m-1 sets of metadata are the first set of metadata, m sets of metadata are the second set of metadata; when m sets of metadata are the first set of metadata, m+1 sets of metadata are the second set of metadata.

[0050] After obtaining the second set of metadata, the signal processing module 32 can further process the second set of metadata to obtain the first data signal. For example, the above processing operations may include digital-to-analog conversion and voltage regulation.

[0051] The enabling period of the aforementioned first enable signal 1st-Latch-EN can be located within a first time period, which can be the delay period during which the signal output module 33 outputs the second data signal to the pixel circuit 10. This delay period can refer to the time period during which the signal output module 33 has finished outputting the second data signal, but the pixel circuit 10 has not yet fully received the second data signal due to the delay. For example, this delay period can refer to... Figure 4 The time period is 410.

[0052] The aforementioned second data signal can be the data signal obtained by the signal processing module 32 processing the first set of metadata. That is, within the previous line time, the second data signal can be obtained by processing the first set of metadata. After the second data signal is output to the pixel circuit 10, but during the delay period when the pixel circuit 10 is still receiving the second data signal, the second set of metadata is converted into the first data signal by triggering the first enable signal 1st-Latch-EN.

[0053] In these embodiments, a signal input module 31, a signal processing module 32, and a signal output module 33 electrically connected to the pixel circuit 10 are provided in the data driving circuit. The signal input module 31 receives image data, which may include a first set of metadata and a second set of metadata serially connected. The signal processing module 32, electrically connected to the signal input module 31, receives a first enable signal 1st-Latch-EN, obtains the second set of metadata from the signal input module 31, processes the second set of metadata, and obtains a first data signal. Since the enabling period of the first enable signal 1st-Latch-EN is within the delay period of the signal output module 33 outputting the second data signal to the pixel circuit 10, and the second data signal is the data signal obtained by the signal processing module 32 processing the first set of metadata, the first set of metadata and the second set of metadata are serially connected. Therefore, during the delay period of outputting the second data signal to the pixel circuit 10, the signal processing module 32 can be triggered to acquire the next set of metadata and the next set of data signals (i.e., the first data signal). This takes into account the delay effect of the data driving circuit outputting the data signal. By processing the signal in advance, the effective proportion of the data signal in one line time is increased, which indirectly increases the charging time of the storage capacitor and helps to improve the display effect of the display panel.

[0054] In some alternative implementations, please continue to refer to Figure 3 and Figure 4In addition to preprocessing the second set of metadata to compensate for signal delay, a switch module 34 can be set between the signal processing module 32 and the signal output module 33 to avoid interference from the first data signal obtained in advance to the signal of the current row.

[0055] In this embodiment, the switch module 34 can be electrically connected between the signal processing module 32 and the signal output module 33. The switch module 34 can remain in the off state when the signal processing module 32 receives the first data signal but does not receive the horizontal synchronization signal.

[0056] The function of the aforementioned row synchronization signal is to select the interval of valid row signals, indicating the start of a row signal. In this example, the row synchronization signal can indicate the time when the output of the first data signal has been reached.

[0057] It should be noted that when the signal processing module 32 obtains the first data signal, by setting the switch module 34 and keeping the switch module 34 in the off state before the output time of the first data signal is reached (i.e., before the horizontal synchronization signal is received), the signal can be isolated, preventing the first data signal from being output to each pixel circuit 10 through the signal output module 33 during the output time of the second data signal. This can maintain the stability of the data signal during the current line time and avoid the premature processing of the first data signal from affecting the display effect of the current display panel.

[0058] In some alternative implementations, please continue to refer to Figure 3 and Figure 4 Furthermore, the aforementioned switch module 34 can remain in the conducting state during the second time period after the signal processing module 32 receives the horizontal synchronization signal.

[0059] The second time period is related to the output duration of the first data signal. That is, after receiving the line synchronization signal, the switch module 34 is turned on, and the on duration of the switch module 34 can be consistent with the output duration of the first data signal.

[0060] It should be noted that after receiving the line synchronization signal, indicating the arrival of the effective line time corresponding to the first data signal, the signal output module 33 needs to output the first data signal to the pixel circuit 10. At this time, it is necessary to ensure that the signal processing module 32 and the signal output module 33 are connected. By keeping the state of the switch module 34 in the on state during the second time period, it can be ensured that the first data signal is stably output through the signal output module 33 during the second time period, so that the first data signal is smoothly output to the pixel circuit 10, thus ensuring the display effect of the display panel.

[0061] In some alternative implementations, please continue to refer to Figures 3 to 5 ,in Figure 5A schematic diagram of an optional detailed circuit structure for signal processing module 32 is shown. Signal processing module 32 may include a reset / set trigger latch, a digital-to-analog converter (DAC), a gamma module (not shown), and an operational amplifier (AMP).

[0062] The reset / set trigger latch can be electrically connected to the signal input module 31. For example, the reset / set trigger latch can be electrically connected to the shift register 313 in the signal input module 31, thereby obtaining the target metadata in the signal input module 31 from the shift register 313.

[0063] The target metadata can be any set of all metadata. For example, the target metadata can be either the second set of metadata or the first set of metadata mentioned above.

[0064] The reset / set trigger latch can receive an enable signal and, upon receiving such a signal, triggers access to or latches target metadata. It should be noted that, when the reset / set trigger latch receives an enable signal, the latching operation and the trigger access operation of the target metadata are performed alternately, thereby accurately achieving the switching of various data signals and stable output.

[0065] The digital-to-analog converter (DAC) can be electrically connected to the reset / set trigger latch and the gamma module. This DAC performs digital-to-analog conversion. Because the target metadata accessed or latched in the reset / set trigger latch is a digital signal, the DAC can convert the target metadata into an analog signal and output it.

[0066] The aforementioned gamma module can be configured with multiple sets of precision resistor strings according to the adjustment accuracy. These precision resistor strings can adjust the voltage of the analog signal through voltage division to obtain a gamma voltage (i.e., a data signal). The obtained gamma voltage conforms to the gamma curve, which can help to subsequently adjust the brightness of the display panel.

[0067] It should be noted that because the gamma module uses multiple sets of precision resistors and adjusts analog signals, its adjustment process has a longer delay compared to the operation of digital circuits, making it the main source of delay in the data drive circuit. Therefore, when setting the delay period for the data signal, the processing delay of the gamma module can be used as a reference for specific settings.

[0068] After obtaining the data signal through the gamma module, the amplitude of the data signal can be adjusted by the operational amplifier AMP before output. It is understood that in the signal processing module 32, the input terminal of the operational amplifier AMP can be electrically connected to the common terminal of the gamma module and the digital-to-analog converter (DAC), and the output terminal of the operational amplifier AMP serves as the output terminal of the signal processing module 32, electrically connected to subsequent links. For example, please continue to refer to... Figure 5 The output of the operational amplifier AMP can be electrically connected to the switching module 34.

[0069] Optionally, the above-mentioned amplitude adjustment of the data signal can be achieved by amplifying the data signal.

[0070] In some optional examples, when the reset / set trigger Latch in the signal processing module 32 receives the first enable signal 1st-Latch-EN, the reset / set trigger Latch can trigger the access of the second set of metadata from the shift register 313. At the same time, the digital-to-analog converter DAC, gamma module and operational amplifier AMP in the signal processing module 32 will work together with the operation of the reset / set trigger Latch to gradually convert the obtained second set of metadata into the first data signal.

[0071] In these embodiments, optional circuit structures of the signal processing module 32 are shown, and the implementation process of converting the second set of metadata into the first data signal is given.

[0072] In some alternative implementations, please continue to refer to Figures 3 to 5 The aforementioned reset / set trigger Latch can be specifically used to latch the second set of metadata when the second enable signal 2nd-Latch-EN is received, so that the signal processing module 32 can stably output the first data signal through the signal output module 33.

[0073] The enabling period of the second enabling signal 2nd-Latch-EN is T1. The start time of T1 can be determined according to the start time of the above-mentioned line synchronization signal. For example, the start time of T1 can be the same as the start time of the above-mentioned line synchronization signal.

[0074] It should be noted that after the reset / set trigger latch receives the first enable signal 1st-Latch-EN, the first data signal obtained by the signal processing module 32 remains in the circuit and is not output through the signal output module 33 because the switch module 34 remains in the off state. When the effective line time of the first data signal is reached (i.e., when the line synchronization signal is received), the switch module 34 switches from the off state to the on state, at which time the first data signal can be output to the pixel circuit 10 through the signal output module 33. When the effective line time of the first data signal is reached, the reset / set trigger latch is enabled by the second enable signal 2nd-Latch-EN. The reset / set trigger latch switches from the trigger access state to the latching state, which can latch the second set of metadata. This ensures that the data signal is stably output through the operational amplifier AMP, switch module 34 and signal output module 33 during the current line time, thus ensuring the display effect of the display panel during the current line time.

[0075] The above text combines Figures 1 to 5 The present application describes in detail the data driving circuit of the embodiments thereof. Based on this, the present application also protects a display panel and an electronic device, wherein the electronic device may include a housing and a display panel, the display panel may include pixel circuitry and the data driving circuitry of any of the examples described above.

[0076] The electronic device may include a display panel or a data driving circuit as described in any of the above examples. The electronic device may be at least one of a wearable device, camera, mobile phone, tablet computer, television, or vehicle-mounted terminal. The electronic device and display panel include the data driving circuit provided in the above embodiments, and therefore the electronic device and display panel possess all the beneficial effects of the aforementioned data driving circuit.

[0077] Based on the above-described data driving circuit, display panel, and electronic device, this application embodiment also provides a driving method for a display panel. In this embodiment, the method may include:

[0078] A1, within a first time period after processing the first set of metadata and upon receiving the first enable signal, obtains the second set of metadata from the image data, processes the second set of metadata, and obtains the first data signal.

[0079] The first time period is a delay period for outputting the second data signal to the pixel circuit. The second data signal can be a data signal obtained by processing the first set of metadata. The image data can include the first set of metadata and the second set of metadata in sequence.

[0080] The above-mentioned display panel driving method can be applied to driver chips, signal processing modules in data driving circuits, and other controllers.

[0081] In these embodiments, because the enabling period of the first enable signal is located within the delay period of outputting the second data signal to the pixel circuit, and the second data signal is a data signal obtained by processing the first set of metadata, which is serial to the second set of metadata, the acquisition of the next set of data signals can be triggered within the delay period of outputting the second data signal to the pixel circuit. This takes into account the delay effect of outputting the data signal, and improves the effective proportion of the data signal in one line time by processing the signal in advance, indirectly increasing the charging time of the storage capacitor and helping to improve the display effect of the display panel.

[0082] In some alternative embodiments, the following step may be included after A1:

[0083] A2, if no line synchronization signal is received, the output of the first data signal to the pixel circuit is prohibited.

[0084] The function of the aforementioned row synchronization signal is to select the interval of valid row signals, indicating the start of a row signal. In this example, the row synchronization signal can indicate the time when the output of the first data signal has been reached.

[0085] In these embodiments, after obtaining the first data signal, and before the output time of the first data signal is reached, by prohibiting the output of the first data signal to the pixel circuit, the stability of the data signal within the current row time can be maintained, and the premature processing of the first data signal can be avoided from affecting the display effect of the current display panel.

[0086] It should be noted that the above-mentioned method of prohibiting the output of the first data signal to the pixel circuit can be achieved by setting a switch module between the pixel circuit and the first link, and controlling the switch module to be in the off state. The first link can be the link after the circuit that generates the first data signal and before the pixel circuit.

[0087] In some alternative embodiments, the following step may be included after A1:

[0088] A3, upon receiving the line synchronization signal, latches the second set of metadata to continuously output the first data signal to the pixel circuit.

[0089] It should be noted that after receiving the first enable signal, the processed first data signal is still retained and not output. Upon receiving the line synchronization signal, the first data signal can be output to the pixel circuit. At this time, the second enable signal can be used to enable the latching of this second set of metadata, thereby ensuring the stable output of the first data signal within the current line time and guaranteeing the display effect of the display panel within the current line time.

[0090] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0091] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A data driving circuit, characterized in that, It includes a signal input module, a signal processing module, and a signal output module electrically connected to the pixel circuit; wherein, The signal input module is used to acquire image data, which includes a first set of metadata and a second set of metadata in serial order. The signal processing module, electrically connected to the signal input module, is used to obtain the second set of metadata from the signal input module upon receiving a first enable signal, and process the second set of metadata to obtain a first data signal. The enable period of the first enable signal is located within a first time period, which is a delay period during which the signal output module outputs the second data signal to the pixel circuit. The second data signal is the data signal obtained by the signal processing module after processing the first set of metadata. The delay period refers to the time period during which the signal output module has finished outputting the second data signal, but the pixel circuit has not yet fully received the second data signal due to the delay. The signal processing module includes: A reset / set trigger, electrically connected to the signal input module, is used to trigger access to or latch target metadata based on the received enable signal, wherein the image data includes the target metadata; A digital-to-analog converter, electrically connected to the reset / set trigger, is used to convert the target metadata into an analog signal; The gamma module, electrically connected to the digital-to-analog converter, is used to adjust the voltage of the analog signal according to the gamma curve to obtain a data signal; An operational amplifier, electrically connected to the common terminal of the gamma module and the digital-to-analog converter, is used to output the data signal after amplitude adjustment; The reset / set trigger is specifically used to latch the second set of metadata when a second enable signal is received. The enable period of the second enable signal is T1, and the start time of T1 is determined according to the start time of the line synchronization signal. The gamma module includes multiple sets of precision resistor strings, which adjust the voltage of the analog signal by voltage division to obtain a data signal.

2. The data driving circuit according to claim 1, characterized in that, Also includes: A switch module, electrically connected between the signal processing module and the signal output module, is used to maintain a cut-off state when the signal processing module receives the first data signal but does not receive a horizontal synchronization signal.

3. The data driving circuit according to claim 2, characterized in that, The switching module is also configured to remain in an on state for a second period of time after the signal processing module receives the line synchronization signal, the second period of time being related to the output duration of the first data signal.

4. A display panel, characterized in that, The display panel includes the data driving circuit according to any one of claims 1 to 3.

5. An electronic device, characterized in that, The electronic device includes the data driving circuit according to any one of claims 1 to 3 or the display panel according to claim 4.

6. A driving method for a display panel, characterized in that, The method is applied to the data driving circuit according to any one of claims 1 to 3, and the method includes: Within a first time period after processing the first set of metadata and upon receiving the first enable signal, the second set of metadata is obtained from the image data, and the second set of metadata is processed to obtain the first data signal; Wherein, the first time period is a delay period for outputting the second data signal to the pixel circuit, the second data signal is a data signal obtained by processing the first set of metadata, and the image data includes the first set of metadata and the second set of metadata serially; the delay period refers to the period when the signal output module has finished outputting the second data signal, but the pixel circuit has not yet fully received the second data signal due to the delay. The process of processing the second set of metadata to obtain the first data signal includes: Based on the received first enable signal, access to the second set of metadata is triggered; Convert the second set of metadata into an analog signal; The voltage of the analog signal is adjusted according to the gamma curve to obtain the first data signal; The first data signal is output after amplitude adjustment; Upon receiving the second enable signal, the second set of metadata is latched. The enable period of the second enable signal is T1, and the start time of T1 is determined according to the start time of the line synchronization signal. The step of adjusting the voltage of the analog signal according to the gamma curve to obtain the first data signal includes: The first data signal is obtained by voltage regulation of the analog signal through voltage division.

7. The method according to claim 6, characterized in that, After obtaining the first data signal, the process further includes: If a line synchronization signal is not received, the output of the first data signal to the pixel circuit is prohibited.

8. The method according to claim 7, characterized in that, After obtaining the first data signal, the process further includes: Upon receiving the line synchronization signal, the second set of metadata is latched to continuously output the first data signal to the pixel circuit.

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