Magnetic storage device

Abstract

Embodiments provide a magnetic storage device that can reduce the size of a storage cell. According to one embodiment, the magnetic storage device includes first to third conductor layers, and a three-terminal storage cell connected to the first to third conductor layers. The first storage cell includes a fourth conductor layer, a magnetoresistance effect element, a two-terminal first switching element, and a two-terminal second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer. The magnetoresistance effect element is connected between the third conductor layer and the fourth conductor layer. The first switching element is connected between the second conductor layer and the fourth conductor layer. The second switching element is connected between the first conductor layer and the third conductor layer.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2021-146187, filed September 8, 2021, and U.S. Patent Application No. 17 / 682667, filed February 28, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to magnetic storage devices. Background Technology

[0004] Magnetic storage devices that use magnetoresistive elements as storage elements are known. Various methods for writing data to magnetoresistive elements have been proposed. Summary of the Invention

[0005] Various embodiments provide a magnetic storage device that can reduce the size of the storage cell.

[0006] Generally, according to one embodiment, a magnetic storage device includes a first conductor layer, a second conductor layer, a third conductor layer, and a three-terminal first storage cell connected to the first, second, and third conductor layers. The first storage cell includes a fourth conductor layer, a first magnetoresistive element, a two-terminal first switching element, and a two-terminal second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer. The first magnetoresistive element is connected between the third and fourth conductor layers. The first switching element is connected between the second and fourth conductor layers. The second switching element is connected between the first and third conductor layers. Attached Figure Description

[0007] Figure 1 This is a block diagram of a magnetic storage device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of a memory cell array according to the first embodiment.

[0009] Figure 3 This is a plan view of the storage cell array according to the first embodiment.

[0010] Figure 4 This is a cross-sectional view of the storage cell array according to the first embodiment.

[0011] Figure 5 This is a cross-sectional view of the magnetoresistive element and peripheral wiring according to the first embodiment.

[0012] Figure 6This is a diagram illustrating an example of the characteristics of the switching element of a magnetic storage device according to a first embodiment.

[0013] Figure 7 This is a diagram illustrating an example of the characteristics of the switching element of a magnetic storage device according to a first embodiment.

[0014] Figure 8 This is a circuit diagram relating to a write operation in a magnetic storage device according to the first embodiment.

[0015] Figure 9 This is a cross-sectional view relating to a write operation in a magnetic storage device according to the first embodiment.

[0016] Figure 10 This is a cross-sectional view relating to a write operation in a magnetic storage device according to the first embodiment.

[0017] Figure 11 This is a circuit diagram relating to a read operation in a magnetic storage device according to the first embodiment.

[0018] Figure 12 This is a cross-sectional view relating to a read operation in a magnetic storage device according to the first embodiment.

[0019] Figure 13 This is a cross-sectional view of the magnetoresistive element and peripheral wiring according to a first modification of the first embodiment.

[0020] Figure 14 This is a circuit diagram relating to a write operation in a magnetic storage device according to a first modified example of the first embodiment.

[0021] Figure 15 This is a circuit diagram relating to a write operation in a magnetic storage device according to a first modified example of the first embodiment.

[0022] Figure 16 This is a cross-sectional view relating to a write operation in a magnetic storage device according to a first modified example of the first embodiment.

[0023] Figure 17 This is a cross-sectional view of the magnetoresistive element and peripheral wiring according to the second modification of the first embodiment.

[0024] Figure 18 This is a circuit diagram relating to a write operation in a magnetic storage device according to a second modified example of the first embodiment.

[0025] Figure 19 This is a cross-sectional view relating to a write operation in a magnetic storage device according to a second modified example of the first embodiment.

[0026] Figure 20 This is a plan view of the storage cell array according to the third modification of the first embodiment.

[0027] Figure 21 This is a cross-sectional view of the magnetoresistive element and peripheral wiring according to the third modification of the first embodiment.

[0028] Figure 22 This is a circuit diagram relating to a write operation in a magnetic storage device according to a third modified example of the first embodiment.

[0029] Figure 23 This is a cross-sectional view relating to a write operation in a magnetic storage device according to a third modification of the first embodiment.

[0030] Figure 24 This is a circuit diagram of a memory cell array according to the second embodiment.

[0031] Figure 25 This is a plan view of the storage cell array according to the second embodiment.

[0032] Figure 26 This is a cross-sectional view of the storage cell array according to the second embodiment.

[0033] Figure 27 This is a circuit diagram of a memory cell array according to the third embodiment.

[0034] Figure 28 This is a plan view of the storage cell array according to the third embodiment.

[0035] Figure 29 This is a cross-sectional view of a storage cell array according to a third embodiment.

[0036] Figure 30 This is a cross-sectional view of a storage cell array according to a third embodiment.

[0037] Figure 31 This is a plan view of the storage cell array according to the fourth embodiment.

[0038] Figure 32 This is a plan view of the storage cell array according to the fifth embodiment.

[0039] Figure 33 This is a circuit diagram of a memory cell array according to the sixth embodiment.

[0040] Figure 34 This is a plan view of the storage cell array according to the sixth embodiment. Detailed Implementation

[0041] In the following description, certain example embodiments are described with reference to the accompanying drawings. In this description, components having the same function and configuration are represented by a common reference numeral. When multiple components with a common reference numeral need to be distinguished from each other, a suffix is ​​added to the common reference numeral. When it is not necessary to distinguish such components, only the common reference numeral is used without adding a suffix. The suffix is ​​not limited to subscripts and superscripts, and includes, for example, lowercase letters, symbols, and indices, which mean that an array is added to the end of the reference numeral.

[0042] In this specification, a magnetic storage device is, for example, a magnetoresistive random access memory (MRAM). A magnetic storage device includes magnetoresistive elements as storage elements. A magnetoresistive element is a variable resistive element with a magnetic tunnel junction (MTJ) and magnetoresistive effect. A magnetoresistive element is also referred to as an MTJ element.

[0043] 1. First Embodiment

[0044] The first embodiment is described.

[0045] 1.1 Configuration

[0046] First, the configuration of the magnetic storage device according to the first embodiment will be described.

[0047] 1.1.1 Magnetic storage devices

[0048] Figure 1 This is a block diagram illustrating an example configuration of a magnetic storage device according to a first embodiment. The magnetic storage device 1 includes a storage cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0049] Storage cell array 10 is a storage unit for data in magnetic storage device 1. Storage cell array 10 includes multiple storage cells MC. Storage cells MC can be associated with groups comprising rows or columns. Storage cells MC in the same row are connected to the same word line WL, and storage cells MC in the same column are connected to the same read bit line RBL and the same write bit line WBL.

[0050] Row selection circuit 11 is used to select rows of memory cell array 10. Row control circuit 11 is connected to memory cell array 10 via word line WL. The decoding result (row address) of address ADD from decoding circuit 13 is provided to row selection circuit 11. Row selection circuit 11 selects word line WL based on the decoding result of address ADD. Word lines WL other than the selected word lines WL are called non-selected word lines WL.

[0051] Column selection circuit 12 is used to select columns of memory cell array 10. Column selection circuit 12 is connected to memory cell array 10 via read bit line RBL and write bit line WBL. The decoding result (column address) of address ADD from decoding circuit 13 is provided to column selection circuit 12. Column selection circuit 12 selects read bit line RBL and write bit line WBL based on the decoding result of address ADD. Read bit line RBL other than the selection bit line is called non-select bit line RBL. Write bit line WBL other than the selection write bit line WBL is called non-select bit line WBL.

[0052] Decoding circuit 13 is a decoder that decodes the address ADD from input / output circuit 17. Decoding circuit 13 provides the decoding result from address ADD to row selection circuit 11 and column selection circuit 12. Address ADD includes the selected column address and the selected row address.

[0053] The write circuit 14 includes, for example, a write driver. The write circuit 14 writes data to the memory cell MC.

[0054] The read circuit 15 includes, for example, a sensing amplifier. The read circuit 15 reads data from the storage cell MC.

[0055] The voltage generation circuit 16 uses a power supply voltage supplied from outside the magnetic storage device 1 to generate voltages for various operations of the storage cell array 10. For example, the voltage generation circuit 16 generates various voltages required during write operations and outputs these voltages to the write circuit 14. The voltage generation circuit 16 generates various voltages required during read operations and outputs these voltages to the read circuit 15.

[0056] Input / output circuit 17 controls communication with the external environment of magnetic storage device 1. Input / output circuit 17 sends address ADD from the external environment of magnetic storage device 1 to decoding circuit 13. Input / output circuit 17 sends command CMD from the external environment of magnetic storage device 1 to control circuit 18. Input / output circuit 17 sends and receives various control signals CNT between the external environment of magnetic storage device 1 and control circuit 18. Input / output circuit 17 sends data DAT from the external environment of magnetic storage device 1 to write circuit 14 and outputs data DAT sent from read circuit 15 to the external environment of magnetic storage device 1.

[0057] For example, control circuit 18 includes a processor (such as a central processing unit (CPU)) and read-only memory (ROM). Control circuit 18 controls the operation of row selection circuit 11, column selection circuit 12, decoding circuit 13, write circuit 14, read circuit 15, voltage generation circuit 16, and input / output circuit 17 based on control signal CNT and command CMD.

[0058] 1.1.2 Storage Cell Array

[0059] The storage cell array of the magnetic storage device according to the first embodiment is described.

[0060] (Circuit Configuration)

[0061] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to the first embodiment. Figure 2 In this context, the word line WL, read bit line RBL, and write bit line WBL are described by a suffix that includes an index ("<>").

[0062] The storage cell array 10 includes multiple storage cells MC, multiple word lines WL, multiple read bit lines RBL, and multiple write bit lines WBL. Figure 2 In the example, the multiple memory cells MC include (M+1)×(N+1) memory cells MC<0,0>, MC<0,1>, ..., MC<0,N>, MC<1,0>, ... and MC<0,N>.<M,N> (M and N are integers of 2 or greater). In Figure 2 The example provides a case where M and N are integers of 2 or greater, but the embodiment is not limited to this. M and N can be 0 or 1. Multiple word lines WL comprise (M+1) word lines WL. <0> WL <1> ...and WL <m>Multiple read bit lines RBL include (N+1) read bit lines RBL. <0> RBL <1> ...and RBL <n>Multiple write bit lines WBL include (N+1) write bit lines WBL. <0> WBL <1> ...and WBL <n>.

[0063] Multiple memory cells (MCs) are arranged in a matrix configuration within the memory cell array 10. Each memory cell (MC) is associated with a group comprising one of multiple word lines (WL) and a group of read bit lines (RBLs) and write bit lines (WBLs) among multiple read bit lines (RBLs) and multiple write bit lines (WBLs). In other words, the memory cells (MCs)<i,j> (0≤i≤M, 0≤j≤N) are connected to word line WL Read bit line RBL <j>and write bit line WBL <j>.

[0064] Storage unit MC<i,j> It is a three-terminal storage unit, which has a connection to the word line WL. The first end is connected to the write bit line WBL <j>The second end is connected to the read bit line RBL <j>The third end. Storage unit MC<i,j> Including switching element SEL1<i,j> and SEL2<i,j> MTJ magnetoresistive element<i,j> and wiring SOTL<i,j> .

[0065] SOTL cabling<i,j> It includes a first part, a second part, and a third part between the first and second parts. (SOTL wiring)<i,j> The first part is connected to the word line WL SOTL cabling<i,j> The second part is connected to the write bit line WBL <j>SOTL cabling<i,j> The third part is connected to the read bit line RBL. <j>Switching element SEL1<i,j> Connected to the SOTL cabling<i,j> The second part is related to the write bit line WBL <j>Between. Magnetoresistive element MTJ<i,j> Connected to the SOTL cabling<i,j> The third part is related to the read bit line RBL. <j>Between. Switching element SEL2<i,j> Connected to the magnetoresistive element MTJ<i,j> With read bit line RBL <j>between.

[0066] Switching elements SEL1 and SEL2 are two-terminal switching elements. Two-terminal switching elements differ from three-terminal switching elements such as transistors in that they do not include a third terminal. When the voltage applied between the two terminals is lower than threshold voltages Vth1 and Vth2, respectively, switching elements SEL1 and SEL2 are in a "high resistance" state or a "closed" state, for example, a non-conductive state. When the voltage applied between the two terminals is at or above the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 change to a "low resistance" state or an "on" state, for example, a conductive state. More specifically, for example, when the voltage applied to the corresponding memory cell MC is lower than the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 act as insulators with high resistance, cutting off current (entering the closed state). When the voltage applied to the corresponding memory cell MC is higher than the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 act as conductors with low resistance, allowing current to flow (entering the on state). Switching elements SEL1 and SEL2 switch between cutting off or allowing current to flow based on the magnitude of the voltage applied to the corresponding memory cell MC, regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current).

[0067] The SOTL (Site Layout Transmission Line) is a current path within a memory cell (MC). For example, when switch element SEL1 is on and switch element SEL2 is off, the SOTL serves as a current path between the word line WL and the write bit line WBL. Conversely, when switch element SEL1 is off and switch element SEL2 is on, a portion of the SOTL serves as a current path between the word line WL and the read bit line RBL.

[0068] The magnetoresistive element (MTJ) is a variable resistance element. The MTJ can switch its resistance value between low and high resistance states based on the current in the path controlled by switching elements SEL1 and SEL2. The MTJ is used as a storage element to store data based on changes in resistance state rather than voluntarily.

[0069] (Floor plan layout)

[0070] The planar layout of the storage cell array according to the first embodiment is described.

[0071] Figure 3 This is a plan view illustrating an example of the planar layout of a memory cell array according to the first embodiment. Figure 3 The structure of insulating layers, etc., is omitted in the text.

[0072] The memory cell array 10 also includes multiple vertical structures V1, multiple vertical structures V2, and multiple vertical structures V3. Each of the multiple vertical structures V1 includes a switching element SEL1. Each of the multiple vertical structures V2 includes a magnetoresistive element MTJ and a switching element SEL2.

[0073] Multiple write bit lines (WBLs) are arranged in the X direction. Each of the multiple write bit lines (WBLs) extends in the Y direction.

[0074] Multiple word lines (WLs) are provided above multiple write bit lines (WBLs). The multiple word lines (WLs) are arranged in the Y direction. Each of the multiple word lines (WLs) extends in the X direction.

[0075] Multiple routing SOTLs are provided above multiple word lines WL. In a planar view, each of the multiple routing SOTLs has a rectangular shape extending in the Y direction relative to the X direction. Each of the multiple routing SOTLs extends in the Y direction. In a planar view, each of the multiple routing SOTLs corresponds to a position where a word line WL and a write bit line WBL overlap each other, and is provided as a matrix configuration.

[0076] Multiple read bit lines (RBLs) are provided above multiple routing SOTLs. The multiple read bit lines (RBLs) are arranged in the X direction. Each of the multiple read bit lines (RBLs) extends in the Y direction. In the plan view, the multiple read bit lines (RBLs) are respectively provided at locations overlapping with the multiple write bit lines (WBLs).

[0077] Multiple vertical structures V1 extend in the Z direction. In the plan view, each of the multiple vertical structures V1 has a circular shape. Each of the multiple vertical structures V1 is connected between a corresponding write bit line WBL and a corresponding wiring SOTL.

[0078] Multiple vertical structures V2 extend in the Z direction. In the planar view, each vertical structure V2 has a circular shape. Each vertical structure V2 is connected to a corresponding read bit line RBL and a corresponding routing SOTL.

[0079] The vertical structure V3 extends in the Z direction. In the plan view, each vertical structure V3 has a circular shape. Each vertical structure V3 is connected to a corresponding word line WL and a corresponding wiring SOTL.

[0080] In the configuration described above, a group consisting of a wiring SOTL and a vertical structure V1, a vertical structure V2 and a vertical structure V3 connected to a corresponding wiring SOTL is used as a storage unit MC.

[0081] (Cross-sectional structure)

[0082] A cross-sectional structure of the memory cell array according to the first embodiment is described.

[0083] Figure 4 This is a cross-sectional view illustrating an example of the cross-sectional structure of a memory cell array according to the first embodiment, the cross-sectional view along... Figure 3 The IV-IV line is obtained. The memory cell array 10 includes a semiconductor substrate 20 and hierarchical structures L1 and L2. Hierarchical structure L1 includes conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and element layers 22_1, 27_1, and 28_1. Hierarchical structure L2 includes conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and element layers 22_2, 27_2, and 28_2. Configurations with the suffix "_x" indicate configurations belonging to hierarchical structure Lx (x is an integer of 1 or greater).

[0084] The hierarchical structures L1 and L2 are stacked in this order along the Z direction on the semiconductor substrate 20. Each of the hierarchical structures L1 and L2 corresponds to Figure 3 The plan layout shown.

[0085] Peripheral circuitry, such as row selection circuitry 11 and column selection circuitry 12, can be provided between semiconductor substrate 20 and layer structure L1. No circuitry may be formed between semiconductor substrate 20 and layer structure L1. When no circuitry is formed between semiconductor substrate 20 and layer structure L1, shallow trench isolation (STI) may be formed in the portion of semiconductor substrate 20 located below layer structure L1.

[0086] Describe the hierarchical structure L1.

[0087] A conductor layer 21_1 is provided above the semiconductor substrate 20. The conductor layer 21_1 serves as the write bit line WBL. The conductor layer 21_1 extends in the Y direction.

[0088] Component layer 22_1 is provided on the upper surface of conductor layer 21_1. Component layer 22_1 serves as a switching element SEL1.

[0089] Conductor layer 23_1 is provided on the upper surface of element layer 22_1. Conductor layer 23_1 serves as a contact. Element layer 22_1 and conductor layer 23_1 are configured in a vertical structure V1.

[0090] Conductor layer 24_1 is provided on the upper surface of conductor layer 23_1. Conductor layer 24_1 serves as a wiring SOTL. Conductor layer 24_1 extends in the Y direction.

[0091] Conductor layer 25_1 is provided in a portion of the lower surface of conductor layer 24_1 that differs from the portion where conductor layer 23_1 is provided. Conductor layer 25_1 serves as a contact. Conductor layer 25_1 is configured with a vertical structure V3.

[0092] Conductor layer 26_1 is provided on the lower surface of conductor layer 25_1. Conductor layer 26_1 serves as word line WL. Conductor layer 26_1 extends in the X direction.

[0093] Component layer 27_1 is provided in the portion between the portion of conductor layer 23_1 and the portion of conductor layer 25_1 on the upper surface of conductor layer 24_1. Component layer 27_1 serves as a magnetoresistive element MTJ.

[0094] Component layer 28_1 is provided on the upper surface of component layer 27_1. Component layer 28_1 serves as a switching element SEL2. Component layers 27_1 and 28_1 are configured with a vertical structure V2.

[0095] Conductor layer 29_1 is provided on the upper surface of element layer 28_1. Conductor layer 29_1 serves as the read bit line RBL. Conductor layer 29_1 extends in the Y direction.

[0096] In the configuration described above, a group in the hierarchical structure L1, including conductor layer 24_1 and vertical structures V1, V2 and V3, is used as a storage unit MC having three terminals respectively connected to conductor layers 21_1, 26_1 and 29_1.

[0097] Hierarchical structure L2 has the same configuration as hierarchical structure L1. That is, conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and element layers 22_2, 27_2, and 28_2 have the same structure and function as conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and element layers 22_1, 27_1, and 28_1, respectively. Therefore, a group in hierarchical structure L2 including conductor layer 24_2 and vertical structures V1, V2, and V3 serves as a storage cell MC with three terminals respectively connected to conductor layers 21_2, 26_2, and 29_2.

[0098] 1.1.3 Magnetoresistive components and peripheral wiring

[0099] Figure 5 yes Figure 4 A cross-sectional view of region V, showing an example of the cross-sectional structure of the magnetoresistive element and peripheral wiring according to the first embodiment. Conductor layer 24 includes an antiferromagnetic layer 24a, a ferromagnetic layer 24b, and a nonmagnetic layer 24c. Element layer 27 includes a ferromagnetic layer 27a, a nonmagnetic layer 27b, a ferromagnetic layer 27c, a nonmagnetic layer 27d, and a ferromagnetic layer 27e.

[0100] First, the details of the structure of conductor layer 24 are described.

[0101] The antiferromagnetic layer 24a is a conductive film exhibiting antiferromagnetism. The antiferromagnetic layer 24a stabilizes the magnetization direction of the ferromagnetic layer 24b through exchange coupling with it. The antiferromagnetic layer 24a contains, for example, platinum-manganese (PtMn).

[0102] A ferromagnetic layer 24b is provided on the upper surface of the antiferromagnetic layer 24a. The ferromagnetic layer 24b is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 24b includes an easy magnetization axis in the direction in which it extends (Y direction). In addition to shape anisotropy, the magnetization direction of the ferromagnetic layer 24b is stabilized along the Y direction through exchange coupling with the antiferromagnetic layer 24a. The magnetization direction of the ferromagnetic layer 24b is reversed according to the direction of the current flowing in the ferromagnetic layer 24b. The ferromagnetic layer 24b contains, for example, cobalt iron (CoFe).

[0103] A nonmagnetic layer 24c is provided on the upper surface of the ferromagnetic layer 24b. The nonmagnetic layer 24c is a nonmagnetic heavy metal conductive film. A spin-orbit moment (SOT) is generated in the nonmagnetic layer 24c by a current flowing through it. The SOT is injected into the ferromagnetic layer 27a. The nonmagnetic layer 24c also causes the ferromagnetic layers 24b and 27a to undergo interlayer exchange coupling. The nonmagnetic layer 24c contains at least one element selected, for example, from platinum (Pt), palladium (Pd), gold (Au), and silver (Ag).

[0104] A ferromagnetic layer 27a is provided on the upper surface of the non-magnetic layer 24c. The ferromagnetic layer 27a is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 27a serves as a storage layer SL. The ferromagnetic layer 27a includes an easy magnetization axis in a direction perpendicular to the film surface (Z direction). A bias magnetic field in the Y direction is applied to the ferromagnetic layer 27a through interlayer exchange coupling between the non-magnetic layer 24c and the ferromagnetic layer 24b at the interface with the non-magnetic layer 24c. The spin-orbit moment generated on the non-magnetic layer 24c is injected into the ferromagnetic layer 27a. The magnetization direction of the ferromagnetic layer 27a is configured to be reversed based on the bias magnetic field in the Y direction and the spin-orbit moment.

[0105] The ferromagnetic layer 27a contains iron (Fe). The ferromagnetic layer 27a may also contain at least one element selected from cobalt (Co) and nickel (Ni). The ferromagnetic layer 27a may also contain boron (B). More specifically, for example, the ferromagnetic layer 27a contains iron cobalt boron (FeCoB) or iron boride (FeB).

[0106] A nonmagnetic layer 27b is provided on the upper surface of the ferromagnetic layer 27a. The nonmagnetic layer 27b is a nonmagnetic insulating film. The nonmagnetic layer 27b serves as a tunnel barrier layer TB. The nonmagnetic layer 27b is provided between the ferromagnetic layers 27a and 27c, and together with these two ferromagnetic layers, forms a magnetic tunnel junction. The nonmagnetic layer 27b serves as a seed material to act as a nucleus for growing a crystalline film from the interface with the ferromagnetic layer 27a during the crystallization process of the ferromagnetic layer 27a. The nonmagnetic layer 27b has a NaCl crystal structure in which the film surface is oriented toward the (001) plane. The nonmagnetic layer 27b contains, for example, magnesium oxide (MgO).

[0107] A ferromagnetic layer 27c is provided on the upper surface of the non-magnetic layer 27b. The ferromagnetic layer 27c is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 27c serves as a reference layer RL. The ferromagnetic layer 27c has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 27c is fixed. Figure 5 In the example, the magnetization direction of ferromagnetic layer 27c points towards ferromagnetic layer 27a. In this context, expressing "the magnetization direction is fixed" means that the magnetization direction is not changed by a torque of the magnitude that would reverse the magnetization direction of ferromagnetic layer 27a. Ferromagnetic layer 27c contains at least one compound selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd).

[0108] A nonmagnetic layer 27d is provided on the upper surface of the ferromagnetic layer 27c. The nonmagnetic layer 27d is a nonmagnetic conductive film. The nonmagnetic layer 27d serves as a spacer layer. The nonmagnetic layer 27d contains at least one element selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr).

[0109] A ferromagnetic layer 27e is provided on the upper surface of the non-magnetic layer 27d. The ferromagnetic layer 27e is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 27e serves as a displacement-eliminating layer. The ferromagnetic layer 27e has an easy magnetization axis in a direction perpendicular to the film surface (Z-direction). The ferromagnetic layer 27e comprises at least one compound selected, for example, from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd).

[0110] Ferromagnetic layers 27c and 27e are antiferromagnetically coupled through a non-magnetic layer 27d. That is, ferromagnetic layers 27c and 27e are coupled with magnetization directions that are antiparallel to each other. This coupling structure of ferromagnetic layer 27c, non-magnetic layer 27d, and ferromagnetic layer 27e is called a synthetic antiferromagnetic (SAF) structure. Through the SAF structure, ferromagnetic layer 27e can counteract the influence of the leakage magnetic field of ferromagnetic layer 27c on the magnetization direction of ferromagnetic layer 27a.

[0111] Depending on whether the magnetization directions of the storage layer SL and the reference layer RL are parallel or antiparallel, the magnetoresistive element MTJ can be in a low-resistance or high-resistance state. According to the first embodiment, the magnetization direction of the storage layer SL is controlled to align with the magnetization direction of the reference layer RL without allowing write current to flow through the magnetoresistive element MTJ. Specifically, a write method using a spin-orbit moment generated by allowing current to flow through the wiring SOTL is employed.

[0112] When a write current Ic0 of a specific magnitude flows to the SOTL wiring, the relative relationship between the storage layer SL and the reference layer RL in the magnetization direction becomes parallel. In this parallel state, the resistance of the magnetoresistive element MTJ is at its lowest; therefore, the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "parallel (P) state," and in this example, it corresponds to the data value "0" state.

[0113] When a write current Ic1, greater than the write current Ic0, flows into the SOTL wiring in the opposite direction to the write current Ic0, the relative relationship between the storage layer SL and the reference layer RL in the magnetization direction becomes antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ is at its highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "antiparallel (AP) state," and in this example, it corresponds to the data value "1" state.

[0114] The following description is based on the data value conventions described above, but the invention is not limited to these conventions. For example, the P state can be a data value "1" state, and the AP state can be a data value "0" state.

[0115] 1.1.4 Switching Elements

[0116] Switching element SEL1 primarily switches from the off state to the on state during write operations. Conversely, switching element SEL2 primarily switches from the off state to the on state during read operations. In this way, the switching timing from the off state to the on state is different for switching elements SEL1 and SEL2. Therefore, the suitable current-voltage characteristics of switching elements SEL1 and SEL2 are different from each other. Specifically, for example, switching element SEL1 preferably has a current-voltage characteristic with snapback. Conversely, switching element SEL2 preferably has a current-voltage characteristic without snapback.

[0117] Figure 6 and Figure 7 This is a diagram illustrating an example of the characteristics of a switching element according to a first embodiment. Figure 6 This is an example of the current-voltage characteristics of a switching element SEL1 with foldback current-voltage characteristics. Figure 7 This is an example of the current-voltage characteristics of the switching element SEL2, which has non-foldback current-voltage characteristics.

[0118] First, refer to Figure 6 Describe the current-voltage characteristics with foldback.

[0119] When the voltage applied across the switching element SEL1 (applied voltage V1) changes from 0V to the threshold voltage Vth1, the current flowing through the switching element SEL1 (current I1) becomes the threshold current Ith1. The threshold current Ith1 is approximately 1μA, which is negligible. Therefore, within the range of applied voltage V1 from 0V to the threshold voltage Vth1, the switching element SEL1 enters the off state.

[0120] When the current I1 exceeds the threshold current Ith1, the switching element SEL1 enters the on state and simultaneously folds back. Folding back is the phenomenon where the voltage drop decreases from the threshold voltage Vth1 and exceeds the current flow of the threshold current Ith1. When the current I1 reaches the holding current Ihold1 (>Ith1), the voltage drop of the switching element SEL1 becomes the holding voltage Vhold1 (…). <Vth1)。

[0121] When the voltage reaches the holding voltage Vhold1 through foldback, the voltage drop of the switching element SEL1 is in a state that is hardly changed by the increase of current I1.

[0122] In this way, in the switching element SEL1, the resistance when entering the on state becomes the holding voltage Vhold1, which is lower than the threshold voltage Vth1. Therefore, when the switching element SEL1 enters the on state, it is easy to allow a larger current to flow.

[0123] refer to Figure 7 Describe the current-voltage characteristics without foldback.

[0124] When the voltage applied across the switching element SEL2 (applied voltage V2) changes from 0V to the threshold voltage Vth2, the current flowing through the switching element SEL2 (current I2) becomes the threshold current Ith2. The threshold current Ith2 becomes approximately 1μA, which is negligible. Therefore, within the range of applied voltage V2 from 0V to the threshold voltage Vth2, the switching element SEL2 enters the off state.

[0125] When the current I2 exceeds the threshold current Ith2, the switching element SEL2 enters the on state without folding back. Therefore, the voltage drop of the switching element SEL2 becomes almost unaffected by the increase in current I2.

[0126] In this manner, when the switching element SEL2 enters the ON state, the voltage drop amount does not instantaneously change. Therefore, when the switching element SEL2 enters the ON state, it is possible to prevent a high voltage from being instantaneously applied to an element (e.g., a magnetoresistive element MTJ) connected in series to the switching element SEL2.

[0127] 1.2 Operation

[0128] Describe the operation of the magnetic storage device according to the first embodiment.

[0129] 1.2.1 Write operation

[0130] Figure 8 is a circuit diagram showing an example of a write operation in the magnetic storage device according to the first embodiment. In Figure 8 the example, the case where data is written into the memory cell MC<m,n> (0 < m < M, and 0 < n < N) among a plurality of memory cells MC is shown.

[0131] When data is written into the memory cell MC<m,n>, the voltage VDD or VSS is applied to the word line WL <m>and write bit line WBL <n>Each one. When voltage VDD is applied to word line WL <m>At that time, voltage VSS is applied to the write bit line WBL. <n>When voltage VSS is applied to word line WL <m>At that time, voltage VDD is applied to the write bit line WBL. <n>Voltage VDD / 2 is applied to everything except word line WL. <m>All word lines WL except for the write bit line WBL <n>All write bit lines WBL and all read bit lines RBL except for the write bit line WBL.

[0132] Voltage VSS is the reference potential. Voltage VSS is, for example, 0V. Voltage VDD (potential difference VDD) to voltage VSS is the voltage that puts switching elements SEL1 and SEL2 into the on state. Potential difference VDD is the voltage that allows current to flow to change the resistive state of the magnetoresistive element MTJ. Potential difference VDD / 2 is the voltage that puts switching elements SEL1 and SEL2 into the off state.

[0133] Therefore, in the word line WL <m>With write bit line WBL <n>A potential difference VDD exists between them. At word line WL <m>Except for the write bit line WBL <n>A potential difference VDD / 2 is generated between the write bit line WBL and the other two. This occurs on the word line WL. <m>A potential difference VDD / 2 appears between the read bit line RBL and the read bit line.

[0134] In addition to the letter line WL <m>In addition to the word line WL and write bit line WBL <n>A potential difference of VDD / 2 appears between them.

[0135] Write bit line WBL <n>With read bit line RBL <n>A potential difference of VDD / 2 appears between them.

[0136] Therefore, the switching element SEL1<m,n> Enter the ON state. Except for the switching element SEL1.<m,n> Switching element SEL1, other than SEL2, enters the off state.<m,n> It has also entered the off state.

[0137] Therefore, current can be allowed to flow through the wiring SOTL<m,n> And without allowing current to flow through the wiring SOTL<m,n> Any wiring other than SOTL.

[0138] In the write operation described above, the memory cell MC<m,n> The state can be called the selection state. Storage cells MC<0,n> to MCn<m-1,n> MC<m+1,n> To MC<M,n> MC<m,0> To MC<m,n-1> and MC<m,n+1> To MC<m,N> The state of a memory cell (MC) that is not in a selected state or a semi-selected state can be called a non-selected state.

[0139] Figure 9 and Figure 10 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a first embodiment. Figure 9 and Figure 10 The diagram schematically illustrates the current flowing to the selected memory cell MC and the magnetization direction of the magnetoresistive element MTJ. Figure 9 This corresponds to the write operation when writing the data "1". Figure 10 This corresponds to a write operation when writing data "0".

[0140] First, refer to Figure 9 Describes the write operation for the data "1". Figure 9 The example shows the case where the write current Ic1 flows from the right word line WL to the left write bit line WBL.

[0141] As described above, the potential difference VDD that puts the switching element SEL1 into the on state appears across the conductor layer 24. By controlling the potential difference VDD, a write current Ic1 flows into the conductor layer 24. By allowing the write current Ic1 to flow into the conductor layer 24, particularly into the non-magnetic layer 24c, a spin orbital moment is generated, causing the magnetization direction of the ferromagnetic layer 27a to be antiparallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0142] Furthermore, the magnetization direction of the ferromagnetic layer 24b matches the direction of the write current Ic1. Therefore, a bias magnetic field in the Y direction generated by the interlayer exchange coupling between the nonmagnetic layer 24c and the ferromagnetic layer 24b is applied to the ferromagnetic layer 27a.

[0143] Therefore, with the aid of the spin orbital moment and the bias magnetic field in the Y direction generated by the exchange coupling, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction that is antiparallel to the magnetization direction of the ferromagnetic layer 27c.

[0144] refer to Figure 10 Describes the write operation for the data "0". Figure 10 The example shows the case where the write current Ic0 flows from the write bit line WBL (on the left) to the word line WL (on the right).

[0145] As described above, the potential difference VDD that puts the switching element SEL1 into the on state is generated at both ends of the conductor layer 24. By controlling the potential difference VDD, a write current Ic0 flows into the conductor layer 24. The write current Ic0 flowing into the conductor layer 24, especially into the non-magnetic layer 24c, generates a spin orbital moment that makes the magnetization direction of the ferromagnetic layer 27a parallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0146] Furthermore, the magnetization direction of the ferromagnetic layer 24b matches the direction of the write current Ic0. Therefore, a bias magnetic field in the Y direction generated by the interlayer exchange coupling between the nonmagnetic layer 24c and the ferromagnetic layer 24b is applied to the ferromagnetic layer 27a.

[0147] Therefore, with the aid of the spin orbital moment and the bias magnetic field in the Y direction generated by the exchange coupling, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction parallel to the magnetization direction of the ferromagnetic layer 27c.

[0148] 1.2.2 Read Operation

[0149] Figure 11 This is a circuit diagram illustrating an example of a read operation in a magnetic storage device according to a first embodiment. Figure 11 In the example, with Figure 8 The same situation is shown from the storage unit MC<m,n> The situation regarding data reading.

[0150] When from storage unit MC<m,n> During data reading, voltages VDD and VSS are applied to the read bit line RBL respectively. <n>Word line WL <m>Voltage VDD / 2 is applied to everything except word line WL. <m>All word lines except WL, except for the read bit line RBL. <n>All read bit lines RBL and all write bit lines WBL except for the read bit line RBL.

[0151] Therefore, in the word line WL <m>With read bit line RBL <n>A potential difference VDD is generated between them. At word line WL <m>In addition to reading the bit line RBL <n>A potential difference VDD / 2 appears between the read bit line RBL and the other read bit line WL. <m>A potential difference VDD / 2 appears between the bit line WBL and any write bit line.

[0152] In addition to the letter line WL <m>In addition to the word line WL and read bit line RBL <n>A potential difference of VDD / 2 appears between them.

[0153] Write bit line WBL <n>With read bit line RBL <n>A potential difference of VDD / 2 exists between them. (Except for the write bit line WBL) <n>(Except for) the write bit line WBL and the corresponding read bit line RBL, there will be no potential difference.

[0154] Therefore, the switching element SEL2<m,n> Enter the ON state. Except for the switching element SEL2.<m,n> All switching elements SEL2 except for SEL1 are turned off.<m,n> Entering the off state.

[0155] Therefore, current can flow through the magnetoresistive element MTJ.<m,n> Without allowing current to flow through the MTJ element, which is otherwise affected by the magnetoresistive effect.<m,n> Any magnetoresistive element other than MTJ.

[0156] In the read operation described above, the memory cell MC<m,n> The state is also called the selection state. Storage cells MC<0,n> to MCn<m-1,n> MC<m+1,n> To MC<m,n> MC<m,0> To MC<m,n-1> and MC<m,n+1> To MC<m,n> The state of a memory cell (MC) that is not in a selected state or a half-selected state is called a non-selected state.

[0157] Figure 12 This is a cross-sectional view illustrating an example of a read operation in a magnetic storage device according to a first embodiment. Figure 12 The diagram schematically illustrates the current flowing to the selected memory cell MC and the magnetization direction of the magnetoresistive element MTJ. Figure 12 The example shows the case where the read current Ir flows from the magnetoresistive element MTJ to the word line WL.

[0158] As described above, the potential difference VDD that puts the switching element SEL2 into the on state occurs at the upper end of element layer 27 and the right end of conductor layer 24. By controlling the potential difference VDD, the read current Ir flows from the upper end of element layer 27 to the right end of conductor layer 24. Since the read current Ir flows into element layer 27, the read circuit 15 can determine whether element layer 27 is in a high-resistance or low-resistance state based on the read current Ir. Furthermore, the read current Ir is controlled to be less than the write currents Ic0 and Ic1. Therefore, dielectric breakdown of the non-magnetic layer 27b can be prevented.

[0159] 1.3. Effects according to the first embodiment

[0160] According to the first embodiment, the wiring SOTL includes a first portion connected to the word line WL, a second portion connected to the write bit line WBL, and a third portion connected to the read bit line RBL. A magnetoresistive element MTJ is connected between the third portion of the wiring SOTL and the read bit line RBL. A switching element SEL1 is connected between the second portion of the wiring SOTL and the write bit line WBL. A switching element SEL2 is connected between the magnetoresistive element MTJ and the read bit line RBL. Each of the switching elements SEL1 and SEL2 is a two-terminal switching element. Therefore, without using three-terminal switching elements such as transistors, a memory cell MC can be formed that uses a spin-orbit moment write method.

[0161] Specifically, in the plan view, the wiring SOTL has a rectangular shape extending in the Y direction. The switching element SEL1 overlaps with the second part of the wiring SOTL in the Z direction. The magnetoresistive element MTJ and the switching element SEL1 are stacked in this order so as to overlap with the third part of the wiring SOTL in the Z direction. Therefore, the size of the memory cell can be reduced compared to the case where the memory cell includes a three-terminal switching element.

[0162] Switching element SEL1 has a current-voltage characteristic with foldback. Therefore, compared to switching elements with non-foldback current-voltage characteristics used in switching element SEL1, a larger write current can be easily allowed to flow in the selected memory cell MC during write operations. This reduces the load on write operations.

[0163] Switching element SEL2 has a non-foldback current-voltage characteristic. Therefore, compared to switching elements with foldback current-voltage characteristics, when SEL2 is used, unintentional high voltage application to the magnetoresistive element MTJ during read operations can be prevented. This prevents degradation of the durability of the magnetoresistive element MTJ.

[0164] The conductor layer 24 used for wiring SOTL includes a ferromagnetic layer 24b and a nonmagnetic layer 24c. The nonmagnetic layer 24c is provided between the ferromagnetic layer 24b and the ferromagnetic layer 27a used as the storage layer SL. The nonmagnetic layer 24c contains at least one element selected from platinum (Pt), palladium (Pd), gold (Au), and silver (Ag). Therefore, the nonmagnetic layer 24c can perform interlayer exchange coupling between the ferromagnetic layers 24b and 27a. Thus, a bias magnetic field along the write current direction can be applied to the ferromagnetic layer 27a. Furthermore, by allowing the write current to flow to the nonmagnetic layer 24c, the nonmagnetic layer 24c can inject a spin-orbit moment into the ferromagnetic layer 27a. Therefore, even when the magnetization direction of the magnetoresistive element MTJ is perpendicular to the film surface, the magnetization direction of the ferromagnetic layer 27a can be reversed without applying an external magnetic field and without allowing the write current to flow to the magnetoresistive element MTJ.

[0165] 1.4 Modified Example

[0166] The first embodiment is not limited to the example described above, and various modifications can be applied.

[0167] 1.4.1 First Amended Example

[0168] In the first embodiment described above, the case of reversing the magnetization direction of the storage layer SL without allowing write current to flow into the magnetoresistive element MTJ is described, but this embodiment is not limited thereto. For example, the magnetic storage device can be operated to assist in reversing the magnetization direction of the storage layer SL by allowing write current to flow into the magnetoresistive element MTJ. In the following description, configurations and operations different from the first embodiment are mainly described. Descriptions of configurations and operations identical to those in the first embodiment may be omitted.

[0169] 1.4.1.1 Magnetoresistive effect components and peripheral wiring

[0170] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element and the peripheral wiring according to a first modified example of the first embodiment. Figure 13 Corresponding to the first embodiment Figure 5 In a first modification of the first embodiment, the conductor layer 24 includes a non-magnetic layer 24c', replacing the antiferromagnetic layer 24a, the ferromagnetic layer 24b, and the non-magnetic layer 24c.

[0171] The nonmagnetic layer 24c' is a nonmagnetic heavy metal conductive film. A spin-orbit moment is generated in the nonmagnetic layer 24c' by a current flowing through it. The spin-orbit moment is injected into the ferromagnetic layer 27a. The nonmagnetic layer 24c' contains at least one element selected from, for example, platinum (Pt), palladium (Pd), gold (Au), silver (Ag), hafnium (Hf), tantalum (Ta), and tungsten (W). The nonmagnetic layer 24c' may be an alloy containing at least one element selected from platinum (Pt), palladium (Pd), gold (Au), silver (Ag), hafnium (Hf), tantalum (Ta), and tungsten (W). The nonmagnetic layer 24c' may further contain boron (B), carbon (C), arsenic (As), antimony (Sb), and bismuth (Bi).

[0172] Component layer 27 is provided on the upper surface of non-magnetic layer 24c'. The configuration of component layer 27 is the same as that of component layer 27 in the first embodiment.

[0173] 1.4.1.2 Write Operation

[0174] Figure 14 This is a circuit diagram illustrating an example of a write operation in a magnetic storage device according to a first modified example of the first embodiment. Figure 14 Corresponding to the first embodiment Figure 8 .

[0175] When data is written to the storage unit MC<m,n> At that time, voltage VDD or VSS is applied to word line WL <m>and write bit line WBL <n>Each of these. A voltage VDD / 2+α or VDD / 2-α is applied to the read bit line RBL. <n>When voltage VDD is applied to word line WL <m>At that time, voltages VSS and VDD / 2+α are applied to the write bit line WBL, respectively. <n>and read bit line RBL <n>When voltage VSS is applied to word line WL <m>At that time, voltages VDD and VDD / 2-α are applied to the write bit line WBL, respectively. <n>and read bit line RBL <n>Voltage VDD / 2 is applied to everything except word line WL. <m>All word lines WL except for the write bit line WBL <n>All write bit lines WBL except for read bit lines RBL <n>All read bit lines RBL.

[0176] The potential difference VDD / 2+α is the voltage that causes switching elements SEL1 and SEL2 to enter the on state. The potential difference VDD / 2-α is the voltage that causes switching elements SEL1 and SEL2 to enter the off state. The potential difference α is the voltage that causes switching elements SEL1 and SEL2 to enter the off state.

[0177] In the word line WL <m>With write bit line WBL <n>A potential difference VDD exists between them. At word line WL <m>With read bit line RBL <n>A potential difference VDD / 2-α exists between them. At word line WL <m>Except for the write bit line WBL <n>A potential difference VDD / 2 appears between the write bit line WBL and the other two. At word line WL <m>In addition to reading the bit line RBL <n>A potential difference VDD / 2 appears between the read bit lines RBL and the other two.

[0178] In addition to the letter line WL <m>In addition to the word line WL and write bit line WBL <n>A potential difference of VDD / 2 exists between them. This applies except for the word line WL. <m>In addition to the word line WL and read bit line RBL <n>A potential difference α appears between them.

[0179] Write bit line WBL <n>With read bit line RBL <n>A potential difference VDD / 2+α appears between them.

[0180] Therefore, the switching element SEL1<m,n> and SEL2<m,n> Enter the ON state. Except for the switching element SEL1.<m,n> All switching elements except SEL1 enter the off state. All switching elements SEL2...<m,n> Entering the off state.

[0181] Therefore, current can be allowed to flow to the wiring SOTL.<m,n> and magnetoresistive element MTJ<m,n> And current is not allowed to flow through except for wiring SOTL<m,n> Any wiring other than SOTL or MTJ except for magnetoresistive elements<m,n> Any magnetoresistive element other than MTJ.

[0182] Figure 15 and Figure 16 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a first modified example of the first embodiment. Figure 15 and Figure 16 Corresponding respectively to the first embodiment Figure 9 and Figure 10 .

[0183] First, refer to Figure 15 Describes the write operation for the data "1". Figure 15 The example shows the case where the write current Ic1 flows from the word line WL (on the right) to the write bit line WBL (on the left) and the current Iw1 flows from the magnetoresistive element MTJ to the write bit line WBL.

[0184] As described above, the potential difference VDD that puts the switching element SEL1 into the on state appears across the conductor layer 24. By controlling the potential difference VDD, a write current Ic1 flows into the conductor layer 24. Since the write current Ic1 flows into the non-magnetic layer 24c' in the conductor layer 24, a spin orbital moment is generated such that the magnetization direction of the ferromagnetic layer 27a is antiparallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c'.

[0185] Furthermore, the potential difference VDD / 2+α that puts the switching element SEL2 into the on state appears at the upper end of element layer 27 and the left end of conductor layer 24. By controlling the potential difference VDD / 2+α, current Iw1 flows from the upper end of element layer 27 to the left end of conductor layer 24. Since current Iw1 flows into element layer 27, a spin-transfer torque is generated that makes the magnetization direction of ferromagnetic layer 27a antiparallel to the magnetization direction of ferromagnetic layer 27c.

[0186] Therefore, with the help of spin orbital moment and spin shift moment, the magnetization direction of ferromagnetic layer 27a is reversed to a direction that is antiparallel to the magnetization direction of ferromagnetic layer 27c.

[0187] The current Iw1 is controlled to be less than the write current Ic1 and greater than the read current Ir (Ir < Iw1 < Ic1). Thus, dielectric breakdown of the non-magnetic layer 27b is prevented, and the magnetization direction of the ferromagnetic layer 27a can be effectively reversed.

[0188] Reference Figure 16 Describe the write operation of the data "0". In Figure 16 the example of, it shows the case where the write current Ic0 flows from the write bit line WBL (on the left side) to the word line WL (on the right side) and the current Iw0 less than the current Iw1 flows from the write bit line WBL to the magnetoresistive effect element MTJ.

[0189] As described above, the potential difference VDD that turns on the switching element SEL1 appears across the conductor layer 24. By controlling the potential difference VDD, the write current Ic0 flows into the conductor layer 24. Since the write current Ic0 flows into the non-magnetic layer 24c' in the conductor layer 24, a spin-orbit torque that makes the magnetization direction of the ferromagnetic layer 27a parallel to the magnetization direction of the ferromagnetic layer 27c is generated. The spin-orbit torque is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c'.

[0190] In addition, the potential difference VDD / 2 + α that turns on the switching element SEL2 appears at the upper end of the element layer 27 and the left end of the conductor layer 24. By controlling the potential difference VDD / 2 + α, the current Iw0 flows from the left end of the conductor layer 24 to the upper end of the element layer 27. Since the current Iw0 flows into the element layer 27, a spin-transfer torque that makes the magnetization direction of the ferromagnetic layer 27a parallel to the magnetization direction of the ferromagnetic layer 27c is generated.

[0191] Therefore, with the assistance of the spin-orbit torque and the spin-transfer torque, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction parallel to the magnetization direction of the ferromagnetic layer 27c.

[0192] The current Iw0 is controlled to be less than the write current Ic0 and greater than the read current Ir (Ir < Iw0 < Ic0). Thus, dielectric breakdown of the non-magnetic layer 27b is prevented, and the magnetization direction of the ferromagnetic layer 27a can be effectively reversed.

[0193] 1.4.1.3 Effects of the First Modification Example According to the First Embodiment

[0194] According to a first modification of the first embodiment, the nonmagnetic layer 24c' may be, for example, an alloy containing at least one element selected from platinum (Pt), palladium (Pd), gold (Au), silver (Ag), hafnium (Hf), tantalum (Ta), and tungsten (W), and may further contain, for example, boron (B), carbon (C), arsenic (As), antimony (Sb), and bismuth (Bi). Therefore, the nonmagnetic layer 24c' can inject a larger spin-orbit moment into the ferromagnetic layer 27a.

[0195] During a write operation, the magnetic storage device 1 is configured to allow current Iw to flow to the magnetoresistive element MTJ in the selected state. Therefore, the magnetoresistive element MTJ can generate a spin-transfer torque. Thus, even when the magnetization direction of the magnetoresistive element MTJ is perpendicular to the film surface, the magnetization direction of the ferromagnetic layer 27a can be reversed without applying an external magnetic field.

[0196] 1.4.2 Second Amended Example

[0197] In the first embodiment and the first modification of the first embodiment described above, cases were described where a bias magnetic field coupled by interlayer exchange and a spin-transfer torque were used to assist the spin-orbit moment, but the embodiments are not limited thereto. For example, a magnetic storage device can use a magnetic field generated by an electric current to assist the spin-orbit moment. In the following description, configurations and operations different from the first embodiment or the first modification of the first embodiment are mainly described. Descriptions of configurations and operations identical to the first embodiment or the first modification of the first embodiment may be appropriately omitted.

[0198] 1.4.2.1 Magnetoresistive effect components and peripheral wiring

[0199] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element and the peripheral wiring according to a second modification of the first embodiment. Figure 17 Corresponding to the first modification example according to the first embodiment Figure 13 In a second modification of the first embodiment, the memory cell array 10 further includes a conductor layer 30. The configuration of the conductor layer 24 and the element layer 27 is the same as that of the conductor layer 24 and the element layer 27 according to the first modification of the first embodiment.

[0200] A conductor layer 30 is provided below the non-magnetic layer 24c'. The conductor layer 30 is a conductive film used to generate the magnetic field to be applied to the magnetoresistive element MTJ. The conductor layer 30 extends in a direction orthogonal to the long side direction of the conductor layer 24 (X direction). The conductor layer 30 is electrically insulated from, for example, all other configurations in the memory cell MC (conductor layers 21, 23, 24, 25, 26, and 29, and element layers 22, 27, and 28). The conductor layer 30 is configured to allow current to flow along the X direction from the first end to the second end.

[0201] exist Figure 17 The example shows a case where the conductor layer 30 is provided below the non-magnetic layer 24c', but the embodiment is not limited to this. For example, the conductor layer 30 may be provided above the non-magnetic layer 24c' (e.g., above the conductor layer 29).

[0202] 1.4.2.2 Write Operation

[0203] During a write operation in the magnetic storage device according to the second modification of the first embodiment, the voltages applied to the various wirings in the storage cell MC are the same as those according to the first embodiment. Figure 8 The voltage is the same in the case of [the situation].

[0204] Figure 18 and Figure 19 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a second modified example of the first embodiment. Figure 18 and Figure 19 Corresponding to the first embodiment Figure 9 and Figure 10 .

[0205] First, refer to Figure 18 Describes the write operation for the data "1". Figure 18 The example shows the write current Ic1 flowing from the word line WL (on the right) to the write bit line WBL (on the left) and the current Ia flowing in the conductor layer 30 in the +X direction (away from the page direction).

[0206] As described above, the potential difference VDD that puts the switching element SEL1 into the on state appears across the conductor layer 24. By controlling the potential difference VDD, a write current Ic1 flows into the conductor layer 24. Because the write current Ic1 flows into the non-magnetic layer 24c' in the conductor layer 24, a spin orbital moment is generated, causing the magnetization direction of the ferromagnetic layer 27a to be antiparallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c'.

[0207] Additionally, current Ia flows into conductor layer 30. Since current Ia is a linear current flowing in the X direction, a circular magnetic field centered on current Ia is generated in the YZ plane. The direction of the corresponding circular magnetic field points in the -Y direction in the portion intersecting with ferromagnetic layer 27a.

[0208] Therefore, with the aid of the spin orbital moment and the magnetic field generated by the current Ia, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction that is antiparallel to the magnetization direction of the ferromagnetic layer 27c.

[0209] refer to Figure 19 Describes the write operation for the data "0". Figure 19 The example shows a write current Ic0 flowing from the write bit line WBL (on the left) to the word line WL (on the right) and a current Ia flowing in the conductor layer 30 in the -X direction (into the page).

[0210] As described above, the potential difference VDD that puts the switching element SEL1 into the on state appears across the conductor layer 24. By controlling the potential difference VDD, a write current Ic0 flows into the conductor layer 24. Because the write current Ic0 flows into the non-magnetic layer 24c' in the conductor layer 24, a spin orbital moment is generated, causing the magnetization direction of the ferromagnetic layer 27a to be parallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c'.

[0211] Additionally, current Ia flows into conductor layer 30. Since current Ia is a linear current flowing in the -X direction, a circular magnetic field centered on current Ia is generated in the YZ plane. The direction of the corresponding circular magnetic field points in the Y direction in the portion intersecting with ferromagnetic layer 27a.

[0212] Therefore, with the aid of the spin orbital moment and the magnetic field generated by the current Ia, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction parallel to the magnetization direction of the ferromagnetic layer 27c.

[0213] 1.4.2.3 Effects of the second modification according to the first embodiment

[0214] According to a second modification of the first embodiment, the conductor layer 30 extends in a direction orthogonal to the SOTL wiring. The magnetic storage device 1 is configured to allow current Ia to flow to the conductor layer 30 during a write operation. Therefore, the conductor layer 30 can apply a magnetic field parallel to the write current to the ferromagnetic layer 27a. Thus, even when the magnetization direction of the magnetoresistive element MTJ is perpendicular to the film surface, the magnetization direction of the ferromagnetic layer 27a can be reversed without applying an external magnetic field or disallowing the write current to flow to the magnetoresistive element MTJ.

[0215] In the second modification of the first embodiment, the case where the magnetization direction of the magnetoresistive element MTJ is perpendicular to the film surface is described, but the embodiment is not limited to this. For example, the magnetization direction of the magnetoresistive element MTJ can be parallel to the film surface. Specifically, when the magnetization direction of the magnetoresistive element MTJ points in the X direction, an auxiliary external magnetic field corresponding to the Z direction is required to reverse the magnetization direction of the ferromagnetic layer 27a, and write current is not allowed to flow to the magnetoresistive element MTJ. In this case, a conductor layer 30 is provided to be aligned with the magnetoresistive element MTJ, for example, in the Y direction. Therefore, the direction of the magnetic field generated by the current Ia can be made to point in the Z direction in the portion intersecting with the ferromagnetic layer 27a. Therefore, even when the magnetization direction of the magnetoresistive element MTJ is parallel to the film surface, the magnetization direction of the ferromagnetic layer 27a can be reversed without applying an external magnetic field or allowing write current to flow to the magnetoresistive element MTJ.

[0216] 1.4.3 Third Modification of the First Embodiment

[0217] In the first embodiment and the first and second modifications of the first embodiment described above, the magnetoresistive element MTJ is described as having a magnetization direction perpendicular to the film surface, but the embodiments are not limited to this. For example, the magnetoresistive element may have a magnetization direction parallel to the film surface. In the following description, configurations and operations different from the first embodiment and the first and second modifications of the first embodiment are mainly described. Descriptions of configurations and operations identical to the first embodiment and the first and second modifications of the first embodiment may be appropriately omitted.

[0218] 1.4.3.1 Planar Layout of Storage Cell Array

[0219] Figure 20 This is a plan view illustrating an example of the planar layout of a memory cell array according to a third modified example of the first embodiment. Figure 20 Corresponding to the first embodiment Figure 3 .

[0220] The memory cell array 10 includes multiple vertical structures V2' instead of multiple vertical structures V2. Each vertical structure V2' includes a magnetoresistive element MTJ and a switching element SEL2.

[0221] Vertical structures V2' extend in the Z direction. In the planar view, each vertical structure V2' has an elliptical shape. The vertical structures V2' are configured such that the major axis of the ellipse is parallel to the short side direction (i.e., the X direction) of the routing SOTL. Each vertical structure V2' is connected between a corresponding read bit line RBL and a corresponding routing SOTL.

[0222] 1.4.3.2 Magnetoresistive effect components and peripheral wiring

[0223] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element and the peripheral wiring according to the third modification of the first embodiment. Figure 21 Corresponding to the first modification example according to the first embodiment Figure 13 The configuration of the conductor layer 24 in the third modification of the first embodiment is the same as that in the first modification of the first embodiment, which includes a non-magnetic layer 24c'. The element layer 27 includes a ferromagnetic layer 27a', a non-magnetic layer 27b, a ferromagnetic layer 27c', a non-magnetic layer 27d, and a ferromagnetic layer 27e'.

[0224] A ferromagnetic layer 27a' is provided on the upper surface of the non-magnetic layer 24c'. A non-magnetic layer 27b is provided on the upper surface of the ferromagnetic layer 27a'. A ferromagnetic layer 27c' is provided on the upper surface of the non-magnetic layer 27b. A non-magnetic layer 27d is provided on the upper surface of the ferromagnetic layer 27c'. A ferromagnetic layer 27e' is provided on the upper surface of the non-magnetic layer 27d.

[0225] Except that ferromagnetic layers 27a', 27c', and 27e' have an easy magnetization axis in the major axis direction (X direction) of the elliptical shape of the vertical structure V2' in the plan view, ferromagnetic layers 27a', 27c', and 27e' are the same as ferromagnetic layers 27a, 27c, and 27e according to the first embodiment. Figure 21 In the example, ferromagnetic layer 27a' has a magnetization direction in the +X direction (away from the page) or the -X direction (into the page). Ferromagnetic layer 27c' has a magnetization direction in the +X direction. Ferromagnetic layer 27e' has a magnetization direction in the -X direction. That is, element layer 27 is used as an in-plane magnetized magnetoresistive effect element MTJ.

[0226] 1.4.3.3 Write Operation

[0227] During a write operation in the magnetic storage device according to the third modification of the first embodiment, the voltages applied to the various wirings in the storage cell MC are the same as those according to the first embodiment. Figure 8 The voltage is the same in the case of [the situation].

[0228] Figure 22 and Figure 23 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a third modified example of the first embodiment. Figure 22 and Figure 23 Corresponding respectively to the first embodiment Figure 9 and Figure 10 .

[0229] First, refer to Figure 22 Describes the write operation for the data "1". Figure 22 The example shows the case where the write current Ic1 flows from the word line WL (on the right) to the write bit line WBL (on the left).

[0230] As described above, the potential difference VDD that puts the switching element SEL1 into the on state appears across the conductor layer 24. By controlling the potential difference VDD, a write current Ic1 flows into the conductor layer 24. Because the write current Ic1 flows into the non-magnetic layer 24c' in the conductor layer 24, a spin orbital moment is generated, causing the magnetization direction of the ferromagnetic layer 27a to be antiparallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c'.

[0231] Therefore, by means of the spin orbital moment, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction that is antiparallel to the magnetization direction of the ferromagnetic layer 27c.

[0232] refer to Figure 23 Describes the write operation for the data "0". Figure 23 The example shows the case where the write current Ic0 flows from the write bit line WBL (on the left) to the word line WL (on the right).

[0233] As described above, the potential difference VDD that puts the switching element SEL1 into the on state appears across the conductor layer 24. By controlling the potential difference VDD, a write current Ic0 flows into the conductor layer 24. Because the write current Ic0 flows into the non-magnetic layer 24c' in the conductor layer 24, a spin orbital moment is generated, causing the magnetization direction of the ferromagnetic layer 27a to be parallel to the magnetization direction of the ferromagnetic layer 27c. The spin orbital moment is injected into the ferromagnetic layer 27a near the non-magnetic layer 24c'.

[0234] Therefore, by means of the spin orbital moment, the magnetization direction of the ferromagnetic layer 27a is reversed to a direction parallel to the magnetization direction of the ferromagnetic layer 27c.

[0235] 1.4.3.4 Effects of the third modification of the first embodiment

[0236] According to a third modification of the first embodiment, the vertical structure V2' including element layer 27 has an elliptical shape in a plan view. The major axis of the ellipse is parallel to the short side direction (X direction) of the wiring SOTL. Therefore, the magnetoresistive element MTJ is configured to have an easy magnetization axis in the X direction. Thus, the magnetoresistive element MTJ can reverse the magnetization direction of the ferromagnetic layer 27a' simply by means of its spin orbital moment, without applying an external magnetic field or using any alternative methods to an external magnetic field.

[0237] 2. Second Embodiment

[0238] According to the second embodiment, the location of the switching element SEL2 differs from that in the first embodiment. The following description primarily focuses on the configuration and operation that differ from the first embodiment. Descriptions of configurations and operations identical to those in the first embodiment may be omitted.

[0239] 2.1 Circuit configuration of the memory cell array

[0240] Figure 24 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to the second embodiment. Figure 24 Corresponding to the first embodiment Figure 2 .

[0241] Switching element SEL2<i,j> Connected to the SOTL cabling<i,j> The first part and the word line WL Between. Switching element SEL1<i,j> Connected to the SOTL wiring<i,j> The second part is related to the write bit line WBL <j>Between. Magnetoresistive element MTJ<i,j> Connected to the SOTL cabling<i,j> The third part is related to the read bit line RBL. <j>between.

[0242] 2.2 Planar Layout of Storage Cell Array

[0243] Figure 25 This is a plan view illustrating an example of the planar layout of a storage cell array according to the second embodiment. Figure 25 Corresponding to the first embodiment Figure 3 .

[0244] In the memory cell array 10, each vertical structure V1 includes a switching element SEL1. Each vertical structure V2 includes a magnetoresistive element MTJ. Each vertical structure V3 includes a switching element SEL2.

[0245] In the above configuration, a group consisting of a wiring SOTL and a vertical structure V1, a vertical structure V2 and a vertical structure V3 connected to a corresponding wiring SOTL are used as a storage unit MC.

[0246] 2.3 Cross-sectional structure of the memory cell array

[0247] Figure 26 This is a cross-sectional view illustrating an example of the cross-sectional structure of a memory cell array according to the second embodiment, which along... Figure 25 The line XXVI-XXVI was obtained. Figure 26 Corresponding to the first embodiment Figure 4 The hierarchical structure L1 includes conductor layers 31_1, 32_1, 34_1, 36_1, and 38_1, and component layers 33_1, 35_1, and 37_1. The hierarchical structure L2 includes conductor layers 31_2, 32_2, 34_2, 36_2, and 38_2, and component layers 33_2, 35_2, and 37_2.

[0248] First, describe the hierarchical structure L1.

[0249] A conductor layer 31_1 is provided above the semiconductor substrate 20. The conductor layer 31_1 serves as the write bit line WBL. The conductor layer 31_1 extends in the Y direction.

[0250] Conductor layer 32_1 is provided on the upper surface of conductor layer 31_1. Conductor layer 32_1 serves as a contact.

[0251] Component layer 33_1 is provided on the upper surface of conductor layer 32_1. Component layer 33_1 serves as a switching element SEL1. Conductor layer 32_1 and component layer 33_1 are configured in a vertical structure V1.

[0252] Conductor layer 34_1 is provided on the upper surface of component layer 33_1. Conductor layer 34_1 serves as a wiring SOTL. Conductor layer 34_1 extends in the Y direction.

[0253] Component layer 35_1 is provided in a portion of the lower surface of conductor layer 34_1 that differs from the portion where component layer 33_1 is provided. Component layer 35_1 serves as a switching element SEL2. Component layer 35_1 is configured with a vertical structure V3.

[0254] Component layers 33_1 and 35_1 are formed using the same process. In this case, component layers 33_1 and 35_1 are provided at the same height. That is, the lower surface of component layer 33_1 lies on the same XY plane as the lower surface of component layer 35_1. Moreover, component layers 33_1 and 35_1 are formed to have the same current-voltage characteristics. For example, all component layers 33_1 and 35_1 have current-voltage characteristics with foldback.

[0255] Conductor layer 36_1 is provided on the lower surface of element layer 35_1. Conductor layer 36_1 serves as word line WL. Conductor layer 36_1 extends in the X direction.

[0256] Component layer 37_1 is provided in the portion between the portion providing component layer 33_1 and the portion providing component layer 35_1 on the upper surface of conductor layer 34_1. Component layer 37_1 serves as a magnetoresistive element MTJ.

[0257] Conductor layer 38_1 is provided on the upper surface of element layer 37_1. Conductor layer 38_1 serves as the read bit line RBL. Conductor layer 38_1 extends in the Y direction.

[0258] In the above configuration, a group in the hierarchical structure L1, including conductor layer 34_1 and vertical structures V1, V2 and V3, is used as a storage unit MC having three terminals respectively connected to conductor layers 31_1, 36_1 and 38_1.

[0259] Hierarchical structure L2 has the same configuration as hierarchical structure L1. That is, conductor layers 31_2, 32_2, 34_2, 36_2, and 38_2, and element layers 33_2, 35_2, and 37_2 have the same structure and function as conductor layers 31_1, 32_1, 34_1, 36_1, and 38_1, and element layers 33_1, 35_1, and 37_1, respectively. Therefore, a group in hierarchical structure L2 including conductor layer 34_2 and vertical structures V1, V2, and V3 serves as a storage unit MC with three terminals respectively connected to conductor layers 31_2, 36_2, and 38_2.

[0260] 2.4 Effects of the Second Embodiment

[0261] According to the second embodiment, the switching element SEL2 is connected between the wiring SOTL and the word line WL. The element layer 33, used as the switching element SEL1, and the element layer 35, used as the switching element SEL2, are provided at the same height. Therefore, element layers 33 and 35 can be formed in the same process. This reduces the manufacturing load of the memory cell array 10. When element layers 33 and 35 are formed in the same process, element layer 35 is formed in the same manner as element layer 33 to have current-voltage characteristics with foldback. Therefore, the effect of easily allowing a larger write current to flow in the selected memory cell MC during write operations can be maintained.

[0262] In the magnetic storage device according to the second embodiment, the configuration and operation of the first modification example, the second modification example, and the third modification example of the first embodiment can be applied. In this case, the magnetic storage device according to the second embodiment can exhibit the same effects as the first modification example, the second modification example, and the third modification example of the first embodiment.

[0263] 3. Third embodiment

[0264] A magnetic storage device according to a third embodiment is described. The third embodiment differs from the first and second embodiments in that the word line WL is shared by multiple storage cells MC. In the following description, the configuration and operation that differ from the first embodiment are primarily described. Descriptions of configurations and operations identical to those in the first embodiment may be omitted.

[0265] 3.1 Circuit configuration of the memory cell array

[0266] Figure 27 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to a third embodiment.

[0267] The storage cell array 10 includes multiple storage cells MC, multiple word lines WLa and WLb, multiple read bit lines RBL, and multiple write bit lines WBL. Figure 27 In the example, eight memory cell MCs are shown in a multi-memory cell MC.<m,n-1> MC<m,n> MC<m,n+1> MC<m,n+2> MC<m+1,n-2> MC<m+1,n-1> MC<m+1,n> and MC<m+1,n+1> Among the multiple word lines WLa and WLb, two word lines WLa are shown. <m>and WLa<m+1> And the two letter lines WLb <m>and WLb<m+1> Five read bit lines (RBLs) are shown in the multiple read bit lines (RBLs). <n-2>、RBL <n-1>、RBL <n>RBL<n+1> and RBL<n+2> Six write bit lines (WBL) are shown among the multiple write bit lines (WBL). <n-2>、WBL <n-1>、WBL <n>WBL<n+1> WBL<n+2> and WBL<n+3> .

[0268] Storage unit MC<m,n-1> Including those connected to the word line WLa <m>The first end is connected to the write bit line WBL <n-1>The second end is connected to the read bit line RBL <n-1>The third end. Storage unit MC<m,n> Including those connected to the word line WLa <m>The first end is connected to the write bit line WBL<n+1> The second end is connected to the read bit line RBL <n>The third end. Storage unit MC<m,n-1> The first end and storage unit MC<m,n> The first end is shared by each other.

[0269] Storage unit MC<m,n+1> Including those connected to the word line WLb <m>The first end is connected to the write bit line WBL<n+1> The second end is connected to the read bit line RBL<n+1> The third end. Storage unit MC<m,n+2> Including those connected to the word line WLb <m>The first end is connected to the write bit line WBL<n+3> The second end is connected to the read bit line RBL<n+2> The third end. Storage unit MC<m,n+1> The first end and storage unit MC<m,n+2> The first end is shared by each other.

[0270] Storage unit MC<m+1,n-2> Including those connected to the word line WLa<m+1> The first end is connected to the write bit line WBL <n-2>The second end is connected to the read bit line RBL <n-2>The third end. Storage unit MC<m+1,n-1> Including those connected to the word line WLa<m+1> The first end is connected to the write bit line WBL <n>The second end is connected to the read bit line RBL <n-1>The third end. Storage unit MC<m+1,n-2> The first end and storage unit MC<m+1,n-1> The first end is shared by each other.

[0271] Storage unit MC<m+1,n> Including those connected to the word line WLb<m+1> The first end is connected to the write bit line WBL <n>The second end is connected to the read bit line RBL <n>The third end. Storage unit MC<m+1,n+1> Including those connected to the word line WLb<m+1> The first end is connected to the write bit line WBL<n+2> The second end is connected to the read bit line RBL<n+1> The third end. Storage unit MC<m+1,n> The first end and storage unit MC<m+1,n+1> The first end is shared by each other.

[0272] Includes eight storage units (MC)<m,n-1> MC<m,n> MC<m,n+1> MC<m,n+2> MC<m+1,n-2> MC<m+1,n-1> MC<m+1,n> and MC<m+1,n+1> This group repeats in both the row and column directions to form the memory cell array 10. That is, in the same row (e.g., the m-th row), two memory cells MC (e.g., MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, MC9 ...<m,n-1> and MC<m,n> ) and connected to word line WLb <m>And two memory cells MC that are adjacent to each other in the column direction (e.g., MC<m,n+1> and MC<m,n+2> They are arranged alternately in the column direction.

[0273] In the memory cell array 10 described above, among the multiple memory cells MC, two memory cells MC connected to the same word line WLa and adjacent to each other in the column direction are described.<m,n-1> and MC<m,n> Configuration of the storage unit MC.<m,n-1> Including switching element SEL1<m,n-1> and SEL2<m,n-1> and magnetoresistive element MTJ<m,n-1> Storage unit MC<m,n> Including switching element SEL1<m,n> and SEL2<m,n> and magnetoresistive element MTJ<m,n> Storage unit MC<m,n-1> and MC<m,n> Shared cabling SOTL<m,n-1^n> In this context, the symbol "n-1^n" indicates the SOTL bridge / crossover / connection of the wiring between column (n-1) and column (n).

[0274] SOTL cabling<m,n-1^n> The first part is connected to the word line WLa <m>SOTL cabling<m,n-1^n> The second part is connected to the write bit line WBL <n-1>SOTL cabling<m,n-1^n> The third part is connected to the read bit line RBL. <n-1>SOTL cabling<m,n-1^n> The fourth part is connected to the write bit line WBL.<n+1> SOTL cabling<m,n-1^n> The fifth part is connected to the read bit line RBL. <n>.

[0275] Switching element SEL1<m,n-1> Connected to the SOTL cabling<m,n-1^n> The second part is related to the write bit line WBL <n-1>Between. Magnetoresistive element MTJ<m,n-1> Connected to the SOTL cabling<m,n-1^n> The third part is related to the read bit line RBL. <n-1>Between. Switching element SEL2<m,n-1> Connected to the magnetoresistive element MTJ<m,n-1> With read bit line RBL <n-1>between.

[0276] Switching element SEL1<m,n> Connected to the SOTL cabling<m,n-1^n> Part 4 and the write bit line WBL<n+1> Between. Magnetoresistive element MTJ<m,n> Connected to the SOTL cabling<m,n-1^n> Part 5 and Read Bit Line RBL <n>Between. Switching element SEL2<m,n> Connected to the magnetoresistive element MTJ<m,n> With read bit line RBL <n>between.

[0277] 3.2 Planar Layout of Storage Cell Array

[0278] Figure 28 This is a plan view illustrating an example of the planar layout of a storage cell array according to a third embodiment.

[0279] The memory cell array 10 includes a vertical structure V1, a vertical structure V2, multiple vertical structures V3a, and multiple vertical structures V3b. Each vertical structure V1 includes a switching element SEL1. Each vertical structure V2 includes a magnetoresistive element MTJ and a switching element SEL2.

[0280] Multiple write bit lines (WBLs) are arranged in the X direction. Each write bit line (WBL) extends in the Y direction.

[0281] Multiple word lines (WLb) are provided above multiple write bit lines (WBL). The multiple word lines (WLb) are arranged in the Y direction. Each word line (WLb) extends in the X direction.

[0282] Multiple routing SOTLs are provided above multiple word lines WLb. In a planar view, each routing SOTL has a rectangular shape. The long and short sides of the routing SOTL intersect the X and Y directions in the XY plane, respectively. In the following description, the long and short sides of the routing SOTL are referred to as the P direction and Q direction, respectively. The angle θ formed by the Y direction and the P direction is, for example, (90 - atan(1 / 3)) degrees. In a planar view, each routing SOTL is provided at a location overlapping a word line WLb (or WLa) and three adjacent write bit lines WBL.

[0283] Multiple read bit lines (RBLs) are provided above multiple routing SOTLs. The multiple read bit lines (RBLs) are arranged in the X direction. Each read bit line (RBL) extends in the Y direction. In a plan view, each read bit line (RBL) is provided between two adjacent write bit lines (WBLs).

[0284] Multiple word lines WLa are provided above multiple read bit lines RBL. The multiple word lines WLa are arranged in the Y direction. Each word line WLa extends in the X direction. In the planar diagram, a word line WLa and a word line WLb are provided corresponding to each other at overlapping locations.

[0285] The vertical structure V1 extends in the Z direction. In the plan view, each vertical structure V1 has a circular shape. Each vertical structure V1 is connected between a corresponding write bit line WBL and a corresponding routing line SOTL.

[0286] The vertical structure V2 extends in the Z direction. In the plan view, each vertical structure V2 has a circular shape. Each vertical structure V2 is connected between a corresponding read bit line RBL and a corresponding wiring SOTL.

[0287] Vertical structure V3a extends in the Z direction. In the plan view, each vertical structure V3a has a circular shape. Each vertical structure V3a is connected between a corresponding word line WLa and a corresponding wiring SOTL.

[0288] The vertical structure V3b extends in the Z direction. In the plan view, each vertical structure V3b has a circular shape. Each vertical structure V3b is connected between a corresponding word line WLb and a corresponding routing SOTL.

[0289] In the above configuration, a group consisting of a routing SOTL and a vertical structure V1, a vertical structure V2, and a vertical structure V3a or V3b connected to a corresponding routing SOTL is used as a storage unit MC. Furthermore, the routing SOTL and vertical structure V3a are shared by two storage unit MCs. The routing SOTL and vertical structure V3b are also shared by two storage unit MCs.

[0290] Two vertical structures V2, each providing a corresponding wiring SOTL for two memory cell MCs, are arranged in the P direction. Furthermore, in the plan view, the center of each vertical structure V2 lies on the axis of symmetry of the wiring SOTL along the P direction. That is, the wiring SOTL and the two vertical structures V2, each providing a corresponding wiring SOTL for two memory cell MCs, are provided along the same axis along the P direction. The two vertical structures V2 can be said to be "coaxial" with each other. In this context, "same" includes substantially the same pattern / position alignment, such as within normal manufacturing tolerances.

[0291] 3.3 Cross-sectional structure of the memory cell array

[0292] Figure 29 This is a cross-sectional view illustrating an example of the cross-sectional structure of a memory cell array according to a third embodiment, which along... Figure 28 The line XXIX-XXIX was obtained. Figure 29 The image shows the configuration that is connected to the word line WLa.

[0293] Layer structure L1 includes conductor layers 41_1, 42_1, 43_1, 46_1, 47_1, 48_1, 49_1, 54_1, 55_1, and 56_1, and component layers 44_1, 45_1, 50_1, 51_1, 52_1, and 53_1. Layer structure L2 includes conductor layers 41_2, 42_2, 43_2, 46_2, 47_2, 48_2, 49_2, 54_2, 55_2, and 56_2, and component layers 44_2, 45_2, 50_2, 51_2, 52_2, and 53_2.

[0294] First, describe the hierarchical structure L1.

[0295] Conductor layers 41_1, 42_1, and 43_1 are provided above the semiconductor substrate 20. Conductor layers 41_1, 42_1, and 43_1 serve as write bit lines WBL that are adjacent to each other. Each conductor layer 41_1, 42_1, and 43_1 extends in the Y direction.

[0296] Component layers 44_1 and 45_1 are provided on the upper surfaces of conductor layers 41_1 and 43_1, respectively. Each component layer 44_1 and 45_1 serves as a switching element SEL1.

[0297] Conductor layers 46_1 and 47_1 are provided on the upper surfaces of element layers 44_1 and 45_1, respectively. Each conductor layer 46_1 and 47_1 serves as a contact. Element layer 44_1 and conductor layer 46_1 are configured in a vertical structure V1. Element layer 45_1 and conductor layer 47_1 are configured in a vertical structure V1.

[0298] The vertical structure V1 can also be on the upper surface of conductor layer 42_1. However, the vertical structure V1 on conductor layer 42_1 is not aligned in the P direction with the vertical structure V1 on conductor layer 41_1 or the vertical structure V1 on conductor layer 43_1. Figure 29 The vertical structure V1 on conductor layer 42_1 is not shown in the figure.

[0299] The conductor layer 48_1, extending in the P direction, contacts the upper surfaces of conductor layer 46_1 and conductor layer 47_1. Conductor layer 48_1 serves as a wiring SOTL. On conductor layer 48_1, the connection portions with conductor layer 46_1 and with conductor layer 47_1 correspond to the second and fourth portions of the wiring SOTL, respectively.

[0300] Conductor layer 49_1 and element layers 50_1 and 51_1 are provided on the upper surface of conductor layer 48_1.

[0301] Conductor layer 49_1 is provided above conductor layer 42_1. On conductor layer 48_1, the connection portion with conductor layer 49_1 corresponds to the first portion of the SOTL wiring. Conductor layer 49_1 serves as a contact.

[0302] Component layer 50_1 is provided between the connection portion with conductor layer 46_1 and the connection portion with conductor layer 49_1. Component layer 51_1 is provided between the connection portion with conductor layer 47_1 and the connection portion with conductor layer 49_1. On conductor layer 48_1, the connection portions with component layer 50_1 and 51_1 correspond to the third and fifth portions of the SOTL wiring, respectively. Each component layer 50_1 and 51_1 serves as a magnetoresistive element (MTJ).

[0303] Component layers 52_1 and 53_1 are provided on the upper surfaces of component layers 50_1 and 51_1, respectively.

[0304] Each component layer 52_1 and 53_1 serves as a switching component SEL2. Component layers 50_1 and 52_1 configure the vertical structure V2. Component layers 51_1 and 53_1 configure the vertical structure V2.

[0305] Conductor layers 54_1 and 55_1 are provided on the upper surfaces of element layers 52_1 and 53_1, respectively. Each conductor layer 54_1 and 55_1 serves as a read bit line RBL. Each conductor layer 54_1 and 55_1 extends in the Y direction.

[0306] Above conductor layers 54_1 and 55_1, conductor layer 56_1 is provided on the upper surface of conductor layer 49_1. Conductor layer 56_1 serves as the word line WLa. Conductor layer 56_1 extends in the X direction.

[0307] In the above configuration, one conductor layer 48_1, two vertical structures V1, two vertical structures V2, and one vertical structure V3a in the hierarchical structure L1 are used as two memory cells MC that share conductor layer 49_1 and conductor layer 56_1.

[0308] Hierarchical structure L2 has the same configuration as hierarchical structure L1. That is, conductor layers 41_2, 42_2, 43_2, 46_2, 47_2, 48_2, 49_2, 54_2, 55_2, and 56_2, and element layers 44_2, 45_2, 50_2, 51_2, 52_2, and 53_2 have the same structure and function as conductor layers 41_1, 42_1, 43_1, 46_1, 47_1, 48_1, 49_1, 54_1, 55_1, and 56_1, and element layers 44_1, 45_1, 50_1, 51_1, 52_1, and 53_1, respectively. Therefore, in hierarchical structure L2, one conductor layer 48_2, two vertical structures V1, two vertical structures V2, and one vertical structure V3a are used as two memory cells MC sharing conductor layers 49_2 and 56_2.

[0309] Figure 30 This is a cross-sectional view illustrating an example of the cross-sectional structure of a memory cell array according to a third embodiment, which along... Figure 28 The line XXX-XXX was obtained. Figure 30 The image shows the configuration connected to the word line WLb.

[0310] Layer structure L1 includes conductor layers 43_1, 57_1, 58_1, 61_1, 62_1, 63_1, 64_1, 65_1, 70_1, and 71_1, and element layers 59_1, 60_1, 66_1, 67_1, 68_1, and 69_1. Layer structure L2 includes conductor layers 43_2, 57_2, 58_2, 61_2, 62_2, 63_2, 64_2, 65_2, 70_2, and 71_2, and element layers 59_2, 60_2, 66_2, 67_2, 68_2, and 69_2.

[0311] First, describe the hierarchical structure L1.

[0312] Figure 30 The configuration of conductor layers 43_1, 57_1, 58_1, 61_1, 62_1, 63_1, 70_1, and 71_1, and element layers 59_1, 60_1, 66_1, 67_1, 68_1, and 69_1 in the configuration is similar to... Figure 29 The conductor layers 41_1, 42_1, 43_1, 46_1, 47_1, 48_1, 54_1 and 55_1 and the element layers 44_1, 45_1, 50_1, 51_1, 52_1 and 53_1 are configured the same.

[0313] Conductor layer 64_1 is provided on the lower surface of conductor layer 63_1.

[0314] Conductor layer 64_1 is provided directly above conductor layer 57_1. The connection portion on conductor layer 63_1 to conductor layer 64_1 corresponds to the first portion of the SOTL wiring. Conductor layer 64_1 serves as a contact.

[0315] Above conductor layer 57_1, conductor layer 65_1 is provided on the lower surface of conductor layer 64_1. Conductor layer 65_1 serves as the word line WLb. Conductor layer 65_1 extends in the X direction. Although in Figure 30 Not specifically shown, however, conductor layer 65_1 passes between vertical structure V1 including element layer 59_1 and conductor layer 61_1 and vertical structure V1 including element layer 60_1 and conductor layer 62_1.

[0316] In the above configuration, one conductor layer 63_1, two vertical structures V1, two vertical structures V2, and one vertical structure V3b in the hierarchical structure L1 are used as two memory cells MC that share conductor layer 64_1 and conductor layer 65_1.

[0317] Hierarchical structure L2 has the same configuration as hierarchical structure L1. That is, conductor layers 43_2, 57_2, 58_2, 61_2, 62_2, 63_2, 64_2, 65_2, 70_2, and 71_2, and element layers 59_2, 60_2, 66_2, 67_2, 68_2, and 69_2 have the same structure and function as conductor layers 43_1, 57_1, 58_1, 61_1, 62_1, 63_1, 64_1, 65_1, 70_1, and 71_1, and element layers 59_1, 60_1, 66_1, 67_1, 68_1, and 69_1, respectively. Therefore, in hierarchical structure L2, one conductor layer 63_2, two vertical structures V1, two vertical structures V2, and one vertical structure V3b serve as two memory cells MC sharing conductor layers 64_2 and 65_2.

[0318] 3.4 Effects of the Third Embodiment

[0319] According to the third embodiment, the wiring SOTL<m,n-1^n> This includes a first part, a second part, a third part between the first and second parts, a fourth part provided on the opposite side of the second part relative to the first part, and a fifth part between the first and fourth parts. (SOTL wiring)<m,n-1^n> The first part is connected to the word line WLa <m>SOTL cabling<m,n-1^n> The second and fourth parts are respectively connected to the write bit line WBL <n-1>and WBL<n+1> SOTL cabling<m,n-1^n> The third and fifth parts are respectively connected to the read bit line RBL. <n-1>and RBL <n>Therefore, the two storage units MC<m,n-1> and MC<m,n> Can share word line WLa <m>.

[0320] SOTL cabling<m,n+1^n+2> This includes a first part, a second part, a third part between the first and second parts, a fourth part provided on the opposite side of the second part relative to the first part, and a fifth part between the first and fourth parts. (SOTL wiring)<m,n+1^n+2> The first part is connected to the word line WLb <m>SOTL cabling<m,n+1^n+2> The second and fourth parts are respectively connected to the write bit line WBL<n+1> and WBL<n+3> SOTL cabling<m,n+1^n+2> The third and fifth parts are respectively connected to the read bit line RBL.<n+1> and RBL<n+2> Therefore, the two storage units MC<m,n+1> and MC<m,n+2> Can share word lines WLb <m>.

[0321] The memory cell array 10 includes word lines WLa <m>and WLb <m>Word line WLa <m>and WLb <m>In the plan view, it is positioned at an overlapping location. Word line WLa <m>Provided in cabling SOTL<m,n-1^n> Above. Word line WLb <m>Provided in cabling SOTL<m,n+1^n+2> Below. Therefore, it is possible to independently select those connected to the same write bit line WBL.<n+1> Two storage units MC<m,n> and MC<m,n+1> .

[0322] The SOTL wiring has a rectangular shape, with its long side extending in a direction that intersects the write bit line WBL and the read bit line at an angle θ (=90-atan(1 / 3) degrees). Therefore, when the word lines WLa and WLb are shared by two memory cells, the magnetoresistive element MTJ can be placed in the most compact package.

[0323] In the planar diagram, the two vertical structures V2 of the shared wiring SOTL are provided on the same axis as the corresponding wiring SOTL. Therefore, compared to the case where the vertical structures V2 are not provided on the same axis as the wiring SOTL, the contact area with the magnetoresistive element MTJ and the wiring SOTL can be increased. Thus, during write operations, the wiring SOTL can inject a larger spin-orbit moment into the magnetoresistive element MTJ.

[0324] The configuration and operation of the first, second, and third modifications of the first embodiment can be applied to the magnetic storage device according to the third embodiment. In this case, the magnetic storage device according to the third embodiment can exhibit the same effects as the first, second, and third modifications of the first embodiment.

[0325] 4. Fourth Embodiment

[0326] This describes a magnetic storage device according to a fourth embodiment. The fourth embodiment differs from the third embodiment in that the two vertical structures V2 of the shared wiring SOTL are not provided on the same axis as the corresponding wiring SOTL. In the following description, the configuration and operation differing from the third embodiment are primarily described. Descriptions of configurations and operations identical to those in the third embodiment may be omitted.

[0327] 4.1 Planar Layout of Storage Cell Array

[0328] Figure 31 This is a plan view illustrating an example of the planar layout of a memory cell array according to the fourth embodiment. Figure 31 Corresponding to the third embodiment Figure 28 .

[0329] In the plan view, multiple vertical structures V2 are arranged in a square grid pattern. Therefore, the two vertical structures V2 provided in the two memory cells MC of the shared routing SOTL are arranged in the X direction. However, the long side of the routing SOTL is in the P direction. Therefore, in the plan view, the center of the vertical structure V2 is offset from the axis of symmetry of the routing SOTL along the P direction to the Q direction.

[0330] 4.2 Effects according to the fourth embodiment

[0331] According to the fourth embodiment, the vertical structure V2 can be arranged at equal intervals in the X and Y directions. Therefore, the processing load of the magnetoresistive element MTJ and the switching element SEL2 can be reduced.

[0332] The configuration and operation of the first, second, and third modifications of the first embodiment can be applied to the magnetic storage device according to the fourth embodiment. In this case, the magnetic storage device according to the fourth embodiment can exhibit the same effects as the first, second, and third modifications of the first embodiment.

[0333] 5. Fifth Embodiment

[0334] A magnetic storage device according to a fifth embodiment is described. The fifth embodiment differs from the third and fourth embodiments in that all word lines are provided above the SOTL wiring. In the following description, the configuration and operation differing from the third embodiment are primarily described. Descriptions of configurations and operations identical to those in the third embodiment may be omitted.

[0335] 5.1 Planar Layout of Storage Cell Array

[0336] Figure 32 This is a plan view illustrating an example of the planar layout of a memory cell array according to the fifth embodiment. Figure 32 Corresponding to the third embodiment Figure 28 .

[0337] The memory cell array 10 includes multiple word lines WLa' and WLb' in place of multiple word lines WLa and WLb. The memory cell array 10 also includes vertical structures V3a' and V3b' in place of vertical structures V3a and V3b.

[0338] Multiple word lines WLa' and WLb' are provided above multiple read bit lines RBL. The multiple word lines WLa' and WLb' are arranged alternately in the Y direction. Each word line WLa' and WLb' extends in the X direction. The spacing (pitch) between word lines WLa' and WLb' in the Y direction is half the spacing between word lines WLa' and WLb' in the Y direction according to the third embodiment.

[0339] The vertical structure V3a' extends in the Z direction. In the plan view, each vertical structure V3a' has a circular shape. Each vertical structure V3a' is connected between a corresponding word line WLa' and a corresponding wiring SOTL.

[0340] The vertical structure V3b' extends in the Z direction. In the plan view, each vertical structure V3b' has a circular shape. Each vertical structure V3b' is connected between a corresponding word line WLb' and a corresponding routing SOTL.

[0341] 5.2 Effects of the Fifth Embodiment

[0342] According to the fifth embodiment, multiple word lines WLa' and WLb' can be positioned at the same height (horizontal). Therefore, multiple word lines WLa' and WLb' can be formed in the same process. This reduces the manufacturing load of the memory cell array 10.

[0343] The configuration and operation of the first, second, and third modifications of the first embodiment can be applied to the magnetic storage device according to the fifth embodiment. In this case, the magnetic storage device according to the fifth embodiment can exhibit the same effects as the first, second, and third modifications of the first embodiment.

[0344] The configuration of the fourth embodiment can be applied to the magnetic storage device according to the fifth embodiment. In this case, the magnetic storage device according to the fifth embodiment can exhibit the same effects as the fourth embodiment.

[0345] 6. Sixth Embodiment

[0346] This describes a magnetic storage device according to a sixth embodiment. The sixth embodiment differs from the third embodiment in that the SOTL wiring is arranged parallel to the word line WL. In the following description, the configuration and operation differing from the third embodiment are primarily described. Descriptions of configurations and operations identical to those in the third embodiment may be omitted.

[0347] 6.1 Circuit Configuration of Memory Cell Array

[0348] Figure 33 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to the sixth embodiment. Figure 33 Corresponding to the third embodiment Figure 27 .

[0349] The memory cell array 10 in this embodiment includes multiple memory cells MC, multiple word lines WL, multiple read bit lines RBL, and multiple write bit lines WBL. Figure 33 In the diagram, eight memory cells (MCs) are shown among multiple memory cells (MCs).<m,n-1> MC<m,n> MC<m,n+1> MC<m,n+2> MC<m+1,n-1> MC<m+1,n> MC<m+1,n+1> and MC<m+1,n+2> Two word lines WL are shown among the multiple word lines WL. <m>and WL<m+1> Four read bit lines (RBLs) are shown in the example of multiple read bit lines (RBLs). <n-1>、RBL <n>RBL<n+1> and RBL<n+2> Four write bit lines (WBL) are shown among the multiple write bit lines (WBL). <n-1>、WBL <n>WBL<n+1> and WBL<n+2> .

[0350] Storage unit MC<m,n-1> Including those connected to the word line WL <m>The first end is connected to the write bit line WBL <n-1>The second end is connected to the read bit line RBL <n-1>The third end. Storage unit MC<m,n> Including those connected to the word line WL <m>The first end is connected to the write bit line WBL <n>The second end is connected to the read bit line RBL <n>The third end. Storage unit MC<m,n-1> The first end and storage unit MC<m,n> The first end is shared by each other.

[0351] Storage unit MC<m,n+1> Including those connected to the word line WL <m>The first end is connected to the write bit line WBL.<n+1> The second end is connected to the read bit line RBL<n+1> The third end. Storage unit MC<m,n+2> Including those connected to the word line WL <m>The first end is connected to the write bit line WBL<n+2> The second end is connected to the read bit line RBL<n+2> The third end. Storage unit MC<m,n+1> The first end and storage unit MC<m,n+2> The first end is shared by each other.

[0352] Storage unit MC<m+1,n-1> Including those connected to the word line WL<m+1> The first end is connected to the write bit line WBL <n-1>The second end is connected to the read bit line RBL <n-1>The third end. Storage unit MC<m+1,n> Including those connected to the word line WL<m+1> The first end is connected to the write bit line WBL <n>The second end is connected to the read bit line RBL <n>The third end. Storage unit MC<m+1,n-1> The first end and storage unit MC<m+1,n> The first end is shared by each other.

[0353] Storage unit MC<m+1,n+1> Including those connected to the word line WL<m+1> The first end is connected to the write bit line WBL<n+1> The second end is connected to the read bit line RBL<n+1> The third end. Storage unit MC<m+1,n+2> Including those connected to the word line WL<m+1> The first end is connected to the write bit line WBL<n+2> The second end is connected to the read bit line RBL<n+2> The third end. Storage unit MC<m+1,n+1> The first end and storage unit MC<m+1,n+2> The first end is shared by each other.

[0354] Includes eight storage units (MC)<m,n-1> MC<m,n> MC<m,n+1> MC<m,n+2> MC<m+1,n-1> MC<m+1,n> MC<m+1,n+1> and MC<m+1,n+2> The group is repeated in both the row and column directions to form a storage cell array 10.

[0355] Among the multiple memory cells MC in the memory cell array 10 described above, two memory cells MC that are connected to the same word line WL and are adjacent to each other in the column direction are described.<m,n-1> and MC<m,n> Configuration of the storage unit MC.<m,n-1> Including switching element SEL1<m,n-1> and SEL2<m,n-1> and magnetoresistive element MTJ<m,n-1> Storage unit MC<m,n> Including switching element SEL1<m,n> and SEL2<m,n> and magnetoresistive element MTJ<m,n> Storage unit MC<m,n-1> and MC<m,n> Shared cabling SOTL<m,n-1^n> .

[0356] SOTL cabling<m,n-1^n> Includes Part 1, Part 2, Part 3, Part 4, and Part 5. Routing SOTL<m,n-1^n> The third part is provided in the wiring SOTL<m,n-1^n> The first part is with wiring SOTL<m,n-1^n> Between the second part. SOTL wiring.<m,n-1^n> The fourth part is relative to the wiring SOTL<m,n-1^n> The first part is provided in conjunction with the SOTL wiring.<m,n-1^n> The opposite side of the second part. Routing SOTL<m,n-1^n> The fifth part is provided in the wiring SOTL<m,n-1^n> The first part is with wiring SOTL<m,n-1^n> Between the fourth part.

[0357] SOTL cabling<m,n-1^n> The first part is connected to the word line WL <m>SOTL cabling<m,n-1^n> The second part is connected to the write bit line WBL <n-1>SOTL cabling<m,n-1^n> The third part is connected to the read bit line RBL. <n-1>SOTL cabling<m,n-1^n> The fourth part is connected to the write bit line WBL. <n>SOTL cabling<m,n-1^n> The fifth part is connected to the read bit line RBL. <n>.

[0358] Switching element SEL1<m,n-1> Connected to the SOTL cabling<m,n-1^n> The second part is related to the write bit line WBL <n-1>Between. Magnetoresistive element MTJ<m,n-1> Connected to the SOTL cabling<m,n-1^n> The third part is related to the read bit line RBL. <n-1>Between. Switching element SEL2<m,n-1> Connected to the magnetoresistive element MTJ<m,n-1> With read bit line RBL <n-1>between.

[0359] Switching element SEL1<m,n> Connected to the SOTL cabling<m,n-1^n> Part 4 and the write bit line WBL <n>Between. Magnetoresistive element MTJ<m,n> Connected to the SOTL cabling<m,n-1^n> Part 5 and Read Bit Line RBL <n>Between. Switching element SEL2<m,n> Connected to the magnetoresistive element MTJ<m,n> With read bit line RBL <n>between.

[0360] 6.2 Planar Layout of Storage Cell Array

[0361] Figure 34 This is a plan view illustrating an example of the planar layout of a memory cell array according to the sixth embodiment. Figure 34 Corresponding to the third embodiment Figure 28 .

[0362] The memory cell array 10 includes vertical structures V1, V2, and V3. Each vertical structure V1 includes a switching element SEL1. Each vertical structure V2 includes a magnetoresistive element MTJ and a switching element SEL2.

[0363] Multiple word lines (WL) are arranged in the Y direction. Each word line (WL) extends in the X direction.

[0364] Multiple write bit lines WBL are provided above multiple word lines WL. The multiple write bit lines WBL are arranged in the X direction. Each write bit line WBL extends in the Y direction.

[0365] Multiple routing SOTLs are provided above multiple write bit lines WBLs. In a plan view, each routing SOTL has a rectangular shape. The long and short sides of the multiple routing SOTLs are parallel to the X and Y directions, respectively. That is, the long side of the routing SOTL is orthogonal to the write bit line WBL. In a plan view, each of the multiple routing SOTLs is provided at a location overlapping one word line WL, two adjacent write bit lines WBL, and two adjacent read bit lines RBL.

[0366] Multiple read bit lines (RBLs) are provided above multiple routing SOTLs. The multiple read bit lines (RBLs) are arranged in the X direction. Each read bit line (RBL) extends in the Y direction. In a plan view, two read bit lines (RBLs) are provided between two adjacent write bit lines (WBLs).

[0367] The vertical structure V1 extends in the Z direction. In the plan view, each vertical structure V1 has a circular shape. Each vertical structure V1 is connected between a corresponding write bit line WBL and a corresponding routing line SOTL.

[0368] The vertical structure V2 extends in the Z direction. In the plan view, each vertical structure V2 has a circular shape. Each vertical structure V2 is connected between a corresponding read bit line RBL and a corresponding wiring SOTL.

[0369] Vertical structures V3 extend in the Z direction. In the plan view, each vertical structure V3 has a circular shape. Each vertical structure V3 is connected between a corresponding word line WL and a corresponding routing SOTL.

[0370] In the above configuration, a group consisting of a wiring SOTL and a vertical structure V1, a vertical structure V2, and a vertical structure V3 connected to a corresponding wiring SOTL is used as a storage unit MC. Furthermore, the wiring SOTL and the vertical structure V3 are shared by the two storage unit MCs.

[0371] Two vertical structures V2, each providing a shared routing SOTL for two memory cell MCs, are arranged in the X direction. In the plan view, the center of the vertical structure V2 is located on the axis of symmetry of the routing SOTL along the X direction. That is, the routing SOTL and the two vertical structures V2, each providing a shared routing SOTL for two memory cell MCs, are provided on the same axis along the X direction.

[0372] 6.3 Effects according to the sixth embodiment

[0373] According to the sixth embodiment, the word line SOTL has a rectangular shape, with its long side extending in a direction intersecting the write bit line WBL and the read bit line at 90 degrees. Therefore, when the word line WL is shared by two memory cells, a magnetoresistive element MTJ can be provided.

[0374] In the plan view, the two vertical structures V2 of the shared wiring SOTL are provided on the same axis as the corresponding wiring SOTL. Therefore, compared to the case where the vertical structures V2 are not provided on the same axis as the wiring SOTL, the contact area between the magnetoresistive element MTJ and the wiring SOTL can be increased. Thus, in the same manner as in the third embodiment, during a write operation, the wiring SOTL can inject a larger spin-orbit moment into the magnetoresistive element MTJ.

[0375] The configuration and operation of the first, second, and third modifications of the first embodiment can be applied to the magnetic storage device according to the sixth embodiment. In this case, the magnetic storage device according to the sixth embodiment can exhibit the same effects as the first, second, and third modifications of the first embodiment.

[0376] 7. Other

[0377] In the first to sixth embodiments and the first to third modifications described above, a memory cell array 10 in which two hierarchical structures L1 and L2 are stacked on a semiconductor substrate 20 is shown, but the embodiments are not limited thereto. For example, three or more hierarchical structures having the same structure can be stacked on the semiconductor substrate 20. For example, a single hierarchical structure can be stacked on the semiconductor substrate 20.

[0378] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0379] Explanation of the mark

[0380] 1: Magnetic storage devices

[0381] 10: Memory cell array

[0382] 11: Row selection circuit

[0383] 12: Column Selection Circuit

[0384] 13: Decoding circuit

[0385] 14: Write the circuit diagram

[0386] 15: Reading the circuit

[0387] 16: Voltage generation circuit

[0388] 17: Input / Output Circuit

[0389] 18: Control Circuit

[0390] 20: Semiconductor substrate

[0391] 21, 23, 24, 25, 29, 31, 32, 34, 36, 38, 41, 42, 43, 46, 47, 48, 49, 54, 55, 56, 57, 58, 61, 62, 63, 64, 65, 70, 71: Conductor layer

[0392] 22, 27, 28, 33, 35, 37, 44, 45, 50, 51, 52, 53, 59, 60, 66, 67, 68, 69: Component Layer

[0393] 24a: Antiferromagnetic layer

[0394] 24b, 27a, 27a', 27c, 27c', 27e, 27e': Ferromagnetic layers

[0395] 24c, 24c', 27b, 27d: Non-magnetic layers< / n> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / n> < / n> < / n> < / m> < / m> < / n> < / n> < / n> < / m> < / m> < / n> < / m> < / m> < / n> < / n> < / m> < / m> < / j> < / j> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / m>

Claims

1. A magnetic storage device, comprising: First conductor layer; Second conductor layer; Third conductor layer; A three-terminal first memory cell is connected to the first conductor layer, the second conductor layer, and the third conductor layer, wherein... The first storage unit includes: A fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer. A first magnetoresistive element is connected between the third conductor layer and the fourth conductor layer. A two-terminal first switching element is connected between the second conductor layer and the fourth conductor layer, and A two-terminal second switching element is connected between the first magnetoresistive element and the third conductor layer.

2. The magnetic storage device according to claim 1, wherein, The first switching element has current-voltage characteristics with foldback.

3. The magnetic storage device according to claim 1, wherein, The second switching element has a non-foldback current-voltage characteristic.

4. The magnetic storage device according to claim 1, further comprising: Fifth conductor layer; The sixth conductor layer; as well as A three-terminal second memory cell is connected to the first conductor layer, the fifth conductor layer, and the sixth conductor layer, wherein... The fourth conductor layer includes a fourth portion connected to the fifth conductor layer and a fifth portion connected to the sixth conductor layer, and The second storage cell shares the fourth conductor layer with the first storage cell, and the second storage cell includes: A second magnetoresistive element is connected between the sixth conductor layer and the fourth conductor layer. A three-terminal switching element is connected between the fifth conductor layer and the fourth conductor layer, and A fourth switching element with two ends is connected between the sixth conductor layer and the second magnetoresistive effect element.

5. The magnetic storage device according to claim 4, wherein, The first conductor layer and the fourth conductor layer extend in a first direction. The second conductor layer and the third conductor layer extend in a second direction intersecting the first direction, and When viewed from a third direction intersecting a plane that includes the first and second directions: The first magnetoresistive element and the second switching element overlap with the third conductor layer and the fourth conductor layer. The first switching element overlaps with the second conductor layer and the fourth conductor layer. The second magnetoresistive element and the fourth switching element overlap with the sixth conductor layer and the fourth conductor layer, and The third switching element overlaps with the fifth conductor layer and the fourth conductor layer.

6. The magnetic storage device according to claim 5, wherein, The first magnetoresistive element and the second magnetoresistive element are aligned with each other along the first direction.

7. The magnetic storage device according to claim 4, wherein, The first conductor layer extends in a first direction. The second conductor layer and the third conductor layer extend in a second direction intersecting the first direction. The fourth conductor layer extends in a fourth direction that intersects both the first and second directions but lies in the same plane as the first and second directions, and When viewed from a third direction intersecting a plane that includes the first and second directions: The first magnetoresistive element and the second switching element overlap with the third conductor layer and the fourth conductor layer. The first switching element overlaps with the second conductor layer and the fourth conductor layer. The second magnetoresistive element and the fourth switching element overlap with the sixth conductor layer and the fourth conductor layer, and The third switching element overlaps with the fifth conductor layer and the fourth conductor layer.

8. The magnetic storage device according to claim 7, wherein, The angle formed by the second direction and the fourth direction is (90 - atan(1 / 3)) degrees.

9. The magnetic storage device according to claim 7, wherein, The first magnetoresistive element and the second magnetoresistive element are aligned with each other along the fourth direction.

10. The magnetic storage device according to claim 7, wherein, The first magnetoresistive element and the second magnetoresistive element are aligned with each other along the first direction, and The centers of the first magnetoresistive element and the second magnetoresistive element are offset from the central axis of the fourth conductor layer along the fourth direction.

11. The magnetic storage device according to claim 7, further comprising: A seventh conductor layer extending in the first direction; An eighth conductor layer extending in the second direction; A ninth conductor layer extending in the second direction; The tenth conductor layer extending in the second direction; The third storage cell is a three-terminal type and is connected to the seventh conductor layer, the fifth conductor layer and the eighth conductor layer; as well as A three-terminal fourth memory cell is connected to the seventh conductor layer, the ninth conductor layer, and the tenth conductor layer, wherein... The third storage unit includes: An eleventh conductor layer, extending in the fourth direction, includes a sixth portion connected to the seventh conductor layer, a seventh portion connected to the fifth conductor layer, an eighth portion connected to the eighth conductor layer, a ninth portion connected to the ninth conductor layer, and a tenth portion connected to the tenth conductor layer. A third magnetoresistive element is connected between the eighth and eleventh conductor layers. A five-terminal switching element is connected between the fifth conductor layer and the eleventh conductor layer, and A six-terminal switching element is connected between the eighth conductor layer and the third magnetoresistive effect element; and The fourth memory cell shares the eleventh conductor layer with the third memory cell, and the fourth memory cell includes: A fourth magnetoresistive element is connected between the tenth and eleventh conductor layers. A seven-terminal switching element is connected between the ninth and eleventh conductor layers, and An eighth switching element with two ends is connected between the tenth conductor layer and the fourth magnetoresistive effect element.

12. The magnetic storage device according to claim 11, wherein, When viewed from the third-party perspective, the first conductor layer is located on the side of the fourth and eleventh conductor layers opposite to the seventh conductor layer.

13. The magnetic storage device according to claim 11, wherein, When viewed from the third-party perspective, the first conductor layer is located on the same side as the seventh conductor layer of the fourth and eleventh conductor layers.

14. The magnetic storage device according to claim 1, wherein, The first conductor layer extends in a first direction. The second conductor layer, the third conductor layer, and the fourth conductor layer extend in a second direction intersecting the first direction, and When viewed from a third direction intersecting a plane that includes the first and second directions: The first magnetoresistive element and the second switching element overlap with the third conductor layer and the fourth conductor layer, and The first switching element overlaps with the second conductor layer and the fourth conductor layer.

15. The magnetic storage device according to claim 14, wherein, The first magnetoresistive element includes: A first ferromagnetic layer having a magnetization direction orthogonal to the plane. The second ferromagnetic layer has a magnetization direction orthogonal to the plane, and The first non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. The fourth conductor layer includes: The second non-magnetic layer is located on the side of the first ferromagnetic layer opposite to the first non-magnetic layer, and The third ferromagnetic layer is located on the side of the second non-magnetic layer opposite to the first ferromagnetic layer, and The second nonmagnetic layer contains at least one element selected from platinum, palladium, gold and silver.

16. The magnetic storage device according to claim 14, wherein, The first magnetoresistive element includes: A first ferromagnetic layer having a magnetization direction orthogonal to the plane. The second ferromagnetic layer has a magnetization direction orthogonal to the plane, and The first non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. The fourth conductor layer includes a second non-magnetic layer, which is located on the side of the first ferromagnetic layer opposite to the first non-magnetic layer. The second nonmagnetic layer contains at least one element selected from platinum, palladium, gold, silver, hafnium, tantalum and tungsten.

17. The magnetic storage device according to claim 14, wherein, The first magnetoresistive element includes: A first ferromagnetic layer having a magnetization direction parallel to the plane. The second ferromagnetic layer has a magnetization direction parallel to the plane, and The first non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. The fourth conductor layer includes a second non-magnetic layer, which is located on the side of the first ferromagnetic layer opposite to the first non-magnetic layer. The second nonmagnetic layer contains at least one element selected from platinum, palladium, gold, silver, hafnium, tantalum and tungsten.

18. The magnetic storage device according to claim 1, further comprising: The twelfth conductor layer; The thirteenth conductor layer; Fourteenth conductor layer; as well as The fifth memory cell is a three-terminal type, which is connected to the twelfth conductor layer, the thirteenth conductor layer, and the fourteenth conductor layer, wherein... The fifth storage unit includes: The fifteenth conductor layer includes: The eleventh part is connected to the twelfth conductor layer. The twelfth portion connected to the thirteenth conductor layer, and The thirteenth part is connected to the fourteenth conductor layer. A fifth magnetoresistive element is connected between the fourteenth and fifteenth conductor layers. A nine-terminal switching element is connected between the thirteenth and fifteenth conductor layers, and A tenth switching element with two ends is connected between the twelfth and fourteenth conductor layers, and The fifth memory cell is located on the side of the first memory cell opposite to the substrate.

19. A magnetic storage device, comprising: First conductor layer; Second conductor layer; Third conductor layer; A three-terminal first memory cell is connected to the first conductor layer, the second conductor layer, and the third conductor layer, wherein... The first storage unit includes: A fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer. A first magnetoresistive element is connected between the third conductor layer and the fourth conductor layer. A two-terminal first switching element is connected between the second conductor layer and the fourth conductor layer, and A two-terminal second switching element is connected between the first conductor layer and the fourth conductor layer, wherein, The first conductor layer extends in a first direction. The second conductor layer, the third conductor layer, and the fourth conductor layer extend in a second direction intersecting the first direction.

20. The magnetic storage device according to claim 19, wherein, The second switching element has current-voltage characteristics with foldback.

21. The magnetic storage device according to claim 19, wherein, When viewed from a third direction intersecting a plane that includes the first and second directions: The first magnetoresistive element overlaps with the third and fourth conductor layers. The first switching element overlaps with the second conductor layer and the fourth conductor layer, and The second switching element overlaps with the first conductor layer and the fourth conductor layer.

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