A zero intermediate frequency receiving I / Q imbalance correction system and method

Abstract

The present invention provides a zero intermediate frequency receiving I / Q imbalance correction system and method, which performs I / Q imbalance correction on I and Q two-way output signals output by a zero intermediate frequency receiver through a first residual DC elimination module, a first compensation coefficient update module, a delay buffer module, a convolution module, a second residual DC elimination module, and a second compensation coefficient update module, wherein the correction process is all real number operations, thus avoiding complex number and trigonometric operations and reducing the number of calculation units; and during the correction process, dynamic correction can be performed according to the compensation coefficients output by the first compensation coefficient update module and the second compensation coefficient update module, thereby reducing the influence of the DC signal on the correction process while reducing the amount of operations.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency communication technology, and in particular to a zero intermediate frequency receiving I / Q imbalance correction system and method. Background Art

[0002] At present, I / Q imbalance correction of broadband zero-IF receivers is generally performed in the analog domain or digital domain. In the analog domain, the damage caused by I / Q imbalance can be reduced to a certain extent by adopting high-performance devices and optimizing circuit design, but such methods increase circuit cost and cannot completely suppress I / Q imbalance. In the digital domain, digital signal processing is used to correct I / Q imbalance, which is mainly divided into estimation based on training sequence and blind correction. The correction method based on training sequence needs to rely on a specific sequence designed under the protocol standard and will occupy channel resources; the blind correction method does not require a known sequence, but only needs to use signals that meet some statistical characteristics to estimate and compensate for I / Q imbalance, which has high applicability. However, the current blind correction method performs complex operations in the process of updating filter coefficients and generating compensation signals, including complex multiplication and complex convolution, which has a large amount of calculation and requires too many hardware resources, and IQ correction cannot be guaranteed to be performed in real time. At the same time, the existing blind correction method ignores the influence of the DC signal and uses an adaptive method to track the filter coefficients. There is a training period before the coefficients converge. During this period, the IQ correction of the signal is not completely effective, and it is impossible to determine when the coefficients converge. Some valid data will be discarded, resulting in data loss. Therefore, it is necessary to provide a solution to reduce the influence of the DC signal on the correction process while reducing the amount of calculation. Summary of the invention

[0003] The object of the present invention is to provide a zero intermediate frequency receiving I / Q imbalance correction system and method, so as to achieve the technical effect of reducing the influence of DC signal on the correction process while reducing the amount of calculation.

[0004] In a first aspect, the present invention provides a zero intermediate frequency receiving I / Q imbalance correction system, comprising: a first residual DC elimination module connected to an I-channel output end of a receiver; a first output port connected to the first residual DC elimination module; a delay buffer module connected to a Q-channel output end of the receiver; a convolution module connected to the delay buffer module; a second residual DC elimination module connected to the convolution module; an operation module connected to the first residual DC elimination module and the second residual DC elimination module; a second output port connected to the operation module; a first compensation coefficient update module connected to the first output port and the second output port; a second compensation coefficient update module connected to the first residual DC elimination module, the second residual DC elimination module and the first compensation coefficient update module; at the same time, the second compensation coefficient update module is connected to the convolution module, and the first compensation coefficient update module is connected to the operation module;

[0005] The first residual DC elimination module is used to eliminate the residual DC signal in the I-channel output signal of the receiver to obtain the first output signal of the first output port; the convolution module is used to perform convolution processing according to the initial compensation coefficient of the second compensation coefficient updating module and the output signal of the delay buffer module; the second residual DC elimination module is used to eliminate the residual DC signal in the output signal of the convolution module; the operation module is used to calculate according to the output signal of the first residual DC elimination module, the initial compensation coefficient of the first compensation coefficient updating module and the output signal of the second residual DC elimination module to obtain the second output signal of the second output port;

[0006] The first compensation coefficient update module is also used to calculate the first compensation coefficient for tracking correction based on the first output signal and the second output signal; the second compensation coefficient update module is also used to calculate the second compensation coefficient for tracking correction based on the first compensation coefficient, the first output signal and the output signal of the second residual DC elimination module, and input it into the convolution module to perform convolution processing on the subsequent signal output by the delay cache module.

[0007] Further, the operation module includes: a multiplier connected to the output end of the first compensation coefficient update module and the output end of the first residual DC elimination module; a first adder connected to the output end of the multiplier and the output end of the second residual DC elimination module; and the second output port is connected to the output end of the first adder.

[0008] Furthermore, the first residual DC elimination module includes a first Alpha filter and a second adder; the input end of the first Alpha filter and the first input end of the second adder are both connected to the I-channel output end of the receiver, and the output end of the first Alpha filter is connected to the second input end of the second adder; the first output port and the first input end of the multiplier are both connected to the output end of the second adder.

[0009] Furthermore, the second residual DC elimination module includes a second Alpha filter and a third adder; the input end of the second Alpha filter and the first input end of the third adder are both connected to the output end of the convolution module; at the same time, the output end of the second Alpha filter is connected to the second input end of the third adder; the output end of the third adder is respectively connected to the first adder and the second compensation coefficient update module.

[0010] In a second aspect, the present invention provides a zero intermediate frequency receiving I / Q imbalance correction method, which is applied to the above-mentioned zero intermediate frequency receiving I / Q imbalance correction system, comprising:

[0011] S1. After the receiver is initially powered on, it only receives a complex white Gaussian noise signal, and initializes the first compensation coefficient of the first compensation coefficient update module and the second compensation coefficient of the second compensation coefficient update module;

[0012] S2. The receiver divides the complex Gaussian white noise signal into two output signals, I and Q, wherein the I output signal is subjected to a first residual DC elimination module to remove the residual DC signal to obtain a first signal over DC compensation; the Q output signal is processed by a delay buffer module and convolved with a second compensation coefficient to obtain a transition signal, and the transition signal is subjected to a second residual DC elimination module to remove the residual DC signal to obtain a second signal over DC compensation;

[0013] S3. Obtain a first output signal of a first output port according to the first signal; and simultaneously obtain a second output signal of a second output port by calculating the second signal, the first signal and the first compensation coefficient;

[0014] S4. updating the first compensation coefficient and the second compensation coefficient according to the first output signal and the second output signal;

[0015] S5. Count whether the updated first compensation coefficient and the second compensation coefficient are in a convergence state; if the updated first compensation coefficient and the second compensation coefficient are not in a convergence state, repeat steps S2-S4; if the updated first compensation coefficient and the second compensation coefficient are in a convergence state, calculate the first initial compensation coefficient of the first residual DC elimination module and the second initial compensation coefficient of the second residual DC elimination module in the tracking correction process according to the time length of the statistical process;

[0016] S6. Dynamically track and correct the input signal according to the first initial compensation coefficient, the second initial compensation coefficient and a preset updating method.

[0017] Furthermore, the implementation of S3 is as follows:

[0018]

[0019] In the above formula, Indicates the current first output signal; Indicates the current first signal; Indicates the current second output signal; Indicates the current second signal; Indicates the current first compensation coefficient.

[0020] Furthermore, the updating method of the first compensation coefficient and the second compensation coefficient in S4 is:

[0021]

[0022] In the formula, represents the updated first compensation coefficient; Indicates the current first compensation coefficient; represents the updated second compensation coefficient; Indicates the current second compensation coefficient; Indicates the current second signal; and Both represent data sets, and =[ , , ..., ], =[ , , ..., ], N represents the number of taps of the second compensation coefficient update module; λ and β is the iteration step coefficient.

[0023] Furthermore, the S4 further includes:

[0024] After the first compensation coefficient and the second compensation coefficient are updated, smoothing is performed in the following manner:

[0025]

[0026]

[0027] In the formula, represents the first compensation coefficient after smoothing; Indicates the first compensation coefficient of the last smoothing process; represents the second compensation coefficient after smoothing; Indicates the second compensation coefficient after the last smoothing process; γ a and γ b Represents the smoothing coefficient.

[0028] Furthermore, the first initial compensation coefficient and the second initial compensation coefficient in S5 are calculated as follows:

[0029]

[0030]

[0031] In the formula, represents the first initial compensation coefficient; represents the second initial compensation coefficient; Mc Indicates the starting time of statistics; M Indicates the time length of the statistical process; m Represents a variable.

[0032] Further, the S6 includes:

[0033] S61. Multiplexing S2 and S3 in the dynamic tracking correction process eliminates the residual DC signal in the I and Q output signals of the receiver and outputs the corrected signal from the first output port and the second output port;

[0034] S62. Adaptively update the first compensation coefficient and the second compensation coefficient in the following manner:

[0035]

[0036]

[0037]

[0038] In the above formula, λ ( n )and β ( n) represents the dynamically updated iteration step coefficient; δ represents a constant;

[0039] S63. Repeat steps S61-S62 to dynamically track and correct the continuous I / Q imbalance input signal.

[0040] The beneficial effects that can be achieved by the present invention are as follows: the zero intermediate frequency receiving I / Q imbalance correction system and method provided by the present invention performs I / Q imbalance correction on the I and Q output signals output by the zero intermediate frequency receiver through the first residual DC elimination module, the first compensation coefficient update module, the delay buffer module, the convolution module, the second residual DC elimination module, the second compensation coefficient update module, etc. The correction process is all real number operations, which avoids complex and trigonometric operations and reduces the number of calculation units; and in the correction process, dynamic correction can be performed according to the compensation coefficients output by the first compensation coefficient update module and the second compensation coefficient update module, thereby reducing the amount of calculation and the influence of the DC signal on the correction process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of the topological structure of a zero intermediate frequency receiving I / Q imbalance correction system provided by an embodiment of the present invention;

[0043] Figure 2 A flowchart of a zero intermediate frequency receiving I / Q imbalance correction method provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of a first compensation coefficient adaptive update result provided by an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of a first adaptive update result of a second compensation coefficient provided by an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of a second adaptive update result of a second compensation coefficient provided by an embodiment of the present invention;

[0047] Figure 6 A spectrum diagram of a broadband received signal before correction provided by an embodiment of the present invention;

[0048] Figure 7A spectrum diagram of a corrected broadband received signal provided by an embodiment of the present invention.

[0049] Icon: 10-zero intermediate frequency receiving I / Q imbalance correction system; 100-first residual DC elimination module; 200-first output port; 300-second compensation coefficient update module; 400-delay buffer module; 500-convolution module; 600-second residual DC elimination module; 700-operation module; 800-second output port; 900-first compensation coefficient update module. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0051] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0052] Please see Figure 1 , Figure 1 A schematic diagram of the topological structure of a zero intermediate frequency receiving I / Q imbalance correction system provided in an embodiment of the present invention.

[0053] In one embodiment, the embodiment of the present invention provides a zero intermediate frequency receiving I / Q imbalance correction system 10, which includes: a first residual DC elimination module 100 connected to an I-way output end of a receiver; a first output port 200 connected to the first residual DC elimination module 100; a delay buffer module 400 connected to a Q-way output end of the receiver; a convolution module 500 connected to the delay buffer module 400; a second residual DC elimination module 600 connected to the convolution module 500; and a first residual DC elimination module 100 connected to the first residual DC elimination module 100. 00, an operation module 700 connected to the second residual DC elimination module 600; a second output port 800 connected to the operation module 700; a first compensation coefficient update module 900 connected to the first output port 200 and the second output port 800; a second compensation coefficient update module 300 connected to the first residual DC elimination module 100, the second residual DC elimination module 600 and the first compensation coefficient update module 900; at the same time, the second compensation coefficient update module 300 is connected to the convolution module 500, and the first compensation coefficient update module 900 is connected to the operation module 700.

[0054] The first residual DC elimination module 100 is used to eliminate the residual DC signal in the I-channel output signal of the receiver to obtain the first output signal of the first output port 200; the convolution module 500 is used to perform convolution processing according to the initial compensation coefficient of the second compensation coefficient updating module 300 and the output signal of the delay buffer module 400; the second residual DC elimination module 600 is used to eliminate the residual DC signal in the output signal of the convolution module 500; the operation module 700 is used to calculate according to the output signal of the first residual DC elimination module 100, the initial compensation coefficient of the first compensation coefficient updating module 900 and the output signal of the second residual DC elimination module 600 to obtain the second output signal of the second output port 800.

[0055] The first compensation coefficient update module 900 is also used to calculate the first compensation coefficient for tracking correction based on the first output signal and the second output signal; the second compensation coefficient update module 300 is also used to calculate the second compensation coefficient for tracking correction based on the first compensation coefficient, the first output signal and the output signal of the second residual DC elimination module 600, and input the convolution module 500 to perform convolution processing on the subsequent signal output by the delay cache module 400.

[0056] In the above implementation process, the I / Q imbalance correction is performed on the I and Q output signals of the zero intermediate frequency receiver through the first residual DC elimination module 100, the first compensation coefficient update module 900, the delay buffer module 400, the convolution module 500, the second residual DC elimination module 600 and the second compensation coefficient update module 300. The correction process is all real number operations, which avoids complex complex operations and trigonometric operations and improves the operation efficiency; and in the correction process, dynamic correction can be performed according to the compensation coefficients output by the first compensation coefficient update module 900 and the second compensation coefficient update module 300, thereby reducing the amount of calculation and reducing the influence of the DC signal on the correction process.

[0057] In one embodiment, the operation module 700 includes: a multiplier connected to the output end of the first compensation coefficient update module 900 and the output end of the first residual DC elimination module 100; a first adder connected to the output end of the multiplier and the output end of the second residual DC elimination module 600; and a second output port 800 connected to the output end of the first adder.

[0058] It should be noted that the operation module 700 may also be replaced by a single chip microcomputer, etc., and is not limited to using only the above structure.

[0059] In one embodiment, the first residual DC elimination module 100 includes a first Alpha filter and a second adder; the input end of the first Alpha filter and the first input end of the second adder are both connected to the I-channel output end of the receiver, and the output end of the first Alpha filter is connected to the second input end of the second adder; the first output port 200 and the first input end of the multiplier are both connected to the output end of the second adder. The second residual DC elimination module 600 includes a second Alpha filter and a third adder; the input end of the second Alpha filter and the first input end of the third adder are both connected to the output end of the convolution module 500; the output end of the second Alpha filter is connected to the second input end of the third adder; the output end of the third adder is respectively connected to the first adder and the second compensation coefficient update module 300.

[0060] In the above implementation process, the Alpha filter can effectively remove the DC signal in the I and Q output signals.

[0061] Please see Figure 2 , Figure 2 A flowchart of a zero intermediate frequency receiving I / Q imbalance correction method provided by an embodiment of the present invention.

[0062] In one implementation, an embodiment of the present invention further provides a zero intermediate frequency receiving I / Q imbalance correction method, which is applied to the above-mentioned zero intermediate frequency receiving I / Q imbalance correction system, and its specific content is as follows.

[0063] S1. After the receiver is initially powered on, it only receives a complex Gaussian white noise signal, and simultaneously initializes a first compensation coefficient of a first compensation coefficient updating module and a second compensation coefficient of a second compensation coefficient updating module.

[0064] Specifically, the first compensation coefficient of the first compensation coefficient updating module is =0; the second compensation coefficient of the second compensation coefficient updating module is =[1,0,0...,0] T .

[0065] S2. The receiver divides the complex Gaussian white noise signal into two output signals, I and Q. The I output signal is subjected to a first residual DC elimination module to remove the residual DC signal, thereby obtaining a first signal with over-DC compensation. The Q output signal is processed by a delay buffer module and convolved with a second compensation coefficient to obtain a transition signal. The transition signal is subjected to a second residual DC elimination module to remove the residual DC signal, thereby obtaining a second signal with over-DC compensation.

[0066] S3. Obtain a first output signal of a first output port according to the first signal; and simultaneously obtain a second output signal of a second output port by calculating the second signal, the first signal and the first compensation coefficient.

[0067] Specifically, S3 is implemented as follows:

[0068]

[0069] In the above formula, Indicates the current first output signal; Indicates the current first signal; Indicates the current second output signal; Indicates the current second signal; Indicates the current first compensation coefficient.

[0070] S4. Update the first compensation coefficient and the second compensation coefficient according to the first output signal and the second output signal.

[0071] Specifically, the updating method of the first compensation coefficient and the second compensation coefficient in S4 is:

[0072]

[0073] In the formula, represents the updated first compensation coefficient; Indicates the current first compensation coefficient; represents the updated second compensation coefficient; Indicates the current second compensation coefficient; Indicates the current second signal; and Both represent data sets, and =[ , , ..., ], =[ , , ..., ], N represents the number of taps of the second compensation coefficient update module; λ and β is the iteration step coefficient.

[0074] In one implementation, after the coefficient is updated, the compensation coefficient may be smoothed according to the obtained jitter of the compensation coefficient to improve the accuracy of the compensation signal. The specific processing method is:

[0075]

[0076]

[0077] In the formula, represents the first compensation coefficient after smoothing; Indicates the first compensation coefficient of the last smoothing process; represents the second compensation coefficient after smoothing; Indicates the second compensation coefficient after the last smoothing process; γ a and γ b Represents the smoothing coefficient.

[0078] S5. Count whether the updated first compensation coefficient and the second compensation coefficient are in a convergence state; if the updated first compensation coefficient and the second compensation coefficient are not in a convergence state, repeat steps S2-S4; if the updated first compensation coefficient and the second compensation coefficient are in a convergence state, calculate the first initial compensation coefficient of the first residual DC elimination module and the second initial compensation coefficient of the second residual DC elimination module in the tracking correction process according to the time length of the statistical process.

[0079] Specifically, the first initial compensation coefficient and the second initial compensation coefficient in S5 are calculated as follows:

[0080]

[0081]

[0082] In the formula, represents the first initial compensation coefficient; represents the second initial compensation coefficient; Mc Indicates the starting time of statistics; M Indicates the time length of the statistical process; m Represents a variable.

[0083] S6. Dynamically track and correct the input signal according to the first initial compensation coefficient, the second initial compensation coefficient and a preset updating method.

[0084] Specifically, in one implementation, S6 includes:

[0085] S61. Multiplexing S2 and S3 in the dynamic tracking correction process eliminates the residual DC signal in the I and Q output signals of the receiver and outputs the corrected signal from the first output port and the second output port;

[0086] S62. Adaptively update the first compensation coefficient and the second compensation coefficient in the following manner:

[0087]

[0088]

[0089]

[0090] In the above formula, λ ( n )and β ( n ) represents the dynamically updated iteration step coefficient; δ represents a constant;

[0091] S63. Repeat steps S61-S62 to dynamically track and correct the continuous I / Q imbalance input signal.

[0092] Through the above implementation process, the amount of calculation is reduced and the influence of the DC signal on the correction process is reduced, thereby improving the performance of the zero intermediate frequency receiver.

[0093] Please see Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 ; Figure 3 A schematic diagram of a first compensation coefficient adaptive update result provided by an embodiment of the present invention; Figure 4 A schematic diagram of a first adaptive update result of a second compensation coefficient provided by an embodiment of the present invention; Figure 5 A schematic diagram of a second adaptive update result of a second compensation coefficient provided by an embodiment of the present invention; Figure 6 A spectrum diagram of a broadband received signal before correction provided by an embodiment of the present invention; Figure 7 A spectrum diagram of a corrected broadband received signal provided by an embodiment of the present invention.

[0094] In one implementation, in order to verify the effect of the above method, the embodiment of the present invention performs corresponding tests:

[0095] To set the amplitude imbalance parameters:

[0096]

[0097] Phase imbalance parameters:

[0098]

[0099] The influence of the I-channel filter is , the Q-path filter influence is , and add DC bias at the same time. Set the number of taps of the second compensation coefficient update module to 2, and the first compensation coefficient The adaptive update result is as follows Figure 3 As shown, the second compensation coefficient The adaptive update results of the first tap b(0) and the second tap b(1) are as follows: Figure 4 and Figure 5 As shown. Figure 3 , Figure 4 and Figure 5 It can be seen that with the dynamic change of I / Q imbalance, the compensation coefficient and After a short training, it can adaptively track the theoretical , value, with good tracking ability.

[0100] like Figure 6 and Figure 7 As shown, by comparison, it can be seen that the image suppression ratio is improved by about 12dB, the entire broadband image is suppressed to the noise floor, and the DC is also suppressed, which meets the system performance indicators and is beneficial to subsequent baseband demodulation.

[0101] In summary, the embodiments of the present invention provide a zero-IF receiving I / Q imbalance correction system and method, which performs I / Q imbalance correction on the I and Q output signals of the zero-IF receiver by setting a first residual DC elimination module, a first compensation coefficient update module, a delay buffer module, a convolution module, a second residual DC elimination module, and a second compensation coefficient update module. The correction process is all real number operations, which avoids complex and trigonometric operations and reduces the number of calculation units; and during the correction process, dynamic correction can be performed according to the compensation coefficients output by the first compensation coefficient update module and the second compensation coefficient update module, thereby reducing the amount of calculation and the influence of the DC signal on the correction process.

[0102] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A zero intermediate frequency receiving I / Q imbalance correction system, characterized in that: include: a first residual DC elimination module connected to an I-channel output terminal of the receiver; a first output port connected to the first residual DC elimination module; A delay buffer module connected to the Q output terminal of the receiver; a convolution module connected to the delay buffer module; a second residual DC elimination module connected to the convolution module; and a calculation module connected to the first residual DC elimination module and the second residual DC elimination module; a second output port connected to the operation module; a first compensation coefficient updating module connected to the first output port and the second output port; a second compensation coefficient updating module connected to the first residual DC elimination module, the second residual DC elimination module and the first compensation coefficient updating module; At the same time, the second compensation coefficient updating module is connected to the convolution module, and the first compensation coefficient updating module is connected to the operation module; The first residual DC elimination module is used to eliminate the residual DC signal in the I-channel output signal of the receiver to obtain the first output signal of the first output port; the convolution module is used to perform convolution processing according to the initial compensation coefficient of the second compensation coefficient updating module and the output signal of the delay buffer module; the second residual DC elimination module is used to eliminate the residual DC signal in the output signal of the convolution module; the operation module is used to calculate according to the output signal of the first residual DC elimination module, the initial compensation coefficient of the first compensation coefficient updating module and the output signal of the second residual DC elimination module to obtain the second output signal of the second output port; The first compensation coefficient update module is also used to calculate the first compensation coefficient for tracking correction based on the first output signal and the second output signal; the second compensation coefficient update module is also used to calculate the second compensation coefficient for tracking correction based on the first compensation coefficient, the first output signal and the output signal of the second residual DC elimination module, and input it into the convolution module to perform convolution processing on the subsequent signal output by the delay cache module.

2. The zero intermediate frequency receiving I / Q imbalance correction system according to claim 1, characterized in that: The operation module includes: a multiplier connected to the output end of the first compensation coefficient updating module and the output end of the first residual DC elimination module; a first adder connected to the output end of the multiplier and the output end of the second residual DC elimination module; and the second output port is connected to the output end of the first adder.

3. The zero intermediate frequency receiving I / Q imbalance correction system according to claim 2, characterized in that: The first residual DC elimination module includes a first Alpha filter and a second adder; the input end of the first Alpha filter and the first input end of the second adder are both connected to the I-channel output end of the receiver, and the output end of the first Alpha filter is connected to the second input end of the second adder; the first output port and the first input end of the multiplier are both connected to the output end of the second adder.

4. The zero intermediate frequency receiving I / Q imbalance correction system according to claim 2, characterized in that: The second residual DC elimination module includes a second Alpha filter and a third adder; the input end of the second Alpha filter and the first input end of the third adder are both connected to the output end of the convolution module; at the same time, the output end of the second Alpha filter is connected to the second input end of the third adder; the output end of the third adder is respectively connected to the first adder and the second compensation coefficient update module.

5. A zero intermediate frequency receiving I / Q imbalance correction method, applied to the zero intermediate frequency receiving I / Q imbalance correction system according to any one of claims 1 to 4, characterized in that: include: S1. After the receiver is initially powered on, it only receives a complex white Gaussian noise signal, and initializes the first compensation coefficient of the first compensation coefficient update module and the second compensation coefficient of the second compensation coefficient update module; S2. The receiver divides the complex Gaussian white noise signal into two output signals, I and Q, wherein the I output signal is subjected to a first residual DC elimination module to remove the residual DC signal to obtain a first signal over DC compensation; the Q output signal is processed by a delay buffer module and convolved with a second compensation coefficient to obtain a transition signal, and the transition signal is subjected to a second residual DC elimination module to remove the residual DC signal to obtain a second signal over DC compensation; S3. Obtain a first output signal of a first output port according to the first signal; and simultaneously obtain a second output signal of a second output port by calculating the second signal, the first signal and the first compensation coefficient; S4. updating the first compensation coefficient and the second compensation coefficient according to the first output signal and the second output signal; S5. Statistically update whether the first compensation coefficient and the second compensation coefficient are in a convergence state; If the updated first compensation coefficient and the second compensation coefficient are not in a converged state, repeating steps S2-S4; if the updated first compensation coefficient and the second compensation coefficient are in a converged state, calculating the first initial compensation coefficient of the first residual DC elimination module and the second initial compensation coefficient of the second residual DC elimination module in the tracking correction process according to the time length of the statistical process; S6. Dynamically track and correct the input signal according to the first initial compensation coefficient, the second initial compensation coefficient and a preset updating method.

6. The method according to claim 5, characterized in that The implementation of S3 is as follows: In the above formula, Indicates the current first output signal; Indicates the current first signal; Indicates the current second output signal; Indicates the current second signal; Indicates the current first compensation coefficient.

7. The method according to claim 6, characterized in that The updating method of the first compensation coefficient and the second compensation coefficient in S4 is: In the formula, represents the updated first compensation coefficient; Indicates the current first compensation coefficient; represents the updated second compensation coefficient; Indicates the current second compensation coefficient; Indicates the current second signal; and Both represent data sets, and =[ , , ..., ], =[ , , ..., ], N represents the number of taps of the second compensation coefficient update module; λ and β is the iteration step coefficient.

8. The method according to claim 7, characterized in that The S4 further comprises: After the first compensation coefficient and the second compensation coefficient are updated, smoothing is performed in the following manner: In the formula, represents the first compensation coefficient after smoothing; Indicates the first compensation coefficient of the last smoothing process; represents the second compensation coefficient after smoothing; Indicates the second compensation coefficient after the last smoothing process; γ a and γ b Represents the smoothing coefficient.

9. The method according to claim 7, characterized in that: The calculation method of the first initial compensation coefficient and the second initial compensation coefficient in S5 is: In the formula, represents the first initial compensation coefficient; represents the second initial compensation coefficient; Mc Indicates the starting time of statistics; M Indicates the time length of the statistical process; m Represents a variable.

10. The method according to claim 7, characterized in that The S6 includes: S61. Multiplexing S2 and S3 in the dynamic tracking correction process eliminates the residual DC signal in the I and Q output signals of the receiver and outputs the corrected signal from the first output port and the second output port; S62. Adaptively update the first compensation coefficient and the second compensation coefficient in the following manner: In the above formula, λ ( n )and β ( n ) represents the dynamically updated iteration step coefficient; δ represents a constant; S63. Repeat steps S61-S62 to dynamically track and correct the continuous I / Q imbalance input signal.

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