Display panel, display driving method thereof and display device

Abstract

The application relates to a display panel, a display driving method thereof and a display device. The display panel comprises a substrate, a driving array layer, a pixel definition layer and a light emitting element. The driving array layer is located on the substrate. The driving array layer comprises a first control circuit and a second control circuit. The pixel definition layer is located on a side of the driving array layer away from the substrate, and the pixel definition layer is provided with pixel openings arranged at intervals. The light emitting element is located on a side of the driving array layer away from the substrate, and the light emitting element comprises an anode, a first light emitting layer, a charge generation layer and a second light emitting layer which are arranged in layers, the anode is located between the driving array layer and the first light emitting layer, and the first light emitting layer and the second light emitting layer are both located in the pixel openings. The output end of the first control circuit is electrically connected with the anode and the input end of the second control circuit, and the output end of the second control circuit is electrically connected with the charge generation layer. The application can improve the display effect of the display panel and the display device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a display driving method thereof and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) is a self-luminous element, which has the advantages of high contrast, wide viewing angle, low power consumption, thinner thickness, etc. With the continuous breakthrough of OLED technology, the efficiency of OLED device is continuously improved. Especially in the stacked OLED device, the current at low gray scale has approached the control limit of Low Temperature Poly-Silicon Thin Film Transistor (LTPS-TFT), which makes the control accuracy of thin film transistor to current decrease at low gray scale, thereby causing the OLED device to have the problem of poor display effect. SUMMARY

[0003] Therefore, it is necessary to provide a display panel, a display driving method thereof and a display device capable of improving display effect in view of the above technical problems.

[0004] In a first aspect, the present application provides a display panel, which comprises a substrate, a driving array layer, a pixel defining layer and a light emitting element.

[0005] The driving array layer is located on the substrate. The driving array layer comprises a first control circuit and a second control circuit. The pixel defining layer is located on the side of the driving array layer away from the substrate, and the pixel defining layer is provided with a pixel opening. The light emitting element is located on the side of the driving array layer away from the substrate, and the light emitting element comprises an anode, a first light emitting layer, a charge generation layer and a second light emitting layer which are stacked, and the anode is located between the driving array layer and the first light emitting layer; the first light emitting layer and the second light emitting layer are both located in the pixel opening.

[0006] The output end of the first control circuit is electrically connected with the anode and the input end of the second control circuit, and the output end of the second control circuit is electrically connected with the charge generation layer.

[0007] The display panel, by setting the first control circuit and the second control circuit, and making the first control circuit electrically connected with the anode and the second control circuit electrically connected with the charge generation layer. It is equivalent to adding the second control circuit for controlling the second light-emitting layer in the original laminated light-emitting device. Thus, at low gray scale, the second light-emitting layer can be controlled to emit light by the second control circuit to increase the current of the second light-emitting layer at low gray scale, thereby improving the current control accuracy, and further improving the color deviation and display unevenness, and improving the display performance. In addition, by electrically connecting the charge generation layer and the second control circuit at the non-pixel opening of the pixel defining layer, the charge generation layer and the second control circuit are electrically connected by increasing the opening size of the pixel opening or setting an additional pixel opening, so that the area occupied by a single pixel does not need to be increased, and the pixel density is avoided to be smaller.

[0008] In one of the embodiments, the charge generation layer comprises a first part and a second part connected to each other.

[0009] The first part is located in the pixel opening, and the second part is located outside the pixel opening and on the pixel defining layer, and the second part is electrically connected with the output end of the second control circuit through the first via connection structure provided on the pixel defining layer.

[0010] Specifically, the display panel further comprises a support column, the support column is located on the side of the pixel defining layer away from the substrate, and is arranged around the pixel opening, and the second part is located on the side of the support column close to the pixel opening.

[0011] In this way, a part of the charge generation layer is formed on the surface of the pixel defining layer, and the part of the charge generation layer is electrically connected with the first via connection structure. This arrangement can reduce the difficulty of the preparation process.

[0012] In one of the embodiments, an electrode layer is arranged on the side of the pixel defining layer close to the driving array layer, and the electrode layer is electrically connected with the first via connection structure and the second control circuit.

[0013] In this way, by arranging the electrode layer, the first via connection structure and the second control circuit can be electrically connected.

[0014] In one of the embodiments, the electrode layer and the anode are arranged in the same layer.

[0015] In this way, the electrode layer can be prepared synchronously in the process of preparing the anode, thereby reducing the difficulty of preparing the display panel.

[0016] In one of the embodiments, the first via connection structure comprises a first via provided on the pixel defining layer, and a conductive layer provided in the first via.

[0017] In this way, the electrical connection performance of the first via connection structure can be more stable.

[0018] In one of the embodiments, the driving array layer further comprises a first data voltage line and a second data voltage line, the first control circuit is electrically connected with the first data voltage line, and the second control circuit is electrically connected with the second data voltage line.

[0019] In this way, the working of the first control circuit and the second control circuit can be controlled by the current control circuit, so as to realize the control of the first light-emitting layer and the second light-emitting layer.

[0020] In one of the embodiments, the first control circuit comprises a first driving transistor and a switching transistor, and the second control circuit comprises a second driving transistor.

[0021] The first data voltage line is electrically connected with the control electrode of the first driving transistor, and the second data voltage line is electrically connected with the control electrode of the second driving transistor.

[0022] The drain electrode of the switching transistor is electrically connected with the source electrode and the anode electrode of the second driving transistor, and the drain electrode of the second driving transistor is electrically connected with the charge generation layer.

[0023] In this way, the circuit structure of the first control circuit and the second control circuit can be simpler, and the circuit complexity of the first control circuit and the second control circuit can be reduced.

[0024] In one of the embodiments, the display panel further comprises a planarization layer, and the planarization layer is located between the pixel definition layer and the driving array layer.

[0025] The second via connection structure and the third via connection structure are arranged on the planarization layer, the second via connection structure is electrically connected with the anode and the first control circuit, and the third via connection structure is electrically connected with the first via connection structure and the second control circuit.

[0026] In this way, the electrical connection stability of the first control circuit and the anode, and the second control circuit and the first via connection structure can be better.

[0027] In a second aspect, the present application further provides a display device, which comprises the display panel in the first aspect.

[0028] The display device is characterized in that the first control circuit and the second control circuit are arranged, the first control circuit is electrically connected with the anode, and the second control circuit is electrically connected with the charge generation layer. In the original stacked light-emitting device, the second control circuit for controlling the second light-emitting layer is added, so that the second light-emitting layer can be controlled to emit light by the second control circuit at a low gray scale, the current of the second light-emitting layer at the low gray scale is increased, and the current control accuracy is improved, thereby improving the color deviation and display unevenness and improving the display performance. In addition, the first via connection structure is arranged on the pixel definition layer to electrically connect the charge generation layer and the second control circuit, so that the charge generation layer and the second control circuit are electrically connected by increasing the opening size of the pixel opening or arranging an additional pixel opening, so that the area of a single pixel is not required to be increased, and the pixel density is not reduced.

[0029] In a third aspect, the present application further provides a display driving method of a display panel, comprising:

[0030] obtaining a current use scenario, the current use scenario comprising a first gray scale scenario and a second gray scale scenario;

[0031] selecting a driving mode according to the current use scenario, wherein the first gray scale scenario corresponds to a first driving mode, and the second gray scale scenario corresponds to a second driving mode; the first driving mode is configured to turn on the first control circuit and turn off the second control circuit to drive the first light-emitting layer and the second light-emitting layer to emit light; and the second driving mode is configured to turn on the second control circuit to drive the second light-emitting layer to emit light.

[0032] The display driving method of the display panel can control the second light-emitting layer to emit light by the second control circuit at a low gray scale, increase the current of the second light-emitting layer at the low gray scale, improve the current control accuracy, and improve the color deviation, display unevenness and display performance. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0034] Figure 1 A relationship curve between current efficiency and gray scale is provided for the present application;

[0035] Figure 2 An LTPS-TFT transfer curve is provided for the present application;

[0036] Figure 3A cross-sectional structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 1.

[0037] Figure 4 A cross-sectional structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 1. Figure 3 An equivalent circuit diagram of the switching transistor and the second driving transistor in FIG. 1 is shown in FIG. 2.

[0038] Figure 5 A cross-sectional structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 1.

[0039] Figure 6 A cross-sectional structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 1.

[0040] Figure 7 A flowchart of a display driving method of a display panel provided by an embodiment of the present application is shown in FIG. 4.

[0041] Legend of reference signs:

[0042] 100 - display panel; 110 - substrate; 120 - driving array layer; 121 - first control circuit; 1211 - switching transistor; 1211a - control electrode; 1211b - drain electrode; 1211c - source electrode; 122 - second control circuit; 1221 - second driving transistor; 1221a - control electrode; 1221b - drain electrode; 1221c - source electrode; 123 - insulating layer; 124 - electrical connection structure; 130 - pixel defining layer; 131 - pixel opening; 132 - first via connection structure; 1321 - first via; 1322 - conductive layer; 133 - accommodating groove; 140 - light emitting element; 1401 - anode; 1402 - first light emitting layer; 1403 - charge generation layer; 1403a - first part; 1403b - second part; 1404 - second light emitting layer; 1405 - electron injection layer; 1406 - cathode; 1407 - first electron transport layer; 1408 - first hole transport layer; 1409 - second electron transport layer; 1410 - second hole transport layer; 1411 - hole injection layer; 150 - electrode layer; 160 - planarization layer; 161 - second via connection structure; 162 - third via connection structure; 170 - support column. DETAILED DESCRIPTION

[0043] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application can be more thoroughly and completely understood.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more light-emitting units present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more light-emitting units present.

[0046] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0047] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0049] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0050] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0051] As described in the background section, with continuous breakthroughs in OLED technology, the efficiency of OLED devices is constantly improving. Figure 1As shown in the figure, the curve a can be considered as a relationship curve between the current efficiency and the gray scale of the OLED device in a period of time, the curve b can be considered as a relationship curve between the current efficiency and the gray scale of the OLED device after the further development of the OLED technology, and the curve c can be considered as a relationship curve between the current efficiency and the gray scale of the OLED device after the further development of the OLED technology. Figure 1 It can be known that, with the continuous development of the OLED technology, the current efficiency of the OLED device has been significantly improved.

[0052] Continuing to refer to Figure 2 As shown in the figure, the curve c represents the LTPS-TFT transfer curve, the curve d can be considered as the current of the single-layer OLED device at the low gray scale, and the curve e can be considered as the current of the stacked OLED device at the low gray scale. It can be known from the figure that, in the stacked OLED device, the current at the low gray scale has approached the control limit of the LTPS-TFT. Meanwhile, due to the influence of the preparation process, the current fluctuation at the low gray scale is relatively large. In this way, the current control accuracy of the TFT at the low gray scale is reduced, and the accurate current value corresponding to the required brightness cannot be obtained. In this case, because the current requirements of the RGB sub-pixels are inconsistent, the inaccurate current control of the TFTs corresponding to the sub-pixels leads to the color cast or display uneven phenomenon, and further leads to the poor display effect of the OLED device.

[0053] Therefore, the present application provides a display panel and a display driving method thereof and a display device. The first control circuit and the second control circuit are arranged, the first control circuit is electrically connected with the anode, and the second control circuit is electrically connected with the charge generation layer. In the original stacked light-emitting device, the second control circuit for controlling the second light-emitting layer is added. In this way, the second light-emitting layer can emit light under the control of the second control circuit at the low gray scale, so as to increase the current of the second light-emitting layer at the low gray scale, thereby improving the current control accuracy, and further improving the color cast and display uneven phenomenon and improving the display performance.

[0054] In a first aspect, an embodiment of the present application provides a display panel, which can be a flexible display panel. For example, the display panel can be a flexible display panel with only display function, or a flexible display panel with both display function and touch function.

[0055] Referring to Figure 3 and Figure 4 As shown in the figure, the display panel 100 includes a substrate 110, a driving array layer 120, a pixel definition layer 130, and a light-emitting element 140. The substrate 110 can be flexible polyimide (PI), rigid glass, or a thin metal sheet, and the like. The substrate 110 of other materials is not discussed in detail herein, and a person skilled in the art can select different kinds of materials according to actual needs.

[0056] Specifically, the driving array layer 120 is located on the substrate 110. The driving array layer 120 includes a first control circuit 121 and a second control circuit 122. The pixel definition layer 130 is located on the side of the driving array layer 120 away from the substrate 110, and the pixel definition layer 130 is provided with pixel openings 131 and first via connection structures 132 arranged at intervals. The material of the pixel definition layer 130 can be polyimide, acrylic or polyethylene terephthalate, etc., and the shape of the orthographic projection of the pixel opening 131 on the substrate 110 can be rectangular or trapezoidal, etc.

[0057] The light emitting element 140 is located on the side of the driving array layer 120 away from the substrate 110, and at least part of the light emitting element 140 is located in the pixel opening 131. The light emitting element 140 includes an anode 1401, a first light emitting layer 1402, a charge generation layer 1403 and a second light emitting layer 1404 arranged in layers, the anode 1401 is located between the driving array layer 120 and the first light emitting layer 1402, and the first light emitting layer 1402 and the second light emitting layer 1404 are both located in the pixel opening 131. The output end of the first control circuit 121 is electrically connected to the anode 1401 and the input end of the second control circuit 122, and the output end of the second control circuit 122 is electrically connected to the charge generation layer 1403 through the first via connection structure 132.

[0058] It should be noted that, in Figure 3 , the driving array layer 120 further includes other structures, and only part of the structures are shown in the figure. In Figure 4 , T1 represents a switching transistor 1211, T2 represents a second driving transistor 1221, EL1 represents the first light emitting layer 1402, and EL2 represents the second light emitting layer 1404. In addition, the light emitting element 140 further includes a cathode 1406 located on the side of the second light emitting layer 1404 away from the anode 1401.

[0059] It can be understood that the charge generation layer 1403 can generate equal numbers of electrons and holes, and transmit them to the first light emitting layer 1402 and the second light emitting layer 1404 on both sides respectively, so that the first light emitting layer 1402 and the second light emitting layer 1404 emit light. The charge generation layer 1403 can include a p-type charge generation layer and an n-type charge generation layer stacked together. The p-type charge generation layer and the n-type charge generation layer constitute an organic semiconductor heterojunction, which utilizes the high-efficiency charge generation effect of the organic semiconductor heterojunction to improve the injection efficiency of the charge generation layer 1403 to the carriers, and is conducive to improving the display effect of the display panel.

[0060] The display panel 100 described above, by setting the first control circuit 121 and the second control circuit 122, and making the first control circuit 121 electrically connected with the anode 1401, and the second control circuit 122 electrically connected with the charge generation layer 1403. It is equivalent to adding the second control circuit 122 for controlling the second light emitting layer 1404 in the original laminated light emitting device. The light emitting principle of the first light emitting layer 1402 and the second light emitting layer 1404 is as follows: when the first control circuit 121 works, the anode 1401 generates holes, the charge generation layer 1403 generates electrons, the holes generated by the anode 1401 and the electrons generated by the charge generation layer 1403 recombine in the first light emitting layer 1402 to generate excitons, and the first light emitting layer 1402 emits light; at the same time, the cathode 1406 generates electrons, the charge generation layer 1403 generates holes, and the electrons generated by the cathode 1406 and the holes generated by the charge generation layer 1403 recombine in the second light emitting layer 1404 to generate excitons, and the second light emitting layer 1404 emits light. When the second control circuit 122 works, the charge generation layer 1403 generates holes, and the electrons generated by the cathode 1406 and the holes generated by the charge generation layer 1403 recombine in the second light emitting layer 1404 to generate excitons, and the second light emitting layer 1404 emits light.

[0061] In this way, at a low gray scale, the second light emitting layer 1404 can be controlled to emit light by the second control circuit 122 to increase the current of the second light emitting layer 1404 at a low gray scale, thereby facilitating improvement of current control accuracy, and further improvement of color deviation and display unevenness, and improvement of display performance. In addition, by setting the first via connection structure 132 on the pixel definition layer 130 to electrically connect the charge generation layer 1403 and the second control circuit 122, the charge generation layer 1403 and the second control circuit 122 are electrically connected without increasing the opening size of the pixel opening 131 or setting additional pixel openings 131, so that the occupied area of a single pixel does not need to be increased, and the pixel density is not reduced.

[0062] It should be noted that the display panel 100 provided by the embodiment of the present application has a large proportion of the second light emitting layer 1404 emitting light at a low gray scale, and the proportion of the second light emitting layer 1404 emitting light gradually decreases as the gray scale increases, so as to achieve a controllable state of high and low gray scale efficiency.

[0063] It can be understood that the light emitting element 140 in the embodiment of the present application can also include a third light emitting layer, the third light emitting layer is located on the side of the second light emitting layer 1404 away from the substrate 110, and a charge generation layer 1403 can also be arranged between the third light emitting layer and the second light emitting layer 1404. Similarly, a third control circuit can also be arranged, and the output end of the third control circuit is electrically connected with the charge generation layer 1403 between the second light emitting layer 1404 and the third light emitting layer, so as to realize the control of the third control circuit on the third light emitting layer. The number of light emitting layers included in the light emitting element 140 is not limited in the embodiment of the present application.

[0064] In one of the embodiments, as shown in Figure 3 The charge generation layer 1403 can include a first part 1403a and a second part 1403b connected with each other. The first part 1403a is located in the pixel opening 131, and the second part 1403b is located outside the pixel opening 131 and is electrically connected with the first via connection structure 132. Specifically, the second part 1403b can be arranged on part of the surface of the pixel defining layer 130, so that the orthographic projection of the second part 1403b on the pixel defining layer 130 covers at least part of the first via connection structure 132.

[0065] In this way, a part of the charge generation layer 1403 is formed on the surface of the pixel defining layer 130, and the first via connection structure 132 is electrically connected with the part of the charge generation layer 1403.

[0066] It can be understood that in the process of preparing the charge generation layer 1403, the first part 1403a and the second part 1403b can be formed at the same time. The first part 1403a can be regarded as the "main body" of the charge generation layer 1403, and the second part 1403b can be regarded as the "intermediate connection structure" for electrically connecting the charge generation layer 1403 with the first via connection structure 132. In this way, the "main body" and the "intermediate connection structure" of the charge generation layer 1403 are completed in the same preparation process, so that the number of preparation processes is reduced and the preparation difficulty is reduced.

[0067] Specifically, as shown in Figure 3 The display panel 100 further includes a support column 170, the support column 170 is located on the side of the pixel defining layer 130 away from the substrate 110 and is arranged around the pixel opening 131, and the second part 1403b is located on the side of the support column 170 close to the pixel opening 131.

[0068] It should be noted that the display panel 100 includes a plurality of light emitting elements 140, and the pixel definition layer 130 is provided with a plurality of pixel openings 131 and a plurality of first via connection structures 132, and each light emitting element 140 corresponds to one pixel opening 131 and one first via connection structure 132. Similarly, the driving array layer 120 includes a plurality of first control circuits 121 and a plurality of second control circuits 122, and each light emitting element 140 corresponds to one first control circuit 121 and one second control circuit 122.

[0069] Taking a specific light emitting element 140 as an example, the periphery of the light emitting element 140 is provided with a support column 170. By locating the second part 1403b of the charge generating layer 1403 on the side of the support column 170 close to the pixel opening 131, the second part 1403b of the charge generating layer 1403 can be prevented from extending towards the adjacent light emitting element 140, thereby avoiding affecting the light emitting performance of the adjacent light emitting element 140. It can be understood that the first via connection structure 132 corresponding to the light emitting element 140 is also located on the side of the support column 170 close to the pixel opening 131, so that the second part 1403b and the first via connection structure 132 are electrically connected.

[0070] In one of the embodiments, referring to FIG. 1, the pixel definition layer 130 is provided with a receiving groove 133, and the electrode layer 150 is arranged in the receiving groove 133. The electrode layer 150 is electrically connected to the first via connection structure 132 and the second control circuit 122. Figure 5 Further, the side of the pixel definition layer 130 close to the driving array layer 120 is provided with the receiving groove 133, and the electrode layer 150 is located in the receiving groove 133. In this way, by arranging the electrode layer 150, the first via connection structure 132 and the second control circuit 122 can be electrically connected.

[0071] Specifically, the electrode layer 150 can be made to cover the first via connection structure 132 in the orthographic projection on the pixel definition layer 130. In this way, the surface area of the side of the electrode layer 150 close to the driving array layer 120 is larger than the cross-sectional area of the first via connection structure 132, which facilitates the electrical connection between the second control circuit 122 and the electrode layer 150, thereby facilitating the electrical connection between the first via connection structure 132 and the second control circuit 122.

[0072] It should be noted that the receiving groove 133 is formed "passively" in the process of preparation, rather than "actively". That is, the electrode layer 150 is formed first, and then the pixel definition layer 130 is formed. After the pixel definition layer 130 is formed, part of the pixel definition layer 130 is arranged around the side and top surface of the electrode layer 150, so that the pixel definition layer 130 forms a receiving groove 133 for accommodating the electrode layer 150.

[0073] In one of the embodiments, the electrode layer 150 and the anode 1401 are arranged in the same layer. In this way, the electrode layer 150 can be prepared simultaneously with the anode 1401 in the process of preparing the anode 1401, thereby reducing the difficulty in preparing the display panel 100.

[0074] Here, the "arranged in the same layer" can be understood as that the electrode layer 150 and the anode 1401 are formed in the same preparation process, and the material and thickness of the electrode layer 150 and the anode 1401 are the same. For example, the material of the electrode layer 150 and the anode 1401 can be silver, copper, aluminum, molybdenum, indium tin oxide, or indium zinc oxide.

[0075] In one of the embodiments, the first via connection structure 132 includes a first via 1321 arranged on the pixel defining layer 130, and a conductive layer 1322 arranged in the first via 1321. In this way, the electrical connection performance of the first via connection structure 132 can be more stable.

[0076] It can be understood that the conductive layer 1322 can be filled in the first via 1321, so that the conductive layer 1322 fills the space in the first via 1321; or the conductive layer 1322 can only cover the sidewall of the first via 1321, that is, the conductive layer 1322 does not fill the space in the first via 1321.

[0077] In one of the embodiments, the material of the conductive layer 1322 includes at least one of a conductive metal, a conductive oxide, and a conductive polymer. For example, the conductive metal can be silver, copper, aluminum, or molybdenum, the conductive oxide can be tin oxide, zinc oxide, cadmium oxide, indium oxide, indium tin oxide, zinc indium oxide, zinc gallium oxide, or zinc aluminum oxide, and the conductive polymer can be a composite conductive polymer or a structural conductive polymer.

[0078] In this way, the conductive layer 1322 can be prepared by various preparation processes, thereby facilitating the reduction of the preparation difficulty. In one example, the conductive polymer layer can be formed in the first via 1321 by ink printing.

[0079] In one of the embodiments, the driving array layer 120 further includes a first data voltage line (not shown) and a second data voltage line (not shown). The first data voltage line is electrically connected with the first control circuit 121, and the second data voltage line is electrically connected with the second control circuit 122. The first data voltage line and the second data voltage line are configured to control the generation of the driving current and the current intensity of the generated driving current. In this way, the first data voltage line and the second data voltage line can be used to control the operation of the first control circuit 121 and the second control circuit 122 respectively, thereby realizing the control of the first light emitting layer 1402 and the second light emitting layer 1404.

[0080] Specifically, the first data voltage line and the second data voltage line are used to receive a data signal and a light-emitting control signal, on the one hand, according to the light-emitting control signal, whether to generate a drive current is controlled, on the other hand, according to the data signal, the current intensity of the generated drive current is controlled.

[0081] In one of the embodiments, the first control circuit 121 includes a first drive transistor (not shown in the figure) and a switch transistor 1211, and the second control circuit 122 includes a second drive transistor 1221. The first data voltage line is electrically connected to the control electrode of the first drive transistor, and the second data voltage line is electrically connected to the control electrode of the second drive transistor 1221. The drain electrode 1211b of the switch transistor 1211 is electrically connected to the source electrode 1221c and the anode 1401 of the second drive transistor 1221. The drain electrode 1221b of the second drive transistor 1221 is electrically connected to the charge generation layer 1403. Further, the drain electrode 1221b of the second drive transistor 1221 is electrically connected to the first via connection structure 132.

[0082] It can be understood that the first control circuit 121 can be a pixel driving circuit, for example: a 7T1C circuit, a 5T1C circuit or a 2T1C circuit.

[0083] In this way, on the one hand, the current ratio of the first light-emitting layer 1402 and the second light-emitting layer 1404 can be controlled, so as to adjust the high and low gray scale efficiency change.

[0084] Specifically, the structural parameters of the switch transistor 1211 and the second drive transistor 1221 are different, the pixel current of the entire light-emitting element 140 is distributed to the switch transistor 1211 as I1, and the pixel current of the entire light-emitting element 140 is distributed to the second drive transistor 1221 as I2, wherein the current of the first light-emitting layer 1402 is I1, and the current of the second light-emitting layer 1404 is I1+I2. With the increase of the gray scale, the current proportion of the second drive transistor 1221 continuously decreases until it is completely closed.

[0085] In one example, at a low gray scale, the second drive transistor 1221 is completely opened, and the second light-emitting layer 1404 emits light; at a transition gray scale, the second drive transistor 1221 is gradually closed, and the first light-emitting layer 1402 and the second light-emitting layer 1404 emit light at the same time; at a high gray scale, the second drive transistor 1221 is completely closed, and the first light-emitting layer 1402 and the second light-emitting layer 1404 emit light at the same time.

[0086] In another example, at a low gray scale, the second drive transistor 1221 is completely opened, and the second light-emitting layer 1404 emits light; at a transition gray scale and a high gray scale, the second drive transistor 1221 is gradually closed, and the first light-emitting layer 1402 and the second light-emitting layer 1404 emit light at the same time.

[0087] In one embodiment, the display panel 100 further includes a planarization layer 160 located between the pixel defining layer 130 and the driving array layer 120. The planarization layer 160 has a second via connection structure 161 and a third via connection structure 162. The second via connection structure 161 is electrically connected to the anode 1401 and the first control circuit 121, and the third via connection structure 162 is electrically connected to the first via connection structure 132 and the second control circuit 122. This improves the stability of the electrical connections between the first control circuit 121 and the anode 1401, and between the second control circuit 122 and the first via connection structure 132.

[0088] It is understood that the conductive materials included in the second via connection structure 161 and the third via connection structure 162 can be the same as the material of the anode, and will not be described again in the embodiments of this application.

[0089] It should be noted that the driving array layer 120 also includes an insulating layer 123 and an electrical connection structure 124. Taking the switching transistor 1211 as an example, the insulating layer 123 is located between the control electrode 1211a and the drain electrode 1211b (source electrode 1211c), one end of the electrical connection structure 124 is connected to the drain electrode 1211b, and the other end of the electrical connection structure 124 is connected to the second via connection structure 161.

[0090] Understandably, referring to Figure 6 As shown, a first electron transport layer 1407 and an electron injection layer 1405 may be stacked between the second light-emitting layer 1404 and the cathode 1406; a first hole transport layer 1408 may be stacked between the second light-emitting layer 1404 and the charge generation layer 1403; a second electron transport layer 1409 may be stacked between the charge generation layer 1403 and the first light-emitting layer 1402; and a hole injection layer 1411 and a second hole transport layer 1410 may be stacked between the first light-emitting layer 1402 and the anode 1401. The embodiments of this application do not limit the stacked structure of the light-emitting element 140.

[0091] Secondly, this application also provides a display device, which includes the display panel described in the first aspect.

[0092] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0093] The display device has the first control circuit and the second control circuit, and the first control circuit is electrically connected with the anode, and the second control circuit is electrically connected with the charge generation layer. In the original stacked light-emitting device, the second control circuit for controlling the second light-emitting layer is added, so that the second light-emitting layer can emit light under low gray scale through the second control circuit to increase the current of the second light-emitting layer under low gray scale, thereby improving the current control accuracy, and improving the color deviation and display unevenness, and improving the display performance. In addition, the first via connection structure is arranged on the pixel definition layer to electrically connect the charge generation layer and the second control circuit, avoiding the increase of the opening size of the pixel opening or the arrangement of additional pixel openings to electrically connect the charge generation layer and the second control circuit, so that the area of a single pixel is not required to be increased, and the pixel density is not reduced.

[0094] In a third aspect, the display panel in the first aspect is also provided with a display driving method. As shown in Figure 7 , the display driving method comprises the following steps.

[0095] S100: acquiring a current use scenario, the current use scenario comprising a first gray scale scenario and a second gray scale scenario. For example, the first gray scale scenario can be a high gray scale scenario, and the second gray scale scenario can be a low gray scale scenario.

[0096] S200: selecting a driving mode according to the current use scenario, wherein the first gray scale scenario corresponds to a first driving mode, and the second gray scale scenario corresponds to a second driving mode; the first driving mode is configured to turn on the first control circuit and turn off the second control circuit to drive the first light-emitting layer and the second light-emitting layer to emit light; and the second driving mode is configured to turn on the second control circuit to drive the second light-emitting layer to emit light.

[0097] Specifically, as shown in Figure 3 and Figure 4 , the first control circuit 121 comprises a first drive transistor (not shown in the figure) and a switch transistor 1211, and the second control circuit 122 comprises a second drive transistor 1221. The first data voltage line is electrically connected with the control electrode of the first drive transistor, and the second data voltage line is electrically connected with the control electrode of the second drive transistor 1221. The drain electrode 1211b of the switch transistor 1211 is electrically connected with the source electrode 1221c of the second drive transistor 1221 and the anode 1401. The drain electrode 1221b of the second drive transistor 1221 is electrically connected with the first via connection structure 132.

[0098] In one example, the driving mode is as follows:

[0099] When in the first driving mode, the switch transistor 1211 is turned on, the second driving transistor 1221 is completely turned off, and the first light emitting layer 1402 and the second light emitting layer 1404 emit light simultaneously.

[0100] When in the second driving mode, the switch transistor 1211 is turned on, the second driving transistor 1221 is completely turned on, and the first light emitting layer 1402 and the second light emitting layer 1404 emit light simultaneously.

[0101] In another example, the current use scene further includes a third gray scale scene, the third gray scale scene corresponds to a third driving mode, and the third gray scale scene can be a transition gray scale scene.

[0102] In one example, when in the third driving mode, the switch transistor 1211 is turned on, the second driving transistor 1221 is partially turned off, and the first light emitting layer 1402 and the second light emitting layer 1404 emit light simultaneously.

[0103] In another example, when in the third driving mode, the switch transistor 1211 is turned on, the second driving transistor 1221 is completely turned off, and the first light emitting layer 1402 and the second light emitting layer 1404 emit light simultaneously.

[0104] It should be understood that, although Figure 7 The steps in the flowchart of FIG. 1 are not necessarily performed in the order indicated by the arrows. Unless explicitly stated, the steps are not necessarily performed in the order indicated by the arrows. There is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps in the flowchart of FIG. 1 can include multiple steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be alternately or alternately executed with at least part of other steps or steps or stages in other steps.

[0105] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure.

[0106] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a driving array layer located on the substrate; the driving array layer comprises a first control circuit and a second control circuit; a pixel definition layer located on a side of the driving array layer away from the substrate, the pixel definition layer being provided with a pixel opening; a light emitting element located on a side of the driving array layer away from the substrate, the light emitting element comprising an anode, a first light emitting layer, a charge generation layer and a second light emitting layer which are stacked, the anode being located between the driving array layer and the first light emitting layer; the first light emitting layer and the second light emitting layer are both located within the pixel opening; wherein an output end of the first control circuit is electrically connected with the anode and an input end of the second control circuit, and an output end of the second control circuit is electrically connected with the charge generation layer; the charge generation layer comprises a second part, the second part being located outside the pixel opening and on the pixel definition layer; the display panel further comprises a support column, the support column being located on a side of the pixel definition layer away from the substrate and being arranged around the pixel opening; the second part is located on a side of the support column close to the pixel opening.

2. The display panel of claim 1, wherein, The charge generation layer comprises a first part and a second part which are connected with each other; the first part is located within the pixel opening, and the second part is electrically connected with the output end of the second control circuit through a first via connection structure provided on the pixel definition layer.

3. The display panel of claim 2, wherein, An electrode layer is arranged on a side of the pixel definition layer close to the driving array layer, the electrode layer electrically connecting the first via connection structure and the second control circuit.

4. The display panel of claim 3, wherein, The electrode layer and the anode are arranged in the same layer.

5. The display panel of any of claims 2-4, wherein, The first via connection structure comprises a first via provided on the pixel definition layer and a conductive layer provided in the first via.

6. The display panel of any one of claims 1-4, wherein, The driving array layer further comprises a first data voltage line and a second data voltage line, the first control circuit being electrically connected with the first data voltage line, and the second control circuit being electrically connected with the second data voltage line.

7. The display panel of claim 6, wherein, The first control circuit comprises a first driving transistor and a switching transistor, and the second control circuit comprises a second driving transistor; the first data voltage line is electrically connected with a control electrode of the first driving transistor, and the second data voltage line is electrically connected with a control electrode of the second driving transistor; a drain electrode of the switching transistor is electrically connected with a source electrode of the second driving transistor and the anode; a drain electrode of the second driving transistor is electrically connected with the charge generation layer.

8. The display panel of any of claims 2-4, wherein, The display panel further comprises a planarization layer located between the pixel definition layer and the driving array layer; a second via connection structure and a third via connection structure are arranged on the planarization layer, the second via connection structure electrically connecting the anode and the first control circuit, and the third via connection structure electrically connecting the first via connection structure and the second control circuit.

9. A display device comprising: The display panel comprises any one of the display panels according to claims 1-8.

10. A display driving method of the display panel according to any one of claims 1 to 8, characterized by, The method comprises: acquiring a current use scenario, the current use scenario comprising a first gray scale scenario and a second gray scale scenario; According to the current use scene, a driving mode is selected, wherein the first gray scale scene corresponds to a first driving mode, and the second gray scale scene corresponds to a second driving mode; the first driving mode is configured to turn on the first control circuit and turn off the second control circuit to drive the first light-emitting layer and the second light-emitting layer to emit light; and the second driving mode is configured to turn on the second control circuit to drive the second light-emitting layer to emit light.

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