Semiconductor device and semiconductor module

Abstract

A semiconductor device with a fan-out package structure includes: a semiconductor element (11) having a first electrode pad (111) and a second electrode pad (112) on a surface (11a); a sealing element (12) made of an insulating resin material covering a side (11c) of the semiconductor element that connects the aforementioned surface and back surface (11b); and a redistribution layer (13) covering a portion of the surface of the semiconductor element and the sealing element. The redistribution layer includes: an insulating layer (131) made of an insulating resin material; a first redistribution layer (132) at least partially disposed on the side of the semiconductor element and the boundary of the sealing element; and a second redistribution layer (133) electrically connected to the second electrode pad and at least partially extending across the first redistribution layer to the outer side of the outer contour of the semiconductor element, electrically independent of the first redistribution layer.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-119423, filed on July 10, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices with a fan-out package structure and semiconductor modules using the same. Background Technology

[0004] Conventionally, examples of semiconductor devices having semiconductor elements and semiconductor modules using a two-sided heat dissipation structure include, for instance, the structure described in Patent Document 1. The semiconductor module described in Patent Document 1 includes a semiconductor device having power semiconductor elements, two heat sinks disposed on both sides sandwiching the semiconductor device, lead terminals, and wires connecting the semiconductor device to the lead terminals. Furthermore, to prevent short circuits caused by contact between the wires and the heat sinks, a heat sink made of a highly thermally conductive material is disposed between the side of the connecting wires in the semiconductor device and the heat sink facing that side.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2001-156225 Summary of the Invention

[0008] However, the aforementioned semiconductor module utilizes a heat sink to maintain a gap between the semiconductor device and the heat sink at a specified value, thereby preventing contact between the wiring and the heat sink. Therefore, the heat sink becomes an obstacle to achieving a thinner design. Furthermore, the placement of the heat sink between the semiconductor device and the heat sink increases the thermal resistance, thus reducing the heat dissipation performance of the semiconductor module.

[0009] Therefore, the inventors of this invention conducted specific research on the structure of the semiconductor device and the semiconductor module in order to achieve both thinness and high heat dissipation in this semiconductor module. As a result, a semiconductor module with the following structure was conceived: the semiconductor device is made into a fan-out package structure with a redistribution layer, heat sinks are bonded to both sides of the semiconductor device without heat sinks, and lead terminals are connected to the redistribution layer without wires. Thus, a semiconductor module with a two-sided heat dissipation structure that achieves thinness and high heat dissipation without heat sinks or wires is obtained.

[0010] Further specialized research by the inventors of this invention revealed that if the semiconductor device with the envisioned fan-out package structure is made thinner, the contact area between the side of the semiconductor element and the encapsulator covering it decreases, potentially leading to encapsulator peeling at their interface. In the event that the encapsulator peels off from the side of the semiconductor element, cracks may propagate to the portion of the insulating layer constituting the redistribution layer located at the boundary between the side of the semiconductor element and the encapsulator, making it impossible to ensure insulation of the redistribution at that boundary.

[0011] This invention relates to a semiconductor device with a fan-out package structure that ensures insulation of rewiring on the sides of the semiconductor element and the boundary of the package, thereby improving reliability, and to a semiconductor module that uses it to achieve thinness and high heat dissipation.

[0012] To achieve the above objectives, according to a technical solution of the present invention, the semiconductor device is a fan-out packaged semiconductor device comprising: a semiconductor element having a first electrode pad and a second electrode pad on its surface; a sealing element made of an insulating resin material covering a side of the semiconductor element that connects the surface and the back side; and a redistribution layer covering the surface of the semiconductor element and a portion of the sealing element; the redistribution layer having an insulating layer made of an insulating resin material, a first redistribution disposed at least partially on the side of the semiconductor element and the boundary of the sealing element, and a second redistribution electrically connected to the second electrode pad, and at least partially extending across the first redistribution to the outer side of the outer contour of the semiconductor element, and electrically independent of the first redistribution.

[0013] This results in a semiconductor device with a fan-out package structure where a portion of the first rewiring is disposed on the side of the semiconductor element and at the boundary of the package, and a second rewiring electrically independent of the first rewiring is disposed between the boundary and the portion of the first rewiring. Even if the interface between the side of the semiconductor element and the package peels off from the side opposite to the rewiring layer, causing a crack in a portion of the insulating layer of the rewiring layer, the first rewiring prevents the crack from propagating. Therefore, the crack in the insulating layer does not reach the second rewiring, thus ensuring the insulation of the second rewiring.

[0014] According to one aspect of the present invention, a semiconductor module comprises: a semiconductor device having a semiconductor element having a first electrode pad and a second electrode pad on its surface; a first sealing element made of an insulating resin material and covering a side surface of the semiconductor element that connects the surface and the back surface; and a redistribution layer having an insulating layer made of an insulating resin material, a first redistribution line at least partially disposed on the boundary between the side surface of the semiconductor element and the first sealing element, and a second redistribution line electrically connected to the second electrode pad and extending at least partially across the first redistribution line to the outer side of the outer contour of the semiconductor element and electrically independent of the first redistribution line; a first heat dissipation member connected to the back surface of the semiconductor device exposed from the first sealing element via a bonding member; a second heat dissipation member electrically connected to the first electrode pad in the semiconductor device via a bonding member; a lead frame electrically connected to the second redistribution line in the semiconductor device via a bonding member; and a second sealing element covering the semiconductor device, a portion of the first heat dissipation member, a portion of the second heat dissipation member, and a portion of the lead frame.

[0015] Thus, a semiconductor module is constructed with the first and second heat dissipation components arranged in relation to a semiconductor device according to a technical solution of the present invention, which are joined via a bonding member, and the first rewiring and lead frame are electrically connected via the bonding member. This semiconductor module, through the first rewiring, suppresses cracks in the lower part of the second rewiring in the insulating layer, improving reliability, and because the second heat dissipation component and the semiconductor device are directly joined without the need for a heat sink, it achieves a thinner and more efficient heat dissipation structure.

[0016] Furthermore, the parenthesized labels assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent element described in the embodiments described later. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view showing the semiconductor device of the first embodiment.

[0018] Figure 2 It means Figure 1 An enlarged sectional view of region II in the diagram.

[0019] Figure 3 This is an explanatory diagram used to illustrate the configuration relationship between the first rewiring and the second rewiring.

[0020] Figure 4 This is a perspective view of the semiconductor device according to the first embodiment.

[0021] Figure 5A This is a cross-sectional view showing the process of attaching a semiconductor substrate to a support substrate in the manufacturing process of the semiconductor device according to the first embodiment.

[0022] Figure 5B It means to continue Figure 5A A cross-sectional view of the manufacturing process of a semiconductor device.

[0023] Figure 5C It means to continue Figure 5B A cross-sectional view of the manufacturing process of a semiconductor device.

[0024] Figure 5D It means to continue Figure 5C A cross-sectional view of the manufacturing process of a semiconductor device.

[0025] Figure 5E It means to continue Figure 5D A cross-sectional view of the manufacturing process of a semiconductor device.

[0026] Figure 5F It means to continue Figure 5E A cross-sectional view of the manufacturing process of a semiconductor device.

[0027] Figure 5G It means to continue Figure 5F A cross-sectional view of the manufacturing process of a semiconductor device.

[0028] Figure 5H It means to continue Figure 5G A cross-sectional view of the manufacturing process of a semiconductor device.

[0029] Figure 5I It means to continue Figure 5H A cross-sectional view of the manufacturing process of a semiconductor device.

[0030] Figure 5J It means to continue Figure 5I A cross-sectional view of the manufacturing process of a semiconductor device.

[0031] Figure 5K It means to continue Figure 5J A cross-sectional view of the manufacturing process of a semiconductor device.

[0032] Figure 5L It means to continue Figure 5K A cross-sectional view of the manufacturing process of a semiconductor device.

[0033] Figure 6A This is a cross-sectional view showing the structure of a comparative example semiconductor device.

[0034] Figure 6B It is used to explain in Figure 6A The illustration shows the loss of insulation in the rewiring caused by the peeling extension between the side of the semiconductor element and the encapsulator in the comparative example semiconductor device.

[0035] Figure 6CThis is an explanatory diagram used to illustrate the insulation assurance of the second rewiring based on the first rewiring in the semiconductor device of the first embodiment.

[0036] Figure 7 This is a cross-sectional view showing an example of a semiconductor module constructed using the semiconductor device of the first embodiment.

[0037] Figure 8 This is a cross-sectional view showing another example of a semiconductor module constructed using the semiconductor device of the first embodiment.

[0038] Figure 9 This is a cross-sectional view showing another example of a semiconductor module constructed using the semiconductor device of the first embodiment.

[0039] Figure 10 This is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment.

[0040] Figure 11 It is equivalent to Figure 1 The diagram is a cross-sectional view showing the semiconductor device of the second embodiment.

[0041] Figure 12 This is a cross-sectional view showing the structure of the comparative example in the simulation calculation.

[0042] Figure 13 It is a cross-sectional view showing the structure of an embodiment in the simulation calculation.

[0043] Figure 14 This is a graph showing the results of simulation calculations corresponding to the applied electric field's withstand voltage.

[0044] Figure 15 This is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment, and a partial cross-sectional view showing the vicinity of the first rewiring.

[0045] Figure 16 This is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment.

[0046] Figure 17A It means Figure 16 A sectional view of the section between XVIIA and XVIIA.

[0047] Figure 17B It is equivalent to Figure 17A The figure is a cross-sectional view showing another configuration example of the first rewiring of the second variation of the second embodiment.

[0048] Figure 18A This is a cross-sectional view showing the formation process of the redistribution layer of a semiconductor device in other embodiments.

[0049] Figure 18B It means to continue Figure 18A A cross-sectional view of the process for forming the redistribution layer.

[0050] Figure 18C This is a cross-sectional view showing a structural example of the redistribution layer of a semiconductor device in another embodiment. Detailed Implementation

[0051] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same reference numerals will be used to describe the identical or equivalent parts.

[0052] (First Embodiment)

[0053] Reference Figures 1-4 The semiconductor device 1 of the first embodiment will be described.

[0054] exist Figure 2 For ease of explanation, in the direction along the thickness direction of the semiconductor element 11 described later, the direction from the back surface 11b towards the surface 11a is designated as "up," and the opposite direction as "down," and these directions are indicated by arrows. Figure 3 In order to facilitate understanding of the configuration relationship of the rewiring 132 and 133 in the redistribution layer 13 described later, dashed lines are used to represent the outer contour of a portion of the constituent elements covered by the insulating layer 131 in the semiconductor device 1. Furthermore, in Figure 3 In order to easily understand the arrangement of the first rewiring 132 relative to the semiconductor element 11, the outer contour of the semiconductor element 11 is represented by a double-dotted line. Figure 4 In order to facilitate observation and understanding, although not representing a cross-section, the external exposed layers 135 and 136, which will be described later, are shaded.

[0055] 〔structure〕

[0056] The semiconductor device 1 in this embodiment is, for example, such as Figure 1As shown, the device includes a semiconductor device 11 having electrode pads 111, 112 and a terminal structure 113 on its surface 11a, a sealing element 12 covering the surrounding area, and a redistribution layer 13 connected to the electrode pads 111, 112. The redistribution layer 13 has a first redistribution 132 that covers part of the surface 11a of the semiconductor device 11 and the sealing element 12 and is electrically independent of the electrode pads 111, 112, and a second redistribution 133 and a third redistribution 134 connected to the electrode pads 111, 112. One end of the second redistribution 133 is connected to the second electrode pad 112, and the other end extends to the outside of the outer contour of the semiconductor device 11. That is, the semiconductor device 1 is a fan-out package structure in which the redistribution layer 13 extends to the outside of the outer contour of the semiconductor device 11 as part of the redistribution.

[0057] Semiconductor element 11, for example, has a first electrode pad 111 and a plurality of second electrode pads 112 made of a metal material such as Cu (copper) on its surface 11a, a terminal structure portion 113, and an upper insulating film 114 covering the terminal structure portion 113 and a portion of the surface 11a. Semiconductor element 11 is, for example, a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), manufactured using known semiconductor processes. Semiconductor element 11 may also have, for example, a third electrode pad (not shown) formed on its back side 11b, and this third electrode pad can be connected to other components via a bonding member made of solder or the like.

[0058] The first electrode pad 111 and the third electrode pad (not shown) are, for example, a pair of electrodes constituting the emitter electrode and the collector electrode, forming a current path in the direction connecting the surface 11a and the back surface 11b of the semiconductor element 11. At least one of the plurality of second electrode pads 112 is used as a gate electrode to control the on / off state of the current between the first electrode pad 111 and the third electrode pad. The first electrode pad 111 is as follows: Figure 1 As shown, it is connected to the third rewiring 134. Multiple second electrode pads 112 are respectively connected to the second rewiring 133. The portion of the semiconductor element 11 other than the back surface 11b is covered by the mounting hardware 12.

[0059] The terminal structure 113 is a portion formed to maintain the withstand voltage of the semiconductor element 11. For example, it is formed near the outer contour of the surface 11a of the semiconductor element 11 and is formed into a ring that surrounds a predetermined area including the first electrode pad 111. The terminal structure 113 can be made into any structure that can improve the withstand voltage of the semiconductor element 11 by mitigating the electric field through a protective ring, a Resurf (short for Reduced Surface Field), etc., and is formed by a known semiconductor process.

[0060] The insulating film 114 on the component is made of any insulating material such as polyimide, and is formed in such a way that it covers a predetermined area containing the terminal structure portion 113.

[0061] Encapsulation 12 such Figure 1 As shown, the component covering the side 11c of the semiconductor element 11 that connects the surface 11a and the back surface 11b is made of, for example, any insulating resin material such as epoxy resin. Viewed from the normal direction of the surface 11a of the semiconductor element 11, the outer contour of the encapsulator 12 is further outward than the outer contour of the semiconductor element 11. In other words, the shape of the encapsulator 12 is larger than the shape of the semiconductor element 11. For example, the encapsulator 12 is configured such that one side 12a located on the same side as the surface 11a of the semiconductor element 11 forms a single surface together with the surface 11a of the semiconductor element 11. On the other hand, the other side 12b of the encapsulator 12 opposite to one side 12a, together with the back surface 11b of the semiconductor element 11, constitutes the back surface 1b of the semiconductor device 1.

[0062] The redistribution layer 13 has an insulating layer 131 covering a portion of the semiconductor element 11 and the package 12, a first redistribution 132 electrically independent of the electrode pads 111 and 112, and a second redistribution 133 and a third redistribution 134 connected to the electrode pads 111 or 112. The redistribution layer 13 is formed, for example, by a known redistribution forming technique.

[0063] Furthermore, regarding the redistribution layer 13, it is permissible for at least a portion of the first redistribution layer 132 to be disposed between the second redistribution layer 133 and the boundary portion, with the boundary portion being the side 11c of the semiconductor element 11 and the encapsulator 12. It is not limited to this. Figure 1 The wiring example shown is shown. For example, the rewiring layer 13 can also be a multilayer wiring structure with multiple insulating films and rewiring layers stacked together, which can be modified as appropriate.

[0064] Insulating layer 131, for example, Figure 1 As shown, a multilayer structure is formed by stacking a first layer 1311, a second layer 1312, and a third layer 1313, all made of any insulating material such as polyimide. The insulating layer 131 is formed, for example, through multiple film deposition processes and a patterning process performed by photolithography. The insulating layer 131 has a predetermined pattern shape that covers the second rewiring 133 connected to the second electrode pad 112 and the third rewiring 134 connected to the first electrode pad 111, while exposing a portion of these rewirings.

[0065] Additionally, insulating layer 131, for example, Figure 2As shown, from the viewpoint of ensuring insulation, it is preferable that the thickness t1 of the portion of the first layer 1311 located below the first rewiring 132 is greater than the thickness t2 of the portion of the second layer 1312 located above the first rewiring 132.

[0066] The redistribution wiring 132-134 is, for example, composed of conductive metallic materials with Cu, Al (aluminum), Ti (titanium), Au (gold), Ag (silver), Pd (palladium), W (tungsten), Ni (nickel), Zn (zinc), Pb (lead), etc. The redistribution wiring 132-134 is formed, for example, by electroplating or non-electroplating.

[0067] Furthermore, the rewiring 132-134 can be defined by the boundary between the side 11c of the semiconductor element 11 and the boundary of the package 12, and the first rewiring 132 can be positioned between the boundary and a portion of the second rewiring 133 as described later; it is not limited to this. Figure 1 The wiring pattern shown is illustrated. For example, the second rewiring 133 can also be a multi-layer structure. In this case, the dimensions and thicknesses of the rewirings 132 and 134 can be appropriately changed according to the wiring pattern of the second rewiring 133. Thus, the wiring patterns, dimensions, and thicknesses of the rewirings 132 to 134 can be appropriately changed as long as the configuration relationship described later is satisfied. Furthermore, in this specification, for the sake of convenience, the rewirings formed in different locations are referred to as "first rewiring 132", "second rewiring 133", and "third rewiring 134", respectively, and this does not limit the total number of rewirings and insulating layers formed in the rewiring layer 13.

[0068] To prevent peeling from extending at the boundary between the side 11c of the semiconductor element 11 and the encapsulator 12, and in the event that a crack occurs in the portion of the insulating layer 131 located at this boundary, leading to a second rewiring 133, a first rewiring 132 is provided. The first rewiring 132 is, for example, as shown in... Figure 1 As shown, at least a portion is disposed on the boundary between the side 11c of the semiconductor element 11 and the package 12, and this boundary is between the second rewiring 133. For example, the first rewiring 132 is preferably as follows: Figure 3 As shown, it is made into a frame shape and configured to cover the outer contour of the semiconductor element 11 in a top view, that is, to completely cover the boundary between the side 11c of the semiconductor element 11 and the enclosure 12, but it is not limited to this. For example, in a top view, the first rewiring 132 may be a shape that only covers the edge of the edge forming the outer contour of the semiconductor element 11 that intersects with the second rewiring 133. In this case, it is also possible to suppress cracks in the insulating layer 131 that reach the second rewiring 133.

[0069] The first rewiring step 132 is as follows: Figure 1As shown, the first rewiring 132 is formed on the first layer 1311 of the insulating layer 131 and is configured to be separated from the rewiring 133, 134 by a portion of the insulating layer 131. That is, the first rewiring 132 is electrically independent of the rewiring 133, 134 and the electrode pads 111, 112.

[0070] In addition, at least a portion of the first rewiring 132 is disposed on the boundary between the side 11c of the semiconductor element 11 and the encapsulator 12, and is disposed between the boundary and the second rewiring 133. Its pattern shape can be appropriately changed according to the shape of the semiconductor element 11, etc.

[0071] One end of the second rewiring 133 is connected to the second electrode pad 112 of the semiconductor element 11, and the other end extends to the outer side of the outer contour of the semiconductor element 11. The second rewiring 133 is formed, for example, in the same number as the second electrode pad 112, and is disposed on the first rewiring 132, spaced apart from a portion of the insulating layer 131, extending across the first rewiring 132. At least a portion of the plurality of second rewiring 133 is exposed from the insulating layer 131 in a region outside the outer contour of the semiconductor element 11, and the exposed portion is covered by a first external exposure layer 135 made of any conductive material such as Ni or Au.

[0072] The third rewiring step 134 is as follows: Figure 1 As shown, one end is connected to the first electrode pad 111, and the other end, on the opposite side, is exposed from the sealing element 12. The portion of the third rewiring 134 exposed from the insulating layer 131 is covered by a second external exposure layer 136 made of any conductive material such as Au.

[0073] External exposed layers 135, 136, for example Figure 4 As shown, the exposed portions of the outer layers 131 function as external electrodes that can be connected to the first electrode pad 111 and the second electrode pad 112 from the outside. The outer exposed layers 135 and 136 are electrode portions exposed to the outside in place of the first electrode pad 111 or the second electrode pad 112, and may also be referred to as the "first external electrode" and the "second external electrode", respectively.

[0074] The first external exposed layer 135 is disposed at a distance from the second external exposed layer 136 electrically connected to the first electrode pad 111, and its shape and planar dimensions are smaller than those of the second external exposed layer 136. Multiple first external exposed layers 135 are... Figure 4 In the examples, they are set to have the same shape and planar dimensions and are configured equally, but it is not limited to this. They can also be set to have different shapes and planar dimensions, or they can be configured unevenly.

[0075] In addition, the external exposed layers 135 and 136 are structures that are exposed outside the redistribution layer 13 and can be used for connection with the outside. They can be plating layers made of Ni, Au, etc., or bumps made of solder, etc.

[0076] The above describes the basic structure of the semiconductor device 1 according to this embodiment. The semiconductor device 1 has a fan-out package structure, meaning that even if peeling occurs between the sidewall 11c of the semiconductor element 11 and the sealing member 12, and a crack is generated in the insulating layer 131 due to this peeling, the crack is suppressed by the first redistribution 132. Therefore, compared to conventional fan-out package semiconductor devices, the propagation of cracks in the insulating layer 131 towards the second redistribution 133, which extends from the inner side of the outer contour of the semiconductor element 11 to the outer side, is suppressed, ensuring the insulation of the second redistribution 133. Details will be described later.

[0077] [Manufacturing Method]

[0078] Next, refer to Figures 5A to 5L An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described.

[0079] First, a semiconductor element 11 is prepared, having a first electrode pad 111, a second electrode pad 112, a terminal structure portion 113, and an insulating film 114 covering the terminal structure portion 113 on its surface 11a. Furthermore, for example, an arbitrary support substrate 200 is prepared, having an adhesive sheet (not shown) with high adhesion to Si (silicon) on its surface. And, as... Figure 5A As shown, the surface 11a of the semiconductor element 11 is attached to the support substrate 200 to temporarily fix the semiconductor element 11.

[0080] Next, a mold (not shown) is prepared, and the semiconductor element 11, temporarily fixed to the support substrate 200, is covered with a resin material such as epoxy resin by compression molding or the like. This is then cured by heating or the like, thereby forming a sealant 12 covering the back surface 11b and side surface 11c of the semiconductor element 11. Then, for example, by heat treatment or the like, the semiconductor element 11 covered by the sealant 12 is peeled off from the support substrate 200. Thus, the semiconductor element 11 is... Figure 5B As shown, the back side 11b and side side 11c are covered by the sealing fastener 12, and the surface 11a side is exposed from the sealing fastener 12.

[0081] Next, for example, a solution containing a resin material such as polyimide is applied by spin coating and then dried. Figure 5CAs shown, a first layer 1311, constituting a part of the insulating layer 131, is formed. For example, by patterning using photolithography or the like, the first layer 1311 is formed into a predetermined pattern shape that exposes at least a portion of the first electrode pad 111 and the second electrode pad 112 in the semiconductor element 11 and covers one side 12a of the encapsulator 12. Next, for example, by vacuum deposition using sputtering or the like, a seed layer (not shown) made of a conductive material such as Cu is formed, covering the first layer 1311 and the exposed portion of the semiconductor element 11. Then, for example, as... Figure 5D As shown, through the same process as the first layer 1311, a resist film R1 with a predetermined pattern shape is formed, which is made of any insulating material and partially exposes a seed layer (not shown). Thus, a portion of the first layer 1311 in the seed layer (not shown), and at least the region located at the boundary between the side 11c of the semiconductor element 11 and the sealant 12, becomes exposed from the resist film R1.

[0082] Then, as Figure 5E As shown, for example, a first rewiring 132 made of a conductive material such as Cu is formed by electroplating. The first rewiring 132 is above the first layer 1311 and is a pattern shape at least partly disposed on the boundary between the side 11c of the semiconductor element 11 and the encapsulator 12.

[0083] Next, for example, Figure 5F As shown, the resist film R1 is removed using a stripping solution or the like, exposing a seed layer (not shown). Then, the portion of the seed layer (not shown) exposed by the removal of the resist film R1 is removed using an etching solution or the like. As a result, the seed layer (not shown) is removed except for the portion covered by the first redistribution 132, thereby exposing a portion of the first layer 1311 and the electrode pads 111 and 112 to the outside.

[0084] Next, for example, Figure 5G As shown, a second layer 1312, made of any insulating resin material such as polyimide and formed into a predetermined pattern shape, is formed through the same process as the first layer 1311. The second layer 1312 is formed into a pattern shape that exposes at least a portion of the electrode pads 111, 112 and covers other areas including the first rewiring 132.

[0085] Next, a seed layer (not shown) is formed by vacuum deposition, such as by sputtering, to cover the exposed portions of the second layer 1312 and the electrode pads 111, 112, and is made of a conductive material such as Cu. Then, for example, as... Figure 5HAs shown, a second resist film R2, made of any insulating material and covering a portion of the second layer 1312, is formed using the same process as the resist film R1, and is shaped according to a predetermined pattern. At this time, a portion of the second layer 1312 connected to the second electrode pad 112, as well as the electrode pads 111 and 112, are exposed from the second resist film R2.

[0086] Then, as Figure 5I As shown, for example, by electroplating, a second rewiring 133 is formed that covers a portion of the first layer 1311 and is connected to the second electrode pad 112, and a third rewiring 134 covers at least a portion of the first electrode pad 111. The rewiring 133 and 134 are made of a conductive metallic material such as Cu, for example, in the case of electroplating.

[0087] Next, as Figure 5J As shown, for example, the second resist film R2 is removed using a stripping solution or the like, exposing a seed layer (not shown). Then, the portion of the seed layer (not shown) exposed by the removal of the second resist film R2 is removed using an etching solution or the like. As a result, the seed layer (not shown) is removed except for the portion covered by the redistribution lines 133 and 134, and a portion of the second layer 1312 is exposed to the outside.

[0088] Next, for example, Figure 5K As shown, a third layer 1313, made of any insulating resin material such as polyimide and formed into a predetermined pattern shape, is formed through the same process as the first layer 1311. The third layer 1313 is formed into a pattern shape that exposes at least a portion of the rewiring 133, 134 and covers the other areas.

[0089] Next, as Figure 5L As shown, the surface covering the back surface 11b of the semiconductor element 11 is removed from the encapsulator 12, exposing the back surface 11b of the semiconductor element 11 from the encapsulator 12. This forms another surface 12b on the encapsulator 12, which, together with the back surface 11b of the semiconductor element 11 on the opposite side of the surface 11a side of the semiconductor element 11, forms the back surface 1b of the semiconductor device 1. Then, a third electrode pad (not shown) covering the area including the back surface 11b of the semiconductor element 11 is formed by any vacuum deposition method, such as sputtering.

[0090] Furthermore, the removal of the sealant 12 can be performed by grinding with a grinding tool (not shown), or by any other method such as cutting, etching, or polishing; there are no particular limitations. Additionally, the third electrode pad (not shown) can be formed to cover not only the back side 11b of the semiconductor element 11, but also part or all of the other side 12b of the sealant 12.

[0091] Finally, for example, by means of non-electroplation, a first external exposed layer 135 is formed that covers the portion of the second rewiring 133 exposed from the third layer 1313, and a second external exposed layer 136 is formed that covers at least a portion of the third rewiring 134.

[0092] For example, the semiconductor device 1 of this embodiment can be manufactured through the above-described process. Furthermore, the above description uses the case of manufacturing one semiconductor device 1 using one semiconductor element 11 as a representative example, but it is not limited to this; of course, multiple semiconductor devices 1 can also be manufactured using a semiconductor substrate having multiple semiconductor elements 11. In the case of manufacturing multiple semiconductor devices 1 together, the manufacturing processes are basically the same except that a dicing process is added after the formation of the external exposed layers 135 and 136.

[0093] 〔Effect〕

[0094] Next, refer to Figures 6A to 6C This illustrates the effect of the first rewiring 132, which is disposed on the boundary between the side 11c of the semiconductor element 11 and the enclosure 12.

[0095] in addition, Figures 6A to 6C This is an enlarged cross-sectional view, showing the boundary between the semiconductor element and the package 12 covering its sides, as well as a portion of the rewiring layer with rewiring located on that boundary. Furthermore, in Figure 6B , Figure 6C In order to make it easier to understand the electrical connection between the rewiring 305 and the back surface 11b of the semiconductor element 11, the part where the electrical connection occurs is indicated by a thick line for convenience.

[0096] First, as a comparative example, for example, such as Figure 6A The semiconductor device 300 shown is a fan-out package structure having a semiconductor element 301, a package 302 and a redistribution layer 303, and having no portion in the redistribution layer 303 corresponding to the first redistribution 132.

[0097] Semiconductor device 300 is a fan-out package structure in which the back side 301b of semiconductor element 301 is exposed from the packager 302, and mainly the side 301c is covered by the packager 302. It has a redistribution layer 303 that covers the surface 301a of semiconductor element 301 and a portion of the packager 302. Semiconductor device 300 is, for example, as shown in the example... Figure 6A As shown, a terminal structure 3011 for pressure-resistant holding and an insulating film 3012 covering it are provided near the outer contour of the surface 301a, and the back surface 301b of the semiconductor element 301 is exposed from the sealing device 302. The sealing device 302 contacts the side surface 301c of the semiconductor element 301, and the thinner the semiconductor element 301, the smaller the contact area with the side surface 301c.

[0098] Semiconductor device 300 may experience interface delamination between side surface 301c of semiconductor element 301 and encapsulator 302, for example, due to stress caused by the difference in the coefficients of linear expansion between semiconductor element 301 and encapsulator 302, from the back surface 301b towards surface 301a. This interface delamination may occur, for example, as... Figure 6B As indicated by the hollow arrow, if the crack extends further towards surface 301a, it causes cracks to form in the insulating layer 304 within the redistribution layer 303. If the cracks in the insulating layer 304 further propagate, they reach the redistribution 305 positioned at the boundary between the side surface 301c of the semiconductor element 301 and the encapsulator 302, where insulation cannot be guaranteed due to the cracks in the insulating layer 304. Specifically, if the side surface 301c of the semiconductor element 301 is not in close contact with the encapsulator 302, the redistribution 305 will be electrically connected to the back surface 301b along the surface and side surface 301c of the cracks in the insulating layer 304. That is, insulation of the redistribution 305 cannot be guaranteed.

[0099] In contrast, the semiconductor device 1 of this embodiment is constructed such that a portion of a first rewiring 132, made of a material harder than the insulating layer 131, is disposed at the boundary between the side surface 11c of the semiconductor element 11 and the encapsulator 12, and between this boundary and the second rewiring 133. Therefore, even if peeling occurs between the side surface 11c of the semiconductor element 11 and the encapsulator 12, resulting in a crack in the portion of the insulating layer 131 located at their boundary, this crack will, for example, Figure 6C As shown, the process ends at the first rewiring 132. Therefore, even if a crack occurs in the insulating layer 131, the portion that is at the same potential as the back surface 11b of the semiconductor element 11 stops at the first rewiring 132. Thus, due to the presence of the first rewiring 132, the crack in the insulating layer 131 is prevented from extending to the second rewiring 133. As a result, the insulation of the second rewiring 133 can be ensured without a short circuit between the second rewiring 133 and the back surface 11b of the semiconductor element 11.

[0100] [Structure example of a semiconductor module]

[0101] Next, refer to Figure 7 An example of a semiconductor module using the semiconductor device 1 of this embodiment will be described. Figure 7 In the diagram, dashed lines represent the wiring portions of the second heat sink 3 that connect to the outside in other cross sections, as described later.

[0102] Semiconductor device 1, for example, Figure 7 As shown, if applied to a semiconductor module with a two-sided heat dissipation structure, it is preferable to achieve both thinness and high heat dissipation of the semiconductor module. Furthermore, this specification describes the application of semiconductor device 1 to a semiconductor module with a two-sided heat dissipation structure as a representative example, but is not limited to this application example.

[0103] Semiconductor modules such as Figure 7 As shown, the device includes a semiconductor device 1, a first heat sink 2, a second heat sink 3, a lead frame 4, a connector 5, and a sealing element 6. The semiconductor module sandwiches the semiconductor device 1 and has two heat sinks 2 and 3 arranged opposite each other, forming a two-sided heat dissipation structure that releases the heat generated by the semiconductor device 1 to the outside from both sides through these heat sinks 2 and 3.

[0104] Semiconductor device 1, for example, Figure 7 As shown, the back side 1b is connected to the first heat sink 2 via a connector 5, and the second external exposed layer 136 covering the third redistribution 134 in the surface 1a side is connected to the second heat sink 3 via the connector 5. The semiconductor device 1 is configured, for example, such that the entire area of ​​the back side 1b is contained within the outer contour of the upper surface 2a of the first heat sink 2. Let one surface of the second heat sink 3 exposed to the outside be one surface 3a, and let the other surface of the second heat sink 3 facing the semiconductor device 1 be another surface 3b. In the semiconductor device 1, for example, at least the portion of the second redistribution 133 covered by the first external exposed layer 135 is positioned outside the outer contour of the other surface 3b of the second heat sink 3. The second redistribution 133 of the semiconductor device 1 is electrically connected to the lead frame 4 via the connector 5 in the region outside the outer contour of the second heat sink 3.

[0105] First heat sink 2 Figure 7As shown, it is a plate-shaped structure having an upper surface 2a and a lower surface 2b in a surface-to-back relationship, and is made of a metallic material such as Cu or Fe. A first heat sink 2 mounts a semiconductor device 1 on the upper surface 2a via a solder joint 5, and the lower surface 2b is exposed from the sealing member 6. The first heat sink 2 serves as, for example, a current path for energizing the semiconductor device 1, with a portion of the upper surface 2a extending to the outside of the sealing member 6. That is, in this embodiment, the first heat sink 2 serves two functions: a heat dissipation component and wiring. Furthermore, the first heat sink 2 can be referred to as a "first heat dissipation component".

[0106] 2nd heat sink 3rd Figure 7 As shown, it is a plate-shaped structure with one side 3a and the other side 3b positioned on opposite sides of the semiconductor device 1, and is made of the same material as the first heat sink 2. In the second heat sink 3, the other side 3b is disposed opposite to a portion of the upper surface 2a of the semiconductor device 1, while one side 3a is exposed from the sealing member 6. The second heat sink 3 is electrically connected to the third rewiring 134 via the connector 5, and like the first heat sink 2, it serves as a current path for the semiconductor element 11. Furthermore, in relation to... Figure 7 In different cross-sections, a portion of the other side 3b of the second heat sink 3 extends to the outside of the sealing member 6, serving as both a heat dissipation component and an electrical wiring component. Additionally, the second heat sink 3 can be referred to as the "second heat dissipation component".

[0107] Lead frame 4 is, for example, a conductive component made of metallic materials such as Cu or Fe. Lead frame 4 is, for example, as... Figure 7 As shown, the first external exposed layer 135, which covers a portion of the second redistribution 133, is electrically connected to the semiconductor device 1 via the bonding member 5 in an exposed area outside the outer contour of the second heat sink 3. The lead frame 4, for example, has a plurality of leads, the same number as the second electrode pads 112, which are electrically connected to the second redistribution 133.

[0108] Furthermore, regarding these leads, for example, before the sealing member 6 is formed, multiple adjacent leads are connected by tie bars (not shown), and after the sealing member 6 is formed, the tie bars are removed by stamping or the like, thus separating them. Alternatively, the lead frame 4 may also be constructed as the same component as the second heat sink 3, and connected by tie bars (not shown) before the sealing member 6 is formed. In this case, the lead frame 4 is also separated from the second heat sink 3 by removing the tie bars by stamping or the like after the sealing member 6 is formed.

[0109] The connector 5 is a connector that joins the components of the semiconductor module together. For electrical connection, conductive materials such as solder or conductive resin can be used.

[0110] The sealing element 6 is made of, for example, a thermosetting resin such as epoxy resin, such as... Figure 7 As shown, the semiconductor device 1, a portion of the heat sinks 2 and 3, a portion of the lead frame 4, and the connector 5 are covered. When the sealing member 12, which constitutes a part of the semiconductor device 1, is designated as the "first sealing member", the sealing member 6 can be referred to as the "second sealing member" that covers the semiconductor device 1.

[0111] This semiconductor module, for example, has a structure in which the second rewiring 133 of the semiconductor device 1 is joined to the lead frame 4 by a connector 5 in a region outside the outer contour of the second heat sink 3. Therefore, unlike conventional semiconductor modules disclosed in Japanese Patent Application Publication No. 2001-156225, it does not require a wire connection between the semiconductor device 1 and the lead frame 4. Furthermore, since no wire is used, it is not necessary to place a heat sink between the semiconductor device 1 and the second heat sink 3 to prevent contact between the wire and the second heat sink 3. As a result, the thickness of the semiconductor module can be reduced accordingly, eliminating the thermal resistance of the heat sink and thus reducing the thermal resistance from the semiconductor device 1 to the second heat sink 3.

[0112] In this way, the semiconductor module using semiconductor device 1 does not require heat sinks and wiring connections between components, resulting in a thinner and lower thermal resistance structure compared to the past. Furthermore, by using semiconductor device 1, the insulation of the second rewiring 152 of semiconductor device 1 is ensured by the first rewiring 132 disposed on the boundary between the side 11c of semiconductor element 11 and the sealing member 12, the reliability of semiconductor module is improved.

[0113] [First variation of a semiconductor module]

[0114] Both the first and second heat dissipation components are made of heat sinks, but are not limited to this. For example, the first and second heat dissipation components could also be... Figure 8 The device shown is composed of a thermally conductive insulating substrate 7 and heat sinks 2 and 3, with the thermally conductive insulating substrate 7 bonded to the semiconductor device 1.

[0115] The thermally conductive insulating substrate 7 includes a conductive portion 71, an insulating portion 72, and a thermally conductive portion 73, which are stacked in this order, and the conductive portion 71 and the thermally conductive portion 73 are electrically independent by being separated by the insulating portion 72. In the thermally conductive insulating substrate 7, for example, the conductive portion 71 is mainly made of a metallic material such as Cu, the insulating portion 72 is mainly made of an insulating material such as Al2O3 (alumina) or AlN (aluminum nitride), and the thermally conductive portion 73 is mainly made of a metallic material such as Cu. The thermally conductive portion 73 of the thermally conductive insulating substrate 7 is bonded to the first heat sink 2 or the second heat sink 3 via a bonding member such as solder (not shown). As the thermally conductive insulating substrate 7, for example, a DBC (short for Direct Bonded Copper) substrate can be used. Regarding the conductive portion 71 in the thermally conductive insulating substrate 7, for example, a portion is used as wiring for connection to an external power source, or connected to other wiring such as the lead frame 4, enabling electrical interaction with the semiconductor element 11.

[0116] In this case, the semiconductor module insulates the semiconductor device 1 from the heat sinks 2 and 3 via the thermally conductive insulating substrate 7, resulting in a structure that eliminates the need for an additional insulating layer between the heat sinks 2 and 3 and external coolers when connecting them to such devices. Therefore, Figure 8 The semiconductor module shown can also improve reliability when connected to external coolers, etc.

[0117] In addition, the first and second heat dissipation components can be made of thermally conductive insulating substrate 7 in part, as described above, or they can be made entirely of thermally conductive insulating substrate 7.

[0118] [Second variation of the semiconductor module]

[0119] In the above example, a structure is shown in which the first external exposed layer 135 in the semiconductor device 1 is disposed outside the outer contour of the second heat sink 3, and the lead frame 4 is directly bonded to the first external exposed layer 135 via the connector 5, but is not limited to this connection structure.

[0120] For example, if the portion of the second heat dissipation component connected to the semiconductor device 1 is made of a thermally conductive insulating substrate 7, it can also be like this. Figure 9 As shown, the entire area of ​​the semiconductor device 1 is disposed inside the outer contour of the second heat dissipation member. In this case, the conductive portion 71 has a first connecting portion 711 connected to the second external exposed layer 136 of the semiconductor device 1, and a second connecting portion 712 connected to the first external exposed layer 135, which are electrically independent. Furthermore, a portion of the second connecting portion 712 of the conductive portion 71 is disposed outside the outer contour of the semiconductor device 1, and this portion is connected to the lead frame 4 via the connector 5.

[0121] With this connection structure, the second rewiring 133 of the semiconductor device 1 is electrically connected to the lead frame 4 in the semiconductor module, and there is no heat sink between the second heat dissipation component and the semiconductor device 1, resulting in a structure that achieves thinner profile and lower thermal resistance compared to the past.

[0122] According to this embodiment, even if a crack is generated in the insulating layer 131 due to the interface peeling between the side 11c of the semiconductor element 11 and the encapsulator 12, the propagation of the crack is suppressed by the first rewiring 132 disposed on the interface. Therefore, the crack in the insulating layer 131 will not extend to the second rewiring 133 disposed on the first rewiring 132, and the short circuit between the second rewiring 133 and the back surface 11b of the semiconductor element 11 is suppressed, thus ensuring the insulation of the second rewiring 133.

[0123] Furthermore, by using the semiconductor device 1 with this fan-out package structure to form a semiconductor module, it is also possible to make a structure in which no heat sink is provided between the surface 1a of the semiconductor device 1 and the heat dissipation component, making it easier to achieve thinner profiles and lower thermal resistance.

[0124] (A variation of the first embodiment)

[0125] Semiconductor element 11 can also be, for example, as Figure 10 As shown, a protrusion 11ca is formed on the side 11c. The protrusion 11ca improves the adhesion to the sealant 12 through the anchoring effect compared to other parts of the side 11c. Therefore, even if peeling occurs from the back side 1b of the semiconductor device 1 between the side 11c of the semiconductor element 11 and the sealant 12, the propagation of peeling at the protrusion 11ca is suppressed, and cracks in the insulating layer 131 can be suppressed.

[0126] The uneven portion 11ca can be formed, for example, during the preparation of the semiconductor element 11 by scribing the semiconductor substrate with a 2000-count cutting tool. Alternatively, the above objective can be achieved by forming fine unevenness on the entire cross-section using laser scribing or the like.

[0127] According to this variation, the peeling propagation between the side 11c of the semiconductor element 11 and the sealing member 12 is suppressed, which can further improve the effect of the first embodiment described above.

[0128] (Second Implementation)

[0129] Reference Figure 11 The semiconductor device 1 of the second embodiment will be described.

[0130] The semiconductor device 1 in this embodiment is, for example, such as Figure 11As shown, the first rewiring 132 covers the entire area of ​​the terminal structure 113, which differs from the first embodiment described above. In this embodiment, this difference will be the main focus of the explanation.

[0131] In this embodiment, the first rewiring 132 is a pattern shape that covers the terminal structure 113 except for the boundary between the side surface 11c of the semiconductor element 11 and the encapsulator 12. Specifically, the first rewiring 132 is disposed on the terminal structure and extends across the boundary between the side surface 11c of the semiconductor element 11 and the encapsulator 12 to the encapsulator 12. This is to suppress the influence of external charges such as moisture in the air on the electric field distribution of the terminal structure 113 and to suppress the voltage drop of the semiconductor element 11.

[0132] Next, regarding the effect of suppressing voltage drop by covering the terminal structure 113 with the first rewiring 132, refer to, for example... Figure 12 The comparative example shown does not have the first rewiring 132.

[0133] If the semiconductor device 1 is exposed to external gases for an extended period, moisture from the air and other substances may adhere to its outer surface, causing external charges to penetrate from the outer surface of the insulating layer 131 into the interior. The inventors of this invention have discovered that if such external charges reach the terminal structure 113, the electric field distribution within the terminal structure 113 is disrupted, resulting in a drop in withstand voltage. This result was obtained by the inventors of this invention using known simulation software to calculate the change in withstand voltage characteristics caused by external charges in a comparative example where the terminal structure 113 does not have the first rewiring 132 and an embodiment where the terminal structure 113 is covered by the first rewiring 132.

[0134] Specifically, Figure 12 The structure shown is a comparative example of a semiconductor device in which the terminal structure portion 113 is a protective ring, the insulating layer 131 is made of polyimide, and the first rewiring 132 covering the terminal structure portion 113 is not present. Furthermore, the insulating layer 131 is covered by an oxide film. Additionally, as a structure corresponding to the semiconductor device 1 of this embodiment, an example is a structure in which the terminal structure portion 113 is a protective ring, the insulating layer 131 is made of polyimide, and the first rewiring 132 covering the terminal structure portion 113 is disposed within the insulating layer 131.

[0135] In addition, Figure 12 The structure shown, with an insulating layer 131 thickness of 10 μm, is used as Comparative Example 1. A structure with an insulating layer 131 thickness of 20 μm is used as Comparative Example 2. Figure 13 The structure shown, in which the insulating layer 131 has a thickness of 20 μm, is used as an example.

[0136] Furthermore, regarding the simulation, for Comparative Examples 1 and 2 and the embodiment, the change in withstand voltage when an external charge is applied to the entire interface between the oxide film and the insulating layer 131 was calculated. The applied electric field in this simulation was set to -5 × 10⁻⁵. 12 ~1×10 13 C / cm 2 The range.

[0137] The simulation results are represented in Figure 14 middle.

[0138] In Comparative Example 1, at -2×10 12 ~5×10 12 C / cm 2 Within the range, the withstand voltage remains above 1900V, but at -5×10 12 C / cm 2 Withstand voltage below 900V, at 1×10 13 C / cm 2 The withstand voltage is below 1500V. This result shows that the withstand voltage decreases due to the change in the electric field distribution of the terminal structure 113 composed of the guard ring caused by the external charge.

[0139] In Comparative Example 2, at -2×10 12 ~5×10 12 C / cm 2 Within the range, the withstand voltage remains above 1900V, at 1×10 13 C / cm 2 The withstand voltage remains around 1800V, but at -5×10 12 C / cm 2 The withstand voltage is below 900V. In Comparative Example 2, the thickness of the insulating layer 131 made of polyimide was increased, thereby achieving a slight effect in maintaining the withstand voltage, but it was not sufficient.

[0140] In contrast, in the embodiment, at -5×10 12 ~1×10 13 C / cm 2 Throughout the entire range, the withstand voltage is above 1900V. This result indicates that by distributing the first rewiring 132 between the outer surface of the insulating layer 131 and the terminal structure 113, the intrusion of external charges into the insulating layer 131 is hindered by the first rewiring 132, and the withstand voltage drop is suppressed.

[0141] According to this embodiment, the first rewiring 132 is arranged on the terminal structure 113 to cover it, thereby also serving as a shielding layer against external charges, and becoming a semiconductor device 1 that can obtain the effect of voltage withstand in addition to the insulation guarantee of the second rewiring 133.

[0142] Furthermore, the first rewiring 132, which also functions as a shielding layer, can be formed in the same way as the second rewiring 133 and the third rewiring 134 during the rewiring formation process, so there is no need for layout changes of the semiconductor element 11. Therefore, it becomes a structure that suppresses voltage drop, while also suppressing the increase in manufacturing costs.

[0143] Furthermore, the above explanation cited the example of voltage drop caused by external charges due to the adhesion of moisture in the air. However, even without moisture in the air, if there are charges on the surface of the insulating layer, they will affect the electric field distribution of the terminal structure 113, creating electric field concentration points and causing voltage drop. Even in such cases, the first rewiring 132 covering the terminal structure 113 functions as a shielding layer, suppressing the generation of electric field concentration points caused by charges on the surface of the insulating layer, thus achieving voltage suppression.

[0144] (First variation of the second embodiment)

[0145] The first rewiring step 132 can also be, for example, as follows: Figure 15 As shown, the structure ensures that the insulation of the second rewiring 133 is independent of the structure that suppresses the arrival of external charges to the terminal structure 113.

[0146] Specifically, the first rewiring 132 may have a boundary cover 1321 disposed on the boundary between the side 11c of the semiconductor element 11 and the encapsulator 12, and a terminal cover 1322 disposed on the terminal structure 113 to cover it. That is, in the first rewiring 132, the boundary cover 1321 serves to ensure the insulation of the second rewiring 133, and the terminal cover 1322 serves to suppress the voltage drop.

[0147] This modified example also achieves the effects of the second embodiment described above in the semiconductor device 1.

[0148] (Second variation of the second embodiment)

[0149] The first rewiring step 132 can also be, for example, as follows: Figure 16As shown, a portion is connected to the external exposed portion 137 exposed from the insulating layer 131. Like the external exposed layers 135 and 136, the external exposed portion 137 is made of any conductive material such as Au or Ni, and can be formed by electroplating or non-electroplating. For example... Figure 17A As shown, the first rewiring 132 is exposed from the second layer 1312 and the third layer 1313, and the externally exposed portion 137 is stacked on the exposed portion to become externally exposed. Therefore, even if the crack in the insulating layer 131 caused by the interface peeling between the side 11c of the semiconductor element 11 and the sealant 12 reaches the first rewiring 132, the potential of the first rewiring 132 can be adjusted to a predetermined range, and the signal transmission in the second rewiring 133 can be stabilized.

[0150] Specifically, when a crack in the insulating layer 131 reaches the first rewiring 132, the first rewiring 132 becomes a potential that is the same as or at the same level as the potential of the back surface 1b of the semiconductor device 1. At this time, if the potential difference between the first rewiring 132 and the second rewiring 133 becomes a predetermined value or higher, the signal transmission of the second rewiring 133 may be blocked.

[0151] However, by connecting a portion of the first rewiring 132 to the external exposure portion 137 exposed from the insulating layer 131, even if a crack in the insulating layer 131 reaches the first rewiring 132, the potential of the first rewiring 132 can be adjusted via the external exposure portion 137. In this case, by adjusting the potential of the first rewiring 132 so that its potential difference with the second rewiring 133 is below a predetermined value, the obstruction to signal transmission in the second rewiring 133 is suppressed, and the signal transmission is stabilized.

[0152] Furthermore, the first rewiring 132 is not limited to the example described above, where it is disposed above the interface between the side 11c of the semiconductor element 11 and the encapsulator 12, separated by a portion of the insulating layer 131. For example, it could also be as follows: Figure 17B As shown, it is formed by directly covering the upper part of the interface. In this case, even if the first rewiring 132 becomes the same potential as the back surface 1b of the semiconductor device 1, the signal transmission of the second rewiring 133 can be made more stable because the distance from the second rewiring 133 is increased.

[0153] Furthermore, in this modified example, by adjusting the potential of the first rewiring 132, the influence of external charges on the terminal structure 113 can be mitigated, further suppressing the voltage drop. This is effective even without cracks in the insulation layer 131.

[0154] Furthermore, if an initial crack occurs in the insulating layer 131 of the manufactured semiconductor device 1, the occurrence of the initial crack can be confirmed by measuring the potential of the first rewiring 132 via the external exposure portion 137. Therefore, by conducting an initial inspection after manufacturing the semiconductor device 1, it is possible to confirm whether a crack has occurred in the insulating layer 131, and it is also possible to easily prevent the shipment of defective products.

[0155] According to this modified example, in addition to the effects of the second embodiment described above, it is also possible to stabilize the signal transmission of the second rewiring 133 even when the crack in the insulating layer 131 extends to the first rewiring 132. Furthermore, regardless of the presence or absence of a crack in the insulating layer 131, the potential adjustment of the first rewiring 132 mitigates the influence of external charges on the terminal structure 113, thereby suppressing voltage drop.

[0156] (Other implementation methods)

[0157] The present invention has been described with reference to embodiments, but it should be understood that the invention is not limited to these embodiments and constructions. The invention also includes various modifications and equivalent variations. In addition, various combinations and forms, and further, other combinations and forms containing only one element, or more or less thereof, also fall within the scope and spirit of the invention.

[0158] (1) For example, the first rewiring 132 may be a structure having a boundary cover 1321 and a terminal cover 1322, with a portion of the boundary cover 1321 connected to an external exposed portion 137 exposed from the insulating layer 131. In this case, the semiconductor element 11 may have a protrusion 11ca on the side 11c. Thus, the above embodiments can be appropriately combined within the possible range.

[0159] (2) In the first embodiment described above, an example was described in which the first redistribution 132 was disposed on the boundary between the side surface 11c of the semiconductor element 11 and the encapsulator 12, separated by a portion of the insulating layer 131, but this is not a limitation. For example, the first redistribution 132 may also abut against the surface 11a of the semiconductor element 11 or the insulating film 114 on the element, and similarly to the second variation of the second embodiment described above, it is formed to directly seal the boundary between the side surface 11c of the semiconductor element 11 and the encapsulator 12.

[0160] (3) In the first embodiment and its variations described above, the example of the semiconductor element 11 having a terminal structure 113 is used as a representative example, but the semiconductor element 11 may also have a structure without the terminal structure 113.

[0161] (4) In the first embodiment described above, an example was given of forming the third rewiring 134 through a process different from the first rewiring 132. However, the third rewiring 134 can also be formed through the same process as the first rewiring 132. For example, it can also be formed as follows: Figure 18A As shown, the pattern shape of the resist film R1 formed on the first layer 1311 is changed, such as... Figure 18B As shown, the first rewiring 132 and the third rewiring 134 are formed simultaneously by electroplating. This is also the case for the second embodiment and its variations described above.

[0162] Furthermore, semiconductor device 1 may also be, for example, as follows Figure 18C As shown, an electrode layer 138 is provided between the first electrode pad 111 and the third redistribution 134, and between the second electrode pad 112 and the second redistribution 133. In this case, when forming the first redistribution 132, after forming the electrode layer 138 on each of the electrode pads 111 and 112, the second redistribution 133 and the third redistribution 134 can be formed through the same process as in the first embodiment described above. This is also the case for the second embodiment and its variations described above.

Claims

1. A semiconductor device, which is a fan-out packaged semiconductor device, characterized in that, have: A semiconductor device having a first electrode pad and a second electrode pad on its surface; A sealing element, made of an insulating resin material, covers the side of the semiconductor element that connects the aforementioned surface and back surface; and A redistribution layer covers the aforementioned surface of the semiconductor element and a portion of the aforementioned packager; The aforementioned redistribution layer has: The insulating layer is made of insulating resin material; The first rewiring is at least partially disposed on the boundary between the aforementioned side of the semiconductor element and the aforementioned encapsulator. as well as The second rewiring is electrically connected to the second electrode pad and extends at least a portion of it across the first rewiring to the outside of the outer contour of the semiconductor element, and is electrically independent of the first rewiring.

2. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned semiconductor element has one or more of the aforementioned second electrode pads; The aforementioned redistribution layer has one or more of the aforementioned first redistribution layers, and also has a third redistribution layer that is electrically connected to the aforementioned first electrode pad and is partially exposed from the aforementioned insulating layer. A portion of the second rewiring is exposed from the insulation layer, and the portion exposed from the insulation layer is covered by the first outer exposed layer; The portion of the third rewiring exposed from the insulation layer is covered by the second outer exposed layer.

3. The semiconductor device as claimed in claim 2, characterized in that, The planar dimensions of the first external exposed layer and the second external exposed layer are different.

4. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned first rewiring is composed of a conductive material with one of Cu, Al, Ti, Au, Ag, Pd, W, Ni, Zn, and Pb as its main component.

5. The semiconductor device as claimed in claim 1, characterized in that, A portion of the aforementioned insulating layer is disposed between the aforementioned first rewiring and the aforementioned boundary.

6. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device has an annular terminal structure that surrounds the first electrode pad. The terminal structure is a portion for holding the first electrode pad under pressure and is disposed near the outer contour of the surface.

7. The semiconductor device as claimed in claim 6, characterized in that, The first rewiring configuration is located on the terminal structure and extends across the boundary to the area of ​​the sealing element.

8. The semiconductor device as claimed in claim 6, characterized in that, The first rewiring has a boundary covering portion that is disposed on the boundary and a terminal covering portion that is separate from the first rewiring and disposed on the terminal structure portion.

9. The semiconductor device as claimed in claim 1, characterized in that, A portion of the first rewiring described above is connected to the conductive external exposed portion that is exposed from the insulating layer described above.

10. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor element described above has a recessed or convex portion on the aforementioned side surface.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The aforementioned insulating layer consists of multiple layers composed of insulating materials. Let the layer located below the first rewiring in the above-mentioned insulating layer be the first layer, and let the layer covering the first rewiring in the above-mentioned insulating layer be the second layer; The thickness of the portion of the first layer located directly below the first rewiring is greater than the thickness of the portion of the second layer located above the first rewiring.

12. A semiconductor module, characterized in that, have: A semiconductor device includes a semiconductor element having a first electrode pad and a second electrode pad on its surface, a first sealing element made of an insulating resin material and covering a side surface of the semiconductor element that connects the surface and the back surface, and a redistribution layer having an insulating layer made of an insulating resin material, a first redistribution line at least partially disposed on the boundary between the side surface of the semiconductor element and the first sealing element, and a second redistribution line electrically connected to the second electrode pad, at least partially extending across the first redistribution line to the outside of the outer contour of the semiconductor element and electrically independent of the first redistribution line. The first heat dissipation component is connected via a connector to the back side of the semiconductor device exposed from the first sealing element. The second heat dissipation component is electrically connected to the first electrode pad in the semiconductor device via the aforementioned bonding member. The lead frame is electrically connected to the second rewiring in the semiconductor device via the aforementioned connector; and The second seal covers the semiconductor device, a portion of the first heat dissipation component, a portion of the second heat dissipation component, and a portion of the lead frame.

13. The semiconductor module as described in claim 12, characterized in that, A portion of the aforementioned semiconductor device is an exposed area located outside the outer contour of the aforementioned second heat dissipation component; The aforementioned lead frame is electrically connected to the aforementioned second rewiring via the aforementioned connector in the aforementioned exposed area.

14. The semiconductor module as described in claim 12, characterized in that, The lower surface of the first heat dissipation component, opposite to the side facing the semiconductor device, is exposed from the second sealing component. The opposite side of the second heat dissipation component to the semiconductor device is exposed from the second sealing component.

15. The semiconductor module as described in any one of claims 12 to 14, characterized in that, The first heat dissipation component and part or all of the second heat dissipation component are thermally conductive and insulating substrates in which conductive parts, insulating parts and thermally conductive parts are stacked in sequence, and the conductive parts are connected to the semiconductor device.

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