Fourier series detection device for weak periodic signal in strong noise background based on FPGA

Abstract

The application discloses a Fourier series detection device for weak periodic signals under strong noise based on FPGA. The device comprises a program-controlled amplification module, an AD acquisition module, an FPGA Fourier detection module, an STM32 control module and an OLED display module. The program-controlled amplification module amplifies the amplitude of the periodic signals carrying strong noise. The AD acquisition module digitizes the amplified signals. The FPGA Fourier series detection module filters the strong noise and detects the Fourier series of the acquired digital signals. The STM32 controls the program-controlled amplification multiple, the AD acquisition rate, the OLED display and the communication with the FPGA. The OLED displays the Fourier series of the signals. The application has the advantages of accurate Fourier series detection, real-time Fourier series display and the like. The application can detect the spectrum of weak periodic signals under extremely low signal-to-noise ratio and can be applied to the fields of photoelectric signal detection such as Fourier transform infrared spectrum detection and Fourier transform terahertz spectrum detection.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital signal processing, and particularly relates to a Fourier series detection device for weak periodic signals under strong noise based on FPGA. BACKGROUND

[0002] Weak signals exist everywhere in nature, and how to detect a harmonic component from a periodic signal mixed with strong noise is an inevitable problem in engineering application and scientific research. For example, in the photoelectric field, the absorption spectrum of a substance to far-infrared signals or terahertz signals is researched; in the signal system field, the characteristics and transmission rules of seismic waves are detected; in the biomedical field, the breathing and heartbeat of a fetus are monitored; all of these need to detect weak signals from strong noise, and the signals are completely submerged in the noise.

[0003] In the prior art, the main instrument for detecting a harmonic component of a weak periodic signal is a phase-locked amplifier. The phase-locked amplifier uses a single-frequency signal with the same frequency or multiple frequencies as the measured signal as a reference to modulate the measured signal, filter the sum frequency signal and background noise, and obtain the amplitude and phase of the harmonic of the measured signal. The phase-locked amplifier can greatly suppress background noise and detect weak signals with extremely low signal-to-noise ratio. The phase-locked amplifier mainly includes an analog phase-locked amplifier and a digital phase-locked amplifier. The analog phase-locked amplifier has fast detection speed, but is easily affected by the external environment and drifts, has low detection precision, and has large volume. The digital phase-locked amplifier is stable, has strong anti-interference ability, and has high detection precision, but has complex technology, high cost, and large volume.

[0004] Therefore, there is an urgent need for a Fourier series detection device for weak periodic signals, which has strong anti-interference ability, high detection precision, small volume, and low cost. SUMMARY

[0005] In order to solve the above technical defects in the prior art, the application provides a Fourier series detection device for weak periodic signals under strong noise based on FPGA.

[0006] The technical scheme for achieving the object of the application is a Fourier series detection device for weak periodic signals in a strong noise background based on FPGA, comprising a program-controlled amplification module, an AD acquisition module, an FPGA Fourier series detection module, an STM32 control module and an OLED display module; the program-controlled amplification module, the AD acquisition module and the FPGA Fourier series detection module are connected in sequence, and the STM32 module is connected with the program-controlled amplification module, the AD acquisition module, the FPGA Fourier series detection module and the OLED display module; the program-controlled amplification module is used for amplifying the amplitude of a to-be-detected signal; the AD acquisition module is used for digitally acquiring the amplified to-be-detected signal; the FPGA Fourier detection module is used for filtering out strong noise and detecting the Fourier series of a to-be-detected digital signal; the STM32 control module is used for controlling the gain of the program-controlled amplification module, the rate of the AD acquisition module, the display of the OLED and the communication with the FPGA Fourier series detection module; and the OLED display module is used for displaying the Fourier series of the periodic signal in real time.

[0007] Preferably, the program-controlled amplification circuit comprises two-stage amplification circuits, the first-stage amplification circuit is an adjustable-gain amplification circuit, the amplification multiple is selected by the STM32 control module, and the second-stage amplification circuit is a fixed-gain amplification circuit.

[0008] Preferably, the FPGA Fourier series detection module comprises a direct digital frequency synthesis DDS, a multiplier, a low-pass filter, a frequency controller, a RAM and a communication module; the direct digital frequency synthesis DDS, the multiplier and the low-pass filter are connected in sequence, the direct digital frequency synthesis DDS is used for generating frequency-controllable sine and cosine signals, the to-be-detected signal and the sine and cosine signals generated by the direct digital frequency synthesis DDS are multiplied by the multiplier to obtain a lock frequency signal, the low-pass filter filters out noise of the lock frequency signal to obtain a direct current signal; the frequency controller is connected with the direct digital frequency synthesis DDS and the communication module, and is used for controlling the frequency generated by the direct digital frequency synthesis DDS; the RAM is connected with the low-pass filter and the communication module, stores the Fourier series of the direct current signal and outputs the Fourier series by the communication module; and the communication module communicates with the STM32 control module, and is used for sending a received frequency control word to the frequency controller and sending data of the RAM to the STM32 control module.

[0009] Preferably, the direct digital frequency synthesizer DDS adopts a structure of reading data from a ROM, and the data of a quarter period of sine and cosine are stored in the ROM.

[0010] Preferably, the low-pass filter comprises a comb filter, a half-band filter and a shaping filter connected in sequence.

[0011] Preferably, the number of the comb filters is 2, the number of the half-band filters is 5, and the number of the shaping filters is 1.

[0012] Preferably, the communication module adopts asynchronous communication, and combines the sine Fourier series and the cosine Fourier series of the direct current signal into one signal and sends the signal to the STM32 control module.

[0013] Preferably, the STM32 control module decomposes one detection result from the FPGA Fourier series detection module into two signals, i.e., the sine Fourier series and the cosine Fourier series, and displays the two signals on the OLED display screen.

[0014] Compared with the prior art, the present application has the following advantages: the detection frequency accuracy of the present application is 0.01 Hz, the detection dynamic range is 96 dB, and the sampling rate of the to-be-detected signal is 50 MHz; the passband bandwidth of the low-pass filter of the present application is 0.3 Hz, the stopband cutoff frequency is 1 Hz, and the stopband attenuation is -110 dB, which can suppress 10 5 times of noise of the to-be-detected signal, and the relative error of the detection result is not more than 3% under 10 4 times of noise; the present application can display the sine Fourier series and the cosine Fourier series of the to-be-detected signal in the form of data on the OLED in real time; the present application is concentrated in a single FPGA chip, has small volume, low cost, strong anti-interference, and strong scalability.

[0015] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims, and the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0017] Figure 1 is a system structure diagram of the present application.

[0018] Figure 2 is an FPGA Fourier series detection structure diagram of the present application.

[0019] Figure 3 is a low-pass filter circuit structure diagram of the present application.

[0020] Figure 4 is a shaping filter amplitude characteristic diagram of the present application. DETAILED DESCRIPTION

[0021] It is readily understood that, based on the technical solution of this invention, various embodiments of the invention can be conceived by those skilled in the art without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention. Rather, these embodiments are provided to enable those skilled in the art to gain a more thorough understanding of the invention. Preferred embodiments of the invention are described below in conjunction with the accompanying drawings, which form part of this application and, together with the embodiments of the invention, serve to illustrate the innovative concept of the invention.

[0022] like Figure 1 As shown, a Fourier series detection device for weak periodic signals under strong noise background based on FPGA includes a programmable amplifier module, an AD acquisition module, an FPGA Fourier series detection module, an STM32 control module, and an OLED display module; the programmable amplifier module, the AD acquisition module, and the FPGA Fourier series detection module are connected in sequence, and the STM32 control module is connected to the programmable amplifier module, the AD acquisition module, the FPGA Fourier series detection module, and the OLED display module respectively.

[0023] The working process of this invention is as follows: the signal under test is first amplified by a process-controlled amplifier circuit, and the amplification gain is controlled by STM32. The amplified signal enters the AD acquisition module, and the AD acquisition rate is controlled by STM32 to 50MHz. The acquired digital signal enters the FPGA Fourier series detection module for strong noise filtering and Fourier series detection. The detection result is sent to STM32, and after being controlled by STM32, it is displayed in data form by OLED.

[0024] Specifically, the programmable amplifier module consists of two cascaded amplifier stages. The first stage amplifier circuit is a gain-adjustable differential amplifier circuit with adjustable gain, while the second stage amplifier circuit is a gain-fixed amplifier circuit with a gain of 40dB. The two cascaded amplifier circuits have an adjustable gain range of 40 to 73dB.

[0025] Specifically, the AD acquisition module can acquire signals between 0 and 5V, with a 16-bit acquisition bit and a sampling rate of 50MHz.

[0026] Specifically, the FPGA Fourier series detection module includes a direct digital frequency synthesizer (DDS), a multiplier, a low-pass filter, a frequency controller, RAM, and a communication module, such as... Figure 2The input signal to be tested is multiplied by the harmonic signal generated by the DDS through the multiplier to obtain a frequency-locked signal, which enters the low-pass filter to filter out strong noise and detect the harmonic amplitude, and the obtained approximate direct current signal is the component of the harmonic frequency. The frequency controller is controlled by the STM32, and the frequency control word is refreshed every 3.5 seconds. The communication module combines the sine Fourier series and the cosine Fourier series into a signal, and the expanded data is sent to the STM32 for communication with the STM32 through asynchronous communication.

[0027] Specifically, the DDS adopts a ROM storage structure, and the data of a quarter period of a sine (cosine) is stored in the ROM. The frequency control word of the DDS is 32 bits, the data width is 8 bits, and the data depth is 1024. When reading data, the frequency control word is accumulated to read the address, and the address is judged. For a sine signal, the address is less than 1024, the address is directly written to read the data, the address is greater than 1023 and less than 2048, the address is updated to 2047 minus the address value, the address is greater than 2047 and less than 3072, the address is updated to the address value minus 2048, and the read data is taken as a negative number, and the address is greater than 3071 and less than 4096, and the address is updated to 4096 minus the address value. For a cosine signal, the same as the sine signal.

[0028] Specifically, the low-pass filter circuit is as shown in Figure 3 There are 8 low-pass filters inside, which are cascaded in turn, and can completely filter out strong noise and extract the Fourier series. The first two are comb filters, the middle five are half-band filters, and the last one is a shaping filter; each comb filter is 256 times decimation, the order is 5, the stopband attenuation is-68dB, the input is 24 bits, and the output data is truncated to 24 bits. The frequency-locked signal is originally 50MHz, which is reduced to 763Hz after 2 times of 256 times decimation; each half-band filter is 2 times decimation, the filter coefficient quantization is 16 bits, the input data is 24 bits, and the output data is truncated to 24 bits. The input signal is 763Hz, which is reduced to 24Hz after 5 times of 2 times decimation. The shaping filter adopts a finite impulse response FIR filter, the order is 200, the structure is a Blackman structure, the filter coefficient quantization is 18 bits wide, the input data is 24 bits, and the output is truncated to 24 bits. At a sampling rate of 24Hz, the passband frequency is 0.3Hz, and the stopband attenuation is-110dB. The amplitude response of the shaping low-pass filter is as shown in Figure 4 .

[0029] Specifically, the STM32 control module controls the entire detection device, first, it controls the gain of the program-controlled amplification module, amplifies the weak signal to the appropriate range, at the same time, it controls the rate of the AD acquisition module, which is 500KHz, it also controls the OLED display detection result, finally, it controls the Fourier series detection module in the FPGA, STM32 controls the frequency control word of DDS through the asynchronous communication in the FPGA; STM32 updates the frequency control word of DDS every 3.5s, so that DDS generates the fundamental wave signal, the second harmonic signal and the high harmonic signal with the same frequency as the weak periodic signal to be detected, STM32 receives a detection result sent by FPGA, which is decomposed into two signals: sine Fourier series and cosine Fourier series, which are displayed on the OLED display screen respectively.

[0030] Specifically, the OLED display module displays the final detection result, which displays the sine Fourier series and the cosine Fourier series in the form of numerical value, and it is controlled by STM32, and updates the displayed result every 3.5s.

[0031] The above description is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

[0032] It should be understood that, in order to simplify the present application and help the skilled in the art to understand the various aspects of the present application, in the above description of the exemplary embodiments of the present application, various features of the present application are sometimes described in a single embodiment, or described with reference to a single figure. However, the present application should not be interpreted as the features included in the exemplary embodiments are the necessary technical features of the patent claims.

[0033] It should be understood that the modules, units, components and the like included in the device of one embodiment of the present application can be adaptively changed to be arranged in the device different from the embodiment. Different modules, units or components included in the device of the embodiment can be combined into one module, unit or component, or they can be divided into multiple sub-modules, sub-units or sub-components.

Claims

1. A Fourier series detection device for weak periodic signals in a strong noise background based on FPGA, characterized in that, The program-controlled amplification module, the AD acquisition module, the FPGA Fourier series detection module, the STM32 control module and the OLED display module are sequentially connected, and the STM32 module is connected with the program-controlled amplification module, the AD acquisition module, the FPGA Fourier series detection module and the OLED display module; the program-controlled amplification module is used for amplifying the amplitude of the to-be-detected signal; the AD acquisition module is used for digitally collecting the amplified to-be-detected signal; the FPGA Fourier detection module is used for filtering strong noise and detecting Fourier series of the to-be-detected digital signal; the STM32 control module is used for controlling the gain of the program-controlled amplification module, the rate of the AD acquisition module, the display of the OLED and the communication with the FPGA Fourier series detection module; the OLED display module is used for displaying the Fourier series of the periodic signal in real time; the FPGA Fourier series detection module comprises a direct digital frequency synthesis (DDS), a multiplier, a low-pass filter, a frequency controller, a RAM and a communication module; the direct digital frequency synthesis (DDS), the multiplier and the low-pass filter are sequentially connected; the direct digital frequency synthesis (DDS) is used for generating frequency-controllable sine and cosine signals; the to-be-detected signal and the sine and cosine signals generated by the direct digital frequency synthesis (DDS) are multiplied by the multiplier to obtain a frequency-locked signal; the low-pass filter filters noise of the frequency-locked signal to obtain a direct current signal; the frequency controller is connected with the direct digital frequency synthesis (DDS) and the communication module; the frequency controller is used for controlling the frequency generated by the direct digital frequency synthesis (DDS); the RAM is connected with the low-pass filter and the communication module; the RAM stores the Fourier series of the direct current signal and outputs the Fourier series under the control of the communication module; the communication module communicates with the STM32 control module and is used for sending the received frequency control word to the frequency controller and sending the data of the RAM to the STM32 control module. 2.The Fourier series detection device for weak periodic signal in strong noise background based on FPGA according to claim 1, wherein, The program-controlled amplification circuit comprises two-stage amplification circuits; the first-stage amplification circuit is adjustable gain amplification; the amplification circuit selects an amplification multiple through the STM32 control module; and the second-stage amplification circuit is fixed gain amplification.

3. The FPGA-based device for detecting Fourier series of weak periodic signals in a strong noise background according to claim 1, characterized in that, The direct digital frequency synthesizer (DDS) adopts a structure of reading data from a ROM; the ROM stores data of a quarter period of sine and cosine.

4. The FPGA-based device for detecting Fourier series of weak periodic signals in a strong noise background according to claim 1, characterized in that, The low-pass filter comprises a comb filter, a half-band filter and a shaping filter which are sequentially connected.

5. The FPGA-based apparatus for detecting Fourier series of weak periodic signals in a strong noise background according to claim 4, characterized in that, The number of the comb filters is 2, the number of the half-band filters is 5, and the number of the shaping filter is 1.

6. The FPGA-based apparatus for detecting Fourier series of weak periodic signals in a strong noise background according to claim 1, wherein, The communication module adopts asynchronous communication; sine Fourier series and cosine Fourier series of the direct current signal are combined into one signal which is sent to the STM32 control module.

7. The FPGA-based apparatus for detecting Fourier series of weak periodic signals in a strong noise background according to claim 6, characterized in that, The STM32 control module decomposes one detection result sent by the FPGA Fourier series detection module into two signals: sine Fourier series and cosine Fourier series, and displays the two signals on the OLED display screen.

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