A signal processing system and method for FPGA high sampling rate signals

Abstract

The application discloses a signal processing system of FPGA high sampling rate signal, comprising: a multi-phase local oscillator generation module configured to generate a plurality of high sampling rate local oscillator signals; a plurality of complex mixing modules corresponding to the plurality of high sampling rate local oscillator signals; the complex mixing module is configured to receive the corresponding high sampling rate local oscillator signal and the high sampling rate signal, and to complexly mix the corresponding high sampling rate local oscillator signal and the high sampling rate signal to obtain a plurality of intermediate frequency signals; a filtering and decimation module configured to receive the plurality of intermediate frequency signals and to filter and decimate the intermediate frequency signals to obtain a low sampling rate signal. The signal processing of the high sampling rate signal is completed, and finally the low sampling rate signal capable of being directly processed by the FPGA is obtained. The multiplexing of the multi-phase local oscillator generation module greatly saves the logic resources of the FPGA, and the phase control mode is more flexible and has higher applicability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and in particular to a signal processing system and method for high sampling rate signals of FPGA. BACKGROUND

[0002] In the current communication system, the modulation and demodulation function has a large amount of calculation, and is usually implemented by using FPGA devices which are easy to be processed in parallel. The radio frequency signal received by the antenna is sent to the ADC (Analog to Digital Convertor) device for analog / digital conversion after being down-converted by the radio frequency channel, and then is sent to the FPGA device for demodulation operation. With the development of technology and the needs of practical application, the sampling rate and sampling accuracy are getting higher and higher, and the traditional CMOS interface and LVDS interface cannot meet the design requirements, while the JESD204B interface based on CML can well solve this problem, and the single-channel rate of the interface can reach 12.5 Gb / s. Implementing the JESD204B interface between the ADC and the FPGA processing chip can effectively complete the high-speed data transmission between chips, and has the advantages of reducing the number of device pins and the size of the package, reducing the occupied layout space, and reducing power consumption.

[0003] With the increase of the transmission rate between chips, the working clock of the FPGA cannot rise to the sampling frequency range of the signal, and cannot directly process the signal, so it is necessary to down-sample the high sampling signal, and the down-sampling usually needs to process the signal by mixing. The usual way is to use the DDS module of the FPGA to generate the local oscillator signal with high sampling rate required for mixing, and to mix the high sampling rate signal. However, due to the limited clock frequency at which the FPGA can stably work, the sampling frequency of the signal is limited. Therefore, we propose a signal processing system and method for high sampling rate signals of FPGA to solve the above problems. SUMMARY

[0004] In view of the above defects or deficiencies in the prior art, it is desirable to provide a signal processing system and method for high sampling rate signals of FPGA which saves the logic resources of FPGA and has stronger applicability.

[0005] In a first aspect, the present application provides a signal processing system for high sampling rate signals of FPGA, comprising:

[0006] A multi-phase local oscillator generation module, configured to generate a plurality of local oscillator signals with high sampling rate;

[0007] a plurality of complex mixing modules corresponding to a plurality of high sampling rate local oscillator signals; the complex mixing module is configured to receive the corresponding high sampling rate local oscillator signal and high sampling rate signal, and to complex mix the corresponding high sampling rate local oscillator signal and high sampling rate signal to obtain a plurality of intermediate frequency signals;

[0008] a filtering and decimation module configured to receive the plurality of intermediate frequency signals, filter and decimate the intermediate frequency signals to obtain a low sampling rate signal.

[0009] According to the technical scheme provided by the embodiment of the application, the multi-phase local oscillator generation module comprises a multi-phase local oscillator generation subunit and an operation unit in communication connection;

[0010] The multi-phase local oscillator generation subunit is configured to generate a first local oscillator signal.

[0011] The operation unit is configured to obtain the working frequency of the FPGA, and calculate a plurality of phase signals according to the sampling rate of the first local oscillator signal and the working frequency of the FPGA.

[0012] The operation unit is further configured to complex multiply the plurality of phase signals with the first local oscillator signal respectively to calculate a plurality of high sampling rate local oscillator signals.

[0013] According to the technical scheme provided by the embodiment of the application, the initial phase of the first local oscillator signal is 0.

[0014] According to the technical scheme provided by the embodiment of the application, the sampling frequency of the high sampling rate signal is four times the working frequency of the FPGA.

[0015] In a second aspect, the application provides a signal processing method of a signal processing system based on the FPGA high sampling rate signal, comprising the following steps:

[0016] obtaining a plurality of high sampling rate local oscillator signals; the high sampling rate local oscillator signals are calculated by a multi-phase local oscillator generation module;

[0017] receiving the corresponding high sampling rate local oscillator signal and high sampling rate signal, and complex mixing the corresponding high sampling rate local oscillator signal and high sampling rate signal to obtain a plurality of intermediate frequency signals;

[0018] receiving the plurality of intermediate frequency signals, filtering and decimating the intermediate frequency signals to obtain a low sampling rate signal.

[0019] According to the technical scheme provided by the embodiment of the application, in the step of obtaining a plurality of high sampling rate local oscillator signals, the following steps are included:

[0020] generating a first local oscillator signal; the first local oscillator signal is generated by a multi-phase local oscillator generation subunit;

[0021] obtaining a working frequency of the FPGA, and calculating a plurality of phase signals according to a sampling rate of the first local oscillator signal and the working frequency of the FPGA;

[0022] performing complex multiplication on the plurality of phase signals and the first local oscillator signal respectively to obtain a plurality of high sampling rate local oscillator signals.

[0023] According to the technical scheme provided in the embodiments of the present application, the phase signal is calculated according to the following formula:

[0024]

[0025] wherein, ph n is the nth phase signal; f0 is the frequency of the first local oscillator signal; f f is the working frequency of the FPGA.

[0026] In a third aspect, the present application provides a server, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the FPGA high sampling rate signal processing method described above when executing the computer program.

[0027] In a fourth aspect, the present application provides a computer readable storage medium, which has a computer program, and the computer program implements the steps of the FPGA high sampling rate signal processing method described above when executed by a processor.

[0028] In summary, the present application specifically discloses a specific principle of a FPGA high sampling rate signal processing system. The present application designs a plurality of phase local oscillator generation modules connected in communication, a plurality of complex mixing modules, and a filtering and decimation module. The plurality of complex mixing modules are correspondingly arranged with a plurality of high sampling rate local oscillator signals, and the plurality of high sampling rate local oscillator signals are generated by the plurality of phase local oscillator generation modules. Each complex mixing module receives a corresponding high sampling rate local oscillator signal and a high sampling rate signal, and performs complex mixing on the corresponding high sampling rate local oscillator signal and the high sampling rate signal to obtain a plurality of intermediate frequency signals. The filtering and decimation module receives the plurality of intermediate frequency signals, and performs filtering and decimation on the intermediate frequency signals to obtain a low sampling rate signal. Compared with the prior art, the present application greatly saves the logic resources of the FPGA by multiplexing the plurality of phase local oscillator generation modules, and is more flexible by using phase control.

[0029] Further, to generate the high sampling rate local oscillator signal, the multi-phase local oscillator generation module has a multi-phase local oscillator generation subunit and an operation unit in communication connection, the first local oscillator signal is generated by the multi-phase local oscillator generation subunit, the working frequency of the FPGA is obtained by the operation unit, a plurality of phase signals are calculated according to the sampling rate of the first local oscillator signal and the working frequency of the FPGA, and finally a plurality of high sampling rate local oscillator signals are calculated by respectively performing complex multiplication of the plurality of phase signals and the first local oscillator signal. BRIEF DESCRIPTION OF DRAWINGS

[0030] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, when read in conjunction with the accompanying drawings:

[0031] Figure 1 The principle diagram of the FPGA high sampling rate signal signal processing system.

[0032] Figure 2 The principle diagram of the multi-phase local oscillator generation module.

[0033] Figure 3 The principle diagram of a kind of server.

[0034] Marked in the figure: 1, multi-phase local oscillator generation module; 2, complex frequency mixing module; 3, filter extraction module; 11, multi-phase local oscillator generation subunit; 12, operation unit;

[0035] 501, CPU; 502, ROM; 503, RAM; 504, bus; 505, I / O interface; 506, input part; 507, output part; 508, storage part; 509, communication part; 510, driver; 511, detachable medium. DETAILED DESCRIPTION

[0036] The application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings.

[0037] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0038] Embodiment 1

[0039] Please refer to Figure 1 The principle diagram of the first embodiment of the FPGA high sampling rate signal signal processing system provided by the present application is shown, which comprises:

[0040] The multi-phase local oscillator generation module 1, the plurality of complex mixing modules 2 and the filtering and decimation module 3 are connected in communication;

[0041] The multi-phase local oscillator generation module 1 is configured to generate a plurality of high sampling rate local oscillator signals; the high sampling rate local oscillator signal is much higher than the working frequency of the FPGA.

[0042] The type of the multi-phase local oscillator generation module 1 can be a DDS module.

[0043] As shown in Figure 1 The number of high sampling rate local oscillator signals can be four.

[0044] The plurality of complex mixing modules 2 are provided in correspondence with the plurality of high sampling rate local oscillator signals; the complex mixing module 2 is configured to receive the corresponding high sampling rate local oscillator signal and the high sampling rate signal, and perform complex mixing on the corresponding high sampling rate local oscillator signal and the high sampling rate signal to obtain a plurality of intermediate frequency signals.

[0045] The type of the complex mixing module 2 can be a complex mixer, which can convert a radio frequency signal into an intermediate frequency signal.

[0046] The filtering and decimation module 3 is configured to receive the plurality of intermediate frequency signals, and perform filtering and decimation on the intermediate frequency signals to obtain a low sampling rate signal.

[0047] The type of the filtering and decimation module 3 can be a decimation filter, which can improve the sampling rate of data by decimation.

[0048] The multiplexing of the multi-phase local oscillator generation module greatly saves the logic resources of the FPGA, and the phase control method is more flexible.

[0049] Further, as shown in Figure 2 The multi-phase local oscillator generation module 1 includes a multi-phase local oscillator generation subunit 11 and an operation unit 12 connected in communication;

[0050] The multi-phase local oscillator generation subunit 11 is configured to generate a first local oscillator signal.

[0051] The type of the multi-phase local oscillator generation subunit 11 can be a DDS module.

[0052] The initial phase of the first local oscillator signal can be set to 0.

[0053] The operation unit 12 is configured to obtain the working frequency of the FPGA, and calculate a plurality of phase signals according to the sampling rate of the first local oscillator signal and the working frequency of the FPGA.

[0054] Here, the sampling frequency of the high sampling rate signal can be set to four times the operating frequency of the FPGA.

[0055] The arithmetic unit 12 is further configured to perform complex multiplication of multiple phase signals with the first local oscillator signal to calculate multiple high sampling rate local oscillator signals.

[0056] The model of the arithmetic unit 12 can be PaddlePi-K210.

[0057] Example 2

[0058] A signal processing method based on the FPGA high sampling rate signal signal processing system described in Embodiment 1 includes the following steps:

[0059] Multiple high-sampling-rate local oscillator signals are acquired; the high-sampling-rate local oscillator signals are calculated by the multi-phase local oscillator generation module 1.

[0060] The system receives the corresponding high-sampling-rate local oscillator signal and high-sampling-rate signal, and performs complex mixing on the corresponding high-sampling-rate local oscillator signal and high-sampling-rate signal to obtain multiple intermediate frequency signals;

[0061] It receives multiple intermediate frequency (IF) signals and filters and extracts the IF signals to obtain a low sampling rate signal.

[0062] Furthermore, the acquisition of multiple high-sampling-rate local oscillator signals includes the following steps:

[0063] A first local oscillator signal is generated; the first local oscillator signal is generated by the multi-phase local oscillator generation subunit 11.

[0064] The operating frequency of the FPGA is obtained, and multiple phase signals are calculated based on the sampling rate of the first local oscillator signal and the operating frequency of the FPGA.

[0065] Multiple phase signals are multiplied by the first local oscillator signal to obtain multiple high sampling rate local oscillator signals.

[0066] Furthermore, the phase signal is calculated according to the following formula:

[0067] ph n =cos(f0 / f f )×2pi×(n-1 / 4)+jsin[cos(f0 / f f )×2pi×(n-1 / 4)」;

[0068] Among them, ph n f is the nth phase signal; f0 is the frequency of the first local oscillator signal; f f This refers to the operating frequency of the FPGA.

[0069] In the embodiment, four high sampling rate signals are represented by ss1, ss2, ss3 and ss4; four high sampling rate local oscillator signals are represented by aa1, aa2, aa3 and aa4; the first local oscillator signal is represented by dd1; and four phase signals are represented by ph1, ph2, ph3 and ph4.

[0070] The phase signals ph1, ph2, ph3 and ph4 are calculated by the following formula:

[0071]

[0072]

[0073]

[0074]

[0075] The high sampling rate local oscillator signals aa1, aa2, aa3 and aa4 are generated by performing complex multiplication of ph1, ph2, ph3 and ph4 with dd1.

[0076] The high sampling rate signals ss1, ss2, ss3 and ss4 are complex-mixed with the corresponding high sampling rate local oscillator signals aa1, aa2, aa3 and aa4 to obtain four intermediate frequency signals.

[0077] The four intermediate frequency signals are filtered and decimated to obtain low sampling rate signals that can be directly processed by the FPGA.

[0078] Through the above steps, the signal processing of the high sampling rate signals is completed, and the low sampling rate signals that can be directly processed by the FPGA are finally obtained. The method can process high sampling rate signals that are much higher than the working frequency of the FPGA, and significantly saves the FPGA resources.

[0079] Embodiment 3

[0080] A server includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the FPGA high sampling rate signal signal processing method according to Embodiment 2 when executing the computer program.

[0081] In the embodiment, as Figure 3As shown, the computer system includes a central processing unit (CPU) 501 which can perform various appropriate actions and processes according to programs stored in a read only memory (ROM) 502 or programs loaded from a storage section into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the system are also stored. The CPU 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0082] The following components are connected to the I / O interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section including a display device such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive is also connected to the I / O interface 505 as necessary. A removable recording medium 511 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is attached to the drive 510 as necessary, so that a computer program read therefrom is installed into the storage section 508 as necessary.

[0083] In particular, according to embodiments of the present application, the above-mentioned processes with reference to the flowcharts Figure 1 The processes described can be implemented as computer software programs. For example, embodiment 3 of the present application includes a computer program product comprising a computer program carried on a computer readable medium, the computer program comprising program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section, and / or installed from a removable recording medium. When the computer program is executed by the central processing unit (CPU) 501, the above-mentioned functions defined in the system of the present application are performed.

[0084] It should be noted that the computer-readable medium shown in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or component. In the present application, the computer-readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or component. The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0085] The flowcharts and block diagrams in the drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment or a part of code containing one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different order than that shown in the drawings. For example, two blocks that are shown in succession can actually be executed substantially in parallel, and sometimes in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams or flowcharts, and the combination of blocks in the block diagrams or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0086] The units described in the embodiments of the present application can be implemented by software, or by hardware, or by a combination of software and hardware. The units described can be located in a single processor, or distributed over several processors. In some cases, the names of the units described are not intended to limit the scope of the units themselves. For example, the obtaining module can also be described as an "obtaining module configured to obtain a plurality of to-be-detected instances in the basic table".

[0087] As another aspect, the present application also provides a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist independently without being assembled into the electronic device. The computer readable medium carries one or more programs, which, when executed by the electronic device, enable the electronic device to implement the signal processing method for FPGA high sampling rate signal as described in the above embodiments.

[0088] The units described in the embodiments of the present application can be implemented by software, or by hardware, or by a combination of software and hardware. The units described can be located in a single processor, or distributed over several processors. In some cases, the names of the units described are not intended to limit the scope of the units themselves. For example, the obtaining module can also be described as an "obtaining module configured to obtain a plurality of to-be-detected instances in the basic table".

[0089] As another aspect, the present application also provides a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist independently without being assembled into the electronic device. The computer readable medium carries one or more programs, which, when executed by the electronic device, enable the electronic device to implement the signal processing method for FPGA high sampling rate signal as described in the above embodiments.

[0090] The above description is only the preferred embodiment of the present application and the explanation of the technical principles. It should be understood by those skilled in the art that the scope of the protection of the present application is not limited to the technical solutions formed by the specific combinations of the above technical features. It should also cover other technical solutions formed by the combinations of the above technical features or their equivalent features without departing from the concept of the present application. For example, the technical solutions formed by the mutual replacements of the above features and the technical features disclosed in the present application (but not limited to) with similar functions.

Claims

1. A signal processing system for FPGA high sampling rate signals, characterized by, include: A multi-phase local oscillator generation module (1) is configured to generate multiple high-sampling-rate local oscillator signals; Multiple complex mixing modules (2) are configured to correspond to multiple high sampling rate local oscillator signals; the complex mixing module (2) is configured to receive the corresponding high sampling rate local oscillator signal and high sampling rate signal, and to perform complex mixing on the corresponding high sampling rate local oscillator signal and high sampling rate signal to obtain multiple intermediate frequency signals; The filtering and extraction module (3) is configured to receive multiple intermediate frequency signals and filter and extract the intermediate frequency signals to obtain a low sampling rate signal, so as to save the logic resources of the FPGA. The multi-phase local oscillator generation module (1) includes: a multi-phase local oscillator generation subunit (11) and a processing unit (12) connected by communication; The multi-phase local oscillator generation subunit (11) is configured to generate a first local oscillator signal; The arithmetic unit (12) is configured to obtain the operating frequency of the FPGA and calculate multiple phase signals based on the sampling rate of the first local oscillator signal and the operating frequency of the FPGA. The arithmetic unit (12) is also configured to perform complex multiplication of multiple phase signals with the first local oscillator signal respectively to calculate multiple high sampling rate local oscillator signals; The initial phase of the first local oscillator signal is 0; The sampling frequency of the high sampling rate signal is four times the operating frequency of the FPGA; The phase signal is calculated using the following formula: Wherein, ph n is the nth phase signal; f0 is the frequency of the first local oscillator signal; f f is the working frequency of the FPGA.

2. A signal processing method of a signal processing system of a high sampling rate signal of an FPGA according to claim 1, characterized by, Includes the following steps: Multiple high-sampling-rate local oscillator signals are acquired; the high-sampling-rate local oscillator signals are calculated by the multi-phase local oscillator generation module (1); The system receives the corresponding high-sampling-rate local oscillator signal and high-sampling-rate signal, and performs complex mixing on the corresponding high-sampling-rate local oscillator signal and high-sampling-rate signal to obtain multiple intermediate frequency signals; It receives multiple intermediate frequency (IF) signals and filters and extracts the IF signals to obtain a low sampling rate signal.

3. The signal processing method of claim 2, wherein, The acquisition of multiple high-sampling-rate local oscillator signals includes the following steps: The first local oscillator signal is generated by the multi-phase local oscillator generation subunit (11). The operating frequency of the FPGA is obtained, and multiple phase signals are calculated based on the sampling rate of the first local oscillator signal and the operating frequency of the FPGA. Multiple phase signals are multiplied by the first local oscillator signal to obtain multiple high sampling rate local oscillator signals.

4. A server comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein, When the processor executes the computer program, it implements the steps of a signal processing method for FPGA high sampling rate signals as described in any one of claims 2 to 3.

5. A computer readable storage medium having a computer program, characterized in that When the computer program is executed by the processor, it implements the steps of the signal processing method for FPGA high sampling rate signals as described in any one of claims 2 to 3.

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