A method for implementing matrix-vector multiplication after QR decomposition based on a vector processor

Abstract

The application relates to a QR decomposition-based matrix-vector multiplication implementation method based on a vector processor, and the QR decomposition algorithm is a vsip_cqrd_f function in a VSIP library, the VSIP library is a vector, signal and image processing library launched by a GE intelligent platform, and is an open standard application programming interface specially provided for developers who need to use intensive signal and image processing. The technical scheme of the application mainly comprises the following steps: step one, judging whether input matrix C needs transposition conjugate processing and whether the matrix C is on the left or right in matrix multiplication, so as to enter different branch processing; step two, pre-processing the A matrix; step three, adopting different processing schemes according to the quantity size to realize matrix-vector multiplication operation. The application is designed and realized for the QR decomposition-based matrix-vector multiplication in the light of the advantages of the vector processor, such as large storage space, on-chip cache and efficient and fast data transmission, and can play a great advantage in complex matrix operation.

Description

Technical Field

[0001] This invention relates to code optimization for high-performance digital signal processor (DSP) chips, and more specifically, to a method for implementing matrix multiplication after QR decomposition based on a vector processor. Background Technology

[0002] The VSIP library is a vector, signal, and image processing library launched by GE's intelligent platform. It is an open standard application programming interface designed for developers who need to use enhanced signal and image processing. If you directly call the original functions in the VSIP library, you will lose the excellent hardware performance of the vector processor. To take advantage of the hardware advantages of high-performance processors and improve the parallelism and efficiency of algorithms, it is a good choice to optimize the algorithms in the VSIP library and adapt them to different high-performance processors.

[0003] In modern processors, the VLIW architecture with vector processing units has increasingly become the typical structure for high-performance digital signal processors. Domestic high-performance DSPs have developed rapidly, resulting in many high-performance processors produced by different companies. These processors typically feature abundant register resources and numerous execution units. Vector processors generally consist of multiple processing units, supporting vector-based data loading, computation, and storage. Each processing unit contains multiple independent multi-functional components, typically including addition, multiplication, shifting, comparison, vector element accumulators, and scalar vector conversion units. Vector processors generally support Single Instruction Multiple Data (SIMD) operations, meaning that under the control of the same vector instruction, all processing units simultaneously perform the same operation on the corresponding local registers, achieving data-level parallelism in application development. To accelerate data access speed, vector processors typically have internal or external caches. To effectively leverage the performance advantages of DSP vector processing hardware, there is an urgent need for optimized, efficient matrix multiplication algorithms. Matrix multiplication, as a crucial part frequently used in many scientific applications, is inherently computationally intensive and demanding, making the research on parallel algorithms for matrix and vector multiplication a perennial topic in high-performance computing. In addition, matrix multiplication is often used to evaluate the performance and efficiency of new processor architectures, and to explore how to perform high-performance optimizations on new architectures.

[0004] Patent application CN 103294648A, published on September 11, 2013, discloses a block matrix multiplication vectorization method supporting a vector processor with multiple MAC processing units. This method expands each element of each row of the multiplicand A into a vector data and multiplies it by a row of data from matrix B. This scheme differs from the implementation method of this invention, and it also does not implement matrix-vector multiplication after QR decomposition.

[0005] Patent application CN 114090954A, published on February 25, 2022, discloses an optimization method for integer matrix multiplication kernel based on FT-2000+. This method differentiates the design content of sub-functions based on the different lengths of the input and output matrix data. Combining the FT-2000+ architecture, it determines the register allocation strategy and matrix block strategy to optimize integer matrix multiplication. This method differs from the implementation of the proposed solution, and it also does not implement matrix-vector multiplication after QR decomposition.

[0006] This invention relates to a matrix multiplication implementation method based on a vector processor after QR decomposition. The QR decomposition algorithm is the vsip_cqrd_f function in the VSIP library. After calling the cqrd function, the output QRD structure is retrieved. This structure mainly includes a complex matrix A, a complex vector cI, and a real vector beta. The upper triangular part of the complex matrix A is the R matrix, and the lower triangular part is the Q matrix. Using the above data as input to the algorithm, matrix-vector multiplication operations with the Q matrix in QR decomposition are implemented in four different cases. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention proposes a method for implementing matrix multiplication after QR decomposition based on a vector processor.

[0008] The technical solution of the present invention includes the following steps:

[0009] Step 1: Determine whether the input matrix C needs transpose and conjugate, and whether matrix C is on the left or right side of the matrix multiplication, to determine which sub-function to use for processing. The processing methods for each sub-function are largely similar; this solution mainly describes the common processing methods.

[0010] Step 2: Preprocess matrix A by setting the elements on the diagonal to 1, the elements in the upper right part of the diagonal to 0, and leaving the elements in the lower left part unchanged. After transformation, divide matrix A into columns and name each column a vector in sequence. , For example: vectors Contains the values ​​of the first column of matrix A, and the values ​​of each component are named... , .

[0011] Step 3, Matrix C and Vector To perform matrix multiplication, the entire C matrix and vectors are transferred via DMA. Transmitted to cache, vector Each row of matrix C takes P numbers and passes them to the vector operation unit, while a multiplication instruction is executed. The multiplication result is then passed to the temporary vector register TR. Next, the (P+1)th to (2P)th data are taken and processed in the same way, accumulating the result with the corresponding value already stored in TR. This process continues until one row of matrix C is processed. The value of TR is then passed to the vector element accumulator VEA, where it is accumulated, multiplied by beta, and stored in the designated space in DDR. The next row is then processed, and this process continues until all rows are processed, resulting in a vector of length m stored in DDR. .

[0012] The specific method of step 3 of the present invention includes the following steps:

[0013] Step 3.1: Determine how to process the data based on its size. If the original data is extremely small, proceed to step 3.2. If the original data size does not exceed the cache size, proceed to step 3.3. If the original data size exceeds the cache size, proceed to step 3.4.

[0014] Step 3.2: When the data volume is extremely small, it will be processed directly in DDR using scalar methods.

[0015] Step 3.3: When the data volume does not exceed the cache size, transfer the entire C matrix and vectors via DMA. Transmitted to cache, vector Each row of matrix C takes P numbers and passes them to the vector operation unit, while a multiplication instruction is executed. The multiplication result is then passed to the temporary vector register TR. Next, the (P+1)th to (2P)th data are taken and processed in the same way, accumulating the result with the corresponding value already stored in TR. This process continues until one row of matrix C is processed. The value of TR is then passed to the vector element accumulator VEA, where it is accumulated, multiplied by beta, and stored in the designated space in DDR. The next row is then processed, and this process continues until all rows are processed, resulting in a vector of length m stored in DDR. ;

[0016] Step 3.4: When the data volume exceeds the cache size, the cache is divided into three parts. The first part is used to store vectors. The remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is completed, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, as in step 3.3. The transfer and calculation are carried out in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins at the same time. The above steps are repeated until all calculations are completed.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] Based on the hardware characteristics of vector processors, this invention ported and optimized the matrix multiplication after QR decomposition in the VSIP library, making full use of the hardware performance advantages, improving the utilization efficiency of computing units, and achieving higher instruction parallelism. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the preprocessing of matrix A in step 2 of the present invention.

[0020] Figure 2 For step 3 of this invention, matrix C and vector Perform matrix multiplication and update vectors Formula diagram.

[0021] Figure 3 This is a flowchart of step 3 of the present invention.

[0022] Figure 4 This is a schematic diagram of the calculation process in step 3 of the present invention. Detailed Implementation

[0023] The present invention will now be further described in conjunction with the accompanying drawings and embodiments.

[0024]

[0025] Referring to Table 1, a schematic diagram of the matrix operations considered in this invention is provided. This represents the Q-matrix obtained by transposing and conjugating it. Taking matrix multiplication as an example, if the left matrix is ​​Q and the right matrix is ​​C, and the size of the left matrix Q is M*M and the right matrix is ​​M*K, then the output matrix will be M*K. Whether to perform transpose and conjugate operations on the input matrix C depends on the situation. After processing, matrix A contains a portion of the contents of matrix Q. Matrix A is then processed by setting the diagonal elements to 1, the upper-right diagonal elements to 0, and leaving the lower-left diagonal elements unchanged. Figure 1 As shown. After the transformation, matrix A is divided into columns, and each column is named a vector in sequence. , For example: vectors Contains the values ​​of the first column of matrix A, and the values ​​of each component are named... , .

[0026] refer to Figure 2 , Figure 3 After dividing matrix A into columns, the processing method is determined based on the size of the original data. When the original data is extremely small, scalar processing is performed directly in DDR. When the size of the original data does not exceed the cache size, the entire matrix C and vectors are transferred via DMA. The data is transferred to the cache, and matrix C is processed row by row. The specific calculation process can be found in the next paragraph. This continues until all calculations are completed, resulting in a vector of length m stored in DDR. When the size of the original data exceeds the cache size, the cache is divided into three parts. The first part is used to store vectors. The remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is complete, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, and the transfer and calculation are carried out in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the calculated part is transferred back to DDR via DMA. After the transfer is completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins at the same time. The above steps are repeated until all calculations are completed.

[0027] refer to Figure 4 A schematic diagram of the calculation process in step 3 of this invention. Let vector... ={ }, matrix C={ }, { }, { Let the vector operation unit have 4 processing units, which can process 4 data simultaneously, i.e., P=4. During the first row calculation, the first time, { is transferred from the cache} }and{ These data are fed into the vector operation unit, where vector multiplication is performed. = , = , = , = ,Will , , , Pass the data to the vector register TR, and then begin the second operation. , The data is transmitted to the vector processing unit for multiplication. = ,Will Pass it into the vector register TR, and combine it with... Add them together, and { , , , Store the elements into the vector accumulator VEA, accumulate them, and then multiply by... And return it to DDR; the second line is calculated similarly.

[0028] In summary, after reading this invention document, those skilled in the art can make various other corresponding modifications to the technical solutions and concepts based on this invention without creative mental effort, and all of these modifications fall within the scope of protection of this invention.

Claims

1. A method for implementing matrix-vector multiplication after QR decomposition based on a vector processor, characterized in that: Includes the following steps, Step 1, determine the input matrix Do we need transpose, conjugate, and matrix? Whether to proceed on the left or right side of the matrix multiplication, so as to enter different sub-functions for processing, the processing flow of each sub-function includes the following common steps; Step 2: Preprocess matrix A by setting the diagonal elements to 1, the upper right elements of the diagonal to 0, and leaving the lower left elements unchanged. After transformation, divide matrix A into columns and name each column a vector in sequence. , ,vector Contains the values ​​of the first column of matrix A, and the values ​​of each component are named... , ; Step 3, Matrix with vector To perform matrix multiplication, transfer the entire C matrix and vectors via DMA. Transmitted to cache, vector Each row of matrix C takes P numbers and passes them to the vector operation unit, while a multiplication instruction is executed. The multiplication result is then passed to the temporary vector register TR. Next, the (P+1)th to (2P)th data are taken and processed in the same way, accumulating the result with the corresponding value already stored in TR. This process continues until one row of matrix C is processed. The value of TR is then passed to the vector element accumulator VEA, where it is accumulated, multiplied by beta, and stored in the designated space in DDR. The next row is then processed, and this process continues until all rows are processed, resulting in a vector of length m stored in DDR. ; The specific method of step 3 includes the following steps. Step 3.1: Determine how to process the data based on its size. If the original data is extremely small, proceed to step 3.

2. If the original data size does not exceed the cache size, proceed to step 3.

3. If the original data size exceeds the cache size, proceed to step 3.

4. Step 3.2: When the data volume is extremely small, it will be processed directly in DDR using scalar methods. Step 3.3: When the data volume does not exceed the cache size, transfer the entire C matrix and vectors via DMA. Transmitted to cache, vector Each row of matrix C takes P numbers and passes them to the vector operation unit, while a multiplication instruction is executed. The multiplication result is then passed to the temporary vector register TR. Next, the (P+1)th to (2P)th data are taken and processed in the same way, accumulating the result with the corresponding value already stored in TR. This process continues until one row of matrix C is processed. The value of TR is then passed to the vector element accumulator VEA, where it is accumulated, multiplied by beta, and stored in the designated space in DDR. The next row is then processed, and this process continues until all rows are processed, resulting in a vector of length m stored in DDR. ; Step 3.4: When the data volume exceeds the cache size, the cache is divided into three parts. The first part is used to store vectors. The remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is completed, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, as in step 3.

3. The transfer and calculation are carried out in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins at the same time. The above steps are repeated until all calculations are completed.

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