A bit line leakage current compensation and BCAM multiplexing circuit and compensation method

Abstract

The present invention relates to a bitline leakage current compensation and BCAM multiplexing circuit and compensation method. The bitline leakage current compensation and BCAM multiplexing circuit includes a storage array composed of multiple SRAM cells and a compensation module. Each column of SRAM cells shares a bit line and constitutes a basic storage module. The compensation module includes eight PMOS transistors P0 to P7 and two compensation capacitors C1 and C2. The drains of P0, P1, P2, and P3 serve as the four input terminals of the compensation module and are connected to the four bit lines of the storage module. The upper plate connection terminals out and outb of C1 and C2 serve as the result output terminals when the storage module performs normal read and write operations. The lower plate connection terminals bout and boutb of C1 and C2 serve as the result output terminals when the storage module performs BCAM addressing operations. The compensation module of the present invention can reduce addressing or reading errors caused by leakage current.

Description

Technical Field

[0001] The present invention relates to the technical field of static random access memory, and in particular to a bit line leakage current compensation and BCAM multiplexing circuit, and a bit line leakage current compensation method applied to the bit line leakage current compensation and BCAM multiplexing circuit. Background Art

[0002] As technology advances, the size of complementary metal oxide semiconductors (CMOS) decreases, and their power supply voltage also decreases, which in turn reduces the threshold voltage of transistors. This leads to an increase in subthreshold leakage current, which has an increasingly significant impact on the performance of static random-access memory (SRAM). For example, leakage current on an SRAM bit line can increase SRAM read time and even cause SRAM read failures.

[0003] As a special application of in-memory computing, Binary Content Addressable Memory (BCAM) performs comparison operations within the memory by comparing the input data bit by bit with the stored data, improving search efficiency while reducing power consumption. BCAM addressing typically works by connecting the addressed data and its inverse to the left and right word lines of the memory cell, addressing it by column. When the addressing data matches the addressed data, the addressed column does not discharge, and the bit lines at both ends remain at a high level. However, if bit line leakage current occurs, even in the case of a match, the bit line voltage will drop due to the bit line leakage current, and the subsequent judgment will be mismatched, resulting in erroneous results.

[0004] To alleviate or even eliminate the impact of leakage current on the bit line on SRAM performance, existing technical solutions can be summarized into the following two types:

[0005] (1) Design of storage unit: Figure 1The circuit structure for bitline leakage equalization (BLE) is shown. This method primarily utilizes the proposed 8T SRAM memory cell structure for leakage compensation. When a wordline is not being accessed, if bitline leakage current occurs, the proposed memory cell injects the same leakage current into the bitline. NMOS transistors M3 and M4 are used as leakage compensation devices. NMOS transistors M1, M2, M3, and M4 are of identical size. If leakage occurs, the resulting leakage current is I1 + I3 = I2 + I4, where I1 = I4 and I2 = I3. This results in balanced leakage, eliminating the voltage difference on the bitline caused by leakage current. This solution utilizes two redundant transistors for leakage compensation at the expense of area. The advantage is fast compensation speed, but the disadvantage is that it is susceptible to temperature and transistor process effects. If the NMOS transistors are not completely uniform in size, accurate compensation cannot be achieved.

[0006] (2) Design of bit line auxiliary circuit: Figure 2 Figure 2 shows the circuit structure of an X-Calibration circuit in the prior art. The X-Calibration circuit structure operates as follows: A series capacitor on the bit line changes the difference between the upper and lower plates of the capacitor by controlling the on and off switching of a PMOS transistor. This, in turn, utilizes the characteristic that the difference between the upper and lower plates of the capacitor remains constant to compensate for the bit line voltage drop caused by leakage. However, this circuit structure requires two normally-on PMOS transistors on the bit line to generate current to ensure that the leakage current eventually stabilizes, significantly increasing read time and power consumption.

[0007] In addition, when using BCAM mode, addressing determination is required. Figure 3 This is an existing BCAM mode determination module. This structure consists of two sense amplifiers and a two-input AND gate. During BCAM addressing, columns are addressed, and the bit lines BL and BLB serve as inputs to the two sense amplifiers, respectively, and are compared with a reference voltage VREF at the other input. Output terminals OUT and OUT1, connected to the two bit lines, serve as inputs to a two-input AND gate. The voltage level at the output terminal OUT3 of the two-input AND gate indicates whether the addressing result matches. A high level "1" indicates a match, while a low level "0" indicates a mismatch. During the addressing process, a match is only achieved when neither the left or right bit line is discharged. At this point, the bit line voltages BL and BLB are both greater than VREF, and both OUT and OUT1 output a high level "1." The output terminal OUT3 of the two-input AND gate also outputs a high level "1." This method uses two sense amplifiers and a two-input AND gate to implement addressing, which occupies a certain area. Summary of the Invention

[0008] Based on this, it is necessary to provide a bit line leakage current compensation and BCAM multiplexing circuit, as well as a bit line leakage current compensation method applied to the bit line leakage current compensation and BCAM multiplexing circuit, in order to overcome the problem of bit line leakage current at the expense of read time and power consumption in the existing technology.

[0009] To achieve the above object, the present invention adopts the following technical solutions:

[0010] A bitline leakage current compensation and BCAM multiplexing circuit includes a storage array consisting of multiple SRAM cells and a compensation module. Each column of SRAM cells shares a bitline and forms a basic storage module. The compensation module is used to compensate for the bitline leakage current of the storage module. The compensation module includes eight PMOS transistors P0 to P7 and two compensation capacitors C1 and C2.

[0011] The top plate of C1 is connected to the drains of P0 and P6, and the bottom plate is connected to the drains of P4 and P2. The top plate of C2 is connected to the drains of P1 and P7, and the bottom plate is connected to the drains of P5 and P3. The sources of P4-P7 are connected to power supply VDD. The gates of P0-P3 are controlled by control signal V1, the gates of P4 and P5 are controlled by control signal V2, and the gates of P6 and P7 are controlled by control signal M1. The drains of P0 and P1 serve as two inputs of the compensation module. The drains of P2 and P3 serve as the other two inputs of the compensation module, connected to the bit lines BL, BLB, BL1, and BLB1 on either side of the storage module, respectively.

[0012] The upper plate connection terminals out and outb of C1 and C2 serve as leakage-compensated output terminals of the memory module when performing normal read and write operations. The lower plate connection terminals bout and boutb of C1 and C2 serve as leakage-compensated output terminals of the memory module when performing BCAM addressing operations.

[0013] Furthermore, PMOS transistors P4-P7 function as a mode selection module for switching memory module modes. During the leakage compensation phase, when the compensation module's control signals V2 = VSS and M1 = VDD (normal read / write mode), the top plate connections of C1 and C2, out and outb, output the results of normal read / write operations performed by the memory module. When the compensation module's control signals V2 = VDD and M1 = VSS (BCAM addressing mode), the bottom plate connections of C1 and C2, bout and boutb, output the results of BCAM addressing performed by the SRAM memory module.

[0014] Furthermore, the bitline leakage current compensation and BCAM multiplexing circuit also includes a sense amplifier module. This sense amplifier module comprises a first-stage sense amplifier unit, a second-stage sense amplifier unit, and four mode select transistors SK1 through SK4. SK1 through SK4 are connected to the input of the first-stage sense amplifier unit. One of the outputs of the first-stage sense amplifier unit is connected to the gate of a pass transistor in the second-stage sense amplifier unit.

[0015] Furthermore, the first-stage sensitive amplifier unit includes four PMOS transistors P02, P12, P22, and P32, and three NMOS transistors N02, N12, and N22. The gate of P02 is connected to the gate of N02, the drain of N12, the drain of P12, and the drain of P32. The drain of P02 is connected to the drain of P22, the drain of N02, and the gate of P12 and the gate of N12. The sources of P02 and P12 are connected to VDD, the sources of N02 and N12 are connected to the drain of N22, and the source of N22 is connected to VSS. The gates of P22, P32, and N22 are controlled by a control signal SAE.

[0016] The drain of P22 serves as the output OUT of the first-stage sensitive amplifier unit, and the drain of P32 serves as the other output OUTB of the first-stage sensitive amplifier unit. The source of P22 serves as the input of the first-stage sensitive amplifier unit and is connected to the drains of SK1 and SK2. The source of P32 serves as the other input of the first-stage sensitive amplifier unit and is connected to the drains of SK3 and SK4. SK2 and SK4 are controlled by control signal A, while SK1 and SK3 are controlled by the inverse of control signal A. The source of SK1 is connected to the output out of the compensation module, the source of SK2 is connected to the output bout of the compensation module, the source of SK3 is connected to the output outb of the compensation module, and the source of SK3 is connected to a reference voltage VREF.

[0017] Furthermore, the second-stage sensitive amplifier unit includes four PMOS transistors P42, P52, P62, and P72, and three NMOS transistors N32, N42, and N52. The gate of P42 is connected to the gate of N32, the drain of N42, the drain of P52, and the drain of P72. The gate of P52 is connected to the drain of P42, the drain of P62, the drain of N32, and the gate of N42. The drain of N52 is connected to the sources of N32 and N42. The sources of P42 and P52 are connected to VDD, and the source of N52 is connected to VSS. The gates of N52 and P72 are controlled by control signal SAE1, and the gate of P62 is connected to the output terminal OUTB of the first-stage sensitive amplifier unit.

[0018] The drain of P62 serves as the output terminal OUT1 of the second-stage sensitive amplifier unit, the drain connection terminal of P72 serves as another output terminal OUTB1 of the second-stage sensitive amplifier unit, the source of P62 is connected to the output terminal boutb of the compensation module, and the source of P72 is connected to the reference voltage VREF.

[0019] Furthermore, the sensitive amplifier unit cooperates with the memory module's mode switching to output the sensitive amplification result in that mode. When the memory module is in normal read / write mode, the control signal A of the sensitive amplifier unit is set to a high level, SAE is normally enabled, SAE1 is disabled, and the first-stage sensitive amplifier unit operates to amplify the voltage signals at the memory module's result output terminals out and outb. Furthermore, the first-stage sensitive amplifier unit output terminals OUT and OUTB output the sensitive amplification result in normal read / write mode.

[0020] When the storage module is in BCAM addressing operation, the control signal A of the sensitive amplifier unit is set to a low level, and the SAE and SAE1 enable signals are normally enabled. The first-stage and second-stage sensitive amplifier units operate normally, and the voltage signals at the storage module's result output terminals bout and boutb are compared with the reference voltage VREF. The output terminal OUT1 of the second-stage sensitive amplifier unit is used as the addressing signal matching signal in the BCAM addressing mode.

[0021] Furthermore, the SRAM cell uses an 8TSRAM cell consisting of 8 transistors. The 8TSRAM cell includes two PMOS transistors P01 and P11 and six NMOS transistors N01, N11, N21, N31, N41, and N51. The gate of P01 is connected to the drain of P11, the gate of N01, the drain of N11, the source of N41, and the source of N51. The gate of P11 is connected to the drain of P01, the drain of N01, the gate of N11, the source of N21, and the source of N31. The sources of P01 and P11 are connected to VDD, and the sources of N01 and N11 are connected to VSS. The gates of N21 and N41 are connected to word line WL, the gate of N31 is connected to word line LWL, and the gate of N41 is connected to word line RWL. The drain of N21 is connected to the bit line BL, the drain of N31 is connected to the bit line BL1, the drain of N41 is connected to the bit line BLB, and the drain of N51 is connected to the bit line BLB1.

[0022] Furthermore, the two pairs of bit lines BL and BLB, as well as BL1 and BLB1, in the memory module are connected to a precharge module. The precharge module is composed of multiple precharge units, with one precharge unit corresponding to a pair of bit lines. The precharge units include three PMOS transistors P31, P32, and P33. P31, P32, and P33 are controlled by a control signal PRE. The sources of P32 and P33 are connected to VDD, and the drains of P32 and P33 are connected to the bit lines BL and BLB, respectively. The source and drain of P31 are connected to the drains of P32 and P33, respectively.

[0023] Furthermore, when the memory module performs normal read and write operations, the word line WL=VDD, RWL=LWL=VSS, and the bit lines BL and BLB serve as main bit lines, and BL1 and BLB1 serve as auxiliary bit lines. When the memory module performs BCAM addressing operations, the word line WL=VSS, and the word line signals of RWL and LWL serve as the input pair of the searched data. At this time, the bit lines BL and BLB serve as auxiliary bit lines, and BL1 and BLB1 serve as main bit lines.

[0024] The present invention also relates to a bit line leakage current compensation method, which is applied to the aforementioned bit line leakage current compensation and BCAM multiplexing circuit. The bit line leakage current compensation method comprises the following steps:

[0025] Precharge the two pairs of bit lines BL, BLB and BL1, BLB1 to VDD;

[0026] The main bit line pair and the auxiliary bit line pair are determined according to the operation mode. The auxiliary bit lines perform leakage current detection on the main bit lines and make the following decisions based on the operation mode:

[0027] (1) When the operation mode is the normal read / write mode, BL and BLB are the main bit line pair, and BL1 and BLB1 are the auxiliary bit line pair; in the leakage compensation stage, the control signal V2 = VSS, M1 = VDD, and the VDD value is input to the capacitor plate connected to the auxiliary bit line pair BL1 and BLB1 to achieve the compensation operation;

[0028] (2) When the operation mode is BCAM mode, BL1 and BLB1 are main bit lines, and BL and BLB are auxiliary bit lines. In the leakage compensation stage, the control signal V2 = VDD, M1 = VSS, and the VDD value is input to the capacitor plates connected to the auxiliary bit line pair BL and BLB to realize the compensation operation.

[0029] The technical solution provided by the present invention has the following beneficial effects:

[0030] 1. The circuit designed in this invention not only performs the read and write functions of a standard SRAM, but also supports BCAM mode reuse, reducing addressing errors caused by leakage current. The compensation module can compensate in both SRAM read and write modes and BCAM mode, enabling accurate data reads even in the presence of high bitline leakage current. This provides stable performance without sacrificing read time or power consumption.

[0031] 2. The sensitive amplifier module designed in the present invention cooperates with the compensation module to coordinate the mode switching of the storage module. In the BCAM mode, it can also serve as an addressing determination module to determine whether the addressing is successful based on the output result of the sensitive amplifier module. Compared with the traditional BCAM addressing determination module, it reduces the area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a circuit diagram of a neutral line leakage balance structure in the prior art;

[0033] Figure 2 The circuit structure diagram of X-Calibration in the prior art;

[0034] Figure 3 FIG. 1 is a circuit structure diagram of a BCAM addressing determination circuit in the prior art;

[0035] Figure 4 1 is a circuit structure diagram of the compensation module in Example 1 of the present invention;

[0036] Figure 5 This is a circuit connection diagram of the compensation module, storage module, and pre-charge module in Example 1 of the present invention;

[0037] Figure 6 Based on Figure 4 Circuit structure diagram of the mode selection module;

[0038] Figure 7 1 is a circuit structure diagram of the sense amplifier module in Example 1 of the present invention;

[0039] Figure 8 Based on Figure 5 The circuit structure diagram of the 8TSRAM unit;

[0040] Figure 9 This is a schematic diagram of an overall circuit of a bit line leakage current compensation and BCAM multiplexing circuit according to embodiment 1 of the present invention;

[0041] Figure 10 Based on Figure 9 The circuit structure is in the timing waveform diagram of the normal SRAM read and write mode;

[0042] Figure 11 Based on Figure 9 The circuit structure is a diagram showing the difference in bit line voltage after the bit line leakage compensation structure under different bit line leakage current conditions in a 55nm CMOS process.

[0043] Figure 12 In order to use the traditional SRAM circuit (hereinafter referred to as CONV) and the Figure 9The circuit structure shows the required read time when the bit line difference reaches 200mV under different bit line leakage current conditions;

[0044] Figure 13 This is a flow chart of a bit line leakage current compensation method in embodiment 2 of the present invention. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0046] Example 1

[0047] The present invention introduces a bit line leakage current compensation and BCAM multiplexing circuit, comprising a memory array, a compensation module, a sense amplifier module, and a precharge module. The memory array is composed of multiple SRAM cells, each column of which shares a bit line and constitutes a basic memory module.

[0048] First, the compensation module is introduced. Figure 4 The circuit diagram of the compensation module shown in FIG. Figure 5 The diagram shows the connection between the compensation module and the storage module. The compensation module includes eight PMOS transistors P0-P7 and two compensation capacitors C1 and C2. The upper plate of C1 is connected to the drains of P0 and P6, and the lower plate is connected to the drains of P4 and P2. The upper plate of C2 is connected to the drains of P1 and P7, and the lower plate is connected to the drains of P5 and P3. The sources of P4-P7 are connected to the power supply VDD. The gates of P0-P3 are controlled by control signal V1, the gates of P4 and P5 are controlled by control signal V2, and the gates of P6 and P7 are controlled by control signal M1. The drains of P0 and P1 serve as two inputs of the compensation module. The drains of P2 and P3 serve as the other two inputs of the compensation module, connected to the bit lines BL, BLB, BL1, and BLB1 on both sides of the storage module, respectively. The upper plate connection terminals out and outb of C1 and C2 serve as the output terminals after leakage compensation when the storage module performs normal read and write operations; the lower plate connection terminals bout and boutb of C1 and C2 serve as the output terminals after leakage compensation when the storage module performs BCAM addressing operations.

[0049] See also Figure 6 The PMOS transistors P4 to P7 in the compensation module constitute the mode selection module, which can realize the switching of the circuit between the normal SRAN read and write mode and the BCAM addressing mode.

[0050] Second, see Figure 7 The sensitive amplifier module shown in the figure is primarily composed of a first-stage sensitive amplifier unit, a second-stage sensitive amplifier unit, and four mode select transistors SK1 to SK4. The first-stage sensitive amplifier unit is controlled by a control signal SAE, while the second-stage sensitive amplifier unit is controlled by a control signal SAE1 and the first-stage sensitive amplifier unit. SK1, SK2, and SK3, SK are connected to the two input terminals of the first-stage sensitive amplifier unit, respectively. SK2 and SK4 are controlled by a control signal A, while SK1 and SK3 are controlled by the inverse of control signal A. The source of SK1 is connected to the output terminal out of the compensation module, the source of SK2 is connected to the output terminal bout of the compensation module, and the source of SK3 is connected to the output terminal outb of the compensation module. The source of SK3 is connected to a reference voltage VREF. The two input terminals of the second-stage sensitive amplifier unit are connected to the output terminal boutb of the compensation module and the reference voltage VREF, respectively.

[0051] Next, the memory array and precharge module are described. The memory array is composed of multiple SRAM cells. Each column of SRAM cells shares a bit line and constitutes a basic memory module. The SRAM cell in this embodiment is an 8TSRAM cell composed of 8 transistors. Figure 8 The 8TSRAM cell shown. The four pass transistors in the 8TSRAM cell connect to the four bit lines BL, BLB, BL1, and BLB1, respectively. BL and BL1 are located on the left side of the 8TSRAM cell, while BLB and BLB1 are located on the right side. The two pass transistors at the top share the word line WL, while the two pass transistors at the bottom connect to word lines LWL and RWL, respectively. Therefore, each memory module shares the bit lines BL, BLB, BL1, and BLB1.

[0052] The precharge module is used to precharge the bit lines BL, BLB, BL1, and BLB1, bringing the voltage signals within the bit lines to a high level, namely, VDD. The precharge module consists of multiple precharge units, with one precharge unit corresponding to a pair of bit lines, namely, BL and BLB or BL1 and BLB1.

[0053] Based on the aforementioned circuit structure and the relationship between modules, the following describes in detail how the bit line leakage current compensation and BCAM multiplexing circuit of this embodiment executes and compensates for the common SRAM read / write mode and the BCAM addressing mode under the condition of bit line leakage current.

[0054] First, let's explain the generation of bitline leakage current. The main reason for bitline leakage current is that the gate control capability of the SRAM cell's transmission tube is weak, resulting in leakage. Although the SRAM cell's transmission tube is turned off by giving the word line a low level, the low threshold voltage of the transmission tube itself causes the transmission tube to not be completely turned off. As a result, when the storage node inside the SRAM cell is at a low level and the bit line is at a high level, the charge on the bit line flows to the storage node inside the SRAM cell at a low level, causing the leakage of bitline current. At this time, the voltage signal collected on the bit line is no longer accurate, especially for storage modules composed of multiple SRAM cells distributed in a row. Due to the shared bit line, when more SRAM cells have transmission tube leakage, the leakage of bitline current will be increased, thereby exacerbating the inability of the voltage signal on the bit line to accurately reflect the actual situation of the storage module. Whether reading, writing or BCAM addressing, the voltage signal of the bit line has errors. When the error exceeds a certain range, it will cause erroneous results.

[0055] Based on the above situation, let's use specific numerical examples. In a memory module, the number of "1s" stored is less than the number of "0s" stored. That is, in a column of SRAM cells, the number of storage nodes Q storing "1s" is less than the number storing "0s." During a read operation, even if the bit line reads "1" (the storage node Q of the row being read stores "1"), the bit line does not discharge. Due to leakage from other rows where Q stores "0s," the bit line voltage drops, resulting in inaccurate data read from the row being read.

[0056] Based on the above situation, the bit line compensation for the circuit of this embodiment performing normal read and write operations and BCAM addressing operations is described in detail below.

[0057] 1. SRAM normal read and write mode

[0058] Precharge Operation: At the beginning of the precharge operation, the bit lines BL and BLB, as well as BL1 and BLB1, are precharged to the power supply voltage VDD through the precharge unit. A low voltage level (VSS) is applied to V1, turning on PMOS transistors P0, P1, P2, and P3. A high voltage level (VDD) is applied to control signal V2, turning off PMOS transistors P4 and P5. At this point, the top and bottom plate voltages of capacitors C1 and C2 are charged to VDD. The control signals WL, RWL, and LWL are low, turning off the SRAM cell's transfer transistors.

[0059] Read operation: After the precharge is completed, the word line WL is turned on with a high level to start the read operation of the SRAM cell. At this time, the BL and BLB corresponding to the transmission tube connected to WL are the main bit lines, and BL1 and BLB1 are the auxiliary bit lines.

[0060] For the storage node Q, the value read at this time is Q1. Since there is a leakage current on the main bit line BL, which is set as Ileakage, the voltage of the main bit line V BL =VDD-ΔV, ΔV is the voltage leakage caused by V BL At the same time, since the auxiliary bit line BL1 and the main bit line BL are connected to the storage node on the same side of the storage module, leakage will also occur on the auxiliary bit line BL1, and the leakage situation is consistent with the leakage situation of the main bit line BL, so V BL1 =V BL =VDD-ΔV.

[0061] In the SRAM cell undergoing a read operation, since Q is 1 and QB is "0", the main bit line BLB is discharged with a discharge current of Icell. This bit line discharge current Icell is caused by the low level of QB, which will cause V BLB The voltage drops to V BLB =VDD-ΔV1. Since the SRAM cell with Q=1 needs to be read, the bit line discharge current Icell corresponding to Q=1 and QB=0 needs to be read, that is, ΔV1 is the voltage difference between the bit lines BL and BLB to be read.

[0062] In the absence of bit line current leakage, under normal circumstances, after the read operation is completed, the voltage on BL will be greater than the voltage on BLB, that is, V BL >V BLB , the voltage difference between the two ends of the main bit line is V BL -V BLB =ΔV1, BL and BLB will read normally after being connected to the sense amplifier. However, due to the leakage current on the main bit line, the voltage difference between the two ends of the main bit line is V BL -V BLB =ΔV1-ΔV. The voltage difference between the two ends decreases or even becomes negative. This may cause the sense amplifier module to output a read error after the bit line is connected to the sense amplifier module after the read operation. Based on this, leakage compensation operation is required. The details are as follows:

[0063] Leakage compensation: When the read operation is completed, the upper and lower plates of C1 correspond to the voltages of BL and BL1 respectively, so the upper and lower plate capacitor voltages of C1 are V BL =V BL1 =VDD-ΔV, the voltage difference between the upper and lower plates of C1 is 0. The upper plate capacitor voltage of C2 corresponds to the BLB voltage, that is, V BLB =VDD-ΔV1, the voltage of the capacitor on the lower plate of C2 is V BLB1 = VDD, the voltage difference between the upper and lower plates of C2 is -ΔV1. This is because RWL is not turned on, so there is no voltage change on BLB1.

[0064] At this point, control signal V1 is set to a high level, turning off PMOS transistors P0, P1, P2, and P3. Control signal V2 is set to a low level, turning on P4 and P5. At this point, the voltage across the bottom plates of capacitors C1 and C2 is VDD. Because capacitors maintain the voltage difference between their top and bottom plates, the voltage across the top plate of capacitor C1 becomes VDD, while the voltage across the top plate of capacitor C2 remains at VDD-ΔV1. The top plates of both capacitors are connected to the sense amplifier module, which reads the corresponding voltage signals.

[0065] After leakage compensation, the input voltage of the sense amplifier module connected to BL changes from VDD-ΔV to VDD, while the input voltage of the sense amplifier module connected to BLB remains VDD-ΔV1. The input difference V BL -V BLB =ΔV1, compensating for the decrease ΔV of the difference due to leakage, and the sensitive amplifier module can amplify correctly.

[0066] If the SRAM cell is read as 0, there is also bit line leakage current on the BLB. The reading and compensation methods are the same as above. The voltage difference caused by the leakage current on the BLB bit line can also be compensated to V BLB superior. Figure 10 The timing diagram shows the circuit of this embodiment performing normal SRAM read and write operations.

[0067] 2.BCAM addressing mode

[0068] After precharging the bit lines, the word line WL is turned off, and the left and right word lines LWL and RWL are turned on one by one. The left and right word lines are connected to the addressed data and its inverse, respectively. At this time, BL1 and BLB1 are the main bit lines, and BL and BLB are auxiliary bit lines. The compensation method is the same as in the normal read and write mode. Then, through the sense amplifier module, the bout and boutb voltage signals of BL1 and BLB1 after leakage compensation are compared with the reference voltage VREF voltage signal. The result is used to make the addressing decision based on the output signal OUT1 of the second-stage sense amplifier unit.

[0069] According to the technical solution provided in this embodiment, the above-described circuit structure can detect leakage current at the beginning of a read operation without requiring two permanently open PMOS transistors to inject current into the bit line. Even in the presence of high bit line leakage current, correct data can still be read, demonstrating highly stable performance. Furthermore, this circuit is capable of switching modes, compensating for bit line leakage current in both normal read / write mode and BCAM addressing mode, thereby reducing errors caused by bit line leakage. Furthermore, the proposed mode-selectable sense amplifier acts as an addressing decision module when the circuit is in BCAM mode, reducing the area required by traditional addressing decision modules.

[0070] In order to further understand the circuit of this embodiment, the specific circuit structure of each module or unit is described in detail below.

[0071] like Figure 8 As shown, the above-mentioned 8TSRAM unit includes two PMOS transistors P01 and P11 and six NMOS transistors N01, N11, N21, N31, N41, and N51. The gate of P01 is connected to the drain of P11, the gate of N01, the drain of N11, the source of N41, and the source of N51. The gate of P11 is connected to the drain of P01, the drain of N01, the gate of N11, the source of N21, and the source of N31. The sources of P01 and P11 are connected to VDD, and the sources of N01 and N11 are connected to VSS. The gates of N21 and N41 are connected to word line WL, the gate of N31 is connected to word line LWL, and the gate of N41 is connected to word line RWL. The drain of N21 is connected to bit line BL, the drain of N31 is connected to bit line BL1, the drain of N41 is connected to bit line BLB, and the drain of N51 is connected to bit line BLB1. N21, N31, N41, and N51 are transmission transistors.

[0072] The specific connection method for the compensation module is as follows: the upper plate of capacitor C1 is connected to the drain of P0 and the drain of P6 respectively, and the lower plate of C1 is connected to the drain of P4 and the drain of P2 respectively. The upper plate of capacitor C2 is connected to the drain of P1 and the drain of P7 respectively, and the lower plate of C2 is connected to the drain of P5 and the drain of P3 respectively. The gate of P0 is connected to the control signal V1, the source is connected to the main bit line BL, and the drain is connected to the upper plate of capacitor C1. The gate of P1 is connected to the control signal V1, the source is connected to the main bit line BLB, and the drain is connected to the upper plate of capacitor C2. The gate of P2 is connected to the control signal V1, the source is connected to the auxiliary bit line BL1, and the drain is connected to the lower plate of capacitor C1 and the drain of P4 respectively. The gate of P3 is connected to the control signal V1, the source is connected to the auxiliary bit line BLB1, and the drain is connected to the lower plate of capacitor C2 and the drain of P5 respectively. The gate of P4 is connected to the control signal V2, the source is connected to the power supply VDD, and the drain is connected to the lower plate of capacitor C1 and the drain of P2 respectively. The gate of P5 is connected to the control signal V2, the source is connected to the power supply VDD, and the drain is connected to the lower plate of capacitor C2 and the drain of P3 respectively. The gate of P6 is connected to the control signal M1, the source is connected to the power supply VDD, and the drain is connected to the top plate of capacitor C1 and the drain of P0 respectively. The gate of P7 is connected to the control signal M1, the source is connected to the power supply VDD, and the drain is connected to the top plate of capacitor C2 and the drain of P1 respectively.

[0073] like Figure 7 As shown, the specific connection method for the sense amplifier module is as follows: the first-stage sense amplifier unit includes four PMOS transistors P02, P12, P22, and P32, and three NMOS transistors N02, N12, and N22. P02's gate is connected to N02's gate, and its source is connected to power supply VDD. P12's gate is connected to N12's gate, and its source is connected to VDD. P22's gate is connected to control signal SAE, its source is connected to main bit line BL, and its drain is connected to the drain of P02, the drain of N02, the gate of P12, and the gate of N12, respectively. P32's gate is connected to control signal SAE, and its drain is connected to the gate of P02, the drain of P12, the gate of N02, and the drain of N12, respectively. N02's gate is connected to the gate of P02, the drain of P12, the drain of P32, and the drain of N12, respectively, and its source is connected to the drain of N22. The gate of N12 is connected to the drain of P02, the gate of P12, the drain of P22, and the drain of N02, respectively, and the source is connected to the drain of N22. The gate of N22 is connected to the control signal SAE, and the source is connected to VSS.

[0074] The drain of P22 serves as the output OUT of the first-stage sensitive amplifier unit, and the drain of P32 serves as the other output OUTB of the first-stage sensitive amplifier unit. The source of P22 serves as the input of the first-stage sensitive amplifier unit and is connected to the drains of SK1 and SK2. The source of P32 serves as the other input of the first-stage sensitive amplifier unit and is connected to the drains of SK3 and SK4. SK2 and SK4 are controlled by control signal A, and SK1 and SK3 are controlled by the inverse of control signal A. The source of SK1 is connected to the output of the compensation module (out), the source of SK2 is connected to the output of the compensation module (bout), the source of SK3 is connected to the output of the compensation module (outb), and the source of SK3 is connected to a reference voltage (VREF).

[0075] The second-stage sensitive amplifier unit includes four PMOS transistors (P42, P52, P62, and P72) and three NMOS transistors (N32, N42, and N52). The gate of P42 is connected to the gate of N42, and its source is connected to the power supply VDD. The gate of P52 is connected to the gate of N52, and its source is connected to VDD. The gate of P62 is connected to the output terminal OUTB of the first-stage sensitive amplifier unit, and its drain is connected to the drain of P42, the drain of N32, the gate of P52, and the gate of N42, respectively. The gate of P72 is connected to the control signal SAE1, its source is connected to the reference voltage VREF, and its drain is connected to the gate of P42, the drain of P52, the gate of N32, and the drain of N42, respectively. The gate of N32 is connected to the gate of P42, the drain of P52, the drain of P72, and the drain of N42, respectively, and its source is connected to the drain of N52. The gate of N42 is connected to the drain of P42, the gate of P52, the drain of P62, and the drain of N32, respectively. Its source is connected to the drain of N52. The gate of N52 is connected to the control signal SAE1, and its source is connected to VSS. The drain of P62 serves as the output terminal OUT1 of the second-stage sensitive amplifier unit, and the drain of P72 serves as another output terminal OUTB1 of the second-stage sensitive amplifier unit. The source of P62 is connected to the output terminal boutb of the compensation module, and the source of P72 is connected to the reference voltage VREF.

[0076] like Figure 5 As shown, the specific connection method of the pre-charging unit is as follows: the pre-charging unit includes three PMOS tubes P31, P32, and P33; P31, P32, and P33 are controlled by the control signal PRE, the sources of P32 and P33 are connected to VDD, and the drains of P32 and P33 are connected to the bit lines BL and BLB or BL1 and BLB1 respectively; the source and drain of P31 are connected to the drains of P32 and P33 respectively.

[0077] Based on the above specific circuit structure, the operation modes of the normal read / write mode and the BCAM addressing mode are described below in combination with detailed circuit results.

[0078] 1. SRAM normal read and write mode

[0079] First, precharge the bit lines BL and BLB, BL1, and BLB1 to VDD. Then, turn on the word line WL of the SRAM cell to be read. At this time, BL and BLB are the main bit lines, and BL1 and BLB1 are auxiliary bit lines. Switch the compensation module and the sense amplifier module to normal read and write mode, first set the control signal V1 to a low level, and set M1 and V2 to a high level. At this time, the capacitor voltages of the upper and lower plates of C1 are the voltages of the bit lines BL and BL1, respectively. The capacitor voltages of the upper and lower plates of C2 are the voltages of the bit lines BLB and BLB1, respectively. Since BL and BLB are the main bit lines at this time, that is, the capacitor voltages of the upper plates of C1 and C2 are read, V1 is pulled up to a high level, and V2 is pulled down to a low level. At this time, the lower plates of C1 and C2 are compensated so that the voltage drop of C1 and C2 caused by the bit line current leakage is compensated back to VDD. Then adjust the sensitive amplifier module and set the control signal A to a high level. At this time, the inverse signal of A is a low level, so that SK1 and SK3 are turned on, and the first-stage sensitive amplifier unit is connected to the upper plate connection terminals out and outb of C1 and C2. When the sensitive amplifier is working, the control signal SAE is set to a low level and SAE1 is set to a high level. Only the first-stage sensitive amplifier unit works, and the voltages of BL and BLB are input to the first-stage sensitive amplifier unit. After amplifying the read and write results, they are output from the output terminals OUT and OUTB of the first-stage sensitive amplifier unit.

[0080] 2. BCAM addressing mode

[0081] First, precharge the bit lines BL and BLB, BL1, and BLB1 to VDD. Then, turn on the word lines LWL and RWL of the SRAM cell to be addressed. At this time, BL and BLB are auxiliary bit lines, and BL1 and BLB1 are main bit lines. Switch the compensation module and the sense amplifier module to the BCAM addressing mode, first set the control signal V1 to a low level, and set M1 and V2 to a high level. At this time, the capacitor voltages of the upper and lower plates of C1 are BL and BL1, respectively. The capacitor voltages of the upper and lower plates of C2 are BLB and BLB1, respectively. After the bit line addressing is completed, since BL1 and BLB1 are the main bit lines at this time, that is, the capacitor voltages of the lower plates of C1 and C2 are read, V1 is pulled up to a high level, and M1 is pulled down to a low level. At this time, the upper plates of C1 and C2 are compensated, so that the voltage drop of C1 and C2 caused by the bit line current leakage is compensated back to VDD. Then, the sensitive amplifier module is adjusted and the control signal A is set to a low level. At this time, the inverse signal of A is a high level, so that SK2 and SK4 are turned on, and one end of the first-stage sensitive amplifier unit and the second-stage sensitive amplifier unit are connected to the lower plate connection terminals bout and boutb of C1 and C2 respectively. When the sensitive amplifier is working, the control signal SAE is set to a low level and SAE1 is set to a low level. The first-stage sensitive amplifier unit and the second-stage sensitive amplifier unit are working, the voltage of BL1 is input to the first-stage sensitive amplifier unit, and the voltage of BLB1 is input to the second-stage sensitive amplifier unit. After amplifying the BCAM addressing result, it is output from the output terminal OUT1 of the second-stage sensitive amplifier unit.

[0082] The addressing determination method is as follows: if the search data matches the data stored in the search column (the data stored at point Q), the bit lines BL1 and BLB1 do not discharge, their voltages are both VDD, the OUT terminal output of the first-stage sensitive amplifier unit is high, the OUTB output is low, and the OUT1 output of the second-stage sensitive amplifier unit is high, indicating a match. If the search data does not match the data stored in the search column, one or both of the bit lines BL1 and BLB1 discharge. This causes the bit line voltage at this time to be lower than VREF. The sense amplifier output terminal OUT1 is low, indicating a mismatch. The sense amplifier module addressing output data table is shown below:

[0083] BCAM Addressing Output Data Table

[0084]

[0085]

[0086] As shown in the table above, in BCAM addressing mode, if only bit lines BL1 and BLB1 are not discharged, the searched column matches the addressed data, and OUT1 outputs a high level "1." If one or both bit lines are discharged, OUT1 outputs a low level "0." The searched column does not match the addressed data.

[0087] Based on the above design, the final circuit diagram provided by this embodiment including the storage module, compensation module, sense amplifier module and pre-charge module is as follows: Figure 9 It should be emphasized that: Figure 9 The solution is only one of the ways to protect the bit line leakage current compensation and BCAM multiplexing circuit in this case, and it is not a feature that limits the scope of protection of this case. Figure 9 The pre-charging unit is only one form of the pre-charging function provided in this embodiment. In other embodiments, other circuits with the same function composed of different components can still be designed to replace this circuit to achieve the same circuit function.

[0088] Performance Testing

[0089] To verify the effectiveness of the solution provided by this embodiment, this embodiment also designed the integrated circuit in Example 1 using the SMIC 55nm process on Cadence Virtuoso software, and conducted comprehensive tests on various performances of the circuit in a simulation system.

[0090] 1. If Figure 11 The figure shows the bit line voltage difference under different bit line leakage current conditions using a conventional SRAM circuit and the circuit provided by an embodiment of the present invention in a 55nm CMOS process. It can be seen that under simulation conditions of a 1.2V power supply voltage, a TT process angle, and a temperature of 25°C, after the precharge is completed (precharge ends at 2.0ns), the word line is turned on, and the BL terminal reads "1" and the BLB terminal reads "0". At this time, VBLB decreases. If there is no leakage, VBL>VBLB, and the bit line difference is greater than 0. Due to the leakage current at the BL terminal, which also exists when the word line is turned on, the VBL terminal voltage continues to decrease during this period. After the read operation is completed, the bit line difference decreases or even becomes negative compared to the case without leakage. This may lead to read errors. When the bit line leakage current compensation structure is implemented at 3.0ns, the bit line difference increases in a very short time. This effectively compensates for the bit line leakage current.

[0091] 2. If Figure 12Figure 2 shows the read times required for a conventional SRAM circuit (hereinafter referred to as CONV) and the circuit provided by an embodiment of the present invention under different bit line leakage currents, when the bit line difference reaches 200mV. (When the bit line difference is 200mV, the sense amplifier can amplify normally and has sufficient margin for the sense amplifier.) As can be seen, under simulation conditions of a 1.2V power supply voltage, a TT process angle, and a temperature of 25°C, the results show that when the leakage current is relatively low, the read time of the conventional SRAM circuit is slightly shorter than that of the circuit structure provided by the embodiment of the present invention. However, when the leakage current increases to approximately 10μA, the read time of the conventional SRAM circuit is longer than that of the circuit structure provided by the embodiment of the present invention. Furthermore, as the leakage current increases further, the read time of the conventional SRAM structure increases rapidly, while the read time of the circuit structure provided by the embodiment of the present invention remains essentially unchanged. Furthermore, under the same leakage current, the read time of the conventional SRAM structure is much longer than that of the circuit structure provided by the embodiment of the present invention.

[0092] In summary, the circuit structure provided in this embodiment effectively mitigates SRAM read efficiency degradation and failures caused by bitline leakage current. Even in the presence of high bitline leakage current, it can still read correct data, demonstrating stable performance. The leakage compensation circuit is capable of switching between normal read / write and BCAM addressing modes. In BCAM addressing mode, this structure can reduce addressing errors caused by leakage current. Furthermore, the mode-selectable sense amplifier module, comprised of two serial sense amplifiers in BCAM mode, eliminates the need for a two-input AND gate compared to conventional addressing decision modules, thereby reducing area.

[0093] Example 2

[0094] like Figure 13 As shown, this embodiment introduces a bit line leakage current compensation method, which is applied to the bit line leakage current compensation and BCAM multiplexing circuit as described above. The bit line leakage current compensation method includes the following steps:

[0095] Precharge the two pairs of bit lines BL, BLB and BL1, BLB1 to VDD;

[0096] The main bit line pair and the auxiliary bit line pair are determined according to the operation mode. The auxiliary bit lines perform leakage current detection on the main bit lines and make the following decisions based on the operation mode:

[0097] (1) When the operation mode is the normal read / write mode, BL and BLB are the main bit line pair, and BL1 and BLB1 are the auxiliary bit line pair; in the leakage compensation stage, the control signal V2 = VSS, M1 = VDD, and the VDD value is input to the capacitor plate connected to the auxiliary bit line pair BL1 and BLB1 to achieve the compensation operation;

[0098] (2) When the operation mode is BCAM mode, BL1 and BLB1 are main bit lines, and BL and BLB are auxiliary bit lines. In the leakage compensation stage, the control signal V2 = VDD, M1 = VSS, and the VDD value is input to the capacitor plates connected to the auxiliary bit line pair BL and BLB to realize the compensation operation.

[0099] It should be noted that after precharging, the main bitline pair discharges. If leakage current is present on the main bitline, an equal amount of leakage current should also be present on the corresponding auxiliary bitline. The auxiliary bitlines are used to detect the leakage current on the main bitline. The two pairs of bitlines on the same side are connected to the upper and lower plates of a capacitor. At this point, the upper and lower plate voltages of the capacitors on the same side of the bitline experiencing leakage current are identical, resulting in a zero capacitor voltage difference. Leakage compensation is then performed on the auxiliary bitline experiencing leakage (charging its voltage to VDD), thereby compensating for the leakage on the main bitline.

[0100] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A bit line leakage current compensation and BCAM multiplexing circuit, characterized in that: It includes a storage array composed of multiple SRAM cells and a compensation module; each column of SRAM cells shares a bit line and constitutes a basic storage module, and the compensation module is used to compensate for the bit line leakage current of the storage module; the compensation module includes 8 PMOS transistors P0 to P7 and 2 compensation capacitors C1 and C2; The upper plate of C1 is connected to the drains of P0 and P6, and the lower plate is connected to the drains of P4 and P2; the upper plate of C2 is connected to the drains of P1 and P7, and the lower plate is connected to the drains of P5 and P3; the sources of P4 to P7 are connected to the power supply VDD; the gates of P0 to P3 are controlled by the control signal V1, the gates of P4 and P5 are controlled by the control signal V2, and the gates of P6 and P7 are controlled by the control signal M1; the drains of P0 and P1 serve as two input terminals of the compensation module; the drains of P2 and P3 serve as the other two input terminals of the compensation module, respectively connected to the bit lines BL, BLB, BL1, and BLB1 on both sides of the storage module; Among them, the upper plate connection terminals out and outb of C1 and C2 serve as the output terminals after leakage compensation when the storage module performs normal read and write operations; the lower plate connection terminals bout and boutb of C1 and C2 serve as the output terminals after leakage compensation when the storage module performs BCAM addressing operations.

2. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 1, characterized in that: PMOS tubes P4~P7 serve as a mode selection module for implementing mode switching of the storage module. In the leakage compensation stage, when the control signal V2 of the compensation module is VSS and M1 is VDD, which is the normal read and write mode, the upper plate connection terminals out and outb of C1 and C2 output the results of the normal read and write operations performed by the storage module. When the control signal V2 of the compensation module is VDD and M1 is VSS, which is the BCAM addressing mode, the lower plate connection terminals bout and boutb of C1 and C2 output the results of the BCAM addressing operation performed by the storage module.

3. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 2, characterized in that: The bit line leakage current compensation and BCAM multiplexing circuit also includes a sensitive amplifier module; the sensitive amplifier module includes a first-stage sensitive amplifier unit, a second-stage sensitive amplifier unit, and four mode selection tubes SK1 to SK4; SK1 to SK4 are connected to the input end of the first-stage sensitive amplifier unit; one of the output ends of the first-stage sensitive amplifier unit is connected to the gate of one of the transmission tubes in the second-stage sensitive amplifier unit.

4. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 3, characterized in that: The first-stage sensitive amplifier unit includes four PMOS transistors P02, P12, P22, and P32, and three NMOS transistors N02, N12, and N22; the gate of P02 is connected to the gate of N02, the drain of N12, the drain of P12, and the drain of P32; the drain of P02 is connected to the drain of P22, the drain of N02, and the gate of P12 and the gate of N12; the sources of P02 and P12 are connected to VDD, the sources of N02 and N12 are connected to the drain of N22, the source of N22 is connected to VSS, and the gates of P22, P32, and N22 are controlled by a control signal SAE; Among them, the drain connection end of P22 serves as the output end OUT of the first-stage sensitive amplifier unit, and the drain connection end of P32 serves as the other output end OUTB of the first-stage sensitive amplifier unit; the source of P22 serves as the input end of the first-stage sensitive amplifier unit and is connected to the drains of SK1 and SK2, and the source of P32 serves as the other input end of the first-stage sensitive amplifier unit and is connected to the drains of SK3 and SK4. SK2 and SK4 are controlled by the control signal A, and SK1 and SK3 are controlled by the opposite signal of the control signal A; the source of SK1 is connected to the output end out of the compensation module, the source of SK2 is connected to the output end bout of the compensation module, the source of SK3 is connected to the output end outb of the compensation module, and the source of SK3 is connected to a reference voltage VREF.

5. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 4, characterized in that: The second-stage sensitive amplifier unit includes four PMOS transistors P42, P52, P62, and P72 and three NMOS transistors N32, N42, and N52; the gate of P42 is connected to the gate of N32, the drain of N42, the drain of P52, and the drain of P72; the gate of P52 is connected to the drain of P42, the drain of P62, the drain of N32, and the gate of N42; the drain of N52 is connected to the sources of N32 and N42; the sources of P42 and P52 are connected to VDD, and the source of N52 is connected to VSS; the gates of N52 and P72 are controlled by the control signal SAE1; P62 serves as a transmission tube of the sensitive amplifier and its gate is connected to the output terminal OUTB of the first-stage sensitive amplifier unit; Among them, the drain of P62 serves as the output end OUT1 of the second-stage sensitive amplifier unit, and the drain connection end of P72 serves as another output end OUTB1 of the second-stage sensitive amplifier unit; the source of P62 is connected to the output end boutb of the compensation module, and the source of P72 is connected to the reference voltage VREF.

6. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 5, characterized in that: The sensitive amplifier unit cooperates with the mode switching of the storage module to output the sensitive amplification result in the mode; when the storage module is in the normal read / write mode, the control signal A of the sensitive amplifier unit is set to a high level, SAE is normally enabled, and SAE1 is disabled; the first-stage sensitive amplifier unit works, and the second-stage sensitive amplifier unit does not work; the voltage signals of the result output terminals out and outb of the storage module are amplified, and the output terminals OUT and OUTB of the first-stage sensitive amplifier unit output the sensitive amplification result in the normal read / write mode; When the storage module is in the BCAM addressing operation, the control signal A of the sensitive amplifier unit is set to a low level, and the SAE and SAE1 enable signals are enabled normally; the first-stage sensitive amplifier unit and the second-stage sensitive amplifier unit operate normally, and the voltage signals of the storage module result output terminals bout and boutb are compared with the reference voltage VREF, and the output terminal OUT1 of the second-stage sensitive amplifier unit is used as the addressing signal matching signal in the BCAM addressing mode.

7. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 2, characterized in that: The SRAM cell adopts an 8T SRAM cell composed of 8 transistors; the 8T The SRAM cell includes two PMOS transistors P01 and P11 and six NMOS transistors N01, N11, N21, N31, N41, and N51; the gate of P01 is connected to the drain of P11, the gate of N01, the drain of N11, the source of N41, and the source of N51, and the gate of P11 is connected to the drain of P01, the drain of N01, the gate of N11, the source of N21, and the source of N31; the sources of P01 and P11 are connected to VDD, and the sources of N01 and N11 are connected to VSS; the gates of N21 and N41 are connected to the word line WL, the gate of N31 is connected to the word line LWL, and the gate of N41 is connected to the word line RWL; the drain of N21 is connected to the bit line BL, the drain of N31 is connected to the bit line BL1, the drain of N41 is connected to the bit line BLB, and the drain of N51 is connected to the bit line BLB1.

8. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 7, characterized in that: The two pairs of bit lines BL, BLB and BL1, BLB1 of the storage module are connected to the pre-charge module; the pre-charge module is composed of multiple pre-charge units, and one pre-charge unit corresponds to a pair of bit lines; the pre-charge unit includes three PMOS tubes P31, P32, and P33; P31, P32, and P33 are controlled by a control signal PRE, the sources of P32 and P33 are connected to VDD, and the drains of P32 and P33 are respectively connected to one of the pairs of bit lines of the storage module; the source and drain of P31 are respectively connected to the drains of P32 and P33.

9. The bit line leakage current compensation and BCAM multiplexing circuit according to claim 7, characterized in that: When the memory module performs normal read and write operations, the word line WL=VDD, RWL=LWL=VSS, and the bit lines BL and BLB serve as main bit lines, and BL1 and BLB1 serve as auxiliary bit lines. When the memory module performs a BCAM addressing operation, the word line WL is set to VSS, and the word line signals of RWL and LWL are used as an input pair of searched data. At this time, the bit lines BL and BLB are used as auxiliary bit lines, and BL1 and BLB1 are used as main bit lines.

10. A bit line leakage current compensation method, characterized in that: The method is applied to the bit line leakage current compensation and BCAM multiplexing circuit according to any one of claims 1 to 9, wherein the bit line leakage current compensation method comprises the following steps: Precharge the two pairs of bit lines BL, BLB and BL1, BLB1 to VDD; The main bit line pair and the auxiliary bit line pair are determined according to the operation mode. The auxiliary bit lines perform leakage current detection on the main bit lines and make the following decisions based on the operation mode: (1) When the operation mode is normal read / write mode, BL and BLB are the main bit line pair, and BL1 and BLB1 are the auxiliary bit line pair; in the leakage compensation stage, the control signal V2 = VSS, M1 = VDD, and the VDD value is input to the capacitor plate connected to the auxiliary bit line pair BL1 and BLB1 to realize the compensation operation; (2) When the operation mode is BCAM mode, BL1 and BLB1 are main bit lines, and BL and BLB are auxiliary bit lines. In the leakage compensation stage, the control signal V2 = VDD, M1 = VSS, and the VDD value is input to the capacitor plates connected to the auxiliary bit line pair BL and BLB to realize the compensation operation.

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