An etching method and a preparation method of a semiconductor device

Abstract

This invention discloses an etching method and a method for fabricating semiconductor devices. The etching method includes: depositing a first barrier layer on the surface of a SiC substrate; etching the first barrier layer using a first etching gas to form multiple first openings; and forming a protective layer on the SiC substrate to prevent the SiC substrate from being etched. The first etching gas includes a carbon-fluorine based gas and a gas containing hydrogen. This invention reduces the over-etching of the underlying SiC layer during the opening process of the barrier layer on the SiC substrate, thereby improving the performance and manufacturing yield of subsequent semiconductor devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing, and more specifically, relates to an etching method and a method for preparing semiconductor devices. Background Technology

[0002] As a third-generation wide-bandgap semiconductor, SiC possesses a series of characteristics such as high breakdown electric field, large bandgap, fast migration speed of saturated electrons, and high thermal conductivity. Based on these advantages, SiC has become the most promising material in the field of power electronics.

[0003] Currently, SiC power devices include metal-oxide-semiconductor field-effect transistors (MOSFETs) used in applications above 900V to replace silicon insulated gate bipolar transistors (IGBTs), and Schottky diodes (SBDs) used in applications above 600V to replace silicon fast recovery diodes (FRDs). At present, the commercial application of SiC power devices in the domestic and international markets is still dominated by Schottky diodes (SBDs).

[0004] In the fabrication of SiC SBD devices, ion implantation, as a key process directly affecting device performance, is continuously optimized throughout the fabrication process. Under the same energy conditions, the depth and width of ion implantation directly affect the device's breakdown voltage performance. Therefore, the SiO2 opening process in the ion implantation region becomes a very important step. This process requires that the N-type SiC in the underlying ion implantation region be virtually free of over-etching during the SiO2 opening process; otherwise, it will directly affect the ion implantation depth. Therefore, achieving a high selectivity (>15) for the underlying Nx-type SiC without affecting the device's electrical properties during the SiO2 opening process is a significant challenge.

[0005] Existing SiC SBD device fabrication methods often involve adding CO to a C4F8 or C4F8+Ar gas system during the etching of SiO2 material to improve the etching selectivity of SiO2 for SiC. However, this method only achieves a maximum selectivity of 2-3 for SiO2 in the C4F8 gas system and a maximum selectivity of 6 in the C4F8+Ar gas system. This maximum selectivity of only 6 in both systems leads to excessive over-etching of the N-type SiC in the underlying ion implantation region, resulting in insufficient subsequent ion implantation depth and consequently affecting the performance and yield of the SBD device. Furthermore, the impact of CO addition on electrical properties is unknown. Summary of the Invention

[0006] The purpose of this invention is to propose an etching method and a semiconductor device fabrication method, which reduces the amount of over-etching of the underlying SiC layer when performing an opening process on the barrier layer on the SiC substrate, thereby improving the performance and manufacturing yield of the subsequent semiconductor devices.

[0007] In a first aspect, the present invention provides an etching method, comprising:

[0008] A first barrier layer is deposited on the surface of a SiC substrate;

[0009] The first barrier layer is etched using a first etching gas to form a plurality of first openings, and a protective layer is formed on the SiC substrate to prevent the SiC substrate from being etched. The first etching gas includes a carbon-fluorine gas and a gas containing H.

[0010] Optionally, the gas containing H is a gas that does not contain F;

[0011] Alternatively, the gas containing H may be a gas containing F, wherein the ratio of H to F is greater than or equal to 2.

[0012] Optionally, before etching the first barrier layer with the first etching gas to form a plurality of first openings and forming a protective layer on the SiC substrate, the method further includes:

[0013] The first barrier layer is etched to a set depth using a second etching gas.

[0014] Optionally, the set depth is 1 / 4 to 1 / 5 of the total etching depth of the first barrier layer.

[0015] Optionally, after etching the first barrier layer with a first etching gas to form a plurality of first openings and forming a protective layer on the SiC substrate, the method further includes:

[0016] The protective layer is removed using a processing gas that reacts with the protective layer.

[0017] Optionally, the fluorocarbon gas includes at least one of CHF3, CF4, and C4F8.

[0018] Optionally, the gas containing H element includes at least one of H2, CH4, CH3F, and C2H2.

[0019] Optionally, the protective layer is a carbon thin film layer, and the processing gas includes O2.

[0020] Optionally, the material of the first barrier layer is silicon oxide or silicon nitride.

[0021] Optionally, the first etching gas and / or the second etching gas may further include a physical bombardment gas.

[0022] Optionally, the process parameters used to etch the first barrier layer with the first etching gas to form a plurality of first openings and to form a protective layer on the SiC substrate include:

[0023] The flow rate range of the fluorocarbon gas is 50-200 sccm;

[0024] The flow rate range of the gas containing H is 50-200 sccm;

[0025] The pressure range of the process chamber is 1-20 mTorr;

[0026] The power range of the upper electrode center is 1-500W;

[0027] The power range of the upper electrode edge is 500-3000W;

[0028] The power range of the lower electrode is 100-1000W.

[0029] Optionally, the process parameters used to remove the protective layer using oxidizing gas include:

[0030] The chamber pressure range is 1-10 mTorr;

[0031] The power range of the upper electrode center is 1-300W;

[0032] The power range of the upper electrode edge is 100-800W;

[0033] The power range is 10-50W;

[0034] The O2 flow rate range is 20-100 sccm.

[0035] In a second aspect, the present invention provides a method for fabricating a semiconductor device, comprising:

[0036] The first barrier layer is etched using the etching method described in any one of the first aspects, wherein the SiC substrate includes a SiC substrate body layer and a SiC epitaxial layer, and the first impedance layer is formed on the upper surface of the SiC epitaxial layer;

[0037] Ion implantation and ion activation are performed on the surface of the SiC epitaxial layer exposed by the multiple first openings to form multiple doped regions in the SiC epitaxial layer, wherein some doped regions are located in the active region and the remaining doped regions are located in the terminal region.

[0038] Remove the first barrier layer;

[0039] A first metal layer is formed on the doped region located in the active region, and a second metal layer is formed on the back side of the SiC substrate;

[0040] A third metal layer is formed on the SiC epitaxial layer located in the active region, and a first electrode layer is formed on the third metal layer. The third metal layer covers the first electrode layer and forms a Schottky contact with the surface of the SiC epitaxial layer.

[0041] A first dielectric layer is formed on the SiC epitaxial layer located in the terminal region, and a passivation layer is formed on the first dielectric layer;

[0042] A back electrode layer is formed on the surface of the second metal layer.

[0043] Optionally, the SiC epitaxial layer is an N-type SiC epitaxial layer, and the ion implantation is a P-type ion implantation;

[0044] Alternatively, the SiC epitaxial layer is a P-type SiC epitaxial layer, and the ion implantation is an N-type ion implantation.

[0045] The beneficial effects of this invention are as follows:

[0046] The etching method of the present invention uses carbon-fluorine gas and a gas containing H as etching gas when etching the barrier layer on the SiC substrate to form an opening. While etching the barrier layer to form an opening, a protective layer can be formed on the SiC surface exposed at the bottom of the opening. This protective layer effectively prevents the SiC from being over-etched, thereby reducing the amount of over-etching of the underlying SiC when forming an opening on the barrier layer on the SiC layer, and thus improving the performance and manufacturing yield of subsequent semiconductor devices.

[0047] The semiconductor device fabrication method of the present invention adopts the etching method of the first aspect. When etching the barrier layer on the SiC epitaxial layer to open the ion implantation region, the over-etching of the SiC epitaxial layer in the lower ion implantation region is effectively reduced, thereby ensuring sufficient ion implantation depth and improving the performance and manufacturing yield of the subsequent semiconductor device.

[0048] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0049] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0050] Figure 1 A diagram showing the steps of an etching method according to Embodiment 1 of the present invention is provided.

[0051] Figure 2 The graph shows the effect of H2 on the etching rate and the selectivity ratio of SiO2 to SiC in an etching method according to Embodiment 1 of the present invention.

[0052] Figure 3 The graph shows the effect of the proportion of H2 in the etching gas on the selectivity ratio of SiO2 to SiC in different CD regions in an etching method according to Embodiment 1 of the present invention.

[0053] Figure 4 This invention presents an electron microscope (EM) image and a vertical EDX analysis image (i.e., surface EDX analysis image) of the SiC surface carbon deposition before oxidation treatment in an etching method according to Embodiment 1 of the present invention.

[0054] Figure 5 The image shows an electron microscope (EM) image and a vertical EDX analysis image of the carbon deposition on the SiC surface after oxidation treatment in an etching method according to Embodiment 1 of the present invention, i.e., the surface EDX analysis image.

[0055] Figure 6 The image shows an electron microscope (EM) image of the etching result of the opening of the first barrier layer in an etching method according to Embodiment 1 of the present invention.

[0056] Figure 7 The diagram shows the device structure corresponding to each step of the preparation method of a semiconductor device according to Embodiment 2 of the present invention. Detailed Implementation

[0057] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0058] Example 1

[0059] like Figure 1 As shown, an etching method in this embodiment includes:

[0060] S101: Deposit a first barrier layer on the surface of a SiC substrate;

[0061] Specifically, a first barrier layer can be deposited on the surface of an N-type SiC epitaxial layer using a PECVD process. The material of the first barrier layer is silicon oxide or silicon nitride. Then, photoresist (PR) is spin-coated onto the surface of the first barrier layer and PR photolithography is performed to form a patterned photoresist layer.

[0062] S102: Use the second etching gas to etch the first barrier layer to a set depth. Preferably, the set depth is 1 / 4 to 1 / 5 of the total etching depth of the first barrier layer.

[0063] Specifically, the purpose of this step is to ensure the etching rate of the opening while obtaining the desired morphology, depth, and CD (Critical Dimension) value. The second etching gas in this step includes a fluorocarbon gas, which may include at least one of CHF3, CF4, and C4F8; in this embodiment, CHF3 and CF4 are preferred. Preferably, the second etching gas also includes a physical bombardment gas for adjusting the etching morphology; the physical bombardment gas may be Ar or N2.

[0064] The specific process parameters used in this step include:

[0065] The flow rate range for CF4 is 50-70 sccm, with 60 sccm being preferred.

[0066] The flow rate range for CH3F is 10-30 sccm, preferably 20 sccm;

[0067] The flow rate range for Ar is 15-35 sccm, with 25 sccm being preferred.

[0068] The chamber pressure range is 1-20 mT, preferably 1 mT;

[0069] The core power range of the upper electrode is 1-500W, preferably 1W;

[0070] The power range at the edge of the upper electrode is 500-3000W, preferably 1500W.

[0071] The lower electrode power range is 100-1000W, preferably 300W.

[0072] The lower electrode temperature range is 0-30℃, preferably 12℃.

[0073] S103: The first barrier layer is etched using a first etching gas to form multiple first openings, and a protective layer is formed on the SiC substrate. The protective layer is used to prevent the SiC substrate from being etched. The first etching gas includes carbon-fluorine gas and gas containing H element.

[0074] Specifically, the first etching gas contains at least one of the carbon-fluorine gases, including CHF3, CF4, and C4F8, with CHF3 being preferred in this embodiment.

[0075] The first etching gas containing H is a gas that does not contain F; or, the gas containing H is a gas containing F, wherein the ratio of H to F is greater than or equal to 2.

[0076] More specifically, the gas containing H includes at least one of H2, CH4, CH3F, and C2H2. In this embodiment, H2 is preferred.

[0077] Preferably, the first etching gas also includes a physical bombardment gas, such as Ar or N2.

[0078] The process parameters for this step include:

[0079] The flow rate range for CHF3 is 50-200 sccm, with 130 sccm being preferred.

[0080] The H2 flow rate range is 50-200 sccm, with 72 sccm being preferred.

[0081] The Ar flow rate range is 5-50 sccm, with 10 sccm being preferred.

[0082] The chamber pressure range is 1-20 mTorr, preferably 6 mT;

[0083] The power range of the upper electrode center is 1-500W, preferably 1W;

[0084] The power range of the upper electrode edge is 500-3000W, preferably 1200W;

[0085] The power range of the lower electrode is 100-1000W, preferably 400W;

[0086] The lower electrode temperature range is 0℃-30℃, preferably 2℃.

[0087] There is no limit to the process time; it can be set according to the required etching depth.

[0088] The purpose of this step is to etch the first barrier layer to form the desired opening morphology while simultaneously forming a protective layer on the SiC surface at the bottom of the opening, thereby preventing or reducing over-etching of the SiC.

[0089] CHF3 in the first etching gas is the main chemical etching gas, Ar mainly plays the role of physical etching, which is used to break Si-O bonds to carry out chemical reactions, and H2 mainly plays the role of increasing the selectivity of SiO2 for SiC.

[0090] The specific principle behind the formation of the protective layer is as follows:

[0091] During the etching process in this step, CHF3 gas ionizes to produce CF* and F. -The activated CF* in the HF gas dissociates and adsorbs on the SiO2 surface of the first barrier layer, thus undergoing a chemical reaction to generate SiF4 gas, CO2 gas, and CO gas, which is then extracted from the chamber. When CF* is deposited on the surface of SiC, it reacts with SiC to generate carbon deposited on the surface of the SiC material, but F... - It will react with the generated carbon, accelerating the etching rate of SiC while reducing carbon deposition. Therefore, H2 is added to the first etching gas in this step. After H2 ionizes, H2 is generated. + F produced after ionization with CHF3 gas - The HF gas produced is then removed, thereby reducing the amount of F. - The amount of carbon deposited not only reduces the etching rate of SiC, but also increases the amount of carbon deposited, thereby forming a carbon thin film protective layer on the SiC surface. This prevents further etching of SiC by the first etching gas, avoids over-etching of SiC, and improves the selectivity of SiO2 for SiC.

[0092] The specific reaction mechanism is as follows:

[0093] The mechanism by which the selectivity of SiO2 for SiC is increased in the CHF3+H2 gas system lies in the elimination of fluoride ions by hydrogen ions to generate HF(Gas).

[0094] CHF3(Gas)+e - →CF*+F - +HF(Gas)

[0095] H2(Gas) + e- → 2H +

[0096] H + +F - →HF(Gas)

[0097] CF*+SiO2→SiF4(Gas)+CO(Gas)+CO2(Gas)

[0098] CF* + SiC → SiF(Gas) + C(S)

[0099] The proportion window of H2 gas added to the first etching gas was adjusted, and the result is as follows: Figure 2 and Figure 3 As shown, by Figure 2 It can be seen that the selectivity is significantly improved after adding H2, and the etching rates of both SiO2 and SiC decrease with increasing H2 ratio, but the etching rate (RE) of SiC decreases more significantly. Therefore, the selectivity (Sel) of SiO2 for SiC shows an increasing trend. However, for regions with different opening CDs on SiC devices (such as the active region and the field-confined region), such as... Figure 3As shown, with the increase of H2 ratio, the selectivity of SiO2 for SiC increases, and the trend is basically the same. However, the addition of H2 has little effect on the etching morphology of SiO2, and the etching morphology still meets the etching requirements.

[0100] In other embodiments, CHF3 gas in the first etching gas can be replaced with CF4 or C4F8, physical etching gas can be replaced with N2, and H-containing gas to improve selectivity can be replaced with other gases with high H* content after ionization, such as CH4, CH3F or C2H2, i.e., a gas combination of CF4 / C4F8+Ar / N2+CH4 / CH3F / C2H2. In this embodiment, the gas combination of CHF3+Ar+H2 is preferred.

[0101] In this embodiment, after etching the first barrier layer with the first etching gas to form a plurality of first openings and forming a protective layer on the SiC substrate, the method further includes:

[0102] S104: The protective layer is removed using a processing gas that can react with the protective layer.

[0103] The gas being processed can be O2, HeO2, or CO, and in this embodiment, O2 is preferred.

[0104] In this embodiment, O2 is selected as the processing gas to oxidize the previously formed protective layer, thereby removing the protective layer and preventing the carbon film layer from affecting subsequent processes (such as the depth and concentration of ion implantation).

[0105] The process parameters used in this step include:

[0106] The chamber pressure range is 1-10 mTorr, preferably 6 Mt;

[0107] The power range of the upper electrode center is 1-300W, preferably 1W;

[0108] The power range of the upper electrode edge is 100-800W, preferably 400W;

[0109] The power range is 10-50W, preferably 30W;

[0110] The O2 flow rate range is 20-100 sccm, preferably 50 sccm;

[0111] The lower electrode temperature range is 0℃-30℃, preferably 12℃;

[0112] The process time ranges from 30s to 90s.

[0113] The reaction mechanism for removing the protective layer in this step is as follows:

[0114] C + O₂ → CO(Gas) + CO₂(Gas)

[0115] Specifically, after step S103, a significant amount of carbon (i.e., a protective layer) will be generated on the surface of the SiC material. This carbon film-like substance is deposited on the surface of the material. This carbon film needs to be thoroughly removed promptly; otherwise, it will affect subsequent processes (such as the depth and concentration of ion implantation), directly impacting the device's electrical properties and yield. The effectiveness of wet removal of this carbon film is very limited, and it is difficult to observe whether it has been completely removed. In this embodiment, TEM (Transmission Electron Microscope) was used to analyze the carbon deposition on the SiC surface. As shown in Table 1, the key factor affecting electrical properties was identified: the introduction of H2 in step S103 to form C deposition, which affects device yield. A suitable removal solution was found: oxidation treatment in step S104. The TEM image, vertical EDX analysis, and surface EDX analysis of the SiC surface carbon deposition before oxidation treatment are shown in Table 1. Figure 4 As shown in (a), (b), and (c), the electron micrographs, vertical EDX analysis, and surface EDX analysis of the carbon deposition on the SiC surface after oxidation treatment are respectively as follows: Figure 5 As shown in (a), (b), and (c).

[0116] Table 1. Surface carbon deposition depth and device yield:

[0117]

[0118] The method in this embodiment analyzes the possible factors that affect the electrical properties of the device during the etching process and provides targeted solutions, thereby effectively solving the problems of excessive SiO2 etching on the underlying SiC layer and the device yield problem caused by the introduction of H2 or gases with high H* content after ionization during the SiC device fabrication process.

[0119] The preferred process formulations for steps S102-S104 in this embodiment are shown in Table 2.

[0120] Table 2: Etching Process Formulation Table

[0121]

[0122] Using the above process formulation (distinct from existing technologies, employing three gases for etching), the etching step S103 can achieve the following: Figure 6 The etching morphology of the first barrier layer (SiO2) is shown. Figure 6In the image (a), the etching morphology of the first region (active region) of the SiC device is shown, and in the image (b), the morphology of the second region (field confinement region) that is complementary to the first region is shown. The second region has a high selectivity for the underlying SiC layer (up to >15). The electrical properties of the SiC device can then be ensured to remain unaffected by the oxidation process step S104.

[0123] Example 2

[0124] like Figure 7 As shown, this embodiment provides a method for fabricating a semiconductor device, specifically a method for fabricating a SiC Schottky diode. This method includes the following steps:

[0125] S1: The first barrier layer is etched using the etching method of Example 1, wherein the SiC substrate includes a SiC substrate body layer and a SiC epitaxial layer, and the first impedance layer is formed on the upper surface of the SiC epitaxial layer;

[0126] In this embodiment, the SiC substrate includes a SiC substrate body layer and a SiC epitaxial layer, with a first impedance layer formed on the upper surface of the SiC epitaxial layer. The SiC epitaxial layer is an N-type SiC epitaxial layer, and the subsequent ion implantation is P-type ion implantation. In other embodiments, the SiC epitaxial layer may also be a P-type SiC epitaxial layer, with the corresponding subsequent ion implantation being N-type ion implantation. This embodiment uses an N-type SiC epitaxial layer and P-type ion implantation as an example for illustration.

[0127] Referring to step S101 of Example 1, a first barrier layer is deposited on the surface of the SiC substrate. Figure 7 As shown in P1-P4, the specific fabrication process of the SiC substrate and the first barrier layer in this embodiment is as follows:

[0128] First, an N-type SiC epitaxial layer is epitaxially grown on the SiC substrate using a CVD process. Then, a first barrier layer is deposited on the surface of the N-type SiC epitaxial layer using a PECVD process. The material of the first barrier layer is SiO2, preferably N2O+N2+SiH4, deposited at 300°C with a deposition rate of 45 nm / min and a deposition thickness of 1.5-2 μm. The uniformity of the deposited first barrier layer is <3%, and the number of contaminant particles with a diameter >0.3 μm on the surface of the first barrier layer is less than 30. Next, photoresist (PR) is spin-coated onto the surface of the first barrier layer and PR photolithography is performed to form a patterned first photoresist layer.

[0129] The SiO2 opening formed in the preset area of ​​the first barrier layer in this step is to open the window for P-type implantation. This step requires that the sidewalls of the etched opening morphology be vertical (>88°), without footing (wide bottom) and trench (bottom micro-groove) structures, and without over-etching the underlying N-type SiC.

[0130] Therefore, this step uses the etching method of steps S102-S104 in Example 1 to perform opening etching on the first impedance layer on the SiC substrate, such as... Figure 7 As shown on page 5.

[0131] Specifically, the process formulation of steps S102-S103 in Example 1 is first used to perform opening etching on the first barrier layer. During the opening etching of SiO2, a carbon thin film protective layer can be formed on the exposed N-type SiC surface, thereby preventing the first etching gas from further etching the SiC and effectively reducing the over-etching amount of the lower N-type SiC.

[0132] Then, using the method and process formulation of step S104 in Example 1, the deposited carbon thin film protective layer is completely removed by oxidation treatment to avoid the carbon thin film protective layer affecting the depth and concentration of subsequent ion implantation, thus ensuring the electrical properties and yield of the device.

[0133] S2: Ion implantation and ion activation are performed on the surface of the SiC epitaxial layer with multiple first openings to form multiple doped regions in the SiC epitaxial layer, some of which are located in the active region and the rest are located in the terminal region.

[0134] Specifically, such as Figure 7 As shown in P6, P-type ion implantation was performed on the surface of the N-type SiC epitaxial layer exposed by the first opening, and high-temperature activation was carried out at 1600-1800℃.

[0135] S3: Remove the first blocking layer;

[0136] Specifically, the first barrier layer can be removed by etching or grinding processes.

[0137] S4: A first metal layer is formed on the doped region located in the active region, and a second metal layer is formed on the back side of the SiC substrate;

[0138] This step specifically includes:

[0139] S401: A second barrier layer is formed on the N-type SiC epitaxial layer. The material of the second barrier layer is SiO2, such as... Figure 7 As shown on page 7;

[0140] S402: A patterned second photoresist layer is formed on the second barrier layer, such as... Figure 7 As shown on page 8; the method for forming the patterned second photoresist layer can refer to the method for forming the first photoresist layer in step S201.

[0141] S403: Etch the second barrier layer to form multiple second openings exposing multiple P-type doped regions located in the N-type active region, such as... Figure 7As shown on page 9; the second opening can be formed by a dry etching process, and the specific process parameters can be referred to step S102 of Example 1.

[0142] S404: A first metal layer is formed, which covers the second photoresist layer and the surface of the P-type doped region exposed by the second opening. A second metal layer is also formed on the back side of the SiC substrate. Figure 7 As shown on page 10; the first metal layer may include multiple metal layers of different materials, and the first metal layer and the second metal layer can be formed by PVD deposition process.

[0143] S405: Remove the first metal layer and the second photoresist layer on the second barrier layer; the first metal layer and the second photoresist layer on the second photoresist layer can be removed by dry etching.

[0144] S406: A high-temperature annealing process is performed on the substrate to form an ohmic contact between the first metal layer located on the P-type doped region and the second metal layer with the SiC substrate. Figure 7 As shown on page 11;

[0145] S407: Remove the second barrier layer, such as Figure 7 As shown on page 12, the second barrier layer can be removed using BOE (Buffered Oxide Etch).

[0146] S5: A third metal layer is formed on the SiC epitaxial layer located in the active region, and a first electrode layer is formed on the third metal layer. The third metal layer covers the first electrode layer and forms a Schottky contact with the surface of the SiC epitaxial layer.

[0147] This step specifically includes:

[0148] S501: A third metal layer is formed covering the N-type SiC epitaxial layer and the first metal layer. The material of the third metal layer is Ti.

[0149] S502: A Schottky contact is formed between the third metal layer and the N-type SiC epitaxial layer through a high-temperature annealing process.

[0150] S503: A first electrode layer is formed on the third metal layer, the material of the first electrode layer being Al. The above steps are as follows: Figure 7 As shown on page 13.

[0151] S504: Remove the third metal layer and the first electrode layer above the N-type SiC epitaxial layer in the termination region, exposing the N-type SiC epitaxial layer and the P-type doped region in the termination region. Wet etching can be used to remove the third metal layer and the first electrode layer on the termination structure, such as... Figure 7 As shown on page 14.

[0152] S6: A first dielectric layer is formed on the SiC epitaxial layer located in the terminal region, and a passivation layer is formed on the first dielectric layer;

[0153] Specifically, this step includes:

[0154] S601: Forming a first dielectric layer, the first dielectric layer covering the N-type SiC epitaxial layer located in the terminal region and the first electrode layer; the material of the first dielectric layer is SiO2;

[0155] S602: A passivation layer is formed on the first dielectric layer; the passivation layer material is preferably polyimide.

[0156] S603: Remove a portion of the first dielectric layer and passivation layer above the first electrode layer to form a contact area of ​​the first electrode layer, such as... Figure 7 As shown on page 15.

[0157] S7: Form a back electrode layer on the surface of the second metal layer.

[0158] like Figure 7 As shown on page 16, a back electrode layer is finally deposited on the surface of the second metal layer using a PVD process. The material of the back electrode layer can be Ti, Ni, or Ag.

[0159] The semiconductor device fabrication method of this embodiment employs the etching method of Example 1 during the ion implantation region opening etching process of the first barrier layer, that is, by adding H2 or H2-containing ionized gas to the etching gas. * High concentrations of gases, such as H2, CH4, CH3F, and C2H2, cause the F in the chamber to ionize. - Concentration decreases, CF - Upon increasing concentration, the SiO2 adsorbs onto the SiC surface, forming SiF4 to expel the chamber and depositing a carbon layer on the SiC surface to hinder further etching, thereby improving the selectivity of SiO2 for SiC. Simultaneously, the study demonstrated the reason for the low yield of SiC devices after adding H2 or ionized gases with high H* content to the etching gas, and introduced targeted post-processing steps to remove the carbon-like film deposited on the SiC surface, thus ensuring the yield of SiC devices.

[0160] The method of this invention offers valuable insights for improving the performance of SiC SBD devices without altering the hardware. It addresses the problem of insufficient ion implantation depth and consequently poor breakdown voltage performance caused by low selectivity of the underlying N-type SiC layer during the current SiC SBD device fabrication process with a SiO2 opening in the P-type implantation region. This is achieved while ensuring that the device yield remains unaffected. The SiC devices fabricated using this method exhibit excellent breakdown voltage performance because the ion implantation depth and concentration in the P-type ion implantation region of the N-type SiC epitaxial layer are sufficiently guaranteed.

[0161] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. An etching method, characterized in that, include: A first barrier layer is deposited on the surface of a SiC substrate; The first barrier layer is etched using a first etching gas to form a plurality of first openings, and a protective layer is formed on the SiC substrate. The protective layer is used to prevent the SiC substrate from being etched. The first etching gas includes a carbon-fluorine gas and a gas containing H. The process parameters used to etch the first barrier layer with a first etching gas to form multiple first openings and to form a protective layer on the SiC substrate include: The power range of the upper electrode center is 1-500 W; The power range of the upper electrode edge is 500-3000 W.

2. The etching method according to claim 1, characterized in that, The gas containing H is a gas that does not contain F; Alternatively, the gas containing H may be a gas containing F, wherein the ratio of H to F is greater than or equal to 2.

3. The etching method according to claim 1, characterized in that, Before etching the first barrier layer with a first etching gas to form a plurality of first openings and forming a protective layer on the SiC substrate, the method further includes: The first barrier layer is etched to a set depth using a second etching gas.

4. The etching method according to claim 3, characterized in that, The set depth is 1 / 4 to 1 / 5 of the total etching depth of the first barrier layer.

5. The etching method according to claim 1, characterized in that, After etching the first barrier layer with a first etching gas to form a plurality of first openings and forming a protective layer on the SiC substrate, the process further includes: The protective layer is removed using a processing gas that reacts with the protective layer.

6. The etching method according to claim 1, characterized in that, The fluorocarbon gases include at least one of CHF3, CF4, and C4F8.

7. The etching method according to claim 2, characterized in that, The gas containing H element includes at least one of H2, CH4, CH3F, and C2H2.

8. The etching method according to claim 5, characterized in that, The protective layer is a carbon thin film layer, and the processing gas includes O2.

9. The etching method according to claim 1, characterized in that, The material of the first barrier layer is silicon oxide or silicon nitride.

10. The etching method according to claim 3, characterized in that, The first etching gas and / or the second etching gas further include a physical bombardment gas.

11. The etching method according to claim 1, characterized in that, The process parameters used to etch the first barrier layer with a first etching gas to form multiple first openings and to form a protective layer on the SiC substrate include: The flow rate range of the fluorocarbon gas is 50-200 sccm; The flow rate range of the gas containing H is 50-200 sccm; The pressure range of the process chamber is 1-20 mTorr; The lower electrode power range is 100-1000 W.

12. The etching method according to claim 5, characterized in that, The process parameters used to remove the protective layer using the processing gas include: The chamber pressure range is 1-10 mTorr; The power range of the upper electrode center is 1-300 W; The power range of the upper electrode edge is 100-800 W; The power range is 10-50 W; The O2 flow rate range is 20-100 sccm.

13. A method for fabricating a semiconductor device, characterized in that, include: The first barrier layer is etched using the etching method according to any one of claims 1-12, wherein the SiC substrate includes a SiC substrate body layer and a SiC epitaxial layer, and the first barrier layer is formed on the upper surface of the SiC epitaxial layer; Ion implantation and ion activation are performed on the surface of the SiC epitaxial layer exposed by the first openings to form multiple doped regions in the SiC epitaxial layer, wherein some doped regions are located in the active region and the remaining doped regions are located in the terminal region. Remove the first barrier layer; A first metal layer is formed on the doped region located in the active region, and a second metal layer is formed on the back side of the SiC substrate; A third metal layer is formed on the SiC epitaxial layer located in the active region, and a first electrode layer is formed on the third metal layer. The third metal layer covers the first electrode layer and forms a Schottky contact with the surface of the SiC epitaxial layer. A first dielectric layer is formed on the SiC epitaxial layer located in the terminal region, and a passivation layer is formed on the first dielectric layer; A back electrode layer is formed on the surface of the second metal layer.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The SiC epitaxial layer is an N-type SiC epitaxial layer, and the ion implantation is a P-type ion implantation; Alternatively, the SiC epitaxial layer is a P-type SiC epitaxial layer, and the ion implantation is an N-type ion implantation.

Images