A semiconductor test structure and a method for locating a break failure

Abstract

The application provides a semiconductor test structure and a breakpoint failure positioning method. The semiconductor test structure comprises a first metal layer, a plurality of first sub-metal blocks arranged in a matrix along an X direction and a Y direction; a second metal layer, a plurality of second sub-metal blocks arranged in the X direction and the Y direction and arranged above the first sub-metal blocks in a staggered manner, the first sub-metal block and the second sub-metal block adjacent to the first sub-metal block in the staggered manner are connected in a head-to-tail manner through a conductive via to form a plurality of interconnected parallel and head-to-tail chain structures; and a dummy metal filling layer, a plurality of identification marks located at the periphery of the chain structure. Obviously, the semiconductor test structure provided by the application is that a plurality of identification marks are newly formed in the X direction and the Y direction in the dummy metal filling layer formed at the periphery of at least two asymmetric sides of the existing test structure for breakpoint failure analysis through filling or etching.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor testing structure and a failure location method. Background Technology

[0002] Open-circuit failure is the most common failure phenomenon in semiconductor manufacturing, mainly stemming from design and process issues. An open circuit results in a significant voltage drop, disrupting the normal operation of the entire circuit. To monitor or evaluate process stability and design reliability, wafer fabrication plants extract structures with open-circuit risks and use these structures to create repeatable, large-area, easily testable structures for testing. Open-circuit testing is a common test item in wafer fabrication testing (WAT), featuring various structures and involving almost all levels of the manufacturing process. It should be easy to test and easy to analyze for failure. However, designers often neglect the importance of easy failure analysis and location when designing test structures, resulting in increasingly larger test structure areas, which increases the difficulty of slicing and analyzing the failure point.

[0003] Currently, Active Voltage Contrast (AVC) is the most commonly used method for locating open-circuit failure points in ultra-large chain-like test structures. AVC is a function of a nanoprobe instrument. The instrument artificially sets one end of the chain-like test structure to a positive potential and the other end to a negative potential. This divides the open-circuit failure structure into a positive-potential segment and a negative-potential segment, with the open-circuit point as the boundary. Then, an electron beam scans the entire chain-like structure. The positive-potential segment accumulates positive charges on its surface, attracting secondary electrons escaping from the sample surface, thus reducing the number of secondary electrons collected by the SEM probe. Conversely, the negative-potential segment accumulates negative charges on its surface, repelling secondary electrons escaping from the sample surface, resulting in a greater number of secondary electrons collected by the SEM probe. Consequently, the negative-potential segment appears brighter than the positive-potential segment. Therefore, the entire chain-like test structure exhibits a clear difference in brightness and darkness, with the open-circuit point as the boundary. The boundary between the bright and dark areas is the open-circuit failure point. Currently, using AVC (Active Visualization Capability) to locate open circuit failure points in ultra-large chain-like test structures has a drawback: AVC functionality can only be implemented in nanoprobe instruments. Test structures requiring AVC to locate open circuit failure points can only show differences in brightness and darkness within the nanoprobe instrument; once the sample is removed from the instrument, the open circuit point is no longer visible. If the break point is at the edge of the structure, we can scan and store the AVC image and then use structural analysis to locate the break point and perform slice analysis. However, if the test structure area is extremely large and the break point is located in the middle of the structure, then slice analysis of the break point becomes very difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor test structure and a method for locating breakpoint failures using this test structure. This invention proposes a new method for locating breakpoint failures in samples with ultra-large area chain-like test structures using nanoprobe devices, and further proposes a method for locating breakpoint failures based on this test structure. Ultimately, this addresses the technical problem of ultra-large chain-like test structures, where the breakpoints are located in the middle of the test structure, making slicing analysis of the breakpoints difficult or impossible.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a semiconductor testing structure, which may specifically include the following structure:

[0006] The first metal layer includes a number of first sub-metal blocks that are spaced apart sequentially along the X and Y directions and distributed in a matrix.

[0007] The second metal layer includes a plurality of second sub-metal blocks arranged sequentially at intervals and staggered above the first sub-metal block along the X and Y directions. The first sub-metal block and its staggered adjacent second sub-metal blocks are connected end-to-end through conductive vias to form a plurality of interconnected parallel chain-like structures; and,

[0008] A fictitious metal filling layer is provided, including several identification marks located on the periphery of the chain-like structure.

[0009] Furthermore, the semiconductor test structure provided by the present invention may further include an NDC dielectric layer located on the surface of the second metal layer.

[0010] Furthermore, the dummy metal filling layer may specifically include four sub-filling layers distributed along the four sides of the chain structure in the circumferential direction, and at least two of the non-parallel sub-filling layers each have a plurality of identification marks placed at a fixed interval.

[0011] Furthermore, the fixed interval can be in the range of 30μm to 50μm.

[0012] Furthermore, the semiconductor test structure provided by the present invention may further include: an intermetallic dielectric layer located between the first metal layer and the second metal layer, wherein the conductive via penetrates the intermetallic dielectric layer to connect the first sub-metal block and the second sub-metal block.

[0013] Furthermore, the semiconductor test structure proposed in this invention has a size of >200μm×200μm, which is an ultra-large area test structure.

[0014] Secondly, based on the same inventive concept as the semiconductor test structure provided by the present invention described above, and based on this test structure, the present invention also provides a breakpoint failure location method, which may include at least the following steps:

[0015] A semiconductor test structure provided by the present invention as described above is provided, wherein the middle portion of the semiconductor test structure has a breakpoint;

[0016] The pre-processed semiconductor test structure was scanned by electron beam using a nanoprobe device, and the estimated location of the breakpoint in the semiconductor test structure was determined based on the active voltage contrast principle.

[0017] Starting from the estimated position, a range containing the estimated position is formed by extending a preset distance along the X and Y directions. Four identification marks corresponding to the four corners of the range are determined within the dummy metal filling layer, wherein the identification marks are two-dimensional coordinates.

[0018] Using a FIB or SEM device, a carbon deposit mark is formed in the semiconductor test structure corresponding to the interval, and using a nanoprobe device, the relative position of the carbon deposit mark and the estimated position is determined and recorded.

[0019] Using the FIB or SEM equipment again, a new carbon deposit is formed in the semiconductor test structure where the carbon deposit has been formed. Then, using the nanoprobe equipment again, the relative position of the newly formed carbon deposit and the estimated position is determined and recorded. This is to gradually refine the breakpoint corresponding to the estimated position by setting the carbon deposit to gradually move closer to the estimated position.

[0020] Based on the newly formed carbon deposit mark and its relative position to the estimated position, the exact location of the breakpoint corresponding to the estimated position in the semiconductor test structure is determined.

[0021] Furthermore, the shape of the carbon deposit mark can be a regular quadrilateral, and the size of the carbon deposit mark can be 0.5μm×0.5μm to 2μm×2μm. Preferably, the size of the carbon deposit mark is 1μm×0.5μm.

[0022] Furthermore, after determining the exact location of the breakpoint in the semiconductor test structure, the breakpoint failure localization method provided by the present invention may further include: preparing a TEM slice sample of the semiconductor test structure to determine the failure mechanism leading to the open circuit failure.

[0023] Furthermore, the preprocessing step for the semiconductor test structure may include:

[0024] The semiconductor test structure is subjected to a grinding and delamination process to expose the NDC dielectric layer located on the surface of the second metal layer;

[0025] A portion of the dummy metal filling layer corresponding to both ends of the chain structure is removed to expose a portion of the second metal layer of the nanoprobe that facilitates electrical connection to the nanoprobe device.

[0026] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0027] 1. This invention provides a newly designed semiconductor test structure, specifically comprising a first metal layer including a plurality of first sub-metal blocks arranged in a matrix along the X and Y directions at intervals; a second metal layer including a plurality of second sub-metal blocks arranged in a staggered manner above the first sub-metal blocks along the X and Y directions at intervals, wherein the first sub-metal blocks and the adjacent staggered second sub-metal blocks are connected end-to-end through conductive vias to form a plurality of interconnected parallel and connected chain-like structures; and a dummy metal filling layer including a plurality of identification marks located on the periphery of the chain-like structures.

[0028] Obviously, the semiconductor test structure provided by the present invention adds multiple identification marks along the X and Y directions by filling or etching in the dummy metal filling layer formed on the periphery of at least two asymmetric sides of the existing test structure used for breakpoint failure analysis.

[0029] 2. In the breakpoint failure location method based on the semiconductor test structure proposed in this invention, since the semiconductor test structure provided by this invention adds many identification marks for location (each identification mark is a two-dimensional coordinate), during breakpoint failure analysis, the AVC principle of the nanoprobe device can be combined. The identification marks first mark an interval containing the estimated position (approximate position) of the breakpoint. Then, two carbon deposit marks are formed in this interval in stages. Subsequently, as the carbon deposit marks gradually approach the estimated position of the breakpoint, the breakpoint corresponding to the estimated position is gradually refined. This transforms the existing method for locating breakpoint failure points located in the middle of a large chain-like test structure that cannot be located using the nanoprobe device into a method for locating breakpoint failures located at the edge of the structure that can be accurately located using the nanoprobe device, and further reduces the difficulty of slice analysis. Attached Figure Description

[0030] Figure 1 This is a planar perspective view of a chain structure in a semiconductor testing structure provided in one embodiment of the present invention;

[0031] Figure 2 This is a cross-sectional schematic diagram of a portion of the chain-like structure in a semiconductor testing structure provided in one embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of an AVC (Automatic Valve Cushion) in a semiconductor test structure provided in one embodiment of the present invention, showing a chain-like structure with a dummy metal filling layer containing identification marks formed on its periphery.

[0033] Figure 4 Based on Figures 1-3 A flowchart illustrating a method for locating breakpoint failures in a semiconductor test structure provided by the present invention.

[0034] Figure 5 This is a schematic diagram of an AVC (Automatic Circuit-Related Controller) formed in the middle region of a chain structure in a semiconductor test structure provided in one embodiment of the present invention, which includes an open circuit failure point (marked by a dashed circle).

[0035] Figure 6 This is provided in one embodiment of the present invention, including Figure 5 A schematic diagram of the AVC for the range of predicted locations of the corresponding circuit failure points (marked with boxes);

[0036] Figure 7 This is provided in one embodiment of the present invention. Figure 6 A schematic diagram of AVC with carbon deposit marker (carbon deposit Mark1) added to the interval shown;

[0037] Figure 8 This is provided in one embodiment of the present invention. Figure 7 The diagram shows an AVC representation of a newly added carbon deposit marker (Carbon Deposit Mark2) within the shown interval. Detailed Implementation

[0038] As described in the background section, there is a drawback to using AVC (Automatic Vibration Detection) to locate open circuit failure points in large chain-like test structures in existing technologies: AVC functionality can only be implemented in nanoprobe instruments. Test structures requiring AVC to locate open circuit failure points can only show differences in brightness and darkness within the nanoprobe instrument; once the sample is removed from the nanoprobe instrument, the open circuit failure point becomes invisible. In other words, if the open circuit failure point is located at the edge of the test structure, the practical approach is to obtain an AVC image using the nanoprobe instrument, scan and store the AVC image, and then use a method of counting the positions of the open circuit failure points marked on the edge of the test structure to locate the actual position in the middle of the test structure (referred to as the "structure counting method" in this invention) to locate the breakpoint and perform subsequent slicing analysis. However, if the test structure area is extremely large and the breakpoint is located in the middle of the structure, then the aforementioned "structure counting method" cannot be used for slicing analysis to accurately locate the open circuit failure point located in the middle region of the test structure. Therefore, even after marking the edges of AVC images that can only be obtained by placing them in a nanoprobe instrument, it is still impossible to determine the structure by performing a very labor-intensive data structure method when the image is outside the nanoprobe instrument (the distance between the two is too great, and the data structure is like finding a needle in a haystack).

[0039] To address this problem, the inventors of this invention propose modifying the test structure itself, incorporating identifying markers, and then gradually reducing the area of ​​the open circuit failure point in the middle region of the large chain-like test structure using other methods. Finally, the aforementioned numerical structure method is used for accurate localization.

[0040] To address this, the present invention provides a semiconductor test structure and a method for locating breakpoint failures using the test structure. This invention proposes a novel method for locating breakpoint failures in samples with ultra-large area chain-like test structures using nanoprobe devices, and further proposes a method for locating breakpoint failures based on the test structure. Ultimately, this addresses the technical problem of ultra-large chain-like test structures, where the breakpoints are located in the middle of the test structure, making slicing analysis of the breakpoints difficult or impossible.

[0041] The semiconductor test structure proposed in this invention and the breakpoint failure location method using this test structure will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0042] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0043] See Figures 1-3 and combined Figure 5 , Figure 1 This is a planar perspective view of a chain structure in a semiconductor testing structure provided in one embodiment of the present invention; Figure 2 This is a cross-sectional schematic diagram of a portion of the chain-like structure in a semiconductor testing structure provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of an AVC (Automatic Ventilation Control) system in a semiconductor test structure according to an embodiment of the present invention, in which a chain-like structure has a dummy metal filling layer containing identification marks formed on its periphery.

[0044] Specifically, the semiconductor test structure provided by this invention may include: a first metal layer 110, a second metal layer 120, and a dummy metal filling layer 130 containing a plurality of identification marks 1 to n; wherein,

[0045] The first metal layer 110 includes a plurality of first sub-metal blocks 110.1 that are spaced apart sequentially along the X and Y directions and distributed in a matrix.

[0046] The second metal layer 120 includes a plurality of second sub-metal blocks 120.2 arranged sequentially at intervals along the X and Y directions and staggered above the first sub-metal block 110.1. The first sub-metal block 110.1 and its staggered adjacent second sub-metal blocks 120.2 are connected end-to-end through conductive vias CT to form a plurality of interconnected parallel and end-to-end chain structures A; and,

[0047] The dummy metal filling layer 130 includes several identification marks 1 to n located on the periphery of the chain structure A.

[0048] Furthermore, the dummy metal filling layer 130 includes four sub-filling layers 130.1 to 130.4 distributed along the four sides of the chain structure A in the circumferential direction, and at least two of the sub-filling layers are not arranged in parallel (e.g., Figure 5 In both 130.1 and 130.2 shown, a plurality of the identification marks 1 to n are added at fixed intervals.

[0049] As a preferred example, the fixed interval can be in the range of 30μm to 50μm, that is, integers such as 30μm, 35μm, 40μm, 45μm, 50μm, or decimals of any number of digits between 30μm and 50μm.

[0050] Furthermore, see Figure 2 The semiconductor test structure provided by the present invention further includes a metal interlayer dielectric layer 140 located between the first metal layer 110 and the second metal layer 120. The conductive via CT passes through the metal interlayer dielectric layer 140 to connect the first sub-metal block 110.1 and the second sub-metal block 120.2.

[0051] Furthermore, such as Figure 1 or Figure 2 The semiconductor test structure shown also includes an NDC dielectric layer (not shown) located on the surface of the second metal layer.

[0052] It should be noted that the semiconductor test structure provided by the present invention can specifically be a test structure with a size of >200μm×200μm, that is, a chain-like test structure with an ultra-large area.

[0053] Understandably, see Figure 3 and Figure 5It is understood that the present invention only exemplarily forms 5 and 8 identification marks in the sub-filling layers 130.1 and 130.2 corresponding to the two adjacent sides of the chain structure A, respectively. In other embodiments, multiple identification marks of the same or different number can be formed in the sub-filling layers 130.1, 130.2, 130.3 and 130.4 corresponding to the four adjacent sides of the chain structure A, respectively. However, when multiple identification marks are formed in the sub-filling layers corresponding to the two adjacent sides of the chain structure A, the identification marks cannot be formed in two parallel sub-filling layers corresponding to the X or Y directions of the chain structure A. For example, they cannot be formed only in sub-filling layers 130.1 and 130.3 (or only in 130.2 and 130.4).

[0054] Furthermore, in this embodiment of the invention, the numbering method of the identification mark is merely an example of using numbers. In other embodiments, it can also be identified using other characters, such as the letters A, B, C, or a, b, c, etc. This invention does not specifically limit these usages. Figures 1-3 And the following Figures 5-8 In this context, "High" represents the high voltage connected to one end of the chain structure A, and "Low" represents the low voltage connected to the other end of the chain structure A.

[0055] Obviously, the semiconductor test structure provided by this invention adds multiple identification marks along the X and Y directions by filling or etching in a dummy metal filling layer formed on the periphery of at least two asymmetric sides of an existing test structure used for breakpoint failure analysis. Therefore, when performing breakpoint failure analysis using the semiconductor test structure provided by this invention, the AVC principle of a nanoprobe device can be combined. First, an interval containing the estimated (approximate) location of the breakpoint is marked using the identification marks. Then, two carbon deposit marks are formed sequentially within this interval. Subsequently, as the successively formed carbon deposit marks gradually approach the estimated location of the breakpoint, the breakpoint corresponding to the estimated location is gradually refined. This transforms the existing method for locating breakpoint failure points located in the middle of a large chain-like test structure, which cannot be accurately located using a nanoprobe device, into a method for locating breakpoint failures located at the edge of the structure that can be accurately located using a nanoprobe device, further reducing the difficulty of slice analysis.

[0056] Furthermore, based on such Figures 1-3 The present invention also provides a failure location method for the semiconductor test structure corresponding to the layout shown.

[0057] See Figure 4 and combined Figures 5-8The breakpoint failure location method provided by the present invention may include at least the following steps:

[0058] Step S401: Provide a semiconductor test structure having the semiconductor test structure provided by the present invention as described above, wherein the middle portion of the semiconductor test structure has a breakpoint;

[0059] Step S402: The pre-processed semiconductor test structure is scanned with an electron beam using a nanoprobe device, and the estimated location of the breakpoint in the semiconductor test structure is determined based on the active voltage contrast principle.

[0060] Step S403: Starting from the estimated position, extend a preset distance along the X and Y directions to form an interval containing the estimated position, and determine four identification marks corresponding to the four corners of the interval located in the dummy metal filling layer, wherein the identification marks are two-dimensional coordinates;

[0061] Step S404: Using a FIB device or a SEM device, a carbon deposit mark is formed in the semiconductor test structure corresponding to the interval, and using a nanoprobe device, the relative position of the carbon deposit mark and the estimated position is determined and recorded.

[0062] Step S405: Using the FIB device or SEM device again, a new carbon deposit mark is formed in the semiconductor test structure where the carbon deposit mark has been formed. The nanoprobe device is used again to determine and record the relative position of the newly formed carbon deposit mark and the estimated position, so as to gradually refine the breakpoint corresponding to the estimated position by gradually moving the set carbon deposit mark closer to the estimated position.

[0063] After step S406, based on the newly formed carbon deposit mark and its relative position to the estimated position, the accurate position of the breakpoint corresponding to the estimated position in the semiconductor test structure is determined.

[0064] In step S401, existing semiconductor manufacturing processes can be used to form materials such as silicon, germanium, germanium-silicon, silicon carbide, silicon carbide-germanium, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator. Figures 1-3 The semiconductor test structure is a large-area chain structure, and at least one breakpoint (referred to as a breakpoint) is located in the middle of the large-area chain structure to facilitate subsequent breakpoint failure analysis steps.

[0065] See Figure 5 In step S402, as Figure 5As shown in the Active Voltage Contrast (AVC) planar diagram, the semiconductor test structure formed in step S401 can be scanned with an electron beam using a nanoprobe device to obtain an image with connected light and dark areas. Then, based on the principle of active voltage contrast, the estimated location of the breakpoint in the semiconductor test structure can be determined, i.e., Figure 5 The position corresponding to the dashed circle at the boundary between light and dark shown in the diagram.

[0066] However, since the semiconductor test structure formed using step S401 has a dummy metal filling layer on its periphery that encloses the chain-like structure to be electrically tested within the semiconductor test structure, with its top surface at least flush with the top surface of the chain-like structure, it is impossible to electrically connect the nanoprobe using the semiconductor test structure formed using step S401 directly. Therefore, before performing step S402, the breakpoint failure analysis method provided by this invention should also include the following steps:

[0067] Step S401.1: The semiconductor test structure is subjected to a grinding and delamination process to expose the NDC dielectric layer (not shown) located on the surface of the second metal layer;

[0068] Step S401.2 involves removing a portion of the dummy metal filling layer corresponding to both ends of the chain structure, for example, by milling, to expose a portion of the second metal layer that facilitates electrical connection of the nanoprobe device to the nanoprobe.

[0069] In practical applications, to protect the structure and film layer to be tested for electrical properties, other film filling structures or dielectric barrier protective structures will be formed on or around its surface. Therefore, during testing, it is necessary to partially remove these other structures.

[0070] See Figure 6 In step S403, starting from the estimated position, a range is formed by extending a preset distance along the X and Y directions, thus encompassing the estimated position. Figure 6 The boxed area shown is used to identify four identification markers corresponding to the four corners of the interval, located within the dummy metal filling layer, such as... Figure 6 The identification marks 3 and 4 in 130.1 and the identification marks 4 and 5 in 130.2 constitute the four corner coordinates of the interval, namely (4,3), (5,3), (4,4) and (5,4).

[0071] See Figure 7In step S404, a carbon deposit mark, such as carbon deposit Mark1, is formed in the semiconductor test structure corresponding to the interval using a FIB device or a SEM device, and the relative position of the carbon deposit mark and the estimated position is determined and recorded using a nanoprobe device.

[0072] See Figure 8 In step S405, the FIB device or SEM device is used again to form a new carbon deposit mark, such as carbon deposit Mark2, in the semiconductor test structure where the carbon deposit mark has been formed. The nanoprobe device is used again to determine and record the relative position of the newly formed carbon deposit mark and the estimated position, so as to gradually refine the breakpoint corresponding to the estimated position by setting the carbon deposit mark to gradually approach the estimated position.

[0073] As a preferred example, the carbon deposit marks (carbon deposit Mark1 and carbon deposit Mark2) can be in the shape of a regular quadrilateral, such as a rectangle or a square, and the size of the carbon deposit marks can be 0.5μm×0.5μm to 2μm×2μm. Preferably, the size of the carbon deposit marks is 1μm×0.5μm.

[0074] After step S406, the newly formed carbon deposit mark (carbon deposit Mark2) and its distance from the estimated position are very close, and the actual accurate location of the break point can be accurately located using a numerical structure.

[0075] Subsequently, after determining the exact location of the breakpoint in the semiconductor test structure, the breakpoint failure localization method provided by the present invention may further include: preparing a TEM slice sample of the semiconductor test structure to determine the failure mechanism leading to the open circuit failure.

[0076] In summary, 1. This invention provides a newly designed semiconductor test structure, specifically comprising a first metal layer including a plurality of first sub-metal blocks arranged in a matrix along the X and Y directions at intervals; a second metal layer including a plurality of second sub-metal blocks arranged in a staggered manner above the first sub-metal blocks along the X and Y directions at intervals, wherein the first sub-metal blocks and the adjacent staggered second sub-metal blocks are connected end-to-end through conductive vias to form a plurality of interconnected parallel and connected chain-like structures; and a dummy metal filling layer including a plurality of identification marks located on the periphery of the chain-like structures.

[0077] Obviously, the semiconductor test structure provided by the present invention adds multiple identification marks along the X and Y directions by filling or etching in the dummy metal filling layer formed on the periphery of at least two asymmetric sides of the existing test structure used for breakpoint failure analysis.

[0078] 2. In the breakpoint failure location method based on the semiconductor test structure proposed in this invention, since the semiconductor test structure provided by this invention adds many identification marks for location (each identification mark is a two-dimensional coordinate), during breakpoint failure analysis, the AVC principle of the nanoprobe device can be combined. The identification marks first mark an interval containing the estimated position (approximate position) of the breakpoint. Then, two carbon deposit marks are formed in this interval in stages. Subsequently, as the carbon deposit marks gradually approach the estimated position of the breakpoint, the breakpoint corresponding to the estimated position is gradually refined. This transforms the existing method for locating breakpoint failure points located in the middle of a large chain-like test structure that cannot be located using the nanoprobe device into a method for locating breakpoint failures located at the edge of the structure that can be accurately located using the nanoprobe device, and further reduces the difficulty of slice analysis.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for apparatus, user terminals, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0081] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A semiconductor testing structure, characterized in that, include: The first metal layer includes a number of first sub-metal blocks that are spaced apart sequentially along the X and Y directions and distributed in a matrix. The second metal layer includes a plurality of second sub-metal blocks arranged sequentially at intervals and staggered above the first sub-metal block along the X and Y directions. The first sub-metal block and its staggered adjacent second sub-metal blocks are connected end-to-end through conductive vias to form a plurality of interconnected parallel chain-like structures; and, A fictitious metal filling layer includes several identification marks located on the periphery of the chain-like structure; wherein, the identification marks are respectively arranged at a certain interval on two non-parallel sides in the X and Y directions on the periphery of the chain-like structure.

2. The semiconductor test structure as described in claim 1, characterized in that, The semiconductor test structure also includes an NDC dielectric layer located on the surface of the second metal layer.

3. The semiconductor test structure as described in claim 1, characterized in that, The dummy metal filling layer includes four sub-filling layers distributed along the four sides of the chain structure in the circumferential direction, and at least two of the non-parallel sub-filling layers each have multiple identification marks placed at fixed intervals.

4. The semiconductor test structure as described in claim 3, characterized in that, The fixed spacing ranges from 30µm to 50µm.

5. The semiconductor test structure as described in claim 1, characterized in that, The semiconductor test structure further includes a metal interlayer dielectric layer located between the first metal layer and the second metal layer, and the conductive via extends through the metal interlayer dielectric layer to connect the first sub-metal block and the second sub-metal block.

6. The semiconductor test structure as described in claim 1, characterized in that, The dimensions of the semiconductor test structure are >200µm×200µm.

7. A method for locating breakpoint failures, characterized in that, Includes the following steps: A semiconductor test structure as described in any one of claims 1-6 is provided, wherein the semiconductor test structure has a breakpoint at its middle position; wherein the dimensions of the semiconductor test structure are >200µm × 200µm; The pre-processed semiconductor test structure was scanned by electron beam using a nanoprobe device, and the estimated location of the breakpoint in the semiconductor test structure was determined based on the active voltage contrast principle. Starting from the estimated position, a range containing the estimated position is formed by extending a preset distance along the X and Y directions. Four identification marks corresponding to the four corners of the range are determined within the dummy metal filling layer, wherein the identification marks are two-dimensional coordinates. Using a FIB or SEM device, a carbon deposit mark is formed in the semiconductor test structure corresponding to the interval, and using a nanoprobe device, the relative position of the carbon deposit mark and the estimated position is determined and recorded. Using the FIB or SEM equipment again, a new carbon deposit is formed in the semiconductor test structure where the carbon deposit has been formed. Then, using the nanoprobe equipment again, the relative position of the newly formed carbon deposit and the estimated position is determined and recorded. This is to gradually refine the breakpoint corresponding to the estimated position by setting the carbon deposit to gradually move closer to the estimated position. Based on the newly formed carbon deposit mark and its relative position to the estimated position, the exact location of the breakpoint corresponding to the estimated position in the semiconductor test structure is determined.

8. The breakpoint failure location method as described in claim 7, characterized in that, The carbon deposit mark is in the shape of a regular quadrilateral, and the size of the carbon deposit mark is 0.5µm×0.5µm~2µm×2µm.

9. The breakpoint failure location method as described in claim 7, characterized in that, After determining the exact location of the breakpoint in the semiconductor test structure, the method further includes: TEM slice samples of the semiconductor test structure were prepared to determine the failure mechanism leading to open-circuit failure.

10. The breakpoint failure location method as described in claim 7, characterized in that, The preprocessing steps for the semiconductor test structure include: The semiconductor test structure is subjected to a grinding and delamination process to expose the NDC dielectric layer located on the surface of the second metal layer; A portion of the dummy metal filling layer corresponding to both ends of the chain structure is removed to expose a portion of the second metal layer of the nanoprobe that facilitates electrical connection to the nanoprobe device.

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