RC oscillator and electronic device
By designing a two-stage current mirror unit and a bias circuit, external current interference is shielded, and the bias current ratio is adjusted, thus solving the problem of unstable RC oscillator frequency and realizing a high-precision and low-area RC oscillator design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN YSPRING TECH
- Filing Date
- 2022-11-24
- Publication Date
- 2026-06-09
AI Technical Summary
The oscillation frequency of existing RC oscillators is easily affected by power supply voltage and temperature, resulting in frequency instability. Furthermore, adding bias circuitry will increase chip area and power consumption.
A two-stage current mirror unit is used to copy the reference current into two bias currents. The high and low levels are flipped by an oscillation circuit, and a periodic clock oscillation signal is generated by a comparator circuit. External current interference is shielded, and the bias current ratio is adjusted to reduce the size of the resistor and capacitor.
The frequency accuracy of the clock signal was improved, the chip area was reduced, power consumption was lowered, and frequency accuracy was further improved through coarse adjustment of capacitor values and fine adjustment of resistor values.
Smart Images
Figure CN115800923B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of oscillator technology, and more particularly to an RC oscillator and electronic device. Background Technology
[0002] With the rapid development of semiconductor integrated circuit technology, oscillators, as an important basic module in integrated circuit design, are widely used in chips such as analog-to-digital converters (ADCs), charge pumps, and low-dropout regulators (LDOs). Oscillators provide a clock reference frequency for the chip, can be used for switching operations during charge pump boosting, and can set the drive cycle for digital control logic sections.
[0003] Currently, conventional RC oscillators have a simple structure, but their output oscillation frequency is greatly affected by factors such as power supply voltage and temperature. In particular, temperature has a significant impact on the internal current of the RC oscillator, which in turn greatly affects its oscillation frequency. Therefore, a bias circuit is often specially designed to reduce the impact of current on the oscillation frequency. However, adding the corresponding bias circuit will greatly increase the chip area and circuit power consumption.
[0004] Therefore, how to design an oscillator whose output oscillation frequency is not affected by external current and effectively reduces chip area is an urgent problem to be solved. Summary of the Invention
[0005] In view of this, in order to solve the problems of the prior art, this application provides an RC oscillator and an electronic device.
[0006] In a first aspect, this application provides an RC oscillator, including a bias circuit, a comparator circuit, and an oscillation circuit;
[0007] The bias circuit is used to replicate the input reference current into two bias current outputs through a two-stage current mirror unit.
[0008] The oscillation circuit is used to charge and discharge the corresponding capacitors inside the oscillation circuit according to the two bias currents to perform high and low level switching.
[0009] The comparator circuit is used to generate a periodic clock oscillation signal based on the first bias current and the result of high-low level switching.
[0010] In an optional implementation, the bias circuit includes a first-stage current mirror unit and a second-stage current mirror unit.
[0011] The first-stage current mirror unit includes first to fourth switching transistors. The first-stage current mirror unit is used to connect a reference current and copy the reference current to the second-stage current mirror unit.
[0012] The second-stage current mirror unit includes the fifth to tenth switching transistors, and the second-stage current mirror unit is used to replicate the reference current into two bias current outputs.
[0013] In an optional implementation, the first and second terminals of the first switching transistor and the first terminal of the second switching transistor in the first-stage current mirror unit are all connected to the reference current.
[0014] The third terminal of the first switch is connected to the first and second terminals of the third switch and the first terminal of the fourth switch, respectively.
[0015] The third terminal of the third switch is connected to the second terminal of the fourth switch, and both the third terminal of the third switch and the second terminal of the fourth switch are grounded.
[0016] The third terminal of the fourth switch is connected to the second terminal of the second switch, and the third terminal of the second switch is connected to the second-stage current mirror unit.
[0017] In an optional implementation, the first terminals of the fifth, sixth, and seventh switches in the second-stage current mirror unit are all connected to a power supply voltage source.
[0018] The second end of the fifth switch, the second end of the sixth switch, and the second end of the seventh switch are connected in sequence;
[0019] The second and third ends of the fifth switch are respectively connected to the first end of the eighth switch, and the second and third ends of the eighth switch, the first end of the ninth switch, and the first end of the tenth switch are all connected to the first-stage current mirror unit.
[0020] The second terminal of the tenth switch is connected to the third terminal of the seventh switch, and the third terminal of the tenth switch is used to output the first bias current.
[0021] The second terminal of the ninth switch is connected to the third terminal of the sixth switch, and the third terminal of the ninth switch is used to output the second bias current.
[0022] In an optional implementation, the oscillation circuit includes a first oscillation branch, a second oscillation branch, and a third oscillation branch;
[0023] The first oscillation branch and the third oscillation branch have the same structure;
[0024] One end of each of the first oscillation branch, the second oscillation branch, and the third oscillation branch is connected to the two bias currents; the other end of each of the first oscillation branch, the second oscillation branch, and the third oscillation branch is grounded.
[0025] In an optional implementation, the first oscillation branch includes an eleventh switch, a twelfth switch, and a first capacitor;
[0026] The second oscillation branch includes a second capacitor, a third capacitor, and a resistor;
[0027] The second oscillation branch includes a thirteenth switch, a fourteenth switch, and a fourth capacitor.
[0028] In an optional implementation, the first terminal of the eleventh switch is used to connect to the two bias currents;
[0029] The second terminal of the eleventh switch is used to output the first phase control signal, and the third terminal of the eleventh switch is connected to the first terminal of the twelfth switch and one terminal of the first capacitor, respectively.
[0030] The second terminal of the twelfth switch is used to output the second phase control signal, and the third terminal of the twelfth switch and the other terminal of the first capacitor are both grounded.
[0031] In an optional embodiment, the first parallel terminal of the second capacitor, the third capacitor, and the resistor is used to connect the two bias currents;
[0032] The second parallel terminal of the second capacitor, the third capacitor, and the resistor is grounded.
[0033] In an optional implementation, the comparator circuit includes a fifteenth switch, a sixteenth switch, an amplifier, a Schmitt trigger, and multiple inverters connected in series.
[0034] The first terminal of the fifteenth switch and the first terminal of the sixteenth switch are both used to connect to the same bias current; the second terminals of the fifteenth switch and the sixteenth switch are both connected to the input terminal of the amplifier.
[0035] The output of the amplifier is connected to the input of the Schmitt trigger, and the output of the Schmitt trigger is connected to the input of a plurality of inverters connected in series.
[0036] Secondly, embodiments of this application provide an electronic device, which includes the RC oscillator as described above.
[0037] The embodiments of this application have the following beneficial effects:
[0038] The RC oscillator provided in this application includes a bias circuit, a comparator circuit, and an oscillation circuit. The bias circuit is used to replicate the input reference current into two bias current outputs through a two-stage current mirror unit. The oscillation circuit is used to charge and discharge the corresponding capacitors inside the oscillation circuit according to the two bias currents to perform high-low level switching. The comparator circuit is used to generate a periodic clock oscillation signal based on the first bias current and the result of the high-low level switching. The RC oscillator provided in this application has two advantages: First, by setting the structure of the two-stage current mirror unit, it can effectively shield the coupling interference of the oscillation frequency to the current, avoiding the influence of external current on the oscillation frequency. Therefore, when the RC oscillator is applied to a chip, it can effectively improve the frequency accuracy of the clock signal output by the RC oscillator. Second, the RC oscillator provided in this application can reduce the required resistor and capacitor sizes by adjusting the ratio of the two bias currents replicated by the two-stage current mirror unit, thereby effectively reducing the chip area. Attached Figure Description
[0039] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. In the various drawings, similar components are numbered similarly.
[0040] Figure 1 A schematic diagram of a circuit structure for a conventional RC oscillator is shown.
[0041] Figure 2 A schematic diagram of a first structure of an RC oscillator in an embodiment of this application is shown;
[0042] Figure 3 A schematic diagram of a second structure of the RC oscillator in an embodiment of this application is shown;
[0043] Figure 4 A schematic diagram of a third structure of the RC oscillator in an embodiment of this application is shown;
[0044] Figure 5 A timing diagram illustrating the high-low level switching in an embodiment of this application is shown.
[0045] Explanation of key component symbols: 100 - Bias circuit; 110 - First-stage current mirror unit; 120 - Second-stage current mirror unit; 200 - Comparator circuit; 300 - Oscillator circuit; 310 - First oscillation branch; 320 - Second oscillation branch; 330 - Third oscillation branch. Detailed Implementation
[0046] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0047] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0048] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.
[0049] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0050] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.
[0051] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a conventional RC oscillator. In this conventional RC oscillator, the voltage value corresponding to the charging and discharging of the capacitor in the circuit is compared with the fixed voltage value at a certain position in the circuit to perform level flipping, thereby generating a clock oscillation signal based on the level flipping.
[0052] like Figure 1 As shown, KP and KN are two clock signals with opposite phases. If at the initial moment after power-on, the voltage value at the VIP terminal is a fixed voltage value (VIP = I5 * R2), and the voltage value at the VIN terminal is lower than the voltage value at the VIP terminal; at the same time, KP is a low-level signal and KN is a high-level signal, and capacitor C5 is charged through current I4 to store energy.
[0053] When the voltage at the VIN terminal is higher than the voltage at the VIP terminal, the high and low levels flip. At this time, KP is a high-level signal and KN is a low-level signal, and the voltage at the VIN terminal is: VIN = I4 * R2. Capacitor C7 is charged through the current I5.
[0054] When the voltage across capacitor C7 is higher than the voltage at VIN (I4*R2), that is, when the voltage at VIP is higher than the voltage at VIN again, the high and low levels flip; at this point, one cycle of signal oscillation is completed, and subsequent oscillation cycles follow the same pattern.
[0055] The oscillation period (f) is:
[0056]
[0057] Because the current values I4 and I5 are equal in this conventional RC oscillator, the oscillation frequency of the final clock signal depends only on the capacitance and resistance values. In other words, the oscillation frequency is independent of the current. The oscillation frequency error of the final clock signal is only related to operational amplifier mismatch and the delay time of the logic gates in the conventional RC oscillator's oscillation circuit.
[0058] Therefore, if this conventional RC oscillator is used to generate a low-frequency, low-power clock, since the current values of I4 and I5 are equal, the oscillation frequency of the clock oscillation signal is only related to the resistor and capacitor. Consequently, when a smaller oscillation frequency is required, a large resistor and capacitor are needed, and a larger resistor and capacitor will increase the chip area of the RC oscillator, thus requiring a large chip area to meet the requirements.
[0059] Based on this, this application provides an RC oscillator that reduces the values of capacitors and resistors in the circuit by using current ratio to ensure that the oscillation frequency of the RC oscillator output remains unchanged, thereby significantly reducing the chip area of the RC oscillator for low-frequency clocks.
[0060] Example 1
[0061] Please refer to Figure 2 , Figure 3 , Figure 4 This application provides an RC oscillator, including a bias circuit 100, a comparator circuit 200, and an oscillation circuit 300; the bias circuit 100 is used to pass the input reference current (e.g., through a two-stage current mirror unit) to the bias circuit. Figure 4 The IREF1 shown is copied as two bias current outputs; the oscillation circuit 300 is used to charge and discharge the corresponding capacitors inside the oscillation circuit according to the two bias currents to perform high and low level switching; the comparator circuit 200 is used to calculate the first bias current (e.g., ...) based on the two bias currents. Figure 4 The I2 in the clock signal and the result of high and low level switching generate a periodic clock oscillation signal.
[0062] In this embodiment, the bias circuit 100 includes a first-stage current mirror unit 110 and a second-stage current mirror unit 120. Exemplarily, the first-stage current mirror unit 110 includes first to fourth switching transistors, and is used to connect a reference current (e.g., ...). Figure 4 As shown in IREF1), the reference current is copied to the second-stage current mirror unit 120; the second-stage current mirror unit 120 includes the fifth to tenth switching transistors, and the second-stage current mirror unit 120 is used to copy the reference current into two bias current outputs.
[0063] In this embodiment, the first and second terminals of the first switching transistor and the first terminal of the second switching transistor in the first-stage current mirror unit 110 are all connected to a reference current; the third terminal of the first switching transistor is connected to the first and second terminals of the third switching transistor and the first terminal of the fourth switching transistor, respectively; the third terminal of the third switching transistor is connected to the second terminal of the fourth switching transistor, and the third terminals of the third and fourth switching transistors are both grounded; the third terminal of the fourth switching transistor is connected to the second terminal of the second switching transistor, and the third terminal of the second switching transistor is connected to the second-stage current mirror unit 120.
[0064] In this embodiment, the first to fourth switching transistors can be NMOS transistors. Therefore, the first to fourth switching transistors are respectively the first to fourth NMOS transistors. The drain and gate of the first NMOS transistor (NM1) and the gate of the second NMOS transistor (NM2) in the first-stage current mirror unit 110 are all connected to the reference current. The source of the first NMOS transistor (NM1) is connected to the drain and gate of the third NMOS transistor (NM3) and the gate of the fourth NMOS transistor (NM4). The source of the third NMOS transistor (NM3) is connected to the source of the fourth NMOS transistor (NM4). The sources of the third NMOS transistor (NM3) and the fourth NMOS transistor (NM4) are both grounded. The drain of the fourth NMOS transistor (NM4) is connected to the source of the second NMOS transistor (NM2), and the drain of the second NMOS transistor (NM2) is connected to the second-stage current mirror unit 120.
[0065] The first terminals of the fifth, sixth, and seventh switches in the second-stage current mirror unit 120 are all connected to the power supply voltage source; the second terminals of the fifth, sixth, and seventh switches are connected sequentially; the second and third terminals of the fifth switch are respectively connected to the first terminal of the eighth switch; the second and third terminals of the eighth switch, the first terminals of the ninth and tenth switches are all connected to the third terminal of the second switch in the first-stage current mirror unit 110; the second terminal of the ninth switch is connected to the third terminal of the sixth switch, and the third terminal of the ninth switch is used to output the second bias current (I1); the second terminal of the tenth switch is connected to the third terminal of the seventh switch, and the third terminal of the tenth switch is used to output the first bias current (I2).
[0066] In this embodiment, the fifth to eighth switching transistors can be PMOS transistors, which correspond to the first to fourth PMOS transistors respectively. The drains of the first PMOS transistor (PM1), the second PMOS transistor (PM2), and the third PMOS transistor (PM3) in the second-stage current mirror unit 120 are all connected to the power supply voltage source. The gates of the first PMOS transistor (PM1), the second PMOS transistor (PM2), and the third PMOS transistor (PM3) are connected sequentially. The source and gate of the first PMOS transistor (PM1) are both connected to the drain of the fourth PMOS transistor. The gate and source of the fourth PMOS transistor (PM4), the gate of the fifth PMOS transistor (PM5), and the gate of the sixth PMOS transistor (PM6) are all connected to the drain of the second NMOS transistor (NM2) in the first-stage current mirror unit 110; the drain of the fifth PMOS transistor (PM5) is connected to the source of the sixth PMOS transistor (PM6), and the source of the fifth PMOS transistor (PM5) is used to output the second bias current; the drain of the sixth PMOS transistor (PM6) is connected to the source of the third PMOS transistor (PM3), and the source of the sixth PMOS transistor (PM6) is used to output the first bias current.
[0067] The oscillation circuit 300 includes a first oscillation branch 310, a second oscillation branch 320, and a third oscillation branch 330; the first oscillation branch 310 and the third oscillation branch 330 have the same structure; one end of the first oscillation branch 310, the second oscillation branch 320, and the third oscillation branch 330 are all connected to two bias currents; the other end of the first oscillation branch 310, the second oscillation branch 320, and the third oscillation branch 330 are all grounded.
[0068] Exemplary, the first oscillation branch 310 includes an eleventh switch, a twelfth switch, and a first capacitor C1; the second oscillation branch 320 includes a second capacitor C2, a third capacitor C3, and a resistor R1; and the third oscillation branch 330 includes a thirteenth switch, a fourteenth switch, and a fourth capacitor C4.
[0069] The first terminal of the eleventh switch and the first terminal of the thirteenth switch are both used to connect two bias currents. The second terminal of the eleventh switch is used to output the first phase control signal. The third terminal of the eleventh switch is connected to the first terminal of the twelfth switch and one terminal of the first capacitor C1. The second terminal of the twelfth switch is used to output the second phase control signal. The third terminal of the twelfth switch and the other terminal of the first capacitor C1 are both grounded.
[0070] The second capacitor C2, resistor R1, and third capacitor C3 are connected in parallel. The first parallel terminal of the second capacitor C2, resistor R1, and third capacitor C3 is used to connect two bias currents, and the second parallel terminal of the second capacitor C2, resistor R1, and third capacitor C3 is grounded.
[0071] The first terminal of the thirteenth switch is used to connect two bias currents. The second terminal of the thirteenth switch is used to output the second phase control signal. The third terminal of the thirteenth switch is connected to the first terminal of the fourteenth switch and one terminal of the fourth capacitor C4. The second terminal of the fourteenth switch is used to output the first phase control signal. The third terminal of the fourteenth switch and the other terminal of the fourth capacitor C4 are both grounded.
[0072] As an example, the eleventh to fourteenth switches can all be NMOS transistors, and thus, the eleventh to fourteenth switches correspond to the fifth to eighth NMOS transistors, respectively.
[0073] Specifically, the drains of the fifth NMOS transistor (NM5) and the seventh NMOS transistor (NM7) are used to connect two bias currents. The gate of the fifth NMOS transistor (NM5) is used to output the first phase control signal. The source of the fifth NMOS transistor (NM5) is connected to the drain of the sixth NMOS transistor (NM6) and one end of the first capacitor C1, respectively. The gate of the sixth NMOS transistor (NM6) is used to output the second phase control signal. The source of the sixth NMOS transistor (NM6) and the other end of the first capacitor C1 are both grounded.
[0074] The drain of the seventh NMOS transistor (NM7) is used to receive two bias currents. The gate of the seventh NMOS transistor (NM7) is used to output the second phase control signal. The source of the seventh NMOS transistor (NM7) is connected to the drain of the eighth NMOS transistor (NM8) and one end of the fourth capacitor C4. The gate of the eighth NMOS transistor (NM8) is used to output the first phase control signal. The source of the eighth NMOS transistor (NM8) and the other end of the fourth capacitor C4 are both grounded.
[0075] The first phase control signal is the PHN control signal, and the second phase control signal is the PHP control signal. The PHN control signal and the PHP control signal are out of phase.
[0076] Exemplarily, the comparator circuit 200 includes a fifteenth switch, a sixteenth switch, an amplifier COMP, a Schmitt trigger SMIT, and multiple inverters INV connected in series. The specific number of inverters INV is not limited here, and the multiple inverters INV are connected in series.
[0077] The first terminals of both the fifteenth and sixteenth switches are connected to the same bias current. The second terminals of both switches are connected to the input of amplifier COMP. The output of amplifier COMP is connected to the input of Schmitt trigger SMIT, and the output of Schmitt trigger SMIT is connected to the input of multiple inverters INV connected in series. The third terminal of the fifteenth switch is used to input the second phase control signal, and the third terminal of the sixteenth switch is used to input the first phase control signal.
[0078] In one embodiment, both the fifteenth and sixteenth switches are NMOS transistors, and thus, the fifteenth and sixteenth switches correspond to the ninth and tenth NMOS transistors, respectively.
[0079] The gate of the ninth NMOS transistor (NM9) is used to input the PHP control signal, the source of the ninth NMOS transistor (NM9) is used to connect the second bias current, and the drain of the ninth NMOS transistor (NM9) is connected to the first input terminal of the amplifier COMP; the gate of the tenth NMOS transistor (NM10) is used to input the PHN control signal, the drain of the tenth NMOS transistor (NM10) is used to connect the second bias current, and the source of the tenth NMOS transistor (NM10) is connected to the second input terminal of the amplifier COMP.
[0080] In one implementation, such as Figure 3 As shown, this embodiment uses three inverters (INV) as an example for explanation. The input terminal of the first inverter is connected to the output terminal of the Schmitt trigger (SMIT). The output terminal of the first inverter outputs the PHP control signal to the input terminal of the second inverter. The output terminal of the second inverter outputs the PHN control signal to the input terminal of the third inverter. The output terminal of the third inverter outputs a periodic clock oscillation signal (CLK).
[0081] In this embodiment, the input reference current is copied to the oscillation circuit through a two-stage current mirror unit to charge the corresponding capacitor (first capacitor C1 or fourth capacitor C4) and resistor (resistor R1). A fixed voltage value is maintained, i.e., the voltage across resistor R1 is (I2*R1). When the PHN control signal and PHP control signal are input, the PHN control signal instructs the switch to turn on, and the PHP control signal instructs the switch to turn off, providing a second bias current (I1) to charge the first capacitor C1, while the fourth capacitor C4 discharges through the fourteenth switch (NM8).
[0082] When the voltage at the first capacitor C1 is higher than the voltage across the resistor R1, the high and low levels flip, and the input PHN control signal indicates that the switch is turned off, while the PHP control signal indicates that the switch is turned on. At this time, the first capacitor C1 is discharged through the twelfth switch (NM6), and the first bias current (I2) is provided to charge the fourth capacitor C4.
[0083] When the charging voltage of the fourth capacitor C4 is higher than the voltage across the resistor R1, that is, when the voltage at the VIN terminal is higher than the voltage at the VIP terminal, the high and low levels flip again. After two high and low level flips, one cycle of oscillation is completed, and subsequent oscillation cycles can be deduced in the same way.
[0084] like Figure 5 As shown, Figure 5 The timing diagram for the high-low level transition shows the voltage across resistor R1 as follows:
[0085] V R1 =I2*R1;
[0086] Among them, V R1 I1 represents the voltage across resistor R1, and I2 represents the bias current when resistor R1 is charging.
[0087] The voltage across either the first capacitor C1 or the fourth capacitor C4 is:
[0088] V C =I1*T1;
[0089] Among them, V C T1 represents the voltage across either the first capacitor C1 or the fourth capacitor C4, and T1 represents the charging time when the first capacitor C1 or the fourth capacitor C4 is being charged.
[0090] The condition for high-low level switching is V. R1 and V C Since the voltage values at both ends are equal, we can deduce that:
[0091] C1*V R1 =I1*T1;
[0092] Therefore, the oscillation period or oscillation frequency (f) of the clock signal output by the comparator circuit 200 is:
[0093]
[0094] Based on the above formula for calculating the oscillation period, it can be understood that the magnitude of the oscillation period or oscillation frequency is related to the ratio of the two bias currents, the resistance value, and the capacitance value.
[0095] For example, if the second bias current I2 has an error factor, let's assume it's α. Since the first bias currents I1 and I2 are replicated from the same current mirror unit, and assuming the current value of I1 is β times the current value of I2, then the error factor is also β × α times it. Therefore, the error factor α can be removed, resulting in an RC oscillator whose oscillation period is independent of the current value. This ensures that the RC oscillator in this embodiment... Figure 1 If the oscillation frequency accuracy of the conventional RC oscillator shown is the same, the values of the resistor and capacitor can be reduced accordingly by adjusting the ratio between the two bias currents I1 and I2, thus eliminating the need for large resistors and capacitors and effectively reducing the chip area of the RC oscillator.
[0096] The RC oscillator provided in this application embodiment has several advantages. First, by setting a two-stage current mirror unit structure, it can effectively shield the coupling interference of the oscillation frequency to the current and avoid the influence of external current on the oscillation frequency. Therefore, when the RC oscillator is applied to a chip, it can effectively improve the frequency accuracy of the clock signal output by the RC oscillator. Second, the RC oscillator provided in this application embodiment can reduce the required resistor and capacitor sizes by adjusting the ratio of the two bias currents replicated by the two-stage current mirror unit, thereby effectively reducing the chip area. Third, when performing hardware testing on the RC oscillator, since the RC oscillator provided in this application embodiment is a low-area circuit structure RC oscillator, the capacitor value is small. When frequency adjustment is performed during hardware testing, the accuracy of the oscillation frequency can be improved by coarsely adjusting the capacitor value and finely adjusting the resistor value, thereby preventing the hardware test from affecting the circuits inside the RC oscillator.
[0097] This application also provides an electronic device, which includes the RC oscillator of the above embodiments. Any option of the RC oscillator in the above embodiments can be applied to the electronic device of this embodiment, and will not be described in detail here. The electronic device includes, but is not limited to, communication equipment, AM radios, audio generators, frequency synthesizers, central processing units, communication radios, quartz watches, etc.
[0098] In all examples shown and described herein, any specific values should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.
[0099] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0100] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.
Claims
1. An RC oscillator, characterized in that, Includes bias circuit, comparator circuit and oscillator circuit; The bias circuit is used to copy the input reference current into two bias current outputs through a two-stage current mirror unit; the two-stage current mirror unit includes a first-stage current mirror unit and a second-stage current mirror unit; the first-stage current mirror unit is used to input the reference current and copy the reference current to the second-stage current mirror unit. The second-stage current mirror unit is used to replicate the reference current into two bias current outputs; The two-stage current mirror unit is used to adjust the ratio between the two bias currents to reduce the values of the resistance and capacitance inside the RC oscillator accordingly. The oscillation circuit is used to charge and discharge the corresponding capacitors inside the oscillation circuit according to the two bias currents to perform high and low level switching. The oscillation circuit includes a first oscillation branch and a second oscillation branch; The first oscillation branch includes an eleventh switch, a twelfth switch, and a first capacitor; the second oscillation branch includes a thirteenth switch, a fourteenth switch, and a fourth capacitor, and the second oscillation branch also includes a second capacitor, a third capacitor, and a resistor; The first terminals of the eleventh and thirteenth switches are used to connect to the two bias currents; the second terminals of the eleventh and fourteenth switches are used to output the first phase control signal; and the second terminals of the twelfth and thirteenth switches are used to output the second phase control signal. The third terminal of the eleventh switch is connected to the first terminal of the twelfth switch and one terminal of the first capacitor. The third terminal of the twelfth switch and the other terminal of the first capacitor are both grounded. The first parallel terminal of the second capacitor, the third capacitor, and the resistor is used to connect the two bias currents; the second parallel terminal of the second capacitor, the third capacitor, and the resistor is grounded. The comparator circuit is used to generate a periodic clock oscillation signal based on the first bias current and the result of high-low level switching.
2. The RC oscillator according to claim 1, characterized in that, The first-stage current mirror unit includes first to fourth switching transistors, and the first and second terminals of the first switching transistor and the first terminal of the second switching transistor in the first-stage current mirror unit are all connected to the reference current. The third terminal of the first switch is connected to the first and second terminals of the third switch and the first terminal of the fourth switch, respectively. The third terminal of the third switch is connected to the second terminal of the fourth switch, and both the third terminal of the third switch and the second terminal of the fourth switch are grounded. The third terminal of the fourth switch is connected to the second terminal of the second switch, and the third terminal of the second switch is connected to the second-stage current mirror unit.
3. The RC oscillator according to claim 1, characterized in that, The second-stage current mirror unit includes fifth to tenth switching transistors. The first terminals of the fifth, sixth, and seventh switching transistors in the second-stage current mirror unit are all connected to the power supply voltage source. The second end of the fifth switch, the second end of the sixth switch, and the second end of the seventh switch are connected in sequence; The second and third ends of the fifth switch are respectively connected to the first end of the eighth switch, and the second and third ends of the eighth switch, the first end of the ninth switch, and the first end of the tenth switch are all connected to the first-stage current mirror unit. The second terminal of the ninth switch is connected to the third terminal of the sixth switch, and the third terminal of the ninth switch is used to output the second bias current. The second terminal of the tenth switch is connected to the third terminal of the seventh switch, and the third terminal of the tenth switch is used to output the first bias current.
4. The RC oscillator according to claim 1, characterized in that, The oscillation circuit includes a third oscillation branch; The first oscillation branch and the third oscillation branch have the same structure; One end of each of the first oscillation branch, the second oscillation branch, and the third oscillation branch is connected to the two bias currents; the other end of each of the first oscillation branch, the second oscillation branch, and the third oscillation branch is grounded.
5. The RC oscillator according to claim 1, characterized in that, The comparator circuit includes a fifteenth switch, a sixteenth switch, an amplifier, a Schmitt trigger, and multiple inverters connected in series; The first terminal of the fifteenth switch and the first terminal of the sixteenth switch are both used to connect to the same bias current; the second terminals of the fifteenth switch and the sixteenth switch are both connected to the input terminal of the amplifier. The output of the amplifier is connected to the input of the Schmitt trigger, and the output of the Schmitt trigger is connected to the input of a plurality of inverters connected in series.
6. An electronic device, characterized in that, Includes the RC oscillator as described in any one of claims 1-5.