Telemetry capacity expansion method and inter-board synchronous acquisition circuit

Abstract

This invention belongs to the field of clock synchronization technology, and relates to a telemetry expansion method and an inter-board synchronization acquisition circuit. The inter-board synchronization acquisition circuit includes: a first circuit board and at least one set of second circuit boards; the first circuit board includes a first analog-to-digital converter (ADC), a controller chip, a clock chip, and a first clock buffer; the second circuit board includes a second ADC and a second clock buffer; the controller chip's first serial communication interface operates in master mode to configure and read data from the registers of the first ADC and configure the registers of the second ADC; the controller chip's second serial communication interface operates in slave mode to read data from the second ADC. This invention achieves synchronization of the clock feedback path between telemetry expansion and the expanded circuit board, avoiding data reading errors caused by asynchronous clock signals and data input signals on the SPI bus due to signal delays in the transmission path.

Description

Technical Field

[0001] This invention relates to the field of clock synchronization technology, and more specifically, to a telemetry expansion method and an inter-board synchronous acquisition circuit. Background Technology

[0002] In the field of railway power supply monitoring, the number of load circuits requiring monitoring is increasing. When the telemetry capacity of a single railway power RTU (Remote Terminal Unit) cannot meet the needs of field engineering applications, the telemetry capacity is typically expanded by increasing the number of railway power RTUs. The advantage of this solution is that it eliminates the need for redeveloping hardware. However, this solution suffers from several drawbacks: high hardware costs, inflexible configuration, large space requirements, and the inability to achieve synchronous telemetry sampling. Furthermore, upgrading existing railway power RTUs to expand telemetry capacity requires both hardware and software upgrades, resulting in a lengthy development period.

[0003] Furthermore, capacity expansion is achieved by increasing the chassis height and superimposing a telemetry acquisition circuit board on the existing circuit board. The MCU on the existing circuit board manages the ADC chip on the telemetry acquisition circuit board via an SPI serial communication interface, configuring its registers and reading data. While this method saves the hardware cost of one controller chip by sharing a single MCU with the existing circuit board, the ADC chips on the two circuit boards are still unable to achieve synchronous sampling because they are managed by two separate SPI serial communication interfaces of the MCU. Additionally, the SPI serial communication signal between the two circuit boards is affected by the single-ended signal transmission via cable, impacting both transmission rate and communication reliability. Summary of the Invention

[0004] To solve the above-mentioned technical problems, this invention utilizes clock feedback path synchronization to provide a telemetry expansion method and an inter-board synchronous acquisition circuit, realizing a telemetry expansion method and an inter-board synchronous acquisition circuit where a telemetry circuit board with an MCU manages a telemetry circuit board without an MCU.

[0005] In a first aspect, the present invention provides an inter-board synchronous acquisition circuit, comprising a first circuit board and at least one set of second circuit boards;

[0006] The first circuit board includes a first analog-to-digital converter circuit, a controller chip, a clock chip, and a first clock buffer;

[0007] The clock chip is electrically connected to the first analog-to-digital converter circuit via the first clock buffer; the first analog-to-digital converter circuit is electrically connected to the controller chip.

[0008] The second circuit board includes a second analog-to-digital converter circuit and a second clock buffer;

[0009] The second analog-to-digital converter circuit is electrically connected to the second clock buffer;

[0010] The clock chip is electrically connected to the second clock buffer;

[0011] The first analog-to-digital converter circuit and the second analog-to-digital converter circuit are electrically connected; the output terminal of the second analog-to-digital converter circuit is electrically connected to the input terminal of the controller chip.

[0012] The start-up conversion terminal of the first analog-to-digital converter circuit, the start-up conversion terminal of the controller chip, and the start-up conversion terminal of the second analog-to-digital converter circuit are electrically connected;

[0013] The first serial communication interface of the controller chip operates in master mode and is used to configure and read data from the registers of the first analog-to-digital converter circuit on the first circuit board.

[0014] The first serial communication interface of the controller chip operates in master mode and is used to configure the registers of the second analog-to-digital converter circuit on the second circuit board.

[0015] The second serial communication interface of the controller chip operates in slave mode and is used to perform data reading operations on the second analog-to-digital conversion circuit on the second circuit board.

[0016] The first serial communication interface of the controller chip generates a first SCK clock signal for the read operation; the first SCK clock signal is looped back to the controller chip through the second analog-to-digital converter circuit and sent to the second serial communication interface of the controller chip.

[0017] Secondly, the present invention provides a telemetry expansion method, applied to data synchronous acquisition between a first circuit board and at least one group of second circuit boards, including:

[0018] The first circuit board is provided with a first analog-to-digital conversion circuit, a controller chip, a clock chip, and a first clock buffer; the second circuit board is provided with a second analog-to-digital conversion circuit and a second clock buffer.

[0019] The first analog-to-digital converter (ADC) circuit and the second ADC circuit share a synchronous reference clock source. That is, the clock chip is electrically connected to the first ADC circuit through a first clock buffer; the clock chip is electrically connected to the second ADC circuit through a second clock buffer.

[0020] The first analog-to-digital conversion circuit and the second analog-to-digital conversion circuit share a single start-up conversion control signal;

[0021] The first serial communication interface of the controller chip operates in master mode and is used to configure and read data from the registers of the first analog-to-digital converter circuit on the first circuit board.

[0022] The first serial communication interface of the controller chip operates in master mode and is used to configure the registers of the second analog-to-digital converter circuit on the second circuit board.

[0023] The second serial communication interface of the controller chip operates in slave mode and is used to perform data reading operations on the second analog-to-digital conversion circuit on the second circuit board.

[0024] When the controller chip reads the data collected by the second circuit board, the first serial communication interface of the controller chip generates a first SCK clock signal for the read operation; the first SCK clock signal is looped back to the controller chip through the second analog-to-digital converter circuit and sent to the second serial communication interface of the controller chip.

[0025] The beneficial effects of this invention are: this invention realizes the synchronization of the clock feedback path between telemetry expansion and the expanded circuit board, avoiding the problem of data reading errors caused by the asynchronous clock signal and data input signal of the SPI bus due to signal delay in the transmission path.

[0026] Based on the above technical solution, the present invention can be further improved as follows.

[0027] Furthermore, the first circuit board is provided with logic gate units; after the first analog-to-digital converter completes one sampling and conversion, it generates a first data ready signal; after the second analog-to-digital converter completes one sampling and conversion, it generates a second data ready signal; the data ready signal output terminal of the first analog-to-digital converter and the data ready signal output terminal of the second analog-to-digital converter are electrically connected to the input terminal of the controller chip through the logic gate units;

[0028] Furthermore, the first circuit board is provided with a first LVDS chip, a second LVDS chip and a third LVDS chip; the second circuit board is provided with a fourth LVDS chip, a fifth LVDS chip and a sixth LVDS chip;

[0029] The SPI terminal of the first analog-to-digital converter circuit is electrically connected to the first SPI terminal of the controller chip and the first LVDS chip.

[0030] The SPI terminal of the second analog-to-digital converter circuit is electrically connected to the fourth LVDS chip.

[0031] The first LVDS chip is electrically connected to the fourth LVDS chip;

[0032] The second SPI terminal of the first analog-to-digital converter circuit is electrically connected to the second LVDS chip; the SDO terminal of the second analog-to-digital converter circuit is electrically connected to the second LVDS chip through the fifth LVDS chip.

[0033] The clock chip is electrically connected to the sixth LVDS chip via the third LVDS chip; the sixth LVDS chip is electrically connected to the clock buffer.

[0034] Furthermore, the first circuit board also includes a first PT / CT transformer and a first signal conditioning circuit; the first PT / CT transformer is electrically connected to the first analog-to-digital converter circuit through the first signal conditioning circuit.

[0035] Furthermore, the second circuit board also includes a second PT / CT transformer and a second signal conditioning circuit; the second PT / CT transformer is electrically connected to the second analog-to-digital converter circuit through the second signal conditioning circuit.

[0036] Furthermore, the logic gate unit is an OR gate unit.

[0037] Furthermore, the controller chip is an MCU chip.

[0038] Furthermore, the first analog-to-digital conversion circuit includes at least one first analog-to-digital converter; the second analog-to-digital conversion circuit includes at least one second analog-to-digital converter; when there is more than one first analog-to-digital converter, each of the first analog-to-digital converters operates in daisy-chain mode; when there is more than one second analog-to-digital converter, each of the second analog-to-digital converters operates in daisy-chain mode.

[0039] Furthermore, by setting LVDS chips on the first circuit board and the second circuit board, the single-ended clock signal and single-ended data signal are converted into LVDS differential clock signal and LVDS differential data signal before transmission. Attached Figure Description

[0040] Figure 1 This is a circuit diagram of the inter-board synchronous acquisition circuit provided in Embodiment 1 of the present invention;

[0041] Figure 2 A circuit diagram illustrating a specific implementation of the inter-board synchronous acquisition circuit;

[0042] Figure 3This is a schematic diagram without using the clock feedback path synchronization principle;

[0043] Figure 4 This is a schematic diagram of a synchronization principle using a clock feedback path. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0045] Example 1

[0046] As an example, see the attached document. Figure 1 As shown, to solve the above-mentioned technical problems, this embodiment provides an inter-board synchronous acquisition circuit, including a first circuit board and at least one set of second circuit boards;

[0047] The first circuit board includes a first analog-to-digital conversion circuit, a controller chip, a clock chip, and a first clock buffer;

[0048] The clock chip is electrically connected to the first analog-to-digital converter circuit via a first clock buffer; the first analog-to-digital converter circuit is electrically connected to the controller chip.

[0049] The second circuit board includes a second analog-to-digital converter circuit and a second clock buffer;

[0050] The second analog-to-digital converter circuit is electrically connected to the second clock buffer.

[0051] The clock chip is electrically connected to the second clock buffer;

[0052] The first analog-to-digital converter circuit and the second analog-to-digital converter circuit are electrically connected; the output terminal of the second analog-to-digital converter circuit is electrically connected to the input terminal of the controller chip.

[0053] The start-up converter terminal of the first analog-to-digital converter circuit, the start-up converter terminal of the controller chip, and the start-up converter terminal of the second analog-to-digital converter circuit are electrically connected;

[0054] The controller chip's first serial communication interface operates in master mode and is used to configure and read data from the registers of the first analog-to-digital converter circuit on the first circuit board.

[0055] The controller chip's first serial communication interface operates in master mode and is used to configure the registers of the second analog-to-digital converter circuit on the second circuit board.

[0056] The controller chip's second serial communication interface operates in slave mode and is used to read data from the second analog-to-digital converter circuit on the second circuit board.

[0057] The controller chip's first serial communication interface generates a first SCK clock signal for the read operation; this first SCK clock signal loops back to the controller chip via a second analog-to-digital converter circuit and is then sent to the controller chip's second serial communication interface. Optionally, the controller chip is an MCU chip. The number of first circuit boards is not limited to one set; when multiple sets of first circuit boards are set, each set of first circuit boards uses the same principle to connect to the MCU chip.

[0058] Optionally, the first circuit board is provided with logic gate units; after the first analog-to-digital converter completes one sampling and conversion, it generates a first data ready signal; after the second analog-to-digital converter completes one sampling and conversion, it generates a second data ready signal; the data ready signal output terminal of the first analog-to-digital converter and the data ready signal output terminal of the second analog-to-digital converter are electrically connected to the input terminal of the controller chip through the logic gate units; optionally, the logic gate units are OR gate units.

[0059] Optional, as shown in the appendix Figure 2 As shown, a first LVDS chip, a second LVDS chip, and a third LVDS chip are disposed on the first circuit board; a fourth LVDS chip, a fifth LVDS chip, and a sixth LVDS chip are disposed on the second circuit board.

[0060] The SPI terminal of the first analog-to-digital converter circuit is electrically connected to the first SPI terminal of the controller chip and the first LVDS chip.

[0061] The SPI terminal of the second analog-to-digital converter circuit is electrically connected to the fourth LVDS chip.

[0062] The first LVDS chip and the fourth LVDS chip are electrically connected;

[0063] The second SPI terminal of the first analog-to-digital converter circuit is electrically connected to the second LVDS chip; the SDO terminal of the second analog-to-digital converter circuit is electrically connected to the second LVDS chip through the fifth LVDS chip.

[0064] The clock chip is electrically connected to the sixth LVDS chip via the third LVDS chip; the sixth LVDS chip is electrically connected to the clock buffer.

[0065] In practical applications, LVDS chips convert single-ended clock signals and single-ended data signals into LVDS differential clock signals and LVDS differential data signals for transmission between boards, ensuring communication distance, communication rate, and anti-interference capabilities, and improving the reliability of data transmission.

[0066] Optional, as shown in the appendix Figure 2 As shown, the first circuit board further includes a first PT / CT current transformer and a first signal conditioning circuit; the first PT / CT current transformer is electrically connected to the first analog-to-digital converter circuit through the first signal conditioning circuit. Optionally, the first signal conditioning circuit includes a first current / voltage conversion circuit, a first operational amplifier circuit, and a first filter circuit; the first PT / CT current transformer is electrically connected to the input terminal of the first operational amplifier circuit through the first current / voltage conversion circuit; the output terminal of the first operational amplifier circuit is electrically connected to the first analog-to-digital converter circuit through the first filter circuit.

[0067] Optional, as shown in the appendix Figure 2 As shown, the second circuit board also includes a second PT / CT transformer and a second signal conditioning circuit; the second PT / CT transformer is electrically connected to the second analog-to-digital converter circuit through the second signal conditioning circuit. Optionally, the second signal conditioning circuit includes a second current / voltage conversion circuit, a second operational amplifier circuit, and a second filter circuit; the second PT / CT transformer is electrically connected to the input terminal of the second operational amplifier circuit through the second current / voltage conversion circuit; the output terminal of the second operational amplifier circuit is electrically connected to the second analog-to-digital converter circuit through the second filter circuit.

[0068] Optionally, the first analog-to-digital conversion circuit includes at least one first analog-to-digital converter (ADC); the second ADC circuit includes at least one second ADC; when there is more than one first ADC, each first ADC operates in daisy-chain mode; when there is more than one second ADC, each second ADC operates in daisy-chain mode. When the first and second ADCs operate in daisy-chain mode, multiple ADCs can perform synchronous sampling, reducing the controller's control signal usage, simplifying register configuration and data reading processes for the ADCs, and reducing PCB routing complexity.

[0069] The principle of achieving synchronous sampling of ADC is as follows:

[0070] The first analog-to-digital converter (ADC) circuit on the first circuit board and the second ADC circuit on the second circuit board each consist of at least one ADC chip. When there is more than one ADC chip on the same circuit board, the ADC chips share the same clock chip and operate in daisy-chain mode. The communication interface of the ADC chips is a serial SPI interface. The clock chip on the first circuit board outputs a stable fixed-frequency clock signal, providing a unified clock source for the ADC chips on the first circuit board. At the same time, it transmits the clock signal to circuit board 2, providing it to the ADC chips on the second circuit board.

[0071] The ADC chips on the first and second circuit boards share a single START control signal.

[0072] Specifically, the process of configuring registers and reading data from the ADC chips on the first and second circuit boards is as follows:

[0073] (1) On the first circuit board, the MCU’s SPI-1 serial communication interface works in SPI master mode to realize register configuration and data reading operations of the ADC chip on the board;

[0074] (2) On the first circuit board, the MCU’s SPI-1 serial communication interface works in SPI master mode to realize the register configuration operation of the ADC chip on the second circuit board.

[0075] (3) On the first circuit board, the MCU’s SPI-2 serial communication interface works in SPI slave mode to realize the data reading operation of the ADC chip on the second circuit board.

[0076] (4) When the ADC chips on the first circuit board and the second circuit board complete one sampling and conversion, they will generate DRDY1 and DRDY2 signals at the same time. After passing through an OR gate on the first circuit board, the two signals are sent to the interrupt INT pin of the MCU. After the MCU detects the interrupt signal, the MCU enables the DMA read function of SPI-1 and SPI-2. SPI-1 of the MCU completes the sampling and conversion data reading operation of the ADC chip on the first circuit board, and SPI-2 of the MCU completes the sampling and conversion data reading operation of the ADC chip on the second circuit board.

[0077] When the SPI master reads data from the slave, it samples and captures the MISO (Master Input Slave Output) input data signal based on the SCK clock signal generated by the master; as shown in the attached figure. Figure 3 In this case, the clock feedback path synchronization principle is not adopted. Assuming that the transmission path delay of the SPI signal within the board is T0 and the transmission path delay outside the board is Td, when the SPI master reads the slave data, the delay of the MISO data signal on the SPI master side relative to the SCK clock signal is (T0+2Td). When this delay exceeds 1 / 2 of the SPI bus SCK clock cycle, it will cause the SPI master to make an error when reading the slave data. In order to improve the SPI serial communication distance, communication rate, reliability and anti-interference between the first board and the second board, the SPI serial single-ended signal is converted into an LVDS differential signal within the board and then transmitted between the boards using an LVDS chip.

[0078] As attached Figure 4In this design, the clock feedback path synchronization principle is as follows: the SPI-1 serial communication interface on the MCU side operates in master mode, and the SPI-2 serial communication interface on the MCU side operates in slave mode. When the master (MCU) reads data from the slave (ADC chip), the SPI-1 serial communication interface only generates the SCK1 clock signal for the read operation. This SCK1 clock signal loops back to the master side through the transmission path between the first and second circuit boards on the slave side and is sent to the SCK2 clock signal pin of the SPI-2 serial communication interface on the master side. At this time, the time delay of the slave data output signal SOMI transmitted to the MISO2 data signal pin of the SPI-2 serial communication interface on the master side is (T0+2Td), which avoids the problem of data reading errors caused by the asynchronous clock signal and data input signal of the SPI bus due to signal delay in the transmission path.

[0079] This invention achieves synchronization of the clock feedback path between telemetry expansion and the expanded circuit board, avoiding the problem of data reading errors caused by the asynchronous clock signal and data input signal of the SPI bus due to signal delay in the transmission path.

[0080] Example 2

[0081] Based on the same principle as the method shown in Embodiment 1 of the present invention, the embodiments of the present invention also provide a telemetry expansion method, applied to data synchronous acquisition between a first circuit board and at least one group of second circuit boards, including:

[0082] The first circuit board is equipped with a first analog-to-digital converter circuit, a controller chip, a clock chip, and a first clock buffer; the second circuit board is equipped with a second analog-to-digital converter circuit and a second clock buffer.

[0083] The first analog-to-digital converter (ADC) circuit and the second ADC circuit share a common synchronous reference clock source. That is, the clock chip is electrically connected to the first ADC circuit through the first clock buffer; the clock chip is electrically connected to the second ADC circuit through the second clock buffer.

[0084] The first analog-to-digital converter circuit and the second analog-to-digital converter circuit share a single start-up control signal.

[0085] The controller chip's first serial communication interface operates in master mode and is used to configure and read data from the registers of the first analog-to-digital converter circuit on the first circuit board.

[0086] The controller chip's first serial communication interface operates in master mode and is used to configure the registers of the second analog-to-digital converter circuit on the second circuit board.

[0087] The controller chip’s second serial communication interface operates in slave mode and is used to read data from the second analog-to-digital converter circuit on the second circuit board.

[0088] When the controller chip reads data collected by the second circuit board, its first serial communication interface generates a first SCK clock signal for the read operation. This first SCK clock signal loops back to the controller chip via the second analog-to-digital converter circuit and is then sent to the controller chip's second serial communication interface. Optionally, the controller chip is an MCU chip.

[0089] The number of first circuit boards is not limited to one set. When multiple sets of first circuit boards are set, each set of first circuit boards is connected to the MCU chip using the same principle.

[0090] Optionally, the first circuit board is provided with logic gate units; after the first analog-to-digital converter completes one sampling and conversion, it generates a first data ready signal; after the second analog-to-digital converter completes one sampling and conversion, it generates a second data ready signal; the data ready signal output terminal of the first analog-to-digital converter and the data ready signal output terminal of the second analog-to-digital converter are electrically connected to the input terminal of the controller chip through the logic gate units; optionally, the logic gate units are OR gate units.

[0091] Optionally, the first circuit board is provided with a first LVDS chip, a second LVDS chip and a third LVDS chip; the second circuit board is provided with a fourth LVDS chip, a fifth LVDS chip and a sixth LVDS chip;

[0092] The SPI terminal of the first analog-to-digital converter circuit is electrically connected to the first SPI terminal of the controller chip and the first LVDS chip.

[0093] The SPI terminal of the second analog-to-digital converter circuit is electrically connected to the fourth LVDS chip.

[0094] The first LVDS chip and the fourth LVDS chip are electrically connected;

[0095] The second SPI terminal of the first analog-to-digital converter circuit is electrically connected to the second LVDS chip; the SDO terminal of the second analog-to-digital converter circuit is electrically connected to the second LVDS chip through the fifth LVDS chip.

[0096] The clock chip is electrically connected to the sixth LVDS chip via the third LVDS chip; the sixth LVDS chip is electrically connected to the clock buffer.

[0097] Optionally, the first circuit board further includes a first PT / CT transformer and a first signal conditioning circuit; the first PT / CT transformer is electrically connected to the first analog-to-digital converter circuit through the first signal conditioning circuit.

[0098] Optionally, the second circuit board also includes a second PT / CT transformer and a second signal conditioning circuit; the second PT / CT transformer is electrically connected to the second analog-to-digital converter circuit through the second signal conditioning circuit.

[0099] Optionally, the first analog-to-digital conversion circuit includes at least one first analog-to-digital converter (ADC); the second ADC circuit includes at least one second ADC; when there is more than one first ADC, each first ADC operates in daisy-chain mode; when there is more than one second ADC, each second ADC operates in daisy-chain mode. When the first and second ADCs operate in daisy-chain mode, multiple ADCs can perform synchronous sampling, reducing the controller's control signal usage, simplifying register configuration and data reading processes for the ADCs, and reducing PCB routing complexity.

[0100] Optionally, by setting LVDS chips on the first and second circuit boards, the single-ended clock signal and single-ended data signal can be converted into LVDS differential clock signal and LVDS differential data signal for transmission, thereby ensuring communication distance, communication rate and anti-interference ability, and improving the reliability of data transmission.

[0101] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An inter-board synchronous acquisition circuit, characterized in that, Includes a first circuit board and at least one set of second circuit boards; The first circuit board includes a first analog-to-digital converter circuit, a controller chip, a clock chip, and a first clock buffer; The clock chip is electrically connected to the first analog-to-digital converter circuit via the first clock buffer; the first analog-to-digital converter circuit is electrically connected to the controller chip. The second circuit board includes a second analog-to-digital converter circuit and a second clock buffer; The second analog-to-digital converter circuit is electrically connected to the second clock buffer; The clock chip is electrically connected to the second clock buffer; The first analog-to-digital converter circuit and the second analog-to-digital converter circuit are electrically connected; the output terminal of the second analog-to-digital converter circuit is electrically connected to the input terminal of the controller chip. The start-up conversion terminal of the first analog-to-digital converter circuit, the start-up conversion terminal of the controller chip, and the start-up conversion terminal of the second analog-to-digital converter circuit are electrically connected; The first serial communication interface of the controller chip operates in master mode and is used to configure and read data from the registers of the first analog-to-digital converter circuit on the first circuit board. The first serial communication interface of the controller chip operates in master mode and is used to configure the registers of the second analog-to-digital converter circuit on the second circuit board. The second serial communication interface of the controller chip operates in slave mode and is used to perform data reading operations on the second analog-to-digital conversion circuit on the second circuit board. The first serial communication interface of the controller chip generates a first SCK clock signal for the read operation; the first SCK clock signal loops back to the controller chip through the second analog-to-digital converter circuit and is sent to the second serial communication interface of the controller chip.

2. The inter-board synchronous acquisition circuit according to claim 1, characterized in that, The first circuit board is provided with logic gate units; after the first analog-to-digital converter completes one sampling and conversion, it generates a first data ready signal; after the second analog-to-digital converter completes one sampling and conversion, it generates a second data ready signal; the data ready signal output terminal of the first analog-to-digital converter and the data ready signal output terminal of the second analog-to-digital converter are electrically connected to the input terminal of the controller chip through the logic gate units.

3. The inter-board synchronous acquisition circuit according to claim 1, characterized in that, The first circuit board is provided with a first LVDS chip, a second LVDS chip and a third LVDS chip; the second circuit board is provided with a fourth LVDS chip, a fifth LVDS chip and a sixth LVDS chip; The SPI terminal of the first analog-to-digital converter circuit is electrically connected to the first SPI terminal of the controller chip and the first LVDS chip. The SPI terminal of the second analog-to-digital converter circuit is electrically connected to the fourth LVDS chip. The first LVDS chip is electrically connected to the fourth LVDS chip; The second SPI terminal of the controller chip is electrically connected to the second LVDS chip; the SDO terminal of the second analog-to-digital converter circuit is electrically connected to the second LVDS chip through the fifth LVDS chip. The clock chip is electrically connected to the sixth LVDS chip via the third LVDS chip; the sixth LVDS chip is electrically connected to the clock buffer.

4. The inter-board synchronous acquisition circuit according to claim 1, characterized in that, The first circuit board further includes a first PT / CT transformer and a first signal conditioning circuit; the first PT / CT transformer is electrically connected to the first analog-to-digital converter circuit through the first signal conditioning circuit.

5. The inter-board synchronous acquisition circuit according to claim 1, characterized in that, The second circuit board also includes a second PT / CT transformer and a second signal conditioning circuit; the second PT / CT transformer is electrically connected to the second analog-to-digital converter circuit through the second signal conditioning circuit.

6. The inter-board synchronous acquisition circuit according to claim 2, characterized in that, The logic gate unit is an OR gate unit.

7. The inter-board synchronous acquisition circuit according to claim 1, characterized in that, The controller chip is an MCU chip.

8. The inter-board synchronous acquisition circuit according to claim 1, characterized in that, The first analog-to-digital conversion circuit includes at least one first analog-to-digital converter; the second analog-to-digital conversion circuit includes at least one second analog-to-digital converter; when there is more than one first analog-to-digital converter, each of the first analog-to-digital converters operates in daisy-chain mode; when there is more than one second analog-to-digital converter, each of the second analog-to-digital converters operates in daisy-chain mode.

9. A telemetry expansion method, applied to synchronous data acquisition between a first circuit board and at least one set of second circuit boards, characterized in that, include: The first circuit board is provided with a first analog-to-digital conversion circuit, a controller chip, a clock chip, and a first clock buffer; The second circuit board is provided with a second analog-to-digital conversion circuit and a second clock buffer; The first analog-to-digital converter circuit and the second analog-to-digital converter circuit on the second circuit board share a synchronous reference clock source. The clock chip is electrically connected to the first analog-to-digital converter circuit through a first clock buffer; the clock chip is electrically connected to the second analog-to-digital converter circuit through a second clock buffer. The first analog-to-digital conversion circuit and the second analog-to-digital conversion circuit share a single start-up conversion control signal; The first serial communication interface of the controller chip operates in master mode and is used to configure and read data from the registers of the first analog-to-digital converter circuit on the first circuit board. The first serial communication interface of the controller chip operates in master mode and is used to configure the registers of the second analog-to-digital converter circuit on the second circuit board. The second serial communication interface of the controller chip operates in slave mode and is used to perform data reading operations on the second analog-to-digital conversion circuit on the second circuit board. When the controller chip reads the data collected by the second circuit board, the first serial communication interface of the controller chip generates a first SCK clock signal for the read operation; the first SCK clock signal loops back to the controller chip through the second analog-to-digital converter circuit and is sent to the second serial communication interface of the controller chip.

10. The telemetry expansion method according to claim 9, characterized in that, The single-ended clock signal and single-ended data signal are converted into LVDS differential clock signal and LVDS differential data signal by setting LVDS chips on the first circuit board and the second circuit board, and then transmitted.

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