Method for manufacturing circuit board, circuit board, and electronic device

Abstract

A method for manufacturing a circuit board, a circuit board, and an electronic device are disclosed. The method includes: stacking printed circuit boards (PCBs) and adhesive layers in an alternating manner to obtain a PCB stack; the PCB stack includes multiple PCBs and at least one adhesive layer; performing two laminations on the PCB stack, wherein the first lamination and the second lamination include a heating stage, a isothermal stage, and a cooling stage; and fabricating circuit patterns on the outer PCB stack after the two laminations to obtain a circuit board. In this embodiment, the first lamination bonds the PCBs together, and the second lamination releases the stress in the PCB stack after the first lamination, thereby reducing warpage during reflow soldering and improving the flatness of the circuit board.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a method for manufacturing a circuit board, a circuit board, and an electronic device. Background Technology

[0002] When mounting components on a printed circuit board (PCB), reflow soldering is required to solder the components to the pads on the PCB surface. Reflow soldering involves using solder paste (a mixture of solder and flux) to attach the components to the PCB pads, and then heating it to melt the solder and achieve a permanent bond. Different heating methods, such as reflow ovens, infrared heating lamps, or hot air guns, can be used for soldering.

[0003] However, during PCB reflow soldering, the PCB typically warps and deforms due to heat, resulting in decreased flatness and increased warpage. As information and communication technology (ICT) systems become increasingly complex, with larger chip and connector packages and a greater number of solder balls, localized areas of the PCB at the soldering location become more sensitive to warpage. Therefore, it is necessary to reduce PCB warpage after reflow soldering to ensure soldering quality. Summary of the Invention

[0004] This application provides a method for manufacturing a circuit board, a circuit board, and an electronic device, which solves the problem of circuit boards being prone to warping and deformation.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a circuit board, comprising:

[0006] A printed circuit board (PCB) and an adhesive layer are stacked in an alternating manner to obtain a PCB stack; the PCB stack includes multiple PCBs and at least one adhesive layer.

[0007] The PCB stack is laminated twice, wherein the first and second laminations include a heating stage, a constant temperature stage, and a cooling stage.

[0008] Circuit patterns are fabricated on the outer PCB stack after two laminations to obtain the circuit board.

[0009] The above method uses a first pressing to bond the PCBs together, and a second pressing to release the stress in the PCB stack after the first pressing, thereby reducing warping deformation of the formed circuit board during reflow soldering and improving the flatness of the circuit board.

[0010] It should be understood that the outer PCB stack refers to the surface of the PCB stack, which can be one surface or two surfaces.

[0011] In one possible implementation, the interval between the first pressing and the second pressing is not less than a time threshold; and / or, the temperature at which the first pressing is converted to the second pressing is not greater than a temperature threshold.

[0012] The above method determines the time interval between the first and second pressing.

[0013] In one possible implementation, the cooling stage of the second pressing employs multi-stage cooling to fully release the stress in the circuit board.

[0014] In one possible implementation, the cooling time of the second pressing is longer than the cooling time of the first pressing.

[0015] The above method, through slow cooling, fully releases the stress in the circuit board.

[0016] In one possible implementation, after fabricating the circuit pattern on the outer PCB stack after two laminations to obtain the circuit board, the method further includes: performing reverse pressing on the circuit board, wherein the reverse pressing includes a heating stage, a constant temperature stage, and a cooling stage.

[0017] The above method, through reverse pressure, releases the stress formed during the fabrication of the circuit board's circuit pattern and the preceding processes, further reducing the warpage deformation of the formed circuit board during reflow soldering.

[0018] In one possible implementation, the back pressure satisfies at least one of the following conditions;

[0019] The temperature during the isothermal stage of the back pressing is lower than the temperature during the isothermal stage of the first pressing and / or the second pressing.

[0020] The maximum pressure during the isothermal phase of the back pressure test can be 200psi-500psi;

[0021] Reduce the pressure to 100-200 psi 10-30 minutes before the end of the isothermal phase of the back pressure test;

[0022] The cooling stage of the back pressure can employ multi-stage cooling;

[0023] The cooling stage of the back pressure adopts a multi-stage pressure reduction method;

[0024] The end temperature of the back pressure is 30℃-80℃.

[0025] The above method, using the aforementioned back pressure parameters, can fully release the stress inside the circuit board.

[0026] In one possible implementation, the method further includes: applying solder mask to the circuit board; and sequentially reflowing and / or press-baking the solder masked circuit board.

[0027] The above method, by realistically simulating the heat treatment process of reflow soldering, and then pressing and baking the reflowed circuit board, can correct the warping deformation of the circuit board during reflow, thereby reducing the warping deformation of the circuit board during reflow soldering and improving the flatness of the circuit board.

[0028] In one possible implementation, the peak temperature of the reflow is greater than the solidus temperature of the solder, and the peak temperature is maintained for a first duration; the duration during which the reflow temperature is greater than the solidus temperature is a second duration, the second duration being longer than the first duration.

[0029] In one possible implementation, the pressing of the reflowed circuit board includes: hot pressing and cold pressing the reflowed circuit board in sequence, wherein the temperature of the hot pressing is higher than the glass transition temperature of the circuit board, and the temperature of the cold pressing is lower than the glass transition temperature.

[0030] Secondly, embodiments of this application also provide a circuit board, which is prepared by implementing the method described in the first aspect or any one of the first aspects.

[0031] Thirdly, embodiments of this application also provide an electronic device, including a processor, a memory, and the electronic device including the circuit board described in the second aspect, wherein the processor is disposed on and coupled to the circuit board, and the memory is disposed on and coupled to the circuit board.

[0032] It is understood that the circuit board provided in the second aspect and the electronic device provided in the third aspect both include circuit boards prepared by the method described in the first aspect or any one of the methods described in the first aspect. Therefore, the beneficial effects they can achieve can be referred to the corresponding beneficial effects in the first aspect, and will not be repeated here. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0034] Figure 2A A schematic diagram of a circuit board structure provided in an embodiment of this application;

[0035] Figure 2B This is a schematic diagram of another circuit board structure provided in an embodiment of this application;

[0036] Figure 3 A schematic flowchart illustrating a method for fabricating a circuit board according to an embodiment of this application;

[0037] Figures 4A-4C This is a cross-sectional schematic diagram of a structure formed during the fabrication process of a circuit board, as provided in an embodiment of this application.

[0038] Figure 5 An example diagram illustrating the changes in pressure and temperature over time during bimodal pressing, provided in an embodiment of this application;

[0039] Figures 6A-6F Example diagrams illustrating the arrangement of circuit boards in some pressing and baking processes provided for embodiments of this application;

[0040] Figures 7A-7B A schematic diagram comparing the maximum warpage or fluctuation of a circuit board prepared with and without bimodal lamination, reverse lamination, reflow, and pressure baking after reflow, provided for an embodiment of this application; Detailed Implementation

[0041] The embodiments of this application are described below with reference to the accompanying drawings.

[0042] In this document, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, in the description of the embodiments of this application, unless otherwise stated, "multiple" refers to two or more. "Above" includes the stated number; for example, "two or more" includes two.

[0043] In the following text, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0044] The orientations mentioned in the embodiments of this application, such as "upper", "lower", "inner", "outer", "side", "top", "bottom", etc., are only for reference to the directions in the accompanying drawings. Therefore, the orientation terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to imply that the indicated device or element must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this application.

[0045] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation", "connection", "linking", and "set on" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0046] like Figure 1 The image shows an electronic device provided in an embodiment of this application. This electronic device 10 can be a server, a gateway device or network device such as a switch or router, or a terminal such as a laptop, desktop computer, tablet computer, mobile phone, virtual reality device, augmented reality device, smart home device, or in-vehicle device.

[0047] The electronic device 10 may include a circuit board 11 and at least one chip soldered to the circuit board 11. Figure 1 Taking processor 12 as an example, the circuit board 11 can also be used to solder other chips or components, but is not limited to processor 12. Furthermore, circuit board 11 can also couple other chips or components through other connection methods, such as connecting memory 13 to circuit board 11.

[0048] The circuit board 11 consists of at least one printed circuit board (PCB). Each PCB may have one or two wiring layers. Chips or components soldered or otherwise connected on the circuit board 11 are coupled to the wiring layers on or inside the circuit board 11 to enable communication between them.

[0049] In one implementation, the processor 12 can be mounted on and coupled to the circuit board 11. For example, the circuit board 11 has ball grid array (BGA) pads 111, and the processor 12 has BGA solder balls 121. The solder balls 121 of the processor 12 can be soldered to the BGA pads 111 of the circuit board 11 to achieve coupling between the processor 12 and the wiring layer inside the circuit board 11. The processor 12 can communicate with the memory 13 through the circuit board 11.

[0050] Processor 12 can be a central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), deep-learning processing unit (DPU), tensor processing unit (TPU), accelerated processing unit (APU), or other processors. Processor 12 can also be a system on chip (SoC) composed of a CPU and other peripheral devices (such as memory and GPU).

[0051] The memory 13 may include internal memory (also called RAM) and external memory (such as hard disk, flash memory, etc.). The memory 13 may be mounted on the circuit board 11, for example, connected to the circuit board 11 via a connector to achieve coupling with the wiring layer inside the circuit board 11. The connector may be a gold finger connector or other connector. The memory 13 may store executable program code, which includes instructions. The processor 12 executes the instructions stored in the memory 13 to implement various functions of the electronic device and data processing.

[0052] It should also be understood that, not limited to Figure 1 The electronic device shown, electronic device 10 may also include more or fewer units.

[0053] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0054] like Figures 2A-2B The diagram shown is a structural schematic of the circuit board 11.

[0055] like Figure 2A As shown, the circuit board 11 may include, but is not limited to, at least one PCB 110 and an adhesive layer 120 disposed between two adjacent PCB layers.

[0056] like Figure 2A As shown, each PCB 110 layer includes a substrate 1101 and wiring layers 1102 disposed on both surfaces of the substrate 1101. It should be understood that the substrate 1101 used in each PCB layer may be made of the same or different materials.

[0057] The substrate 1101 can be made of insulating materials such as epoxy resin, polyphenylene ether, polypropylene (PP), polytetrafluoroethylene (PTFE), bismaleimide triazine (BT), glass ceramic matrix, or glass, or an aluminum plate covered with insulating material. The wiring layer 1102 can be formed by copper plating on the surface of the substrate 1101.

[0058] like Figure 2BAs shown, the circuit board 11 can be composed of multiple PCBs with different substrate materials, including at least one first PCB 110a, at least one second PCB 110b, and an adhesive layer 120 disposed between two adjacent PCBs. The first PCB 110a includes a substrate 110a1 and wiring layers 110a2 disposed on both surfaces of the substrate 110a1; the second PCB 110b includes a substrate 110b1 and wiring layers 110b2 disposed on both surfaces of the substrate 110b1. Here, we take the example where both surfaces of the substrate contain wiring layers. It should be understood that in some first PCBs 110a or second PCBs 110b, one surface of the substrate contains a wiring layer.

[0059] The substrate 110a1 of the first PCB 110a and the substrate 110b1 of the second PCB 110b are made of different materials. The coefficient of thermal expansion (CTE) of the first PCB 110a is greater than that of the second PCB 110b. It should be understood that "CTE of PCB" in this document refers to the CTE of the PCB substrate.

[0060] like Figure 2B As shown, in order to reduce the warpage of the circuit board, the first PCB110a with high CTE can be placed between two second PCBs110b with low CTE.

[0061] The substrate of the first PCB 110a is a substrate with a coefficient of thermal expansion greater than a first threshold. For example, the first threshold may be 10 ppm / ℃. For instance, the substrate material may be epoxy resin or polyphenylene ether, etc., with a CTE of 10-20 ppm / ℃ in the X and Y directions, such as 17 ppm / ℃. The X and Y directions are both perpendicular to the thickness direction of the substrate, with the X direction perpendicular to the Y direction.

[0062] The substrate of the second PCB110b is a substrate with a coefficient of thermal expansion less than a second threshold. For example, the second threshold may be 5 ppm / ℃. For instance, the substrate material may be BT, aluminum, or glass, with a CTE of 3-5 ppm / ℃ in the X and Y directions. The thickness of the second PCB may be 0.05-0.3 mm, for example, 0.075 mm.

[0063] The aforementioned adhesive layer 120 may be an adhesive layer formed from PP resin material or the like.

[0064] It should be understood that Figure 2A and Figure 2BThe following example illustrates the concept of a 3-layer PCB forming a 6-layer wiring layer. It should be understood that the circuit board 11 is not limited to a 3-layer PCB; it may also include more or fewer PCB layers. It is not limited to a 6-layer wiring layer; it may also include more or fewer wiring layers, such as 4, 8, 10, or 12 layers.

[0065] It should also be understood that the circuit board 11 may include vias (not shown in the figure). Chips or components that are soldered or connected to the circuit board 11 can be connected to their internal wiring layers through vias, and the wiring layers can also be interconnected through through-holes, blind vias, and buried vias.

[0066] It should also be understood that, although not distinguished, different PCB layers, the first PCB, or the second PCB layer in this application generally have different wiring layers, that is, different circuit functions.

[0067] like Figure 3 The diagram shown is a flowchart illustrating a method for fabricating a circuit board according to an embodiment of this application. Figures 4A-4C The diagram shown is a cross-sectional view of the circuit board structure formed during the fabrication process according to an embodiment of this application. This method can be used to form the aforementioned structure. Figure 1 , Figure 2A or Figure 2B The circuit board shown may include, but is not limited to, some or all of the following steps:

[0068] S01: Provide multiple PCBs and at least one adhesive layer.

[0069] Here, "multiple" refers to two or more. A PCB can be obtained by patterning a copper-clad layer.

[0070] Between layers, the PCB can also undergo blackening and / or browning treatments to create a microscopic roughness and organic metal layer on the inner copper surface, enhancing adhesion to the adhesive layer. Blackening involves forming a black oxide film (such as copper oxide) on the inner wiring layer (such as inner copper foil), while browning involves forming an organic film on the inner copper foil.

[0071] S02: Stack a multilayer PCB and at least one adhesive layer to obtain a PCB stack.

[0072] The PCB and adhesive layers are arranged alternately. The material of the substrate for each PCB layer is not limited. For example... Figure 2A As shown.

[0073] In other embodiments, to reduce warpage of the circuit board, the multilayer PCB includes PCBs of different materials. For example, the multilayer PCB includes at least one first PCB 110a and a plurality of second PCBs 110b. The CTE of the first PCB 110a is greater than the CTE of the second PCBs 110b. Figure 4A To prepare Figure 2B The circuit board shown is used as an example for illustration.

[0074] Figure 4A To prepare Figure 2B The circuit board shown is used as an example. A first PCB 110a with a high CTE is placed between two second PCBs 110b with low CTE. In this way, the CTE of the surface PCB of the circuit board is lower, resulting in less thermal expansion and warpage during reflow, and better dimensional stability.

[0075] S03: Perform double-peak lamination on the PCB stack, such as... Figure 4A As shown in the diagram. Bimodal pressing involves two consecutive pressing processes, which can be divided into a first pressing and a second pressing. The highest temperature used in the second pressing is lower than the highest temperature used in the first pressing.

[0076] Specifically, the PCB stack is placed in a laminator and laminated twice consecutively according to the dual-peak lamination parameters to bond the multi-layered PCB together. After the second lamination, when the PCB temperature drops to a preset temperature, such as below 60°C, the pressure is released, the PCB is demolded, and removed from the laminator. "Lamination" refers to bonding the PCB stack together through high temperature and pressure. Both the first and second laminations include a heating phase, a isothermal phase, and a cooling phase. During lamination, parameters such as temperature, pressure, heating rate, pressurization rate, and time need to be controlled at each stage; these parameters are known as the dual-peak lamination parameters. The dual-peak lamination parameters are input into the laminator or used to adjust the temperature, pressure, heating rate, pressurization rate, and time during lamination.

[0077] The first lamination process involves bonding multiple layers of PCB into a single unit using an adhesive material (such as PP resin). Depending on the temperature, the first lamination process includes three stages: heating, holding, and cooling. The heating stage, also known as the initial pressure stage, involves a continuous increase in temperature and pressure. The PP resin melts due to the rising temperature, penetrating the bonding surface and filling gaps in the PCB surface circuitry. Pressure is applied to eliminate air bubbles generated in the molten adhesive layer. The holding stage, also known as the full-pressure stage, maintains a high temperature and maximum pressure to ensure the PP resin near the PCB surface fully cures, the PCB substrate is uniformly plasticized, and the layers are fused together under pressure to form a uniform and dense whole. Once the resin between the PCB layers has fully cured and fused or bonded to the PCB substrate, the cooling stage begins. This cooling stage, also known as the cold pressing stage, involves reducing the temperature of the multilayer PCB under appropriate pressure. It should be understood that during the constant temperature stage, the temperature remains roughly constant at a certain temperature or within a certain temperature range; during the heating stage, the temperature tends to rise; similarly, during the cooling stage, the temperature tends to fall.

[0078] The second lamination involves re-laminating the PCB stack obtained from the first lamination to release stress and other defects from the first lamination. This second lamination process includes three stages: heating, holding, and cooling. During the heating stage, the temperature and pressure gradually increase, causing the polypropylene resin (PP) to soften. Since the adhesive layer (such as PP resin) has already undergone a chain reaction during the first lamination, it will not melt again. In the holding stage, the temperature is maintained at a high level, and the applied pressure reaches its maximum. At this point, the stress in the PCB and adhesive layer diffuses to the edges and is released into the environment. During the cooling stage, the temperature of the PCB multilayer is reduced while maintaining appropriate pressure. Slow cooling reduces stress accumulation. In the second lamination, the applied pressure primarily prevents the already laminated PCB stack from expanding due to heat, while the heat treatment releases stress within the PCB stack.

[0079] Optionally, the heating phase can be carried out in a multi-stage heating manner, and similarly, the cooling phase can also be carried out in a multi-stage cooling manner.

[0080] It should be understood that a single pressing process can also be divided based on pressure, including a pressurization stage, a constant pressure stage, and a depressurization stage. Similarly, the pressurization stage can also employ multi-stage pressurization, and the depressurization stage can also employ multi-stage depressurization.

[0081] The first pressing can be a pressing process used in the prior art, and its pressing parameters can be the parameters used in pressing in the prior art. The second pressing is an additional pressing based on the first pressing, and its pressing parameters can satisfy at least one of the following conditions:

[0082] a) The high-temperature curing temperature is 100℃-400℃, for example, 200℃ or 250℃, and the high-temperature curing time is 20min-100min, for example, 50min or 65min. Here, the high-temperature curing temperature is the temperature of the constant temperature stage, and the high-temperature curing time is the duration of the constant temperature stage.

[0083] b) The maximum pressure during the isothermal stage can be 200 psi-500 psi, such as 250 psi, 300 psi, or 350 psi. Optionally, the maximum pressure during the isothermal stage in the second compression is less than the maximum pressure during the isothermal stage in the first compression.

[0084] c) Reduce the pressure to 100-200 psi 10-30 minutes before the end of the isothermal phase. For example, reduce the pressure to medium pressure, such as 120 psi, 150 psi, or 180 psi, 15 minutes or 20 minutes before the end of the isothermal phase.

[0085] d) The cooling stage adopts multi-stage cooling, with each stage lasting 5-20 minutes. For example, a 3-stage cooling stage is adopted, first reducing the temperature from a high temperature (e.g., 200℃) to 170℃, then successively reducing it to 120℃ and 60℃, with each stage of cooling lasting about 10 minutes.

[0086] e) The end temperature of the second pressing (i.e. the oven exit temperature) is, for example, 30°C-80°C, such as 60°C.

[0087] f) The interval between the first and second pressing operations shall not be less than a time threshold. This time threshold is between 5 and 20 minutes. During this time period, the temperature and pressure at the end of the first pressing operation can be maintained. For example, the time interval between the first and second pressing operations may be 10 minutes.

[0088] g) The temperature at which the first pressing is converted to the second pressing is not greater than a temperature threshold, which can be 80-180℃ or 80-120℃. For example, the temperature at which the first pressing is converted to the second pressing is 100℃.

[0089] Optionally, the total duration of the second pressing can be greater than the total duration of the first pressing, or the duration of the isothermal phase in the second pressing can be greater than the duration of the isothermal phase in the first pressing.

[0090] In this embodiment, the multilayer PCB is pressed together by a first pressing, and the stress inside the pressed PCB is released by a second pressing, thereby reducing the deformation of the circuit board caused by stress.

[0091] It should also be understood that the first and second pressing are consecutive.

[0092] like Figure 5 The diagram shows a schematic of bimodal compression. The first compression consists of a heating stage ①, a isothermal stage ②, and a cooling stage ③. The second compression consists of a heating stage ④, a isothermal stage ⑤, and a cooling stage ⑥. The cooling stage ⑥ in the second compression employs a three-stage cooling process, and the cooling time is longer than that in the first compression cooling stage, in order to fully release stress.

[0093] Table 1 below shows some parameters for the first and second pressing.

[0094]

[0095] Table 1

[0096] As shown in Table 1, in the first pressing, the pressure can be increased to P1 and the temperature to W1. Further, while keeping the temperature W1 constant, the pressure can be increased to its maximum value in multiple stages, for example, in two stages: increasing the pressure to the maximum pressure, sequentially to P2 and P3. In the pressure increase stage, for example, in the first stage, the pressure is increased to P2 after time T2 and held for time T3. In the second stage, the pressure is increased to P3 after time T4 and then held for time T5. Further, keeping the maximum pressure P3 constant, the temperature is increased to the highest temperature in multiple stages, for example, in three stages: increasing the temperature to the highest temperature, sequentially to W2, W3, and W4. In the temperature increase stage, for example, in the first stage, the temperature is increased to W2 after time T6 and held for time T7; in the second stage, the temperature is increased to W3 after time T8 and held for time T9; in the third stage, the temperature is increased to W4 after time T10 and held for time T11. Furthermore, maintain the highest pressure P3 and a certain high temperature W5 for a considerable period of time. The high temperature W5 can be slightly lower than the highest temperature W4. For example, after time T12, the temperature drops from W14 to W15, and then is maintained for time T13. After sufficient integration, multi-stage cooling and depressurization can be employed. For example, first depressurize to P4, then cool to W6, then depressurize to P5 and cool to W7. For instance, during depressurization and cooling, firstly, the pressure drops from P3 to P4 over time T14 and is maintained for time T15; the temperature W5 drops to W6 over time T16 and is maintained for a time T14 + T15 - T16; then, the pressure drops from P4 to P5 over time T17 and is maintained for time T18; the temperature W6 drops to W7 over time T19 and is maintained for a time T17 + T18 - T19.

[0097] In some embodiments, the pressure P1 < P2 < P3. P1 can be 50-150 psi, for example, 90 psi or 110 psi; P2 can be 150-350 psi, for example, 220 psi or 300 psi; P3 can be 300-500 psi, for example, 400 psi or 450 psi. T1 can be 5-20 min, for example, 15 min. T2 and T4 can be 1-8 min, for example, 3 min, which can be determined based on the pressure differential. The larger the pressure differential, the longer the pressurization time T2 or T4 can be. T3 and T5 can be 0-10 min, for example, 4 min.

[0098] In some embodiments, the temperature W1 < W2 < W3 < W4. W1 can be 100-200℃, for example, 150℃; W2 can be 150-220℃, for example, 160℃; W3 can be 150-300℃, for example, 200℃; W4 can be 180-300℃, for example, 210℃. T6, T8, and T10 can be 1-20 min; T7 and T9 can be 0-10 min each, and T11 can be 10-50 min. For example, T6 is 6 min, T7 is 0 min, T8 is 8 min, T9 is 0 min, T10 is 5 min, and T11 is 30 min. The duration of the isothermal phase, T13, can be 60-180 min, and T12 can be 0-20 min.

[0099] In some embodiments, pressure P3 > P4 > P5, and temperature W5 > W6 > W7. P4 can be 150-300 psi, for example, 220 psi; P5 can be 50-200 psi, for example, 150 psi. W6 can be 100-200°C, for example, 130°C; W7 can be 20-100°C, for example, 60°C. The depressurization time T14 and T17 can be 1-10 min; the pressure holding time T15 and T18 can be 10-60 min; and the cooling time T16 and T19 can be 5-60 min.

[0100] As shown in Table 1, in the second pressing, the pressure can be increased to P6 through multiple stages or one stage over time T20, and held for time T21; the temperature can be increased to W8 over time T22, and held for time T20+T21-T22; further, while keeping the temperature W8 constant, the pressure is increased to P7 within time T23 and held for time T24; further, while keeping the pressure P7 constant, the temperature is reduced in multiple stages, for example, in three stages, decreasing to W9, W10, and W11 in sequence. For example, first, the temperature decreases from W8 to W9 over time T25, and is held for time T26; then, the temperature decreases from W9 to W10 over time T27, and is held for time T28; further, the temperature decreases from W9 to W10 over time T29, and is held for time T30.

[0101] In this order, P7 > P6 > P5, W8 > W7, and W8 > W9 > W10 > W11. P6 can be 200-400 psi, for example, 300 psi or 280 psi; P7 can be 100-200 psi, for example, 150 psi or 180 psi. W8 can be 150-250℃, for example, 200℃; W9 can be 150-220℃, for example, 160℃; W3 can be 100-150℃, for example, 110℃; W4 can be 20-100℃, for example, 60℃. T20 can be 1-10 min, T21 can be 20-60 min, T22 can be 5-30 min, T23 can be 1-10 min, and T24 can be 5-30 min. T25, T27, and T29 can be 1-20 min, and T26, T28, and T30 can be 5-30 min. For example, T20 is 3 min, T21 is 50 min, T22 is 20 min, T23 is 3 min, T24 is 15 min, T25, T27, and T29 are 5 min, and T26, T28, and T30 are 12 min, 12 min, and 25 min, respectively.

[0102] It should be understood that Table 1 is an illustrative example, and other time, temperature, pressure, etc., can also be used to control the pressing process.

[0103] Circuit boards obtained by double-peak lamination release stress during the second lamination process, reducing warping during reflow soldering and thus lowering the risk of cracking.

[0104] S04: Fabricate PCB circuit patterns on the PCB stack after double-peak lamination to obtain the circuit board.

[0105] Specifically, circuit patterns can be fabricated on the outer PCB stack after double-peak lamination, where the outer PCB stack refers to the surface of the PCB stack, such as... Figure 4B As shown, S04 may include, but is not limited to, some or all of the following steps:

[0106] S041: Multiple holes 201 are made in the PCB stack after double-peak lamination, penetrating one or more PCB layers.

[0107] Specifically, hole 201 can be prepared by using drilling techniques such as mechanical drilling.

[0108] S042: Metallized PCB stack-up and vias thereon 201.

[0109] The metallization process includes, but is not limited to, one of the following: chemical copper plating, black hole, black shadow, graphene, etc. After metallization, a first metal layer 202 is formed on the upper and lower surfaces of the PCB stack and on the inner wall of the hole 201.

[0110] S043: Electroplating a first metal is performed on the surfaces of the metallized hole 201 and metal layer 202 to form a second metal layer 203 and a via 204.

[0111] It should be understood that after a metal wall is formed on the surface of hole 201, the hole becomes conductive, and at this point it is called via 204.

[0112] S044: The second metal layer 203 on the surface of the patterned PCB stack forms a circuit pattern.

[0113] In some embodiments, after graphical processing, the method may further include a backpressure process to release stresses formed during previous processes.

[0114] S05: Apply back pressure to the circuit board.

[0115] The back-pressure process includes a heating phase, a isothermal phase, and a cooling phase. During the heating phase, both temperature and pressure gradually increase. In the isothermal phase, the temperature remains relatively constant at a high level, and the applied pressure reaches its maximum. At this point, the stress in the circuit board diffuses towards the edges and is released into the environment. During the cooling phase, the temperature and pressure are gradually reduced to decrease stress accumulation. Back-pressure helps to make the circuit board flatter and also releases stress formed during previous processes.

[0116] Back pressing is an additional pressing process based on bi-peak pressing, and its pressing parameters can satisfy at least one of the following conditions:

[0117] a) The temperature during the isothermal stage of the back pressing can be lower than the temperature during the isothermal stage of the first pressing and / or the second pressing.

[0118] b) The maximum pressure during the isothermal phase can be 200psi-500psi, such as 250psi, 300psi or 400psi.

[0119] c) Reduce the pressure to 100-200 psi 10-30 minutes before the end of the isothermal phase. For example, reduce the pressure to medium pressure, such as 120 psi, 150 psi, or 180 psi, 15 minutes or 20 minutes before the end of the isothermal phase.

[0120] d) The temperature can be reduced in multiple stages during the cooling phase, and the pressure can also be reduced in multiple stages. The duration of each stage is 20-80 minutes.

[0121] e) The end temperature of the back pressure (i.e. the furnace exit temperature after back pressure) is 30℃-80℃, for example, the furnace exit temperature is 50℃.

[0122] Optionally, the pressure during the isothermal stage of the second pressing may be greater than or less than the pressure during the isothermal stage of the first or second pressing.

[0123] Table 2 below provides examples of back pressure parameters.

[0124]

[0125] Table 2

[0126] As shown in Table 2, during the back pressure process, the temperature can be raised to the highest temperature W3 in multiple stages, and the pressure rise refers to the highest pressure P3. The high temperature W3 and high pressure P3 are maintained unchanged for a period of time. Then, the temperature and pressure are reduced. The temperature and pressure can be reduced at the same time, or the pressure can be kept unchanged. The temperature is first reduced to the lowest temperature, and then the lowest temperature W5 is kept unchanged. The pressure is then slowly reduced to the lowest pressure.

[0127] In this system, W1 < W2 < W3, W3 > W4 > W5, and P1 < P2 < P3, P3 > P4 > P5. For example, W1 can be 100-180℃, W2 can be 150-200℃, W3 can be 170-250℃, W4 can be 80-150℃, and W5 can be 20-80℃. Another example is W1 at 150℃, W2 at 180℃, W3 at 200℃, W4 at 120℃, and W5 at 60℃. For example, P1 can be 50-150psi, P2 at 150-300psi, P3 at 300-500psi, P4 at 200-400psi, and P5 at 50-150psi; yet another example is P1 at 100psi, P2 at 260psi, P3 at 420psi, P4 at 320psi, and P5 at 100psi, etc.

[0128] It should be understood that, in each stage marked with a serial number, the sum of the heating / cooling time and the holding time is equal to the sum of the pressure heating / cooling time and the pressure holding time. For example, T1 or T2 can be 2-20 minutes, for example, both being 10 minutes. T3, T4, and T5 can be 1-10 minutes. For example, T3 is 10 minutes, T4 is 4 minutes, and T5 is 3 minutes. For example, T6 and T7 can be 10-30 minutes, for example, T6 is 22 minutes and T7 is 3 minutes. For example, T8 can be 30-100 minutes, for example, T8 is 60 minutes. For example, T9 can be 20-60 minutes, and T10 and T11 can be 5-20 minutes, for example, T9 is 40 minutes, and T10 and T11 are both 10 minutes. For example, T12 can be 10-30 minutes, for example, T12 is 20 minutes. For example, T13 can be 20-60 min and T14 can be 10-60 min, such as T13 being 30 min and T14 being 25 min.

[0129] It should be understood that numbers 1-3 can be the heating stage, numbers 4-5 can be the constant temperature stage, and numbers 6-8 can be the cooling stage.

[0130] It should also be understood that back pressure can release stress from previous processes, thereby further reducing warpage of the circuit board during reflow soldering and further reducing the risk of circuit board cracking.

[0131] S06: Apply solder mask to the circuit board. For example... Figure 4C As shown.

[0132] Exposed copper on the surface of a circuit board is prone to oxidation when it reacts with oxygen in the air, which reduces the board's performance and shortens its lifespan. Therefore, solder masking is necessary. The purpose of solder masking is to apply a layer of solder resist (301) to the surface of the circuit board to protect the copper. Green solder resist is the most common type. The "solder masking" process includes applying the solder resist, exposure, and development.

[0133] In some embodiments, after step S05 or S06, a reflow and / or press-bake process may also be included.

[0134] S07: Reflow and / or pressure bake the circuit board.

[0135] Reflow is a heat treatment process similar to reflow soldering, but at this stage, the circuit board is not yet coated with solder and is not being soldered. During reflow, the circuit board needs to be heated to a temperature above the solidus line of the solder and held at that temperature for a preset duration. For example, using a lead-free circuit board and solder paste, the solidus line temperature is 217°C, and the preset duration can be 100-200 seconds, for example, 120-150 seconds. Optionally, the peak temperature of the circuit board (also called the board surface peak temperature) must at least reach the target temperature (above the solidus line temperature), and the residence time at that target temperature must be at least 10-40 seconds, for example, 20-30 seconds. This target temperature can be 240-300°C, for example, 250-270°C.

[0136] It should be understood that the circuit board may warp after reflow. Furthermore, the reflowed circuit board can be press-baked.

[0137] Press-pressing involves applying pressure to a circuit board at a specific temperature. Based on temperature, press-pressing can include both hot and cold pressing. Generally, hot pressing is performed first, followed by cold pressing. The pressures for hot and cold pressing can be the same or different. The pressure can range from 0.1 MPa to 1 MPa, for example, 0.3 MPa. The hot pressing temperature can be higher than the glass transition temperature (Tg) of the circuit board, for example, Tg + 10°C, while the cold pressing temperature is lower than this Tg value, ranging from 20 to 100°C, for example, room temperature or 50°C. The hot pressing duration can be 1-3 hours, and the cold pressing duration can be 0.5-2 hours, for example, 2 hours for hot pressing and 1 hour for cold pressing. It should be understood that "hot pressing" refers to applying pressure to the circuit board at a higher temperature (e.g., above 100°C), while "cold pressing" refers to applying pressure to the circuit board at a lower temperature (e.g., below 100°C).

[0138] During the pressing and baking process, circuit boards can be stacked back-to-back according to the warping direction after reflow. For example... Figure 6A The diagram shows an example of the circuit board arrangement in the press-bake process. Here, the raised surface of the circuit board is referred to as the back side of the circuit board. When circuit boards A and B are placed back to back, their warping directions are opposite. Circuit boards A and B are the circuit boards after the aforementioned reflow process.

[0139] Optionally, the circuit board may or may not warp after reflow; the circuit board can also be arranged in other ways. For example... Figures 6B-6F The following are several circuit board arrangement methods.

[0140] The aforementioned reflow and pressure baking process involves preheating the circuit board at the temperature required for reflow soldering or above, so that the warpage of the circuit board is restored to flatness after pressure baking, which can reduce warpage during subsequent reflow soldering.

[0141] Furthermore, the circuit boards can be tested and packaged.

[0142] This application also provides a circuit board prepared by the above method.

[0143] The following is combined with Figure 7A and Figure 7B Describe the effects that can be achieved by implementing the above methods.

[0144] It is evident that when using bimodal lamination, reverse lamination, reflow, and pressure baking, the maximum warpage or fluctuation of the circuit board after reflow can be controlled within 100µm, which is equivalent to a reduction of more than 80% compared to when bimodal lamination, reverse lamination, reflow, and pressure baking are not used. Therefore, the circuit board prepared by the above method can solve the problem of cracking caused by excessive warpage during the soldering of large-size devices.

[0145] It should be noted that the flowcharts described in the various embodiments of the present invention are merely one example. Without departing from the spirit of the present invention, the steps in each flowchart can be modified or changed in various ways, such as executing the steps in the flowchart in a different order, or deleting, adding or modifying certain steps.

[0146] The technical terminology used in the embodiments of this invention is for illustrative purposes only and is not intended to limit the invention. In this document, the singular forms “a,” “the,” and “the” are used to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of “comprising” and / or “including” in the specification means the presence of the stated feature, integral, step, operation, element, and / or component, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, and / or components.

[0147] It should also be understood that in the various embodiments of this application, "at least one" and "one or more" refer to one, two, or more. References to "one embodiment" or "some embodiments" described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0148] The equivalents (if any) of the corresponding structures, materials, actions, and all means or steps and functional elements in the appended claims are intended to include any structure, material, or action used in conjunction with other expressly claimed elements to perform the function. The description of the invention is given for the purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: A printed circuit board (PCB) and an adhesive layer are stacked in an alternating pattern to obtain a PCB stack; the PCB stack includes multiple PCBs and at least one adhesive layer; the PCB includes a substrate and wiring layers disposed on both surfaces of the substrate; The PCB stack is laminated twice consecutively. Both the first and second laminations include a heating stage, a constant temperature stage, and a cooling stage, and both also include a pressure increase stage, a constant pressure stage, and a pressure decrease stage. The highest temperature of the second lamination is lower than the highest temperature of the first lamination, and the highest pressure of the second lamination is greater than the pressure when the first lamination is converted to the second lamination. During the isothermal phases of the first and second pressing, the applied pressure reaches its maximum value; the maximum pressure during the isothermal phase of the second pressing is less than the maximum pressure during the isothermal phase of the first pressing. The circuit pattern is fabricated on the outer PCB stack after two laminations to obtain the circuit board. The circuit board is subjected to back pressure, which includes a heating stage, a constant temperature stage, and a cooling stage. The temperature of the constant temperature stage during the back pressure is lower than the temperature of the constant temperature stage during the first pressing and / or the second pressing.

2. The method according to claim 1, characterized in that, The interval between the first pressing and the second pressing is not less than a time threshold; and / or, The temperature at which the first pressing is converted to the second pressing does not exceed a temperature threshold.

3. The method according to claim 1 or 2, characterized in that, The cooling stage of the second pressing process employs multi-stage cooling.

4. The method according to claim 1 or 2, characterized in that, The cooling time for the second pressing is longer than the cooling time for the first pressing.

5. The method according to claim 1, characterized in that, The back pressure satisfies at least one of the following conditions: The maximum pressure during the isothermal phase of the back pressure test is 200 psi-500 psi; Reduce the pressure to 100-200 psi 10-30 minutes before the end of the isothermal phase of the back pressure test; The cooling stage of the back pressure adopts multi-stage cooling; The cooling stage of the back pressure adopts a multi-stage pressure reduction method; The end temperature of the back pressure is 30℃-80℃.

6. The method according to any one of claims 1, 2, and 5, characterized in that, The method further includes: The circuit board is solder masked; Reflow and / or pressure heat treatment are performed on the circuit board after solder masking.

7. The method according to claim 6, characterized in that, The peak temperature of the reflow is greater than the solidus temperature of the solder, and the peak temperature is maintained for a first duration; the duration during which the reflow temperature is greater than the solidus temperature is a second duration, and the second duration is greater than the first duration.

8. The method according to claim 6, characterized in that, The pressing and baking process for the reflowed circuit board includes: The reflowed circuit board is subjected to hot pressing and cold pressing in sequence. The temperature of the hot pressing is higher than the glass transition temperature of the circuit board, and the temperature of the cold pressing is lower than the glass transition temperature.

9. A circuit board, characterized in that, The circuit board is prepared by the method described in any one of claims 1-7.

10. An electronic device, characterized in that, It includes a processor, a memory, and a circuit board as described in claim 9, wherein the processor is disposed on and coupled to the circuit board; and the memory is disposed on and coupled to the circuit board.

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