Display device

Abstract

A display device is provided, the display device including: a substrate including a pixel area and a peripheral area; pixels located in the pixel area of the substrate, each including a light emitting device having a light emitting area, the light emitting device including a first electrode, an emission layer, and a second electrode; data lines and scan lines connected to the pixels; a power line configured to supply power to the light emitting device, the power line including a first conductive layer at the same layer as the data lines and a second conductive layer located on the first conductive layer; and an insulating layer between the power line and the first electrode. The first electrode, the emission layer, and the second electrode are stacked at the light emitting area. The second conductive layer includes a first portion corresponding to the light emitting area and a second portion not corresponding to the light emitting area. When viewed in a direction perpendicular to a main surface of the substrate, the second portion is closer to the first electrode than the first portion.

Description

[0001] This application is a divisional application of the patent application No. 201711130304.X with the title of "Display device" and filed on November 15, 2017. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a display device. BACKGROUND

[0003] The display device includes a plurality of pixels each including a display element. Each pixel includes a line and at least one transistor connected to the line. The at least one transistor drives the display element.

[0004] The transistor is electrically connected to the display element to drive the display element using a signal applied from the line.

[0005] At least some of the lines overlap the display element. The line overlapping the display element forms a step difference at a lower portion of the display device. The step difference causes surface unevenness of the display element, which causes a white angle dependency (WAD) according to a viewing angle of the display device. SUMMARY

[0006] Aspects of embodiments of the present disclosure are directed to a display device having improved display quality.

[0007] According to embodiments of the present disclosure, a display device includes a substrate including a pixel region and a peripheral region, a pixel located in the pixel region of the substrate, the pixel including at least one transistor and a light emitting device connected to the transistor, a data line and a scan line connected to the pixel, and a power line supplying power to the light emitting device. The transistor includes an active pattern disposed on the substrate, a source electrode and a drain electrode each connected to the active pattern, and a gate electrode located on the active pattern with a gate insulating layer interposed between the gate electrode and the active pattern. The display device further includes an interlayer insulating layer covering the gate electrode, the interlayer insulating layer including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer stacked in order, and a protection layer located on the interlayer insulating layer. The power line includes a first conductive layer parallel to the data line, the first conductive layer located on the second interlayer insulating layer, and a second conductive layer disposed on the third interlayer insulating layer, the second conductive layer connected to the first conductive layer. The light emitting device is located on the protection layer. The third interlayer insulating layer includes a recess in a region in which the light emitting device and the second conductive layer overlap each other. The second conductive layer is located in the recess.

[0008] The protection layer can include an organic insulating layer.

[0009] The third interlayer insulating layer can include a first sub-insulating layer including an inorganic insulating layer, and a second sub-insulating layer on the first sub-insulating layer, the second sub-insulating layer including an organic insulating layer.

[0010] The recess can include a region in which a portion of the second sub-insulating layer is removed to expose the first sub-insulating layer therethrough.

[0011] The second conductive layer can be on the first sub-insulating layer.

[0012] The recess can include a recessed region in which a partial thickness of the second sub-insulating layer is removed.

[0013] The third interlayer insulating layer can include an organic insulating layer. The recess can expose the first conductive layer therethrough.

[0014] At the recess, the second conductive layer can be in direct contact with the first conductive layer on the first conductive layer.

[0015] The second conductive layer includes a first wire extending in one direction, and a second wire crossing the first wire.

[0016] Each of the pixels can further include a storage capacitor. The storage capacitor can include a lower electrode in the same layer as the gate electrode, and an upper electrode disposed on the first interlayer insulating layer.

[0017] The first wire can extend in a direction parallel to one of the data lines and the scan lines.

[0018] The protective layer can have a planarized surface.

[0019] In the protective layer, a thickness of a region corresponding to the recess can be greater than a thickness of other regions.

[0020] The light emitting device can include a first electrode on the protective layer, a second electrode on the first electrode, and an emission layer between the first electrode and the second electrode.

[0021] The data lines can be in the same layer as the first conductive layer.

[0022] According to an embodiment of the disclosure, a display device includes a substrate including a pixel area and a peripheral area, a pixel located in the pixel area of the substrate, the pixel including at least one transistor and a light emitting device connected to the transistor, a data line and a scan line connected to the pixel, and a power line supplying power to the light emitting device. The transistor includes an active pattern located on the substrate, a source electrode and a drain electrode each connected to the active pattern, and a gate electrode located on the active pattern with a gate insulating layer interposed between the gate electrode and the active pattern. The display device further includes an interlayer insulating layer covering the gate electrode, the interlayer insulating layer including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer sequentially stacked, and a protection layer disposed on the interlayer insulating layer. The light emitting device includes a first electrode disposed on the protection layer, a second electrode disposed on the first electrode, and an emission layer located between the first electrode and the second electrode. The power line includes a first conductive layer parallel to the data line, the first conductive layer being located on the second interlayer insulating layer, and a second conductive layer located on the third interlayer insulating layer, the second conductive layer being connected to the first conductive layer. The third interlayer insulating layer includes a recess in an area in which the light emitting device and the second conductive layer are stacked on each other, the second conductive layer being located in the recess. An interface between the protection layer and the first electrode is a flat surface.

[0023] The protection layer can include an organic insulating layer.

[0024] In the protection layer, a thickness of an area corresponding to the recess can be greater than a thickness of other areas.

[0025] The third interlayer insulating layer can include a first sub-insulating layer including an inorganic insulating layer, and a second sub-insulating layer located on the first sub-insulating layer, the second sub-insulating layer including an organic insulating layer.

[0026] The recess can be an area in which a portion of the second sub-insulating layer is removed to expose the first sub-insulating layer therethrough. The second conductive layer can be located on the first sub-insulating layer.

[0027] The recess can include a recessed area in which a portion of a thickness of the second sub-insulating layer is removed.

[0028] The third interlayer insulating layer can include an organic insulating layer. The recess can expose the first conductive layer therethrough. At the recess, the second conductive layer can be in direct contact with the first conductive layer on the first conductive layer.

[0029] The second conductive layer can include a first wire extending in one direction, and a second wire crossing the first wire.

[0030] The first wire can extend in a direction parallel to the data line or can extend in a direction parallel to the scan line. BRIEF DESCRIPTION OF DRAWINGS

[0031] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments are not intended to be limiting and are to be provided as examples and explanatory instances only. Rather, they are presented as illustrative examples of the application so as to provide those of ordinary skill in the art with an enabling description and disclosure including best modes of practice.

[0032] In the drawings, the size of some of the elements can be exaggerated relative to others for clarity.

[0033] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0034] Figure 2 is a block diagram showing a pixel and a driver in a display device according to an embodiment of the present disclosure.

[0035] Figure 3 is a plan view showing Figure 2 an equivalent circuit diagram of the embodiment of the pixel shown in

[0036] Figure 4 is a plan view showing Figure 3 the pixel shown in

[0037] Figure 5 is a cross-sectional view taken along line I-I’ of Figure 4

[0038] Figure 6 is a cross-sectional view taken along line II-II’ of Figure 4

[0039] Figure 7 Figure 4

[0040] Figure 8 is a plan view showing Figures 2 to 7 the active pattern shown in

[0041] Figure 9 is a plan view showing Figures 2 to 7 the scan line, the light emission control line, and the lower electrode of the storage capacitor shown in

[0042] Figure 10 is a plan view showing Figures 2 to 7 the initialization power line and the upper electrode of the storage capacitor shown in

[0043] Figure 11 is a plan view showing Figures 2 to 7 the data line, the connection line, the auxiliary connection line, the first conductive layer of the power line, and the first bridge pattern shown in

[0044] Figure 12 ​​​​is a plan view showing the second conductive layer of the power line and the second bridge pattern illustrated in Figures 2 to 7

[0045] Figure 13 is a plan view showing the organic light emitting device illustrated in Figures 2 to 7

[0046] Figure 14 is a plan view showing the second conductive layer of the power line and the second bridge pattern illustrated in Figure 12 Figure 13

[0047] Figure 15 is a cross-sectional view taken along line IV-IV' of Figure 14

[0048] Figure 16 is a cross-sectional view taken along line V-V' of Figure 14

[0049] Figure 17 and Figure 18 are views showing a display device according to another embodiment of the disclosure.

[0050] Figure 19 and Figure 20 are views showing a display device according to still another embodiment of the disclosure. DETAILED DESCRIPTION

[0051] Because the present application contemplates various changes and numerous embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The features and methods of embodiments of the present application will become apparent by a detailed description of embodiments and appended drawings. Figure 1 The exemplary embodiments presented herein can have different forms and should not be construed as being limited to the description set forth herein.

[0052] It will be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, a first component, a first region, a first layer or a first section discussed below could be named a second element, a second component, a second region, a second layer or a second section without departing from the spirit and scope of the present application.

[0053] ​​​​​​The same reference numerals are used throughout the drawings to refer to same or like elements. In the drawings, the thickness of certain lines, layers, components, elements or features can be exaggerated for clarity. Throughout this document, the term "comprising" or variations such as "comprise" or "comprises" is not necessarily limited to the items recited. Instead, it is meant to cover a wide range of items including those explicitly recited.

[0054] Furthermore, it will be understood that when an element, component, region, layer or section is referred to as being "on" another element, component, region, layer, or section, it can be directly on the other element, component, region, layer, or section or intervening elements, components, regions, layers, or sections can also be present.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0056] For ease of description, spatially relative terms, such as "top", "bottom", "up", "down", "under", "below", "above", "on", "side", and the like, can be used herein for describing an element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections which have the same or similar characteristics or functions.

[0057] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of", "one or more of", and "one or more selected from the group consisting of" when preceding the list of elements, are intended to cover the elements themselves as an alternative, in addition to the combinations of one or more of the elements. Also, when describing embodiments of the invention, the term "may" is intended to mean one or more embodiments of the invention. Furthermore, the term "exemplary" is intended to mean an example or illustration.

[0058] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, or is "connected," "coupled" or "adjacent" to another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer or intervening elements or layers can be present. In addition, the use of terms such as "connected," "coupled," or the like, are not limited to direct or physical connections or couplings, but can include electrical connection, electrical coupling, or the like, as will be understood by those skilled in the art. When an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, or is "directly connected," "directly coupled" or "directly adjacent" to another element or layer, there are no intervening elements or layers present.

[0059] As used herein, "substantially," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0060] As used herein, the term "use" and variations thereof can be considered synonymous with the term "utilize" and variations thereof.

[0061] Features described with respect to one or more embodiments of the present application can be used in combination with features of other embodiments of the present application. For example, even though a third embodiment can not be specifically described herein, features described in a first embodiment can be combined with features described in a second embodiment to form a third embodiment.

[0062] Hereinafter, exemplary embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings.

[0063] Figure 1 FIG. 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0064] Referring to Figure 1 A display device according to an embodiment of the present disclosure can include a substrate SUB, a pixel PXL disposed on the substrate SUB, a driving unit (e.g., a driver) disposed on the substrate SUB, and a wire unit connecting the pixel PXL and the driving unit, the driving unit driving the pixel PXL.

[0065] The base SUB can include a pixel region PXA and a peripheral region PPA. The pixel region PXA can be a region in which pixels PXL displaying an image are provided. Each pixel PXL will be described later. The peripheral region PPA is a region in which the pixels PXL are not provided, and can be a region in which an image is not displayed. A driving unit for driving the pixels PXL and some of lines connecting the pixels PXL and the driving unit can be provided in the peripheral region PPA. The peripheral region PPA corresponds to a bezel in a final display device, and a width of the bezel can be determined according to a width of the peripheral region PPA.

[0066] The pixel region PXA can have various suitable shapes. For example, the pixel region PXA can be provided in various suitable shapes such as a polygon including a closed shape of straight sides, a circle including curved sides, an ellipse, etc., and a semi-circle, a semi-ellipse, etc., including straight sides and curved sides. When the pixel region PXA includes a plurality of regions, each region can also be provided in various suitable shapes such as a polygon including a closed shape of straight sides, a circle including curved sides, an ellipse, etc., and a semi-circle, a semi-ellipse, etc., including straight sides and curved sides. In addition, the areas of the plurality of regions can be the same as, substantially the same as, or different from each other.

[0067] In this embodiment, a case in which the pixel region PXA is provided as one region having a quadrangular shape including straight sides is described as an example.

[0068] The peripheral region PPA can be provided at one or more sides of the pixel region PXA. In an embodiment of the disclosure, the peripheral region PPA can surround the outer periphery of the pixel region PXA. In an embodiment of the disclosure, the peripheral region PPA can include a lateral portion extending in a width direction thereof and a longitudinal portion extending in a length direction thereof. The longitudinal portions of the peripheral region PPA can be provided as a pair spaced apart from each other along the width direction of the pixel region PXA.

[0069] The pixels PXL can be provided in the pixel region PXA on the base SUB. Each pixel PXL is a unit (e.g., a minimum unit) for displaying an image, and can be provided in a plurality. Each pixel PXL can include an organic light emitting device that emits white light and / or colored light. Each pixel PXL can emit light of one of red, green, and blue, but the disclosure is not limited thereto. For example, each pixel PXL can emit light of a color such as cyan, magenta, or yellow.

[0070] The pixels PXL can be arranged in a matrix form along rows extending in the first direction DR1 and columns extending in the second direction DR2. However, the arrangement form of the pixels PXL is not limited, and the pixels PXL can be arranged in various suitable forms. For example, some of the pixels PXL can be arranged such that the first direction DR1 becomes a row direction, but other pixels PXL can be arranged such that a direction different from the first direction DR1 (e.g., a direction inclined with respect to the first direction DR1) becomes a row direction. Alternatively, the pixels PXL can be arranged such that a direction inclined with respect to the first direction DR1 and the second direction DR2 becomes a column direction, and such that a direction intersecting (e.g., crossing) the column direction becomes a row direction. Here, the column direction can also be inclined with respect to the first direction DR1 and the second direction DR2.

[0071] The driving unit supplies a signal to each of the pixels PXL through the line unit, and thus, the driving of the pixels PXL can be controlled. Figure 2 In the drawing, the line unit is omitted for convenience of description. The line unit will be described later in more detail.

[0072] The driving unit can include a scan driver SDV supplying a scan signal to the pixels PXL through a scan line, an emission driver EDV supplying an emission control signal to the pixels PXL through an emission control line, a data driver DDV supplying a data signal to the pixels PXL through a data line, and a timing controller. The timing controller can control the scan driver SDV, the emission driver EDV, and the data driver DDV.

[0073] The scan driver SDV can be disposed at the longitudinal portions in the peripheral area PPA. Since the longitudinal portions of the peripheral area PPA are disposed as a pair spaced apart from each other along the width direction of the pixel area PXA, the scan driver SDV can be disposed at one or more of the longitudinal portions in the peripheral area PPA. The scan driver SDV can extend along the length direction of the peripheral area PPA.

[0074] In an embodiment of the disclosure, the scan driver SDV can be directly mounted on the substrate SUB. When the scan driver SDV is directly mounted on the substrate SUB, the scan driver SDV can be formed together with the pixels PXL in a process of forming the pixels PXL. However, the mounting position and the forming method of the scan driver SDV are not limited thereto. For example, the scan driver SDV can be formed on a separate chip to be disposed on the substrate SUB in a form of a chip on glass. Alternatively, the scan driver SDV can be mounted on a printed circuit board to be connected to the substrate SUB through a connector.

[0075] Like the scan driver SDV, the emission driver EDV can be provided at a longitudinal portion in the peripheral area PPA. The emission driver EDV can be provided at one or more of the longitudinal portions in the peripheral area PPA. The emission driver EDV can extend in the length direction of the peripheral area PPA.

[0076] In an embodiment of the present disclosure, the emission driver EDV can be mounted directly on the substrate SUB. When the emission driver EDV is mounted directly on the substrate SUB, the emission driver EDV can be formed together with the pixels PXL in a process of forming the pixels PXL. However, the mounting position and forming method of the emission driver EDV are not limited thereto. For example, the emission driver EDV can be formed on a separate chip which is to be provided on the substrate SUB in a form of a chip on glass. Alternatively, the emission driver EDV can be mounted on a printed circuit board which is to be connected to the substrate SUB through a connector.

[0077] In an embodiment of the present disclosure, a case where the scan driver SDV and the emission driver EDV are provided adjacent to each other and at any one of the pair of longitudinal portions of the peripheral area PPA is shown as an example. However, the present disclosure is not limited thereto, and the arrangement of the scan driver SDV and the emission driver EDV can be modified in various suitable ways. For example, the scan driver SDV can be provided at one of the longitudinal portions of the peripheral area PPA, and the emission driver EDV can be provided at the other of the longitudinal portions of the peripheral area PPA. Alternatively, the scan driver SDV can be provided at both of the longitudinal portions of the peripheral area PPA, and the emission driver EDV can be provided at only one of the longitudinal portions of the peripheral area PPA.

[0078] The data driver DDV can be provided in the peripheral area PPA. In particular, the data driver DDV can be provided at a lateral portion of the peripheral area PPA. The data driver DDV can extend in the width direction of the peripheral area PPA.

[0079] In an embodiment of the present disclosure, the positions of the scan driver SDV, the emission driver EDV, and / or the data driver DDV can be changed.

[0080] The timing controller can be connected to the scan driver SDV, the emission driver EDV, and the data driver DDV in various suitable ways through lines. The position at which the timing controller is provided is not limited herein. For example, the timing controller can be mounted on a flexible printed circuit board to be connected to the scan driver SDV, the emission driver EDV, and the data driver DDV through the printed circuit board. The printed circuit board can be provided at various suitable positions, for example, at a side of the substrate SUB and on a back surface of the substrate SUB, and the like.

[0081] Figure 2 is a block diagram illustrating a pixel and a driving unit in a display apparatus according to an embodiment of the present disclosure.

[0082] Referring to Figure 2 , a display apparatus according to an embodiment of the present disclosure can include a pixel PXL, a driving unit, and a line unit.

[0083] The pixel PXL can be provided as a plurality of pixels. The driving unit can include a scan driver SDV, an emission driver EDV, a data driver DDV, and a timing controller TC. In Figure 3 , the positions of the scan driver SDV, the emission driver EDV, the data driver DDV, and the timing controller TC are set for convenience of description. When an actual display apparatus is implemented, the scan driver SDV, the emission driver EDV, the data driver DDV, and the timing controller TC can be provided at other suitable positions in the display apparatus.

[0084] The line unit provides signals from the driving unit to each of the pixels PXL, and can include scan lines, data lines, emission control lines, a power line PL, and an initialization power line. The scan lines can include a plurality of scan lines S1 to Sn, and the emission control lines can include a plurality of emission control lines E1 to En. The data lines can include a plurality of data lines D1 to Dm. The data lines D1 to Dm and the power line PL can be connected to the pixels PXL.

[0085] The pixel PXL can be arranged in a pixel area PXA. The pixel PXL can be connected to the scan lines S1 to Sn, the emission control lines E1 to En, the data lines D1 to Dm, and the power line PL. When a scan signal is supplied from the scan lines S1 to Sn, the pixel PXL can be supplied with a data signal from the data lines D1 to Dm.

[0086] In addition, the pixel PXL can be supplied with a first power source ELVDD, a second power source ELVSS, and an initialization power source Vint from the outside. Here, the first power source ELVDD can be applied through the power line PL.

[0087] Each of the pixels PXL can include a driving transistor and an organic light emitting diode. The driving transistor can control an amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode corresponding to a data signal. Here, before the data signal is supplied, a gate electrode of the driving transistor can be initialized by a voltage of the initialization power source Vint. To this end, the initialization power source Vint can be set to a voltage lower than a voltage of the data signal.

[0088] The scan driver SDV can supply a scan signal to the scan lines S1 to Sn in response to a first gate control signal GCS1 from the timing controller TC. For example, the scan driver SDV can sequentially supply a scan signal to the scan lines S1 to Sn. When the scan signal is sequentially supplied to the scan lines S1 to Sn, the pixels PXL can be sequentially selected in units of horizontal lines.

[0089] The emission driver EDV can supply an emission control signal to the emission control lines E1 to En in response to a second gate control signal GCS2 from the timing controller TC. For example, the emission driver EDV can sequentially supply an emission control signal to the emission control lines E1 to En.

[0090] Here, the emission control signal can be set to have a width wider than that of the scan signal. For example, the emission control signal supplied to the i-th (i is a natural number) emission control line Ei can be supplied to overlap with the scan signal supplied to the (i-1)-th scan line Si-1 and the scan signal supplied to the i-th scan line Si for at least one period.

[0091] In addition, the emission control signal can be set to a gate cutoff voltage (for example, a high voltage) so that the transistor included in the pixel PXL can be cut off, and the scan signal can be set to a gate on voltage (for example, a low voltage) so that the transistor included in the pixel PXL can be turned on.

[0092] The data driver DDV can supply a data signal to the data lines D1 to Dm in response to a data control signal DCS. The data signal supplied to the data lines D1 to Dm can be supplied to the pixel PXL selected by the scan signal.

[0093] The timing controller TC can supply the gate control signals GCS1 and GCS2 generated based on a timing signal supplied from the outside to the scan driver SDV and the emission driver EDV. In addition, the timing controller TC can supply the data control signal DCS to the data driver DDV.

[0094] A start pulse and a clock signal can be included in each of the gate control signals GCS1 and GCS2. The start pulse can control the timing of the first scan signal or the first emission control signal. The clock signal can be used to shift the start pulse.

[0095] A source start pulse and a clock signal can be included in the data control signal DCS. The source start pulse can control the sampling start time of the data. The clock signal can be used to control the sampling operation.

[0096] Figure 2 is shown to illustrate Figure 3An equivalent circuit diagram of an embodiment of the pixel shown in FIG. 1A will be described with reference to FIG. 1B. For convenience of description, it will be described that the pixel PXL is connected to the jth data line Dj and the ith scan line Si. Figure 2 An embodiment of the pixel PXL according to the present disclosure will be described with reference to FIGS. 2A and 2B.

[0097] Referring to Figure 3 and Figure 4 , the pixel PXL according to an embodiment of the present disclosure can include an organic light emitting device OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0098] The anode of the organic light emitting device OLED can be connected to the first transistor T1 via the sixth transistor T6, and the cathode of the organic light emitting device OLED can be connected to the second power supply ELVSS. The organic light emitting device OLED can generate light having a luminance (e.g., a predetermined luminance) corresponding to an amount of current supplied from the first transistor T1.

[0099] The first power supply ELVDD can be set to a voltage higher than that of the second power supply ELVSS, so that a current can flow into the organic light emitting device OLED.

[0100] The seventh transistor T7 can be connected between the initialization power supply Vint and the anode of the organic light emitting device OLED. In addition, the gate electrode of the seventh transistor T7 can be connected to the ith scan line Si. When a scan signal is supplied (e.g., supplied at a low level) to the ith scan line Si, the seventh transistor T7 can be turned on to supply a voltage of the initialization power supply Vint to the anode of the organic light emitting device OLED. Here, the initialization power supply Vint can be set to a voltage lower than that of the data signal.

[0101] The sixth transistor T6 can be connected between the first transistor T1 and the organic light emitting device OLED. In addition, the gate electrode of the sixth transistor T6 can be connected to the ith emission control line Ei. When an emission control signal is supplied (e.g., supplied at a high level) to the ith emission control line Ei, the sixth transistor T6 can be turned off, and otherwise the sixth transistor T6 can be turned on.

[0102] The fifth transistor T5 can be connected between the first power supply ELVDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 can be connected to the ith emission control line Ei. When an emission control signal is supplied (e.g., supplied at a high level) to the ith emission control line Ei, the fifth transistor T5 can be turned off, and otherwise the fifth transistor T5 can be turned on.

[0103] The first electrode of the first transistor (a driving transistor) T1 can be connected to the first power supply ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the anode of the organic light emitting device OLED via the sixth transistor T6. In addition, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the organic light emitting device OLED, corresponding to the voltage of the first node N1. That is, the first power supply ELVDD can be electrically connected to the anode of the organic light emitting device OLED through the first transistor T1.

[0104] The third transistor T3 can be connected between the second electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal is supplied (for example, supplied at a low level) to the i-th scan line Si, the third transistor T3 can be turned on to allow the second electrode of the first transistor T1 to be electrically connected to the first node N1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 can be diode-connected.

[0105] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. In addition, the gate electrode of the fourth transistor T4 can be connected to the (i-1)-th scan line Si-1. When a scan signal is supplied (for example, supplied at a low level) to the (i-1)-th scan line Si-1, the fourth transistor T4 can be turned on to supply the voltage of the initialization power supply Vint to the first node N1.

[0106] The second transistor T2 can be connected between the j-th data line Dj and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si. When a scan signal is supplied (for example, supplied at a low level) to the i-th scan line Si, the second transistor T2 can be turned on to allow the j-th data line Dj to be electrically connected to the first electrode of the first transistor T1.

[0107] The storage capacitor Cst can be connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store a data signal and a voltage corresponding to a threshold voltage of the first transistor T1.

[0108] In another embodiment of the disclosure, the extension direction of the scan lines and the light emission control lines can be set differently. For example, although the scan lines and the light emission control lines extend in the first direction DR1 as the width direction thereof in the embodiment of the disclosure, the scan lines and the light emission control lines can extend in the second direction DR2 as the length direction thereof.

[0109] Figure 3 is illustrated in detail Figure 5The image shows a planar view of the pixels. Figure 4 It is along Figure 6 A sectional view taken from line I-I'. Figure 4 It is along Figure 7 The sectional view taken from line II-II'. Figure 4 It is along Figures 4 to 7 The sectional view taken from line III-III'.

[0110] Based on a pixel PXL located in the i-th row and j-th column of pixel region PXA Figures 4 to 7 The diagram shows two scan lines Si-1 and Si, a light emission control line Ei, a power line PL, and a data line Dj connected to the pixel PXL. Figures 4 to 7 In this text, for ease of description, the scan line in row (i-1) is called "scan line (i-1) Si-1", the scan line in row i is called "scan line i Si", the light emission control line in row i is called "light emission control line Ei", the data line in column j is called "data line Dj", and the power line in column j is called "power line PL".

[0111] refer to Figure 2 The display device may include a substrate SUB, line units, and pixels PXL.

[0112] The substrate SUB may include a transparent insulating material to allow light to pass through it. The substrate SUB may be a rigid substrate. For example, the substrate SUB may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0113] Additionally, the substrate SUB can be a flexible substrate. Here, the substrate SUB can be one of a membrane substrate comprising a polymeric organic material and a plastic substrate. For example, the substrate SUB can include at least one selected from the group consisting of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the materials constituting the substrate SUB can vary and can include fiber-reinforced plastics (FRP), etc.

[0114] The line unit provides signals to each pixel PXL and may include scan lines Si-1 and Si, data line Dj, light emission control line Ei, power line PL, and initialization power line IPL.

[0115] The scan lines Si-1 and Si can extend in the first direction DR1. The scan lines Si-1 and Si can include an (i-1)th scan line Si-1 and an ith scan line Si arranged sequentially along a second direction DR2. The scan lines Si-1 and Si can receive scan signals. For example, the (i-1)th scan line Si-1 can receive an (i-1)th scan signal. The pixels PXL on the ith row can be initialized by the (i-1)th scan signal applied to the (i-1)th scan line Si-1. The ith scan line Si can receive an ith scan signal. The ith scan line Si can branch to be connected to different transistors.

[0116] The emission control lines Ei can extend in the first direction DR1. The emission control lines Ei can be disposed to be separated from the branched ith scan line Si between the ith scan lines Si. The emission control lines Ei can receive emission control signals.

[0117] The data lines Dj can extend in the second direction DR2. The data lines Dj can receive data signals.

[0118] The power lines PL can extend in the second direction DR2. The power lines PL can be disposed to be separated from the data lines Dj. The power lines PL can receive a first power source (see Figure 3 and Figure 2 ELVDD).

[0119] The initialization power line IPL can extend in the first direction DR1. The initialization power line IPL can be disposed between the pixels PXL located in the ith pixel row and the pixels PXL located in the (i+1)th pixel row. The initialization power line IPL can receive an initialization power source Vint.

[0120] Each of the pixels PXL can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and an organic light emitting device OLED.

[0121] The first gate electrode GE1 can be connected to a third drain electrode DE3 of the third transistor T3 and a fourth drain electrode DE4 of the fourth transistor T4. A connection line CNL can be connected between the first gate electrode GE1 and the third drain electrode DE3 and the fourth drain electrode DE4. One end of the connection line CNL can be connected to the first gate electrode GE1 through a first contact hole CH1, and the other end of the connection line CNL can be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2.

[0122] In an embodiment of the disclosure, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 can be formed of a semiconductor layer that is not doped with impurities or a semiconductor layer that is doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 can be formed of a semiconductor layer that is doped with impurities, and the first active pattern ACT1 can be formed of a semiconductor layer that is not doped with impurities.

[0123] The first active pattern ACT1 has a bar shape extending in one direction (e.g., a predetermined direction), and can have a shape that is curved multiple times along the extending direction. When viewed on a plane, the first active pattern ACT1 can be superposed with the first gate electrode GE1. Because the first active pattern ACT1 is formed long, a channel region of the first transistor T1 can be formed long. Accordingly, a driving range of a gate voltage applied to the first transistor T1 can be widened. Accordingly, a gray scale of light emitted from the organic light emitting device OLED can be controlled (e.g., finely controlled).

[0124] The first source electrode SE1 can be connected to one end of the first active pattern ACT1. The first source electrode SE1 can be connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 can be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 can be connected to the third source electrode SE3 of the third transistor T3 and the sixth source electrode SE6 of the sixth transistor T6.

[0125] The second transistor T2 can include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0126] The second gate electrode GE2 can be connected to the i-th scan line Si. The second gate electrode GE2 can be provided as a part of the i-th scan line Si or can be provided in a shape protruding from the i-th scan line Si. In an embodiment of the disclosure, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 can be formed of a semiconductor that is not doped with impurities or a semiconductor that is doped with impurities. For example, the second source electrode SE2 and the second drain electrode DE2 can be formed of a semiconductor that is doped with impurities, and the second active pattern ACT2 can be formed of a semiconductor layer that is not doped with impurities. The second active pattern ACT2 corresponds to a portion superposed with the second gate electrode GE2. One end of the second source electrode SE2 can be connected to the second active pattern ACT2. The other end of the second source electrode SE2 can be connected to the data line Dj through the sixth contact hole CH6. One end of the second drain electrode DE2 can be connected to the second active pattern ACT2. The other end of the second drain electrode DE2 can be connected to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0127] The third transistor T3 can be provided in a dual gate structure in order to prevent or reduce a leakage current. That is, the third transistor T3 can include a 3a-th transistor T3a and a 3b-th transistor T3b. The 3a-th transistor T3a can include a 3a-th gate electrode GE3a, a 3a-th active pattern ACT3a, a 3a-th source electrode SE3a, and a 3a-th drain electrode DE3a. The 3b-th transistor T3b can include a 3b-th gate electrode GE3b, a 3b-th active pattern ACT3b, a 3b-th source electrode SE3b, and a 3b-th drain electrode DE3b. Hereinafter, the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b are collectively referred to as a third gate electrode GE3, the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b are collectively referred to as a third active pattern ACT3, the 3a-th source electrode SE3a and the 3b-th source electrode SE3b are collectively referred to as a third source electrode SE3, and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b are collectively referred to as a third drain electrode DE3.

[0128] The third gate electrode GE3 can be connected to the i-th scan line Si. The third gate electrode GE3 can be provided as a portion of the i-th scan line Si, or can be provided in a shape protruding from the i-th scan line Si. For example, the 3a-th gate electrode GE3a can be provided in a shape protruding from the i-th scan line Si, and the 3b-th gate electrode GE3b can be provided as a portion of the i-th scan line Si.

[0129] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 can be formed of a semiconductor layer not doped with impurities or a semiconductor layer doped with impurities. For example, the third source electrode SE3 and the third drain electrode DE3 can be formed of a semiconductor layer doped with impurities, and the third active pattern ACT3 can be formed of a semiconductor layer not doped with impurities. The third active pattern ACT3 corresponds to a portion overlapping the third gate electrode GE3. One end of the third source electrode SE3 can be connected to the third active pattern ACT3. The other end of the third source electrode SE3 can be connected to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 can be connected to the third active pattern ACT3. The other end of the third drain electrode DE3 can be connected to the fourth drain electrode DE4 of the fourth transistor T4. In addition, the third drain electrode DE3 can be connected to the first gate electrode GE1 of the first transistor T1 through the connection line CNL, the second contact hole CH2, and the first contact hole CH1.

[0130] The fourth transistor T4 can be provided as a dual gate structure in order to prevent or reduce a leakage current. That is, the fourth transistor T4 can include a 4a-th transistor T4a and a 4b-th transistor T4b. The 4a-th transistor T4a can include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a, and the 4b-th transistor T4b can include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. Hereinafter, the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b are collectively referred to as a fourth gate electrode GE4, the 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b are collectively referred to as a fourth active pattern ACT4, the 4a-th source electrode SE4a and the 4b-th source electrode SE4b are collectively referred to as a fourth source electrode SE4, and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b are collectively referred to as a fourth drain electrode DE4.

[0131] The fourth gate electrode GE4 can be connected to the (i-1)-th scan line Si-1. The fourth gate electrode GE4 can be provided as a part of the (i-1)-th scan line Si-1, or can be provided in a shape protruding from the (i-1)-th scan line Si-1. For example, the 4a-th gate electrode GE4a can be provided as a part of the (i-1)-th scan line Si-1. The 4b-th gate electrode GE4b can be provided in a shape protruding from the (i-1)-th scan line Si-1.

[0132] The fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed of a semiconductor layer not doped with impurities or a semiconductor layer doped with impurities. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 can be formed of a semiconductor layer doped with impurities, and the fourth active pattern ACT4 can be formed of a semiconductor layer not doped with impurities. The fourth active pattern ACT4 corresponds to a portion overlapping the fourth gate electrode GE4.

[0133] One end of the fourth source electrode SE4 can be connected to the fourth active pattern ACT4. The other end of the fourth source electrode SE4 can be connected to the initialization power line IPL of the pixel PXL located on the (i-1)th row and the seventh drain electrode DE7 of the seventh transistor T7 of the pixel PXL located on the (i-1)th row. An auxiliary connection line AUX can be disposed between the fourth source electrode SE4 and the initialization power line IPL. One end of the auxiliary connection line AUX can be connected to the fourth source electrode SE4 through the ninth contact hole CH9. The other end of the auxiliary connection line AUX can be connected to the initialization power line IPL located on the (i-1)th row through the eighth contact hole CH8 of the pixel PXL located on the (i-1)th row. One end of the fourth drain electrode DE4 can be connected to the fourth active pattern ACT4. The other end of the fourth drain electrode DE4 can be connected to the third drain electrode DE3 of the third transistor T3. Also, the fourth drain electrode DE4 can be connected to the first gate electrode GE1 of the first transistor T1 through the second contact hole CH2 and the first contact hole CH1.

[0134] The fifth transistor T5 can include a fifth gate electrode GE5, a fifth active pattern ACT5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0135] The fifth gate electrode GE5 can be connected to the emission control line Ei. The fifth gate electrode GE5 can be disposed as a part of the emission control line Ei, or can be disposed in a shape protruding from the emission control line Ei. The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed of a semiconductor layer doped with no impurity or a semiconductor layer doped with an impurity. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed of a semiconductor layer doped with an impurity, and the fifth active pattern ACT5 can be formed of a semiconductor layer doped with no impurity. The fifth active pattern ACT5 corresponds to a portion overlapping the fifth gate electrode GE5. One end of the fifth source electrode SE5 can be connected to the fifth active pattern ACT5. The other end of the fifth source electrode SE5 can be connected to the power line PL through the fifth contact hole CH5. One end of the fifth drain electrode DE5 can be connected to the fifth active pattern ACT5. The other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0136] The sixth transistor T6 can include a sixth gate electrode GE6, a sixth active pattern ACT6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0137] The sixth gate electrode GE6 can be connected to the light emission control line Ei. The sixth gate electrode GE6 can be provided as part of the light emission control line Ei, or can be provided in a shape protruding from the light emission control line Ei. The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 can be formed of a semiconductor layer not doped with impurities or a semiconductor layer doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 can be formed of a semiconductor layer doped with impurities, and the sixth active pattern ACT6 can be formed of a semiconductor layer not doped with impurities. The sixth active pattern ACT6 corresponds to a portion overlapping the sixth gate electrode GE6. One end of the sixth source electrode SE6 can be connected to the sixth active pattern ACT6. The other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 can be connected to the sixth active pattern ACT6. The other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor T7.

[0138] The seventh transistor T7 can include a seventh gate electrode GE7, a seventh active pattern ACT7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0139] The seventh gate electrode GE7 can be connected to the i-th scan line Si. The seventh gate electrode GE7 can be provided as part of the i-th scan line Si, or can be provided in a shape protruding from the i-th scan line Si. The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 can be formed of a semiconductor layer not doped with impurities or a semiconductor layer doped with impurities. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 can be formed of a semiconductor layer doped with impurities, and the seventh active pattern ACT7 can be formed of a semiconductor layer not doped with impurities. The seventh active pattern ACT7 corresponds to a portion overlapping the seventh gate electrode GE7. One end of the seventh source electrode SE7 can be connected to the seventh active pattern ACT7. The other end of the seventh source electrode SE7 can be connected to the sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 can be connected to the seventh active pattern ACT7. The other end of the seventh drain electrode DE7 can be connected to the initialization power line IPL. Further, the seventh drain electrode DE7 can be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL located on the (i+1)-th row. The seventh drain electrode DE7 can be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL located on the (i+1)-th row through the auxiliary connection line AUX, the eighth contact hole CH8, and the ninth contact hole CH9.

[0140] The storage capacitor Cst can include a lower electrode LE and an upper electrode UE. The lower electrode LE can be formed as the first gate electrode GE1 of the first transistor T1.

[0141] The upper electrode UE is overlaid with the first gate electrode GE1 and can cover the lower electrode LE when viewed in plan. As the overlaid area of the upper electrode UE and the lower electrode LE becomes wider, the capacitance of the storage capacitor Cst can increase. The upper electrode UE can extend in the first direction DR1. In an embodiment of the disclosure, a voltage having the same or substantially the same level as the first power supply ELVDD can be applied to the upper electrode UE. The upper electrode UE can have an opening OPN in an area including the first contact hole CH1, in which the first gate electrode GE1 and the connection line CNL contact each other through the first contact hole CH1.

[0142] The organic light emitting device OLED can include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0143] The first electrode AD can be disposed in a light emitting area corresponding to each of the pixels PXL. The first electrode AD can be connected to a seventh source electrode SE7 of the seventh transistor T7 and a sixth drain electrode DE6 of the sixth transistor T6 through a seventh contact hole CH7, a tenth contact hole CH10, and a twelfth contact hole CH12. A first bridge pattern BRP1 can be disposed between the seventh contact hole CH7 and the tenth contact hole CH10. A second bridge pattern BRP2 can be disposed between the tenth contact hole CH10 and the twelfth contact hole CH12.

[0144] The first electrode AD can be electrically connected to a power line PL to be supplied with a first power supply (see ELVDD of Figure 3 and Figure 2 The second electrode CD can be connected to a second power supply (see ELVSS of Figure 3 and Figures 4 to 7 ).

[0145] The first bridge pattern BRP1 and the second bridge pattern BRP2 can connect the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD.

[0146] Hereinafter, a structure of a display device according to an embodiment of the disclosure will be described with reference to Figures 4 to 7 in a stacking order.

[0147] Active patterns ACT1 to ACT7 (hereinafter, collectively referred to as ACT) can be disposed on the substrate SUB. The active patterns ACT can include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 can include a semiconductor material.

[0148] A buffer layer can be disposed between the substrate SUB and the first to seventh active patterns ACT1 to ACT7.

[0149] A gate insulating layer GI can be disposed on the substrate SUB on which the active pattern ACT is formed. The gate insulating layer GI can include at least one of an organic insulating layer and an inorganic insulating layer. For example, the gate insulating layer GI can include an inorganic insulating layer, and the inorganic insulating layer can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON).

[0150] The (i-1)th scan line Si-1, the i-th scan line Si, the emission control line Ei, and the first to seventh gate electrodes GE1 to GE7 can be disposed on the gate insulating layer GI. The first gate electrode GE1 can be a lower electrode LE of the storage capacitor Cst. The second and third gate electrodes GE2 and GE3 can be integrally formed with the i-th scan line Si. The fourth gate electrode GE4 can be integrally formed with the (i-1)th scan line Si-1. The fifth and sixth gate electrodes GE5 and GE6 can be integrally formed with the emission control line Ei. The seventh gate electrode GE7 can be integrally formed with the i-th scan line Si.

[0151] A first interlayer insulating layer IL1 can be disposed on the substrate SUB on which the (i-1)th scan line Si-1, etc. are formed. The first interlayer insulating layer IL1 can include at least one of an organic insulating layer and an inorganic insulating layer. For example, the first interlayer insulating layer IL1 can include the same or substantially the same material as the gate insulating layer GI.

[0152] An upper electrode UE of the storage capacitor Cst and an initialization power line IPL can be disposed on the first interlayer insulating layer IL1. The upper electrode UE can cover the lower electrode LE. The upper electrode UE together with the lower electrode LE can constitute the storage capacitor Cst, and the first interlayer insulating layer IL1 is interposed between the upper electrode UE and the lower electrode LE.

[0153] A second interlayer insulating layer IL2 can be disposed on the substrate SUB on which the upper electrode UE and the initialization power line IPL are disposed. The second interlayer insulating layer IL2 can include at least one of an organic insulating layer and an inorganic insulating layer.

[0154] The data line Dj, the connection line CNL, the auxiliary connection line AUX, the first conductive layer PL1 of the first bridge pattern BRP1, and the power line PL can be disposed on the second interlayer insulating layer IL2.

[0155] The data line Dj can be connected to the second source electrode SE2 through a sixth contact hole CH6 that passes through the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the gate insulating layer GI.

[0156] The connection line CNL can be connected to the first gate electrode GE1 through a first contact hole CH1 passing through the first interlayer insulation layer IL1 and the second interlayer insulation layer IL2. Further, the connection line CNL can be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2 passing through the gate insulation layer GI, the first interlayer insulation layer IL1, and the second interlayer insulation layer IL2.

[0157] The auxiliary connection line AUX can be connected to the initialization power line IPL through an eighth contact hole CH8 passing through the second interlayer insulation layer IL2. Further, the auxiliary connection line AUX can be connected to the fourth source electrode SE4 and the seventh drain electrode DE7 of the pixel PXL located on the (i-1)th row through a ninth contact hole CH9 passing through the gate insulation layer GI, the first interlayer insulation layer IL1, and the second interlayer insulation layer IL2.

[0158] The first bridge pattern BRP1 can be a pattern provided as a medium for connecting the sixth drain electrode DE6 to the first electrode AD between the sixth drain electrode DE6 and the first electrode AD. The first bridge pattern BRP1 can be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 passing through the gate insulation layer GI, the first interlayer insulation layer IL1, and the second interlayer insulation layer IL2.

[0159] The first conductive layer PL1 can be connected to the upper electrode UE of the storage capacitor Cst through a third contact hole CH3 and a fourth contact hole CH4 passing through the second interlayer insulation layer IL2. The first conductive layer PL1 can be connected to the fifth source electrode SE5 through a fifth contact hole CH5 passing through the gate insulation layer GI, the first interlayer insulation layer IL1, and the second interlayer insulation layer IL2.

[0160] The third interlayer insulation layer IL3 can be disposed on the substrate SUB on which the data line Dj or the like is formed. The third interlayer insulation layer IL3 can include at least one of an organic insulation layer and an inorganic insulation layer. For example, the third interlayer insulation layer IL3 can include a first sub-insulation layer IL31 including an inorganic insulation material and a second sub-insulation layer IL32 disposed on the first sub-insulation layer IL31, the second sub-insulation layer IL32 including an organic insulation material.

[0161] The first sub-insulation layer IL31 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide (AlO x ), and hafnium oxide (HfO x ).

[0162] The second sub-insulation layer IL32 can include at least one of a polyacrylate resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0163] The second conductive layer PL2 of the power line PL and the second bridge pattern BRP2 can be disposed on the third interlayer insulation layer IL3. The second bridge pattern BRP2 can be connected to the first bridge pattern BRP1 through the tenth contact hole CH10.

[0164] The second conductive layer PL2 is superposed on the first conductive layer PL1 and can be connected to the first conductive layer PL1 through the eleventh contact hole CH11 passing through the third interlayer insulation layer IL3. Accordingly, since the power line PL includes the first conductive layer PL1 and the second conductive layer PL2, and the first conductive layer PL1 and the second conductive layer PL2 are electrically connected to each other, it is possible to prevent or reduce a voltage drop of power (e.g., the first power supply ELVDD) supplied through the power line PL.

[0165] The protection layer PSV can be disposed on the third interlayer insulation layer IL3 on which the second conductive layer PL2 and the second bridge pattern BRP2 are disposed. The protection layer PSV can include at least one of an organic insulation layer and an inorganic insulation layer. For example, the protection layer PSV can include an organic insulation layer.

[0166] The organic light emitting device OLED can be disposed on the protection layer PSV. The organic light emitting device OLED can include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0167] The first electrode AD can be disposed on the protection layer PSV. The first electrode AD can be connected to the second bridge pattern BRP2 through the twelfth contact hole CH12 passing through the protection layer PSV. Accordingly, the first electrode AD can be electrically connected to the first bridge pattern BRP1. Since the first bridge pattern BRP1 is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7, the first electrode AD can be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0168] A pixel defining layer PDL defining a light emitting area corresponding to each of the pixels PXL can be disposed on the substrate SUB on which the first electrode AD, etc. are formed. The pixel defining layer PDL can expose a top surface of the first electrode AD therethrough and protrude from the substrate SUB along an outer periphery of the pixel PXL.

[0169] The emission layer EML can be disposed in the light emitting area surrounded by the pixel defining layer PDL, and the second electrode CD can be disposed on the emission layer EML. An encapsulation layer SLM covering the second electrode CD can be disposed on the second electrode CD.

[0170] One of the first electrode AD and the second electrode CD can be an anode electrode, and the other of the first electrode AD and the second electrode CD can be a cathode electrode. For example, the first electrode AD can be an anode electrode, and the second electrode CD can be a cathode electrode.

[0171] In addition, at least one of the first electrode AD and the second electrode CD can be a transmissive electrode. For example, when the organic light emitting device OLED is a bottom emission organic light emitting device, the first electrode AD can be a transmissive electrode, and the second electrode CD is a reflective electrode. When the organic light emitting device OLED is a top emission organic light emitting device, the first electrode AD can be a reflective electrode, and the second electrode CD can be a transmissive electrode. When the organic light emitting device OLED is a dual emission organic light emitting device, both of the first electrode AD and the second electrode CD can be transmissive electrodes. Figure 8 In an embodiment, a case in which the organic light emitting device OLED is a top emission organic light emitting device and the first electrode AD is an anode electrode is described as an example.

[0172] The first electrode AD can include a reflective layer capable of reflecting light and a transparent conductive layer disposed above or below the reflective layer. At least one of the transparent conductive layer and the reflective layer can be connected to the seventh source electrode SE7.

[0173] The reflective layer can include a material capable of reflecting light. For example, the reflective layer can include at least one selected from the group consisting of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and an alloy thereof.

[0174] The transparent conductive layer can include a transparent conductive oxide. For example, the transparent conductive layer can include at least one transparent conductive oxide selected from indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0175] The pixel definition layer PDL can include an organic insulating material. For example, the pixel definition layer PDL can include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylether (PAE), a heterocyclic polymer, parylene, an epoxy resin, benzocyclobutene (BCB), a siloxane-based resin, and a silane-based resin.

[0176] The emission layer EML can be disposed on the exposed surface of the first electrode AD. The emission layer EML can have a multi-layer thin film structure including at least a light generating layer (LGL). For example, the emission layer EML can include a hole injection layer (HIL) for injecting holes, a hole transport layer (HTL) having excellent hole transport properties (the HTL serves to increase the chance of hole and electron recombination by suppressing the movement of electrons not bound in the LGL, the LGL serves to emit light by the recombination of injected electrons and injected holes), a hole blocking layer (HBL) for suppressing the movement of holes not bound in the LGL, an electron transport layer (ETL) for smoothly transporting electrons to the LGL, and an electron injection layer (EIL) for injecting electrons. In the emission layer EML, the HIL, the HTL, the HBL, the ETL, and the EIL can be common layers disposed in the pixels PXL adjacent to each other.

[0177] The color of light generated in the LGL can be one of red, green, blue, and white, but the present embodiment is not limited thereto. For example, the color of light generated in the LGL can also be one of magenta, cyan, and yellow.

[0178] The second electrode CD can be a semi-transmissive reflective layer. For example, the second electrode CD can be a thin metal layer having a thickness through which light emitted through the emission layer EML can be transmitted. The second electrode CD can transmit a portion of light emitted from the emission layer EML therethrough, and can reflect the remaining portion of light emitted from the emission layer EML.

[0179] The second electrode CD can include a material having a low work function compared to a transparent conductive layer. For example, the second electrode CD can include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0180] A portion of light emitted from the emission layer EML can not be transmitted through the second electrode CD, and light reflected from the second electrode CD can be reflected again from the reflective layer. That is, light emitted from the emission layer EML can resonate between the reflective layer and the second electrode CD. The light extraction efficiency of the organic light emitting device OLED can be improved by the resonance of light.

[0181] The distance between the reflective layer and the second electrode CD can vary according to the color of light emitted from the emission layer EML. That is, the distance between the reflective layer and the second electrode CD can be adjusted to correspond to a resonance distance according to the color of light emitted from the emission layer EML.

[0182] In an embodiment of the disclosure, the third interlayer insulating layer IL3 can include a recess CCP disposed in a region in which the second conductive layer PL2 and the first electrode AD are stacked on each other, and the second conductive layer PL2 can be disposed in the recess CCP. The recess CCP can be a region in which a portion of the third interlayer insulating layer IL3 is removed. For example, the recess CCP can be an opening through which the second sub-insulating layer IL32 exposes the first sub-insulating layer IL31 in a region in which the second conductive layer PL2 and the first electrode AD are stacked on each other.

[0183] In an embodiment of the disclosure, the second conductive layer PL2 can be disposed on the first sub-insulating layer IL31. Accordingly, a distance between the second conductive layer PL2 and the first electrode AD can increase in a region in which the second conductive layer PL2 and the first electrode AD are stacked on each other. When the distance between the second conductive layer PL2 and the first electrode AD increases, a thickness of the protective layer PSV can increase. That is, a thickness of a region of the protective layer PSV corresponding to the recess CCP can be greater than a thickness of other regions.

[0184] The protective layer PSV can include an organic insulating layer. As a thickness of the organic insulating layer increases, the organic insulating layer can have a planarized surface by removing a step difference of a structure under the organic insulating layer. Accordingly, an interface between the protective layer PSV and the first electrode AD can be a planar surface.

[0185] Because a surface of the first electrode AD is affected by a surface of the protective layer PSV under the first electrode AD, the surface of the first electrode AD can have a planarized shape. When the surface of the first electrode AD has a planarized shape, a display device including the organic light emitting device OLED can prevent or reduce white color angle dependency caused by surface unevenness of the first electrode AD.

[0186] The encapsulation layer SLM can prevent or reduce oxygen and moisture from penetrating into the organic light emitting device OLED. The encapsulation layer SLM can include a plurality of inorganic layers and a plurality of organic layers. For example, the encapsulation layer SLM can include a plurality of encapsulation layers including inorganic layers and organic layers disposed on the inorganic layers. In addition, an inorganic layer can be disposed at an uppermost portion of the encapsulation layer SLM. The inorganic layer can include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide, and combinations thereof.

[0187] Figures 2 to 7 is a plan view illustrating an active pattern shown in Figure 9 is a plan view illustrating a scan line, a light emitting control line, and a lower electrode of a storage capacitor shown in Figures 2 to 7 is a plan view illustrating an active pattern shown in Figure 10 is a plan view illustrating a scan line, a light emitting control line, and a lower electrode of a storage capacitor shown in Figures 2 to 7 is a plan view illustrating an active pattern shown in Figure 11A plan view of the initialization power line and the upper electrode of the storage capacitor shown in FIG. 1. Figures 2 to 7 is a plan view of the data line, the connection line, the auxiliary connection line, the first conductive layer of the power line, and the first bridge pattern shown in FIG. 1. Figure 12 is a plan view of the data line, the connection line, the auxiliary connection line, the first conductive layer of the power line, and the first bridge pattern shown in FIG. 1. Figures 2 to 7 is a plan view of the data line, the connection line, the auxiliary connection line, the first conductive layer of the power line, and the first bridge pattern shown in FIG. 1. Figure 13 is a plan view of the second conductive layer of the power line and the second bridge pattern shown in FIG. 1. Figures 2 to 7 is a plan view of the second conductive layer of the power line and the second bridge pattern shown in FIG. 1. Figure 14 is a plan view of the organic light emitting device shown in FIG. 1. Figure 12 is a plan view of the organic light emitting device shown in FIG. 1. Figure 13 and Figure 15 is a plan view of the second conductive layer of the power line, the second bridge pattern, and the organic light emitting device shown in FIG. 1. Figure 14 is a cross-sectional view taken along line IV-IV’ of FIG. 1. Figure 16 is a cross-sectional view taken along line V-V’ of FIG. 1. In Figure 14 is a cross-sectional view taken along line V-V’ of FIG. 1. In Figures 7 to 13 is a cross-sectional view taken along line V-V’ of FIG. 1. In Figure 15 , components of pixels on the i-th pixel row and the (i+1)-th pixel row are shown for each layer for ease of explanation. In Figure 16 and Figures 2 to 16 , the second interlayer insulating layer, the third interlayer insulating layer, the first conductive layer, the second conductive layer, and the first electrode are shown for ease of description.

[0188] Referring to Figures 17 to 20 , the first to seventh active patterns ACT1 to ACT7 can be disposed on the substrate SUB. The first to seventh active patterns ACT1 to ACT7 can be formed in the same layer by the same process.

[0189] One end of the first active pattern ACT1 can be connected to the first source electrode SE1, and the other end of the first active pattern ACT1 can be connected to the first drain electrode DE1. One end of the second active pattern ACT2 can be connected to the second source electrode SE2, and the other end of the second active pattern ACT2 can be connected to the second drain electrode DE2. One end of the third active pattern ACT3 can be connected to the third source electrode SE3, and the other end of the third active pattern ACT3 can be connected to the third drain electrode DE3. One end of the fourth active pattern ACT4 can be connected to the fourth source electrode SE4, and the other end of the fourth active pattern ACT4 can be connected to the fourth drain electrode DE4. One end of the fifth active pattern ACT5 can be connected to the fifth source electrode SE5, and the other end of the fifth active pattern ACT5 can be connected to the fifth drain electrode DE5. One end of the sixth active pattern ACT6 can be connected to the sixth source electrode SE6, and the other end of the sixth active pattern ACT6 can be connected to the sixth drain electrode DE6. One end of the seventh active pattern ACT7 can be connected to the seventh source electrode SE7, and the other end of the seventh active pattern ACT7 can be connected to the seventh drain electrode DE7.

[0190] The scan lines Si-1, Si, and Si+1, the light emission control lines Ei and Ei+1, and the lower electrodes LE of the storage capacitors Cst can be disposed on a gate insulating layer GI disposed on the first active pattern ACT1 to the seventh active pattern ACT7. The scan lines Si-1, Si, and Si+1, the light emission control lines Ei and Ei+1, and the lower electrodes LE of the storage capacitors Cst can be formed in the same layer by the same process.

[0191] The scan lines Si-1, Si, and Si+1 can include an (i-1)th scan line Si-1, an ith scan line Si, and an (i+1)th scan line Si+1.

[0192] On the ith pixel row, the first gate electrode GE1 is connected to the lower electrode LE (e.g., disposed as the lower electrode LE or as a part of the lower electrode LE), and the fourth gate electrode GE4 is connected to the (i-1)th scan line Si-1 (e.g., disposed as the (i-1)th scan line Si-1 or as a part of the (i-1)th scan line Si-1). The second gate electrode GE2, the third gate electrode GE3, and the seventh gate electrode GE7 can be connected to the ith scan line Si (e.g., disposed as the ith scan line Si or as a part of the ith scan line Si). The fifth gate electrode GE5 and the sixth gate electrode GE6 can be connected to the light emission control line Ei (e.g., disposed as the light emission control line Ei or as a part of the light emission control line Ei).

[0193] On the (i+1)th pixel row, the first gate electrode GE1 is connected to the lower electrode LE (e.g., is disposed as or as part of the lower electrode LE), and the fourth gate electrode GE4 is connected to the ith scan line Si (e.g., is disposed as or as part of the ith scan line Si). The second gate electrode GE2, the third gate electrode GE3, and the seventh gate electrode GE7 can be connected to the (i+1)th scan line Si+1 (e.g., is disposed as or as part of the (i+1)th scan line Si+1). The fifth gate electrode GE5 and the sixth gate electrode GE6 can be connected to the light emission control line Ei+1 (e.g., is disposed as or as part of the light emission control line Ei+1).

[0194] The initialization power line IPL and the upper electrode UE of the storage capacitor Cst can be disposed on the first interlayer insulating layer IL1 disposed above the scan lines Si-1, Si, and Si+1, the light emission control lines Ei and Ei+1, and the lower electrode LE. The initialization power line IPL and the upper electrode UE can be formed in the same layer by the same process.

[0195] The data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4, the first conductive layer PL1 of the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1 can be disposed on the second interlayer insulating layer IL2 disposed above the initialization power line IPL and the upper electrode UE. The data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4, the first conductive layer PL1, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1 can be formed in the same layer by the same process.

[0196] The data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 can be connected to the second source electrode SE2 through the sixth contact hole CH6 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0197] The first conductive layer PL1 can extend in parallel with at least one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 (e.g., the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4) and the scan lines Si-1, Si, and Si+1. The first conductive layer PL1 can be connected to the upper electrode UE through the third contact hole CH3 and the fourth contact hole CH4 passing through the second interlayer insulating layer IL2. In addition, the first conductive layer PL1 can be connected to the fifth source electrode SE5 through the fifth contact hole CH5 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0198] The connection line CNL can be connected to the first gate electrode GE1 through a first contact hole CH1 passing through the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2.

[0199] The auxiliary connection line AUX can be connected to the initialization power line IPL through an eighth contact hole CH8 passing through the second interlayer insulating layer IL2. Also, the auxiliary connection line AUX can be connected to the seventh drain electrode DE7 through a ninth contact hole CH9 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0200] The first bridge pattern BRP1 can be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0201] The second bridge pattern BRP2 and the second conductive layer PL2 of the power line PL can be disposed on a third interlayer insulating layer IL3 disposed on the data line Dj, the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1. The second bridge pattern BRP2 and the second conductive layer PL2 can be formed in the same layer through the same process.

[0202] The second bridge pattern BRP2 can be connected to the first bridge pattern BRP1 through a tenth contact hole CH10.

[0203] The second conductive layer PL2 can include a plurality of first conductive lines CL1 and a plurality of second conductive lines CL2 crossing the first conductive lines CL1.

[0204] One of the first conductive lines CL1 and the second conductive lines CL2 (e.g., the first conductive lines CL1) can extend in a direction parallel to one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and one of the scan lines Si-1, Si, and Si+1 (e.g., the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4). The first conductive lines CL1 are stacked with the first conductive layer PL1 in parallel to the first conductive layer PL1 and can be connected to the first conductive layer PL1 through an eleventh contact hole CH11 passing through the third interlayer insulating layer IL3. Accordingly, since the power line PL includes the first conductive layer PL1 and the second conductive layer PL2, and the first conductive layer PL1 and the second conductive layer PL2 are electrically connected to each other, it is possible to prevent or reduce a voltage drop of power (e.g., the first power source ELVDD) supplied through the power line PL.

[0205] The other one of the first and second conductive lines CL1 and CL2 (e.g., the second conductive line CL2) can be parallel to the other one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1 (e.g., the scan lines Si-1, Si, and Si+1).

[0206] In the present embodiment, a case in which the second conductive line CL2 extends in a direction parallel to the scan lines Si-1, Si, and Si+1 has been shown as an example, but the present disclosure is not limited thereto. For example, the second conductive line CL2 can extend in a direction inclined with respect to the scan lines Si-1, Si, and Si+1.

[0207] A protective layer PSV can be disposed on the third interlayer insulating layer IL3 on which the second conductive layer PL2 and the second bridge pattern BRP2 are formed. The protective layer PSV can include at least one of an organic insulating layer and an inorganic insulating layer. For example, the protective layer PSV can include the organic insulating layer.

[0208] An organic light emitting device OLED can be disposed on the protective layer PSV. Each organic light emitting device OLED can include a first electrode AD disposed on the protective layer PSV, an emission layer EML disposed on the first electrode AD, and a second electrode CD disposed on the emission layer EML.

[0209] The first electrode AD can be connected to the second bridge pattern BRP2 through a twelfth contact hole CH12 passing through the protective layer PSV.

[0210] When the first and second conductive lines CL1 and CL2 of the second conductive layer PL2 are overlapped with the organic light emitting device OLED, a step difference can occur at a lower portion of the organic light emitting device OLED due to the second conductive layer PL2. A surface of the protective layer PSV can have irregularity. The irregularity of the surface of the protective layer PSV can cause irregularity of a surface of the first electrode AD disposed on the protective layer PSV. If the surface of the first electrode AD has irregularity, a surface of emission light of the organic light emitting device OLED can have irregularity. If the surface of the emission light of the organic light emitting device OLED has irregularity, light emitted from the organic light emitting device OLED is emitted non-uniformly according to its direction. Thus, WAD according to a viewing angle of a display device including the organic light emitting device OLED can occur.

[0211] However, in the embodiments of the present disclosure, the display device including the organic light emitting device OLED can prevent or reduce WAD according to its viewing angle.

[0212] This will be described in more detail. The third interlayer insulating layer IL3 includes a recess CCP disposed in a region in which the second conductive layer PL2 and the first electrode AD are stacked on each other, and the second conductive layer PL2 can be disposed in the recess CCP. The recess CCP can be a region in which a portion of the third interlayer insulating layer IL3 is removed. For example, the recess CCP can be an opening through which the second sub-insulating layer IL32 exposes the first sub-insulating layer IL31 in a region in which the second conductive layer PL2 and the first electrode AD are stacked on each other.

[0213] The second conductive layer PL2 can be disposed on the first sub-insulating layer IL31. Accordingly, a distance between the second conductive layer PL2 and the first electrode AD can increase in a region in which the second conductive layer PL2 and the first electrode AD are stacked on each other. When the distance between the second conductive layer PL2 and the first electrode AD increases in the region in which the second conductive layer PL2 and the first electrode AD are stacked on each other, a thickness of the protective layer PSV can increase. The protective layer PSV can include an organic insulating layer. As the thickness of the organic insulating layer increases, the organic insulating layer can have a planarized surface by removing a step difference of a structure under the organic insulating layer. Accordingly, an interface between the protective layer PSV and the first electrode AD can be a planar face.

[0214] Because a surface of the first electrode AD is affected by a layer under the first electrode AD, i.e., a surface of the protective layer PSV, the surface of the first electrode AD can have a planarized shape. When the surface of the first electrode AD has a planarized shape, a display device including the organic light emitting device OLED can prevent or reduce WAD caused by surface non-uniformity of the first electrode AD.

[0215] Hereinafter, a display device according to another embodiment of the disclosure will be described with reference to Figures 17 to 20 A display device according to other embodiments of the disclosure will be described. In Figures 1 to 16 components shown in Figures 17 to 20 are denoted by the same reference numerals as those of components shown in Figures 1 to 16 , and can be described briefly. Also, in Figure 17 , differences from may be mainly described to avoid redundancy.

[0216] Figure 18 Figure 17 are views showing a display device according to another embodiment of the disclosure. Figure 14 is a cross-sectional view taken along line IV-IV' of Figure 18 , and Figure 14 is a cross-sectional view taken along line V-V' of Figure 17 . In Figure 18 and Figures 2 to 14 , a second interlayer insulating layer, a third interlayer insulating layer, a first conductive layer, a second conductive layer, and a first electrode are shown for convenience of description.

[0217] Referring to Figure 17 , Figure 18 and Figure 19 , active patterns ACT1 to ACT7 (hereinafter, referred to as ACT) can be disposed on the substrate SUB. The active patterns ACT can include a first active pattern ACT1 to a seventh active pattern ACT7. The first active pattern ACT1 to the seventh active pattern ACT7 can include a semiconductor material.

[0218] A gate insulating layer GI can be disposed on the substrate SUB on which the active patterns ACT are formed.

[0219] The (i-1)th scan line Si-1, the i-th scan line Si, the emission control line Ei, and the first to seventh gate electrodes GE1 to GE7 can be disposed on the gate insulating layer GI. The first gate electrode GE1 can become a lower electrode LE of the storage capacitor Cst.

[0220] A first interlayer insulating layer IL1 can be disposed on the substrate SUB on which the (i-1)th scan line Si-1, etc. are formed.

[0221] An upper electrode UE of the storage capacitor Cst and an initialization power line IPL can be disposed on the first interlayer insulating layer IL1.

[0222] A second interlayer insulating layer IL2 can be disposed on the substrate SUB on which the upper electrode UE and the initialization power line IPL are disposed.

[0223] The data line Dj, the connection line CNL, the auxiliary connection line AUX, the first bridge pattern BRP1, and the first conductive layer PL1 of the power line PL can be disposed on the second interlayer insulating layer IL2.

[0224] A third interlayer insulating layer IL3 can be disposed on the substrate SUB on which the data line Dj, etc. are formed. The third interlayer insulating layer IL3 can include at least one of an organic insulating layer and an inorganic insulating layer. For example, the third interlayer insulating layer IL3 can be an organic insulating layer including an organic insulating material.

[0225] The second bridge pattern BRP2 and the second conductive layer PL2 of the power line PL can be disposed on the third interlayer insulating layer IL3. The second conductive layer PL2 can include a plurality of first conductive lines CL1 and a plurality of second conductive lines CL2 crossing the first conductive lines CL1. One of the first conductive lines CL1 and the second conductive lines CL2 is superposed on the first conductive layer PL1 and can be electrically connected to the first conductive layer PL1.

[0226] A protective layer PSV can be disposed on the third interlayer insulating layer IL3 on which the second conductive layer PL2 and the second bridge pattern BRP2 are disposed.

[0227] The organic light emitting device OLED can be disposed on the protective layer PSV. The organic light emitting device OLED can include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0228] An encapsulation layer SLM that isolates the organic light emitting device OLED from an external environment can be disposed on the organic light emitting device OLED.

[0229] In an embodiment of the disclosure, the third interlayer insulating layer IL3 can include a recess CCP disposed in an area in which the second conductive layer PL2 and the first electrode AD are stacked on each other, and the second conductive layer PL2 can be disposed in the recess CCP. The recess CCP can be an area in which a portion of the third interlayer insulating layer IL3 is removed. For example, the recess CCP can be an opening through which the third interlayer insulating layer IL3 exposes the first conductive layer PL1 and the second interlayer insulating layer IL2 in an area in which the second conductive layer PL2 and the first electrode AD are stacked on each other. This will be described in more detail. In the area in which the second conductive layer PL2 and the first electrode AD are stacked on each other, the recess CCP can at least expose the first conductive layer PL1 therethrough. In addition, in the area in which the second conductive layer PL2 and the first electrode AD are stacked on each other, the recess CCP can be an opening through which the second interlayer insulating layer IL2 is exposed. Accordingly, in the recess CCP, the first conductive line CL1 of the second conductive layer PL2 is disposed on the first conductive layer PL1 and can be in direct contact with the first conductive layer PL1. In addition, the second conductive line CL2 of the second conductive layer PL2 can be disposed on the second interlayer insulating layer IL2. Here, because the first conductive line CL1 and the first conductive layer PL1 are in direct contact with each other, an eleventh contact hole CH11 through which the first conductive layer PL1 is electrically connected to the second conductive layer PL2 can be omitted.

[0230] As described above, in the area in which the second conductive layer PL2 and the first electrode AD are stacked on each other, the first conductive line CL1 can be disposed on the first conductive layer PL1, and the second conductive line CL2 can be disposed on the second interlayer insulating layer IL2. Accordingly, a distance between the second conductive layer PL2 and the first electrode AD can increase in the area in which the second conductive layer PL2 and the first electrode AD are stacked on each other. When the distance between the second conductive layer PL2 and the first electrode AD increases, a thickness of the protective layer PSV can increase. The protective layer PSV can include an organic insulating layer. As the thickness of the organic insulating layer increases, the organic insulating layer can have a planarized surface by removing a step difference of a structure below the organic insulating layer.

[0231] Because the surface of the first electrode AD is affected by the layer beneath the first electrode AD (i.e., the surface of the protective layer PSV), the surface of the first electrode AD can have a planarized shape. When the surface of the first electrode AD has a planarized shape, display devices including organic light-emitting devices (OLEDs) can prevent or reduce WAD caused by surface inhomogeneities of the first electrode AD.

[0232] Figure 20 and Figure 19 This is a view illustrating a display device according to yet another embodiment of the present disclosure. Figure 14 It is along Figure 20 A sectional view taken from line IV-IV'. Figure 14 It is along Figure 19 A sectional view taken by line V-V'. Figure 20 and Figures 2 to 14 For ease of description, the second interlayer insulating layer, the third interlayer insulating layer, the first conductive layer, the second conductive layer, and the first electrode are shown.

[0233] Reference Figure 19 , Figure 20 and ​ Active patterns ACT1 to ACT7 (hereinafter referred to as ACT) may be disposed on the substrate SUB. The active pattern ACT may include the first active pattern ACT1 to the seventh active pattern ACT7. The first active pattern ACT1 to the seventh active pattern ACT7 may include semiconductor material.

[0234] The gate insulating layer GI can be disposed on a substrate SUB on which an active pattern ACT is formed.

[0235] The (i-1)th scan line Si-1, the i-th scan line Si, the light emission control line Ei, and the first gate electrode GE1 to the seventh gate electrode GE7 can be disposed on the gate insulating layer GI. The first gate electrode GE1 can become the lower electrode LE of the storage capacitor Cst.

[0236] The first interlayer insulating layer IL1 can be disposed on a substrate SUB on which the (i-1)th scan line Si-1 is formed.

[0237] The upper electrode UE of the storage capacitor Cst and the initialization power line IPL can be set on the first interlayer insulation layer IL1.

[0238] The second interlayer insulation layer IL2 can be disposed on a substrate SUB on which the upper electrode UE and the initialization power line IPL are disposed.

[0239] Data line Dj, connecting line CNL, auxiliary connecting line AUX, first bridging diagram BRP1, and the first conductive layer PL1 of power line PL can be disposed on the second interlayer insulation layer IL2.

[0240] A third interlayer insulating layer IL3 can be disposed on the substrate SUB on which the data line Dj and the like are formed. The third interlayer insulating layer IL3 can include at least one of an organic insulating layer and an inorganic insulating layer. For example, the third interlayer insulating layer IL3 can include a first sub-insulating layer IL31 including an inorganic insulating material, and a second sub-insulating layer IL32 disposed on the first sub-insulating layer IL31, the second sub-insulating layer IL32 including an organic insulating layer.

[0241] A second bridge pattern BRP2 and a second conductive layer PL2 of the power line PL can be disposed on the third interlayer insulating layer IL3. The second conductive layer PL2 can include a plurality of first conductive lines CL1 and a plurality of second conductive lines CL2 crossing the first conductive lines CL1. One of the first conductive lines CL1 and the second conductive lines CL2 is superposed on the first conductive layer PL1 and can be electrically connected to the first conductive layer PL1.

[0242] A protective layer PSV can be disposed on the third interlayer insulating layer IL3 on which the second conductive layer PL2 and the second bridge pattern BRP2 are disposed.

[0243] An organic light emitting device OLED can be disposed on the protective layer PSV. The organic light emitting device OLED can include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0244] An encapsulation layer SLM that isolates the organic light emitting device OLED from an external environment can be disposed on the organic light emitting device OLED.

[0245] In an embodiment of the disclosure, the third interlayer insulating layer IL3 can include a recess CCP disposed in a region in which the second conductive layer PL2 and the first electrode AD are superposed on each other, and the second conductive layer PL2 can be disposed in the recess CCP. The recess CCP can be a region in which a portion of the third interlayer insulating layer IL3 is removed. For example, in the region in which the second conductive layer PL2 and the first electrode AD are superposed on each other, the recess CCP can be a recessed region in which a partial thickness of the second sub-insulating layer IL32 is removed. That is, in the second sub-insulating layer IL32, the thickness of the region in which the second conductive layer PL2 and the first electrode AD are superposed on each other can be less than the thickness of the other regions.

[0246] In an embodiment of the disclosure, because the second conductive layer PL2 is disposed at the recess CCP in the region in which the second conductive layer PL2 and the first electrode AD are overlaid with each other, the distance between the second conductive layer PL2 and the first electrode AD can be increased. When the distance between the second conductive layer PL2 and the first electrode AD is increased in the region in which the second conductive layer PL2 and the first electrode AD are overlaid with each other, the thickness of the protective layer PSV can be increased. The protective layer PSV can include an organic insulating layer. As the thickness of the organic insulating layer is increased, the organic insulating layer can have a planarized surface by removing a step difference of a structure under the organic insulating layer. Accordingly, the interface between the protective layer PSV and the first electrode AD can be a planar face.

[0247] Because the surface of the first electrode AD is affected by the surface of the layer under the first electrode AD, i.e., the protective layer PSV, the surface of the first electrode AD can have a planarized shape. When the surface of the first electrode AD has a planarized shape, the display device including the organic light emitting device OLED can prevent or reduce WAD caused by surface unevenness of the first electrode AD.

[0248] As described above, according to the disclosure, the display device removes a step difference generated at a lower portion of the organic light emitting device, so that light generated from the organic light emitting device can be uniformly emitted according to its direction. Accordingly, it is possible to prevent or reduce WAD according to a viewing angle of the display device.

[0249] Example embodiments have been disclosed herein thus far, although specific terminology has been employed, they are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those skilled in the art from this disclosure as it exists at the time of filing, features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically stated otherwise. Accordingly, those skilled in the art will appreciate that in the practice of the present disclosure as set forth in the claims and equivalents thereof, various suitable changes in form and detail can be made without departing from the spirit and scope of the disclosure.

Claims

1. A display device comprising: a substrate including a pixel region and a peripheral region; a plurality of pixels located in the pixel region of the substrate, each of the plurality of pixels including a light-emitting device having a light-emitting region, the light-emitting device including a first electrode, an emission layer, and a second electrode; a data line and a scan line connected to the plurality of pixels; a power line configured to supply power to the light-emitting device, the power line including a first conductive layer at the same layer as the data line and a second conductive layer located on the first conductive layer; and an insulating layer between the power line and the first electrode, wherein the first electrode, the emission layer, and the second electrode are stacked at the light-emitting region, wherein the second conductive layer includes a first portion corresponding to the light-emitting region and a second portion not corresponding to the light-emitting region, and wherein, in a cross section taken in a direction perpendicular to a main surface of the substrate, the second portion is closer to the first electrode than the first portion. the insulating layer includes a recess at a region where the light-emitting device and the power line are stacked on each other, and wherein at least a portion of the second conductive layer is located in the recess.

2. The display device according to claim 1, wherein the insulating layer includes a first insulating layer and a second insulating layer located on the first insulating layer.

3. The display device of claim 2, wherein, the first insulating layer includes:

4. The display device according to claim 3, wherein a first sub-insulating layer located on the first conductive layer; and a second sub-insulating layer located on the first sub-insulating layer, the second sub-insulating layer including an organic insulating layer. the recess includes a region in which a portion of the second sub-insulating layer is removed to expose the first sub-insulating layer therethrough.

5. The display device of claim 4, wherein, the first insulating layer includes an organic insulating layer, and wherein the recess exposes the first conductive layer therethrough.

6. The display device according to claim 3, wherein at the recess, the second conductive layer is in direct contact with the first conductive layer.

7. The display device of claim 6, wherein, the second conductive layer includes:

8. The display device according to claim 2, wherein a plurality of first wires extending in one direction; and a plurality of second wires crossing the plurality of first wires, wherein the plurality of first wires and the plurality of second wires are electrically connected to each other. the second conductive layer has a mesh form.

9. The display device of claim 8, wherein, the plurality of first wires extend in a direction parallel to the data line or the scan line.

10. The display device of claim 9, wherein, the second insulating layer has a planarized surface, and wherein, in the cross section, a thickness of a region in the second insulating layer corresponding to the recess is greater than a thickness of other regions.

11. The display device according to claim 3, wherein 12. The display device according to claim 11, further comprising at least one transistor connected to the light-emitting device, the first electrode is located on the at least one transistor, the emission layer is located on the first electrode, and the second electrode is located on the emission layer. wherein, an interface between the second insulating layer and the first electrode has a planar surface.

13. The display device of claim 12, wherein, the first conductive layer includes a third portion corresponding to the light-emitting region and a fourth portion not corresponding to the light-emitting region.

14. The display device of claim 1, wherein, the third portion corresponds to at least a portion of the first portion, and the fourth portion corresponds to at least a portion of the second portion.

15. The display device of claim 14, wherein, ​

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