Display panel and display device

Abstract

A display panel, comprehensive: Sub-pixel arrays (10), wherein a sub-pixel (10) of the sub-pixel arrays (10) comprises a pixel circuit (11) and a light-emitting element (12); Scan lines (30), wherein one scan line (30) of the scan lines (30) is connected to the pixel circuit (11) and extends along a first direction (X); and Data lines (20), wherein one data line (20) of the data lines (20) is connected to the pixel circuit (11) and extends along a second direction (Y) and the first direction (X) intersects the second direction (Y); wherein the sub-pixel rows (10) comprise a first sub-pixel (101) and a second sub-pixel (102), the first sub-pixel (101) comprises a first pixel circuit (111) and a first light-emitting element (121), the second sub-pixel (102) comprises a second pixel circuit (112) and a second light-emitting element (122), and a light-emitting color of the first light-emitting element (121) differs from a light-emitting color of the second light-emitting element (122); the data lines (20) comprise a first data line (21) which is connected to the first pixel circuit (111) and the second pixel circuit (112); the sampling lines (30) comprise a first sampling line (31), wherein the first sampling line (31) comprises a first sub-sampling line (311) and a second sub-sampling line (312), the first sub-sampling line (311) being connected to the first pixel circuit (111) and the second sub-sampling line (312) being connected to the second pixel circuit (112); the display panel further comprises first power signal lines (41) and initialization signal lines (50), both of which are connected to the pixel circuit (11); the display panel comprises a first region (A1) and a second region (A2) arranged along the second direction (Y); and a line width of the first data line (21) is W11 in the first region (A1) and W12 in the second region (A2); wherein the display panel satisfies at least one of the following: a first power signal line (41) of the first power signal lines (41) extends along the second direction (Y); and a linewidth of the first power signal line (41) in the first region (A1) is W21 and in the second region (A2) is W22, where |W11 - W12| + |W21 - W22| ≠ 0; or An initialization signal line (50) of the initialization signal lines (50) extends along the second direction (Y); and a linewidth of the initialization signal line (50) in the first region (A1) is W31 and in the second region (A2) is W32, where |W11 - W12|+ |W31 - W32| ≠ 0; or both a first power signal line (41) of the first power signal lines (41) and an initialization signal line (50) of the initialization signal lines (50) extend along the second direction (Y); and a line width of the first power signal line (41) is W21 in the first region (A1) and W22 in the second region (A2), and a line width of the initialization signal line (50) is W31 in the first region (A1) and W32 in the second region (A2), where |W11 - W12| + |W21 - W22| + |W31 - W32| ≠ 0.

Description

TECHNICAL AREA

[0001] Embodiments of the present innovation relate to the field of display technology and in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous advancement of science and technology, electronic devices with display functions are becoming increasingly widespread in people's daily lives and work. These devices have brought great convenience and have become indispensable and important tools of modern society.

[0003] The main component that enables an electronic device to perform display functions is the display panel. The display panel comprises a variety of electronic components and signal lines. The design of the signal lines has varying degrees of impact on different aspects of the display panel, such as resolution, display quality, power consumption, and cost. Therefore, providing an optimization scheme for signal line design has become one of the key engineering challenges currently being addressed. SUMMARY

[0004] The present innovation provides a display panel and display device to compensate for the spatial arrangement within the panel, optimize the line width design of signal lines, improve signal transmission quality, and increase display uniformity.

[0005] In a first aspect, embodiments of the present innovation provide a display panel. The display panel comprises sub-pixel arrays, scanning lines, and data lines.

[0006] A sub-pixel array comprises a pixel circuit and a light-emitting element.

[0007] A scanning line is connected to the pixel circuit, and the scanning line extends along a first direction.

[0008] A data line is connected to the pixel circuit, and the data line extends in a second direction. The first direction intersects the second direction.

[0009] The sub-pixel rows comprise at least a first sub-pixel row and a second sub-pixel row. The first sub-pixel row comprises a first pixel circuit and a first light-emitting element. The second sub-pixel row comprises a second pixel circuit and a second light-emitting element. The light-emitting color of the first light-emitting element differs from the light-emitting color of the second light-emitting element.

[0010] The data lines include a first data line. The first data line is connected to the first pixel circuit, and the first data line is also connected to the second pixel circuit.

[0011] The sampling lines comprise a first sampling line. The first sampling line comprises a first sub-sampling line and a second sub-sampling line. The first sub-sampling line is connected to the first pixel circuit, and the second sub-sampling line is connected to the second pixel circuit.

[0012] The display panel also includes initial power signal lines and initialization signal lines, both of which are connected to the pixel circuit.

[0013] The display panel comprises a first region and a second region, arranged along the second direction.

[0014] In the first region, the line width of the first data line is W11, and in the second region, the line width of the first data line is W12.

[0015] The display panel meets at least one of the following criteria:

[0016] A first power signal line extends along the second direction; in the first region the line width of the first power signal line is W21 and in the second region the line width of the first power signal line is W22, where |W11 - W12| + |W21 - W22| ≠ 0.

[0017] Alternatively, an initialization signal line extends along the second direction; in the first region, the line width of the initialization signal line is W31 and in the second region, the line width of the initialization signal line is W32, where |W11 - W12| + |W31 - W32| ≠ 0.

[0018] Alternatively, both the first power signal line and the initialization signal line extend along the second direction; in the first region, the line width of the first power signal line is W21, the line width of the initialization signal line is W31, and in the second region, the line width of the first power signal line is W22 and the line width of the initialization signal line is W32, where |W11 - W12|+ |W21 - W22| + |W31 - W32| ≠ 0.

[0019] Optionally, the display panel includes sub-pixel rows. A sub-pixel row comprises several sub-pixel rows arranged along the first direction. Along the second direction, a first spacing is provided between pixel circuits of adjacent sub-pixel rows.

[0020] The first region overlaps at least partially with the first distance.

[0021] The second region overlaps at least partially with pixel circuits of the multiple sub-pixel rows in the sub-pixel row.

[0022] Optionally, W11 > W12 applies.

[0023] Optionally, the first power signal line extends along the second direction and the display panel satisfies (W11 W12) × (W21 - W22) ≥ 0.

[0024] Optionally, the first power signal line extends along the second direction and the display panel fulfills W21 > W22.

[0025] Optionally, the first power signal line extends along the second direction and the display panel fulfills W21 - W22 > W11 - W12.

[0026] Optionally, the first power signal line extends along the second direction.

[0027] In the first region, the distance between the first data line and the first power signal line that are adjacent to each other is D11, and in the second region, the distance between the first data line and the first power signal line that are adjacent to each other is D12, where D11 < D12.

[0028] Optionally, the first power signal line extends along the second direction.

[0029] In the second region, the first data line includes first winding sections, and the first power signal line includes second winding sections.

[0030] At least one first winding section has the same winding direction as at least one second winding section. Alternatively, at least one first winding section has a winding direction opposite to at least one second winding section.

[0031] Optionally, the initialization signal line extends along the second direction and the display panel satisfies (W11 - W12) × (W31 - W32) ≥ 0.

[0032] Optionally, the initialization signal line extends along the second direction and the display panel fulfills W31 > W32.

[0033] Optionally, the initialization signal line extends along the second direction and the display panel fulfills W31 - W32 > W11 - W12.

[0034] Optionally, the initialization signal line extends along the second direction.

[0035] In the first region, the distance between the first data line and the initialization signal line, which are adjacent to each other, is D21, and in the second region, the distance between the first data line and the initialization signal line, which are adjacent to each other, is D22, where D21 < D22.

[0036] Optionally, the initialization signal line extends along the second direction.

[0037] In the second region, the first data line comprises a first winding section and the initialization signal line comprises third winding sections.

[0038] The display panel fulfills at least one of the following characteristics: at least one first winding section has the same winding direction as at least one third winding section; or at least one first winding section has a winding direction opposite to at least one third winding section.

[0039] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where (W21 - W22) × (W31 - W32) ≥ 0.

[0040] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where W31 - W32 > W21 - W22.

[0041] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where |W21 - W31| + |W22 - W32| ≠ 0.

[0042] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where (W11 - W12) × (W21 - W22) × (W31 - W32) ≥ 0.

[0043] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where W11 - W12 ≠ W21 - W22 ≠ W31 - W32.

[0044] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where W11 - W12 < W21 - W22 < W31 - W32.

[0045] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where (W31 - W32) - (W21 - W22) > (W21 - W22) - (W11 - W12).

[0046] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where W21 ≥ W31 > W11 or W22 > W32 ≥ W12.

[0047] Optionally, both the first power signal line and the initialization signal line extend along the second direction.

[0048] In the second region, the first data line includes a first winding section, the first power signal line includes a second winding section, and the initialization signal line includes a third winding section.

[0049] At least two of the first, second and third winding sections have opposite winding directions.

[0050] Optionally, the sub-pixel rows can also include a third sub-pixel row. This third sub-pixel row comprises a third pixel circuit and a third light-emitting element. The light-emitting color of the first, second, and third light-emitting elements are different.

[0051] The data lines include a second data line, and the second data line is connected to the third pixel circuit.

[0052] Optionally, the sub-pixel rows can also include a fourth sub-pixel row. This fourth sub-pixel row comprises a fourth pixel circuit and a fourth light-emitting element. The light-emitting color of the first, second, third, and fourth light-emitting elements are different.

[0053] The second data line is connected to the fourth pixel circuit.

[0054] Optionally, in the first region the line width of the second data line is W41 and in the second region the line width of the second data line is W42, where |W11 - W12| + |W41 - W42| ≠ 0.

[0055] Optionally, the display panel (W11 - W12) × (W41 - W42) ≥ 0.

[0056] Optionally, the display panel fulfills W11 - W12 ≠ W41 - W42 requirements.

[0057] Optionally, both the first power signal line and the initialization signal line extend along the second direction, where |(W31 - W32) - (W21 - W22)| > |(W11 - W12) - (W41 - W42)|.

[0058] Optionally, the first power signal line extends along the second direction.

[0059] In the second region, the first data line includes a first winding section, the first power signal line includes a second winding section, and the second data line includes a fourth winding section.

[0060] At least two of the first, second and fourth winding sections have opposite winding directions.

[0061] Optionally, the initialization signal line extends along the second direction.

[0062] In the second region, the first data line comprises a first winding section, the initialization signal line comprises a third winding section, and the second data line comprises a fourth winding section.

[0063] At least two of the first, third and fourth winding sections have opposite winding directions.

[0064] Optionally, both the first power signal line and the initialization signal line extend along the second direction.

[0065] In the second region, the first data line includes a first winding section, the first power signal line includes a second winding section, the initialization signal line includes a third winding section, and the second data line includes a fourth winding section.

[0066] At least two of the first, second, third and fourth winding sections have opposite winding directions.

[0067] Optionally, two of the first, second, third and fourth winding sections have winding directions that are opposite to the winding directions of the other two winding sections.

[0068] Optionally, the first winding section has a winding direction that is opposite to the winding direction of the fourth winding section.

[0069] The second winding section has a winding direction that is opposite to the winding direction of the third winding section.

[0070] Optionally, the display panel includes sub-pixel rows. A sub-pixel row comprises multiple sub-pixel rows arranged along the first direction. Along the second direction, a preset region is provided between the first and second sub-scan lines that are closest to each other.

[0071] The first region comprises the preset region.

[0072] The second region does not include the preset region.

[0073] Optionally, the display panel meets at least one of the following criteria: W11 > W12; or the first power signal line extends along the second direction and W21 > W22; or the initialization signal line extends along the second direction and W31 > W32.

[0074] Optionally, the first sub-scanning line includes at least one first ring-shaped structure.

[0075] The display panel fulfills at least one of the following features:

[0076] The first power signal line extends along the second direction; and in a direction perpendicular to a substrate of the display panel, the projection of a first ring-shaped structure intersects at least one of the projections of the first data line or the projection of the first power signal line.

[0076] Alternatively, the initialization signal line extends along the second direction; and in a direction perpendicular to a substrate of the display panel, the projection of a first ring-shaped structure intersects at least one of the projections of the first data line or the projection of the initialization signal line.

[0077] Optionally, the first power signal line extends along the second direction.

[0078] The first sub-scanning line also includes a second ring-shaped structure.

[0079] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, and the projection of the second ring-shaped structure intersects the projection of the first power signal line.

[0080] Optionally, along the first direction, the length of the first ring-shaped structure is La1 and the length of the second ring-shaped structure is La2.

[0081] Along the second direction, the width of the first ring-shaped structure is Wa1 and the width of the second ring-shaped structure is Wa2.

[0082] The display panel meets at least one of the following criteria: La1 ≠ La2 or Wa1 ≠ Wa2.

[0083] Optionally, the display panel must meet at least one of the following criteria: La1 < La2 or Wa1 < Wa2.

[0084] Optionally, the initialization signal line extends along the second direction.

[0085] The first sub-scanning line also includes a third ring-shaped structure.

[0086] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, and the projection of the third ring-shaped structure intersects the projection of the initialization signal line.

[0087] Optionally, along the first direction, the length of the first ring-shaped structure is La1 and the length of the third ring-shaped structure is La3.

[0088] Along the second direction, the width of the first ring-shaped structure is Wa1 and the width of the third ring-shaped structure is Wa3.

[0089] The display panel meets at least one of the following criteria: La1 ≠ La3 or Wa1 ≠ Wa3.

[0090] Optionally, the display panel must meet at least one of the following criteria: La1 < La3 or Wa1 < Wa3.

[0091] Optionally, both the first power signal line and the initialization signal line extend along the second direction.

[0092] The first sub-scanning line further comprises a second ring-shaped structure and a third ring-shaped structure.

[0093] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, the projection of the second ring-shaped structure intersects the projection of the first power signal line, and the projection of the third ring-shaped structure intersects the projection of the initialization signal line.

[0094] Optionally, along the first direction, the length of the first ring-shaped structure is La1, the length of the second ring-shaped structure is La2, and the length of the third ring-shaped structure is La3.

[0095] Along the second direction, the width of the first ring-shaped structure is Wa1, the width of the second ring-shaped structure is Wa2, and the width of the third ring-shaped structure is Wa3.

[0096] The display panel meets at least one of the following criteria: at least two of La1, La2 and La3 are not the same; or at least two of Wa1, Wa2 and Wa3 are not the same.

[0097] Optionally, the display panel fulfills at least one of the following criteria: La1 < La3 ≤ La2; or Wa1 < Wa3 ≤ Wa2.

[0098] Optionally, the first region includes a region within the first ring-shaped structure.

[0099] The second region does not include the region within the first ring-shaped structure.

[0100] Optionally, the display panel must meet at least one of the following criteria:

[0101] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, where W11 > W12.

[0102] Alternatively, the first power signal line extends along the second direction; in the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first power signal line, where W21 > W22.

[0103] Alternatively, the initialization signal line extends along the second direction; in the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the initialization signal line, where W31 > W32.

[0104] Optionally, the display panel must meet at least one of the following criteria:

[0105] The first power signal line extends along the second direction, the first sub-sampling line further includes a second annular structure, and in the direction perpendicular to the substrate of the display panel, the projection of the first annular structure intersects the projection of the first data line and the projection of the second annular structure intersects the projection of the first power signal line, where W11 - W12 > W21 - W22 ≥ 0.

[0106] Alternatively, the initialization signal line extends along the second direction, the first sub-scan line further includes a third ring-shaped structure, and in the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line and the projection of the third ring-shaped structure intersects the projection of the initialization signal line, where W11 - W12 > W31 - W32 ≥ 0.

[0107] Optionally, both the first power signal line and the initialization signal line extend along the second direction.

[0108] The first sub-scanning line further comprises a second ring-shaped structure and a third ring-shaped structure.

[0109] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, the projection of the second ring-shaped structure intersects the projection of the first power signal line, and the projection of the third ring-shaped structure intersects the projection of the initialization signal line.

[0110] The display panel meets W11 - W12 > W31 - W32 ≥ W21 - W22 ≥ 0.

[0111] Optionally, the sub-pixel rows can also include a third sub-pixel row. This third sub-pixel row comprises a third pixel circuit and a third light-emitting element. The light-emitting color of the first, second, and third light-emitting elements are different.

[0112] The data lines include a second data line, and the second data line is connected to the third pixel circuit.

[0113] Optionally, the sub-pixel rows can also include a fourth sub-pixel row. This fourth sub-pixel row comprises a fourth pixel circuit and a fourth light-emitting element. The light-emitting colors of the first, second, third, and fourth light-emitting elements are different.

[0114] The second data line is connected to the fourth pixel circuit.

[0115] Optionally, both the first power signal line and the initialization signal line extend along the second direction.

[0116] The first sub-scanning line further comprises a second ring-shaped structure, a third ring-shaped structure, and a fourth ring-shaped structure.

[0117] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, the projection of the second ring-shaped structure intersects the projection of the first power signal line, the projection of the third ring-shaped structure intersects the projection of the initialization signal line, and the projection of the fourth ring-shaped structure intersects the projection of the second data line.

[0118] Optionally, along the first direction, the length of the first ring-shaped structure is La1, the length of the second ring-shaped structure is La2, the length of the third ring-shaped structure is La3, and the length of the fourth ring-shaped structure is La4.

[0119] Along the second direction, the width of the first ring-shaped structure is Wa1, the width of the second ring-shaped structure is Wa2, the width of the third ring-shaped structure is Wa3, and the width of the fourth ring-shaped structure is Wa4.

[0120] The display panel meets at least one of the following criteria:

[0121] At least two of La1, La2, La3 and La4 are not the same.

[0122] Alternatively, at least two of Wa1, Wa2, Wa3 and Wa4 are not the same.

[0123] Optionally, the display panel fulfills at least one of the following criteria: La1 = La4; or La2 = La3; or Wa1 = Wa4; or Wa2 = Wa3.

[0124] Optionally, the second sub-scanning line includes a fifth ring-shaped structure, a sixth ring-shaped structure, a seventh ring-shaped structure, and an eighth ring-shaped structure.

[0125] In the direction perpendicular to the substrate of the display panel, the projection of the fifth ring-shaped structure intersects the projection of the first data line, the projection of the sixth ring-shaped structure intersects the projection of the first power signal line, the projection of the seventh ring-shaped structure intersects the projection of the initialization signal line, and the projection of the eighth ring-shaped structure intersects the projection of the second data line.

[0126] Optionally, along the first direction, the length of the first ring-shaped structure is La1, the length of the second ring-shaped structure is La2, the length of the third ring-shaped structure is La3, and the length of the fourth ring-shaped structure is La4.

[0127] Along the first direction, the length of the fifth ring-shaped structure is La5, the length of the sixth ring-shaped structure is La6, the length of the seventh ring-shaped structure is La7, and the length of the eighth ring-shaped structure is La8.

[0128] Along the second direction, the width of the first ring-shaped structure is Wa1, the width of the second ring-shaped structure is Wa2, the width of the third ring-shaped structure is Wa3, and the width of the fourth ring-shaped structure is Wa4.

[0129] Along the second direction, the width of the fifth ring-shaped structure is Wa5, the width of the sixth ring-shaped structure is Wa6, the width of the seventh ring-shaped structure is Wa7, and the width of the eighth ring-shaped structure is Wa8.

[0130] The display panel meets at least one of the following criteria: La1 = La5 and Wa1 = Wa5; or La2 = La6 and Wa2 = Wa6; or La3 = La7 and Wa3 = Wa7; or La4 = La8 and Wa4.

[0131] Optionally, both the first power signal line and the initialization signal line extend along the second direction.

[0132] The first sub-scanning line further includes the second ring-shaped structure, the third ring-shaped structure, and the fourth ring-shaped structure.

[0133] In the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure intersects the projection of the first data line, the projection of the second ring-shaped structure intersects the projection of the first power signal line, the projection of the third ring-shaped structure intersects the projection of the initialization signal line, and the projection of the fourth ring-shaped structure intersects the projection of the second data line.

[0134] In the first region, the line width of the second data line is W41, and in the second region, the line width of the second data line is W42.

[0135] The display panel satisfies |W11 - W12| + |W41 - W42| ≠ 0.

[0136] Optionally, the display panel fulfills |(W31 - W32) - (W21 - W22)1 > |(W11 - W12) - (W41 - W42)|.

[0137] Optionally, the light-emitting color of the first light-emitting element is red, the light-emitting color of the second light-emitting element is green, and the light-emitting color of the third light-emitting element is blue.

[0138] Alternatively, the light-emitting color of the first light-emitting element is red, the light-emitting color of the second light-emitting element is blue, and the light-emitting color of the third light-emitting element is green.

[0139] Alternatively, the light-emitting color of the first light-emitting element is green, the light-emitting color of the second light-emitting element is blue, and the light-emitting color of the third light-emitting element is red.

[0140] Optionally, the light-emitting color of the first light-emitting element is red, the light-emitting color of the second light-emitting element is green, the light-emitting color of the third light-emitting element is blue, and the light-emitting color of the fourth light-emitting element is white.

[0141] Alternatively, the light-emitting color of the first light-emitting element is red, the light-emitting color of the second light-emitting element is blue, the light-emitting color of the third light-emitting element is green, and the light-emitting color of the fourth light-emitting element is white.

[0142] Alternatively, the light-emitting color of the first light-emitting element is red, the light-emitting color of the second light-emitting element is white, the light-emitting color of the third light-emitting element is green, and the light-emitting color of the fourth light-emitting element is blue.

[0143] Alternatively, the light-emitting color of the first light-emitting element is blue, the light-emitting color of the second light-emitting element is white, the light-emitting color of the third light-emitting element is red, and the light-emitting color of the fourth light-emitting element is green.

[0144] Alternatively, the light-emitting color of the first light-emitting element is green, the light-emitting color of the second light-emitting element is white, the light-emitting color of the third light-emitting element is red, and the light-emitting color of the fourth light-emitting element is blue.

[0145] Alternatively, the light-emitting color of the first light-emitting element is green, the light-emitting color of the second light-emitting element is blue, the light-emitting color of the third light-emitting element is red, and the light-emitting color of the fourth light-emitting element is white.

[0146] Optionally, the scanning lines may also include a second scanning line, with the first scanning line being connected to the first pixel circuit and the second scanning line being connected to the second pixel circuit.

[0147] Alternatively, the sampling lines also include a second sampling line. The second sampling line includes a third sub-sampling line and a fourth sub-sampling line. The third sub-sampling line is connected to the first pixel circuit, and the fourth sub-sampling line is connected to the second pixel circuit.

[0148] Optionally, the pixel circuit includes a first transistor and a second transistor.

[0149] The first scanning line is connected to the first transistor.

[0150] The second scanning line is connected to the second transistor.

[0151] Optionally, the sub-pixel rows can also include a third sub-pixel row. This third sub-pixel row comprises a third pixel circuit and a third light-emitting element. The light-emitting colors of the first, second, and third light-emitting elements are different.

[0152] The first data line is connected to the third pixel circuit.

[0153] The first sampling line includes a fifth sub-sampling line, and the fifth sub-sampling line is connected to the third pixel circuit.

[0154] Optionally, the sub-pixel rows can also include a fourth sub-pixel row. This fourth sub-pixel row comprises a fourth pixel circuit and a fourth light-emitting element. The light-emitting colors of the first, second, third, and fourth light-emitting elements are different.

[0155] The first data line is connected to the fourth pixel circuit.

[0156] The first sampling line includes a sixth sub-sampling line, and the sixth sub-sampling line is connected to the fourth pixel circuit.

[0157] Optionally, the pixel circuit includes at least a first transistor, a second transistor, a third transistor and a first capacitor.

[0158] The first transistor is connected between the data line and a gate of the third transistor.

[0159] The second transistor is connected between the initialization signal line and the light-emitting element.

[0160] The third transistor is connected between the first power signal line and the light-emitting element.

[0161] The first capacitor is connected between the gate of the third transistor and the light-emitting element, or the first capacitor is connected between the first power signal line and the gate of the third transistor.

[0162] One gate of the first transistor is connected to the first scanning line.

[0163] Alternatively, a gate of the second transistor is connected to the first scanning line.

[0164] Optionally, the pixel circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor.

[0165] The sixth transistor, the third transistor and the seventh transistor are connected in series between the first power signal line and the light-emitting element.

[0166] The first transistor is connected between the data line and the first electrode of the third transistor.

[0167] The second transistor is connected between the initialization signal line and the light-emitting element.

[0168] The fourth transistor is connected to a gate of the third transistor.

[0169] The fifth transistor is connected between a second electrode of the third transistor and the gate of the third transistor.

[0170] The first capacitor is connected between the gate of the third transistor and the first power signal line, or the first capacitor is connected between the gate of the third transistor and the light-emitting element.

[0171] One gate of the first transistor is connected to the first scanning line.

[0172] In a second aspect, embodiments of the present innovation further provide a display device comprising the display panel described in the first aspect.

[0173] In the technical solution of this innovation, a first data line is arranged in the display panel. This first data line is connected to a first pixel circuit in the first sub-pixel row and to a second pixel circuit in the second sub-pixel row. Additionally, a first scanning line is provided. This scanning line comprises a first sub-scan line and a second sub-scan line. The first sub-scan line is connected to the first pixel circuit in the first sub-pixel row, and the second sub-scan line is connected to the second pixel circuit in the second sub-pixel row. This implements a dual-gate line control technology.Furthermore, if at least one of a first power signal line and an initialization signal line is arranged such that it extends along a second direction in the same way as the first data line, at least one of these signal lines will have different line widths in different regions along the second direction, namely in a first region and a second region. This allows the space saved in the row direction by the dual-gate line control technology to be utilized. In addition, based on actual requirements such as the spatial arrangement, the line widths of at least some of the signal lines extending along the column direction can be adaptively increased.On the one hand, this design reduces the impedance of these signal lines, preventing excessive voltage drop during signal transmission. Such a drop would otherwise cause differences in the data, power, and initialization signals received by different sub-pixel rows, thus impairing display accuracy and uniformity. On the other hand, this design prevents excessive width of the signal lines extending along the column direction from interfering with other components or signal lines, thereby balancing the overall spatial arrangement within the panel and achieving efficient use of space. To some extent, this design also contributes to improving the display resolution of the panel.Furthermore, a locally increased line width design can reduce the risk of breaks that can occur due to height differences when these signal lines overlap with other signal lines, thereby ensuring normal signal transmission and preventing display deviations in the display panel. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic representation of the structure of a display panel from the state of the art. Fig. 2 and Fig. Figure 3 shows schematic representations of the structures of two display panels according to one embodiment of the present innovation. Fig. Figure 4 is a schematic representation of the structure of a pixel circuit in which Fig. 2 or Fig. 3 display panels shown. Fig. 5 is a control timing diagram of the in Fig. 4 pixel circuits shown. Fig. 6 and Fig. Figure 7 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. 8 and Fig. Figure 9 shows schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. 10 and Fig. Figure 11 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. Figure 12 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. Figure 13 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. 14 and Fig. Figure 15 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. 16 and Fig. Figures 17 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. 18 and Fig. Figure 19 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. Figure 20 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. Figure 21 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. 22 and Fig. Figures 23 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. Fig. Figure 24 is a schematic representation of the structure of another pixel circuit according to an embodiment of the present innovation. Fig. 25 is a control timing diagram of the in Fig. 24 pixel circuits shown. Fig. 26 and Fig. Figure 27 are schematic representations of the structures of two further pixel circuits according to an embodiment of the present innovation. Fig. Figure 28 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. Figure 29 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. Figure 30 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. Fig. Figure 31 is a schematic representation of the structure of a display device according to an embodiment of the present innovation. DETAILED DESCRIPTION

[0174] The present innovation is described in detail below with reference to the drawings and embodiments. It should be understood that the embodiments described herein serve only for illustration and not to limit the present innovation. Furthermore, it should be noted that, for the sake of clarity, only some, but not all, of the structures relating to the present innovation are shown in the drawings.

[0175] The terms used in the embodiments of the present innovation serve only to describe the embodiments and not to limit the present innovation. It should be noted that positional designations such as "above," "below," "left," and "right" in the embodiments of the present innovation are described from the perspectives shown in the drawings and must not be interpreted as restrictive. Likewise, it should be understood in context that an element formed "on" or "under" another element can be formed not only directly "on" or "under" the other element, but also indirectly via an intervening element. Terms such as "first" and "second" serve only to distinguish between different components and do not indicate any order, number, or importance.For the person skilled in the art, the specific meanings of the aforementioned terms can be understood within the context of the present innovation based on the respective technical circumstances.

[0176] As used herein, the term "comprise" and its variations are to be understood as non-exhaustive, i.e., "including but not limited to". The term "based on" means "at least partially based on". The term "an embodiment" means "at least one embodiment".

[0177] It should be noted that concepts such as "first" and "second" are used in the present innovation to distinguish corresponding content from one another and are not intended to establish order or dependency.

[0178] It should be noted that terms such as "one" and "several" are not restrictive but explanatory in the present innovation and should be understood by those skilled in the art as "at least one" unless the context indicates otherwise.

[0179] Fig. Figure 1 is a schematic representation of the structure of a prior art display panel. With reference to Fig. The display panel comprises a display region and a non-display region. Within the display region, several sub-pixel rows 10 are arranged. Several adjacent sub-pixel rows 10 of different colors emit light at specific brightness levels to achieve color mixing and complete the display of a pixel unit. Several pixel units then work together to form a complete image display. Specifically, a sub-pixel row 10 comprises a pixel circuit 11 and a light-emitting element 12. Furthermore, several signal lines are arranged within the display region, including data lines 20. The data lines 20 supply data signals ...

[0180] In the prior art, however, the data lines 20 running along a column direction are arranged in a one-to-one mapping with sub-pixel columns, meaning that a data line 20 is connected to a column of sub-pixels 10 and delivers data signals 'Data' to each sub-pixel 10 in that column. The scan lines 30 running along a row direction are arranged in a one-to-one mapping with sub-pixel rows, meaning that a scan line 30 is connected to a row of sub-pixels 10 and delivers scan signals 'Scan1' to each sub-pixel 10 in the row. When a scanning signal Scan1 is transmitted to the corresponding sub-pixel row via a specific scanning line 30, the data lines 20 synchronously supply data signals Data to the sub-pixels 10 connected to them in this row, thereby achieving the control and light generation of the sub-pixels 10 in this row.If scanning signals Scan1 are transmitted line by line via the respective scanning lines 30 to the corresponding sub-pixel rows, and data signals Data are simultaneously supplied via the data lines 20, the control and light generation of the sub-pixels 10 of each row can be achieved, thus enabling the display of a complete image. Furthermore, the normal operation of the pixel circuits 11 also requires power signal lines and the like. In some solutions, certain signal lines, such as the first power signal line 41 and the initialization signal line 50, are designed to extend along the column direction. This design necessitates the parallel arrangement of more than one column-direction-related signal line between sub-pixels 10.Since signal lines in the column direction are usually relatively wide, the distance between the sub-pixels 10 becomes excessively large, so that fewer sub-pixels 10 can be arranged in the same space in the row direction, which reduces the resolution of the display panel to some extent.

[0181] Taking into account the aforementioned problems, embodiments of the present innovation provide a display panel. The display panel comprises sub-pixel arrays, scanning lines, and data lines. Each sub-pixel array includes a pixel circuit and a light-emitting element. The scanning lines are connected to the pixel circuits and extend along a first direction. The data lines are connected to the pixel circuits and extend along a second direction. The first direction intersects the second direction. The sub-pixel arrays comprise at least one first sub-pixel array and one second sub-pixel array. The first sub-pixel array comprises a first pixel circuit and a first light-emitting element. The second sub-pixel array comprises a second pixel circuit and a second light-emitting element.The light-emitting color of the first light-emitting element and the light-emitting color of the second light-emitting element are different.

[0182] The data lines comprise a first data line. The first data line is connected to the first pixel circuit and also to the second pixel circuit. The sample lines comprise a first sample line. The first sample line comprises a first sub-sample line and a second sub-sample line. The first sub-sample line is connected to the first pixel circuit, and the second sub-sample line is connected to the second pixel circuit.

[0183] The first direction can be understood as the row direction, and the second direction as the column direction. The data lines extend along the column direction, and the sampling lines extend along the row direction. In embodiments of the present innovation, the data lines are configured to include a first data line. The first data line is separately connected to the first pixel circuit in the first sub-pixel row and the second pixel circuit in the second sub-pixel row. Essentially, one data line is simultaneously connected to two sub-pixel rows of different light-emitting colors. These two sub-pixel rows can be understood as two sub-pixel rows arranged along the first direction, i.e., the row direction. The first data line supplies data signals to the two sub-pixel rows in the same row.Assuming that these two sub-pixel rows must emit light with a predetermined brightness, meaning that these two sub-pixel rows must each receive different data signals, different data signals can be provided via this data line with a time offset. Furthermore, the sampling lines are configured to include a first sampling line. The first sampling line comprises a first sub-sampling line and a second sub-sampling line. The first sub-sampling line is connected to the first pixel circuit of the first sub-pixel row of the two sub-pixel rows, and the second sub-sampling line is connected to the second pixel circuit of the second sub-pixel row of the two sub-pixel rows. In other words, the two sub-pixel rows that receive data signals from the same data line are supplied with sampling signals via two separate sub-sampling lines.When the first sub-scan line supplies a scanning signal to the first pixel circuit, the first data line can supply a corresponding data signal to the first pixel circuit, causing the first pixel circuit to illuminate. Similarly, when the second sub-scan line supplies a scanning signal to the second pixel circuit, the first data line can supply a corresponding data signal to the second pixel circuit, causing the second pixel circuit to illuminate. In this way, the first data line supplies different data signals at different times, controlling the light emission of the first and second sub-pixel rows accordingly. In summary, the key feature of this embodiment is that the pixel circuits of the two sub-pixel rows, which are connected to the same data line, are connected to two separate sub-scan lines.Specifically, the sub-scan lines are connected to the gates of the data write transistors, which are responsible for writing the data signals to the pixel circuits. Therefore, the sub-scan lines can also be referred to as gate lines. Essentially, the embodiments of this innovation employ a dual-gate line driving (DGLD) technology.

[0184] The display panel further includes a first power signal line and an initialization signal line. The first power signal line is connected to the pixel circuits, and the initialization signal line is also connected to the pixel circuits. The display panel comprises a first region and a second region arranged along the second direction. In the first region, the line width of the first data line is W11. In the second region, the line width of the first data line is W12. The display panel satisfies at least one of the following conditions:

[0185] The first power signal line extends along the second direction. In the first region, the linewidth of the first power signal line is W21. In the second region, the linewidth of the first power signal line is W22, where |W11 - W121 + |W21 - W22| ≠ 0. Alternatively, the initialization signal line extends along the second direction. In the first region, the linewidth of the initialization signal line is W31. In the second region, the linewidth of the initialization signal line is W32, where |W11 - W12| + |W31 - W32| ≠ 0. Alternatively, both the first power signal line and the initialization signal line extend along the second direction. In the first region, the linewidth of the first power signal line is W21, and the linewidth of the initialization signal line is W31.In the second region, the line width of the first power signal line is W22 and the line width of the initialization signal line is W32, where |W11 - W12|+ |W21 - W22| + |W31 - W32| ≠ 0.

[0186] As is known to those skilled in the art, the pixel circuits of the display panel require, in addition to sampling and data signals, an external power supply and a reset of the pixel circuits before each displayed image. This means that a connection to the first power signal line and the initialization signal line is necessary. The first power signal line is responsible for providing a power signal to generate a drive current that excites the light-emitting element to emit light. The initialization signal line provides an initialization signal to reset the circuit. In some technical solutions, the first power signal line and the initialization signal line are typically designed to run parallel to the first data line, that is, they extend along the second direction, for example, along the column direction.Based on this, and considering that data signals, power signals, and initialization signals influence the drive current generated by the pixel circuits to varying degrees, which in turn affects the light-emitting brightness of the light-emitting elements and causes deviations between actual and specified brightness, which in turn impair the display quality, it is fundamentally necessary to design the line width of each signal line extending along the column direction to be as large as possible in order to reduce the impedance on the signal lines and improve the signal transmission quality.

[0187] In contrast to the prior art, the embodiments of the present innovation employ a dual-gate line-driving technology in which two sub-pixel rows in the same row are connected by a single data line. This design eliminates the need for half the data lines and creates additional space in the row direction. As a result, the line widths of at least some of the signal lines extending along the column direction can be appropriately increased in the row direction.Based on this, in order to avoid mutual interference with components of the panel's pixel circuits, other signal lines, and the like, it is necessary to appropriately increase the line width of the signal lines extending along the column direction at different positions along the column direction, so that these signal lines have an appropriate spatial allocation to the components and other signal lines in the panel, and thus a balance between impedance optimization and spatial allocation is achieved.In other words, based on the dual-gate line-driving technology described above, the embodiments of the present innovation incorporate an appropriate optimization design for the line widths of at least some of the signal lines extending along the second direction, for example along the column direction, at different positions along the column direction, based on the signal transmission quality and the spatial arrangement in the panel.

[0188] Specifically, two distinct regions can exist along the column direction of the display panel: the first region and the second region. Depending on various factors, the first and second regions have different requirements for the line widths of the signal lines extending along the column direction. To simplify understanding, for example, in areas along the column direction where pixel circuitry and other signal lines are located, the margin for increasing the line width may be relatively small. In areas along the column direction where no pixel circuitry or other signal lines are located, the margin for increasing the line width is relatively large. Therefore, different line widths can be set in areas with and without pixel circuitry and other signal lines.As another example, in areas where signal lines overlap, height differences at the overlapping locations can pose a risk of signal line breaks. Therefore, different line widths can be set in overlapping and non-overlapping sections of the signal lines to prevent breaks. Accordingly, assuming the first data line is a signal line extending along the column direction, for a solution where the first power signal line is also arranged along the column direction, consideration can be given to configuring at least one of these two signal lines to have different line widths in the first and second regions. This means that the difference in line widths between the two regions is non-zero, i.e., |W11 - W12| + |W21 - W22| ≠ 0.Based on the assumption that the first data line is a signal line extending along the column direction, for a solution in which the initialization signal line is also arranged along the column direction, consideration can be given to configuring at least one of these two signal lines such that it has different line widths in the first region and the second region, meaning that the difference in line widths in the two regions is not equal to zero, i.e., |W11 - W12| + |W31 - W32| ≠ 0.Based on the assumption that the first data line is a signal line extending along the column direction, for a solution in which both the first power signal line and the initialization signal line are arranged along the column direction, consideration can be given to configuring at least one of these three signal lines to have different line widths in the first region and the second region, meaning that the difference in line widths in the two regions is not zero, i.e., |W11 - W12| + |W21 - W22| + |W31 - W32| ≠ 0.

[0189] In the aforementioned technical solution, a first data line is arranged in the display panel. This first data line is connected to a first pixel circuit in the first sub-pixel row and to a second pixel circuit in the second sub-pixel row. Additionally, a first sampling line is provided. This first sampling line comprises a first sub-sampling line and a second sub-sampling line. The first sub-sampling line is connected to the first pixel circuit in the first sub-pixel row, and the second sub-sampling line is connected to the second pixel circuit in the second sub-pixel row. In this way, a dual-gate line control technology is implemented.Furthermore, if at least one of a first power signal line and an initialization signal line is arranged such that it extends along a second direction in the same way as the first data line, at least one of these signal lines can be configured to have different line widths in different regions along the second direction, namely in a first region and a second region. This allows the space saved in the row direction by the dual-gate line control technology to be utilized. In addition, based on actual requirements, such as the spatial arrangement, the line widths of at least some of the signal lines extending along the column direction can be adaptively increased.On the one hand, this design reduces the impedance of these signal lines, preventing excessive voltage drop during signal transmission. Such a drop would otherwise cause differences in the data, power, and initialization signals received by different sub-pixel rows, thus preventing any impairment of display accuracy and uniformity. On the other hand, this design prevents excessive width of the signal lines extending along the column direction from interfering with other components or signal lines, thereby balancing the overall spatial arrangement within the panel and achieving efficient use of space. To some extent, this design also contributes to improving the display panel's resolution.Furthermore, a locally increased line width design can reduce the risk of breaks that can occur due to height differences when these signal lines overlap with other signal lines, thus ensuring normal signal transmission and preventing display deviations in the display panel.

[0190] The foregoing constitutes the core of the present innovation, and the technical solutions in the embodiments of the present innovation are clearly and completely described below in conjunction with the drawings of the embodiments of the present innovation. Based on the embodiments of the present innovation, all further embodiments that a person skilled in the art obtains without inventive step are within the scope of protection of the present innovation.

[0191] Fig. 2 and Fig. Figure 3 shows schematic representations of the structures of two display panels according to one embodiment of the present innovation. Fig. Figure 4 is a schematic representation of the structure of a pixel circuit in which Fig. 2 or Fig. 3 display panels shown. Fig. 5 is a control timing diagram of the in Fig. 4 pixel circuits shown. With reference to Fig. 2 to Fig. The display panel comprises sub-pixel rows 10, scanning lines 30, and data lines 20. Sub-pixel row 10 includes a pixel circuit 11 and a light-emitting element 12. The scanning lines 30 are connected to the pixel circuits 11 and extend along a first direction X. The data lines 20 are connected to the pixel circuits 11 and extend along a second direction Y. The first direction X intersects the second direction Y. The sub-pixel rows 10 include at least a first sub-pixel row 101 and a second sub-pixel row 102. The first sub-pixel row 101 includes a first pixel circuit 111 and a first light-emitting element 121. The second sub-pixel row 102 includes a second pixel circuit 112 and a second light-emitting element 121. light-emitting element 122. The light-emitting color of the first light-emitting element 121 and the light-emitting color of the second light-emitting element 122 are different.The data lines 20 comprise a first data line 21. The first data line 21 is connected to the first pixel circuit 111 and also to the second pixel circuit 112. The sampling lines 30 comprise a first sampling line 31. The first sampling line 31 comprises a first sub-sampling line 311 and a second sub-sampling line 312. The first sub-sampling line 311 is connected to the first pixel circuit 111, and the second sub-sampling line 312 is connected to the second pixel circuit 112.

[0192] First, the control process and the operating principle of the display panel provided by the embodiments of the present innovation will be illustrated by way of example using the pixel circuit in the Fig. The 4 sub-pixel rows shown are explained. Fig. The pixel circuit shown comprises a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1. The first transistor T1 is connected between the data line 20 and the gate of the third transistor T3. The second transistor T2 is connected between the initialization signal line 50 and the light-emitting element 12. The third transistor T3 is connected between the first power signal line 41 and the light-emitting element 12. The first capacitor C1 is connected between the gate of the third transistor T3 and the light-emitting element 12. The gates of the first transistor T1 and the second transistor T2 are both connected to the first scanning line 31. In addition to the first power signal line 41, the pixel circuit also requires a second power signal line (not shown in the diagram).The light-emitting element 12 is connected between the third transistor T3 and the second power signal line.

[0193] This pixel circuit is essentially a 3T1C pixel circuit, consisting of three transistors and a capacitor. The 3T1C circuit is an external compensation pixel circuit. The actual drive process can include a display mode. In this mode, the threshold voltage of the third transistor, T3 (the drive transistor), can be detected in advance to compensate for the data signal. The complemented data signal is then written to the pixel circuit, thus compensating for the influence of the drive transistor's threshold voltage during the drive and light emission process. Specifically, the display mode includes a data write phase, ta, and a light emission phase, tb. The data write phase, ta, is simultaneously an initialization phase, tc. During both the data write phase, ta, and the initialization phase, tc, the first transistor, T1, is switched on.According to the known threshold voltage Vth, the data signal Data is compensated. That is, the complemented data voltage Vdata - Vth is applied to the gate of the third transistor T3, i.e., the first node N1. Simultaneously, the initialization signal Vref1 is applied to the anode of the light-emitting element 12, i.e., the second node N2, to reset it. During the light emission phase tb, both the first transistor T1 and the second transistor T2 are switched off. In this case, the third transistor T3 is switched on and provides a drive current to the light-emitting element 12, causing it to emit light. The drive current is determined by the gate-source voltage of the drive transistor, i.e., the third transistor T3, and the threshold voltage of the drive transistor.Thus, the threshold voltage is eliminated from the drive current equation, meaning that by compensating the threshold voltage Vth during data writing, the actual drive current is prevented from being affected by the threshold voltage. The gates of the first transistor T1 and the second transistor T2 receive the Scan1 sampling signal, provided by the first sampling line 31, to establish an on or off state. The source of the first transistor T1 receives the Data signal, provided by the first data line 21, to initiate the writing of the Data signal.

[0194] From the pixel control process in the example above, it is evident that the control process of the sub-pixel array requires that the first data line 21 provide the data signal Data and the first scan line 31 provide the scan signal Scan1 in order to switch on the first transistor T1 in compensation mode and in display mode, thus enabling initialization, data writing, and the like. Based on this, the embodiments of the present innovation, with reference to Fig. 2 and Fig. 3 Two sub-pixel rows 10, arranged along the first direction X, namely the first sub-pixel row 101 and the second sub-pixel row 102, are connected to the same first data line 21, which extends along the second direction Y. Furthermore, these two sub-pixel rows 10 are configured to be connected to two separate sub-scan lines, namely the first sub-scan line 311 and the second sub-scan line 312. In a first phase, the first data line 21 can supply a data signal Data to the first sub-pixel row 101, while the first sub-scan line 311 supplies a scan signal Scan1 to the first sub-pixel row 101. Under the control of the scanning signal Scan1, the first pixel circuit 111 writes the data signal Data in the first sub-pixel row 101 to realize the control and light emission of the first light-emitting element 121.In a second phase, the first data line 21 can similarly supply a data signal Data to the second sub-pixel row 102, while the second sub-scan line 312 supplies a scanning signal Scan1 to the second sub-pixel row 102. Controlled by the scanning signal Scan1, the second pixel circuit 112 in the second sub-pixel row 102 writes the data signal Data to control and emit light from the second light-emitting element 122. In this way, one data line 20 and two sub-scan lines can achieve the time-shifted control and light emission of two sub-pixel rows 10 in two phases; that is, the dual-gate line control scheme is implemented.

[0195] It should be noted that the in Fig. The pixel circuit shown in Figure 4 is merely one example of the present innovation. In this example, the first transistor T1 and the second transistor T2 are connected to the same first scanning line 31 and receive the same scanning signal Scan1, thus achieving synchronous power-on control. This design can reduce the number of scanning lines, simplify spatial arrangement, and improve space utilization. Other suitable pixel circuits, which are not described in detail here, can optionally be used in other embodiments of the present innovation.

[0196] Based on the dual-gate-line control scheme described above, and with reference to Fig. 4 and Fig. As can be seen in Figure 5, the control process of the pixel circuit also requires the cooperation of power signals and the initialization signal Vrefl. That is, it is necessary to provide a first power signal PVDD via the first power signal line 41 and an initialization signal Vrefl via the initialization signal line 50. The display panel further comprises the first power signal line 41 and the initialization signal line 50. The first power signal line 41 is connected to the pixel circuits 11, and the initialization signal line 50 is connected to the pixel circuits 11. Based on this, in an optional embodiment, with further reference to Fig. 2. The first power signal line 41 runs along the second direction Y. The display panel comprises a first region A1 and a second region A2, arranged along the second direction Y. In the first region A1, the line width of the first data line is 21W11. In the second region A2, the line width of the first data line is 21W12. In the first region A1, the line width of the first power signal line is 41W21. In the second region A2, the line width of the first power signal line is 41W22. |W11 - W12| + |W21 - W22| ≠ 0.

[0197] In this embodiment, both the first data line 21 and the first power signal line 41 are arranged such that they extend along the second direction Y, namely the column direction. These two signal lines can be arranged between two different adjacent sub-pixel rows 10. In this way, these two signal lines can be designed with relatively large linewidths to reduce their respective impedance and avoid excessive voltage drop during signal transmission.This ensures that each sub-pixel row 10 connected to the first data line 21 and arranged along the second direction Y, namely the column direction, can receive accurate data signals. It also ensures that each sub-pixel row 10 connected to the first power signal line 41 and arranged along the second direction Y, namely the column direction, can receive power signals with relatively small differences. In this way, these sub-pixel rows 10 can emit light at the specified brightness, thus avoiding problems of inaccurate and uneven display. Furthermore, based on various signal line design requirements, the first data line 21 and / or the first power signal line 41 must be designed with different line widths in different regions along the column direction of the display panel.

[0198] In an optional embodiment, the display panel comprises sub-pixel rows. Each sub-pixel row comprises multiple sub-pixel rows 10 arranged along the first direction X. Along the second direction Y, a first gap is provided between the pixel circuits 11 of adjacent sub-pixel rows. The first region A1 overlaps at least partially with this first gap. The second region A2 overlaps at least partially with the pixel circuits 11 of the sub-pixel rows 10 within the sub-pixel row.

[0199] In this embodiment, the first region A1 can be understood as the gap region between the pixel circuits 11 in adjacent sub-pixel rows, and the second region A2 can be understood as the region in which the pixel circuits 11 are located in the sub-pixel rows. Based on the spatial allocation design requirements, the magnification of the first data line 21 and / or the first power signal line 41 can be appropriately reduced for the region in which the pixel circuits 11 are located in the sub-pixel rows. In the gap region between the pixel circuits 11 in adjacent sub-pixel rows, the first data line 21 and the first power signal line 41 can be widened to a greater degree.In other words, at least one of the first data line 21 and the first power signal line 41 must be designed such that they have different line widths in the first region A1 and the second region A2, where the magnitude of the difference in the line width of the first data line 21 in these two regions |W11 - W12| ≠ 0, or the magnitude of the difference in the line width of the first power signal line 41 in these two regions |W21 - W22| ≠ 0. Therefore, |W11 - W12| + |W21 - W22| ≠ 0. Consequently, in the region occupied by the pixel circuits 11, the relatively narrow first data line 21 and first power signal line 41 can adequately avoid components and other signal lines, prevent parasitic capacitances with other signal lines, capacitor plates, and the like, and also reserve space for the arrangement of other components and signal lines.In the gap region between the pixel circuits 11, the relatively wide first data line 21 and first power signal line 41 can have larger line widths and a lower impedance, thereby reducing the voltage drop occurring on these signal lines during signal transmission and improving the signal transmission quality.

[0200] With continued reference to Fig. In a further optional embodiment, the initialization signal line 50 can also optionally be arranged such that it extends along the second direction Y. In the first region A1, the line width of the initialization signal line 50 is W31. In the second region A2, the line width of the initialization signal line 50 is W32, where |W11 - W12| + |W31 - W32| ≠ 0.

[0201] Likewise, in this embodiment, both the first data line 21 and the initialization signal line 50 are arranged such that they extend along the second direction Y, namely the column direction. These two signal lines can be arranged between two different adjacent sub-pixel rows 10. In this way, these two signal lines can be designed with relatively large line widths in order to reduce their respective impedance and avoid excessive voltage drop during signal transmission.This ensures that each sub-pixel row 10 connected to the first data line 21 and arranged along the second direction Y, namely the column direction, can receive accurate data signals, and it ensures that each sub-pixel row 10 connected to the initialization signal line 50 and arranged along the second direction Y, namely the column direction, can receive initialization signals with relatively small differences. In this way, these sub-pixel rows 10 can emit light at the specified brightness, thus avoiding problems of inaccurate and uneven display.

[0202] Furthermore, based on the spatial allocation requirements for the region where the pixel circuits are located in the sub-pixel rows, the degree of widening of the first data line 21 and / or the initialization signal line 50 can be appropriately reduced. In the gap region between the pixel circuits in adjacent sub-pixel rows, the first data line 21 and the initialization signal line 50 can be widened to a greater degree. In other words, at least one of the first data line 21 and the initialization signal line 50 must be designed to have different line widths in the first region A1 and the second region A2, where the magnitude of the difference in the line width of the first data line 21 in these two regions |W11 - W12| ≠ 0, or the magnitude of the difference in the line width of the initialization signal line 50 in these two regions |W31 - W32| ≠ 0.Therefore, |W11 - W12| + |W31 - W32| ≠ 0. Consequently, in the region occupied by the pixel circuits, the relatively narrow first data line 21 and initialization signal line 50 can adequately avoid components and other signal lines, prevent parasitic capacitances with other signal lines, capacitor plates, and the like, and also reserve space for the arrangement of other components and signal lines. In the gap region between the pixel circuits, the relatively wide first data line 21 and initialization signal line 50 can have larger line widths and a lower impedance, thereby reducing the voltage drop occurring on these signal lines during signal transmission and improving the signal transmission quality.

[0203] With continued reference to Fig. In a further optional embodiment, both the first power signal line 41 and the initialization signal line 50 can optionally be arranged such that they extend along the second direction Y. In the first region A1, the line width of the first power signal line 41 is W21 and the line width of the initialization signal line 50 is W31. In the second region A2, the line width of the first power signal line 41 is W22 and the line width of the initialization signal line 50 is W32, where |W11 - W12| + W21 - W22| + |W31 - W32| ≠ 0.

[0204] Likewise, in this embodiment, the first data line 21, the first power signal line 41, and the initialization signal line 50 are all arranged such that they extend along the second direction Y, namely the column direction. These three signal lines can be arranged between different adjacent sub-pixel rows 10. In this way, these three signal lines can be designed with relatively large line widths. Furthermore, based on the spatial allocation requirements for the region in which the pixel circuits are located in the sub-pixel rows, the magnification of at least one of the first data line 21, the first power signal line 41, and the initialization signal line 50 can be appropriately reduced. In the gap region between the pixel circuits in adjacent sub-pixel rows, these signal lines can be widened to a greater degree.Accordingly, the magnitude of the difference in the line width of the first data line 21 in these two regions |W11 - W12| ≠ 0. Alternatively, the magnitude of the difference in the line width of the first power signal line 41 in these two regions |W21 - W22| ≠ 0. Alternatively, the magnitude of the difference in the line width of the initialization signal line 50 in these two regions |W31 - W32| ≠ 0. Therefore, |W11 - W12| + |W21 - W22| + |W31 - W32| ≠ 0. The widening method for the three signal lines in this embodiment achieves the same or similar effects as those described above for two signal lines and will not be explained again in detail here.

[0205] With continued reference to Fig. 2 and Fig. In an optional embodiment, it may be specified that W11 > W12. In an optional embodiment, it may further be specified that W21 > W22.

[0206] These two embodiments essentially relate to the appropriate reduction of the magnification of the first data line 21 and the first power signal line 41 in the second region A2, namely in the region where the pixel circuits 11 are located in the sub-pixel rows, while in the first region A1, namely in the gap region between the pixel circuits 11 in adjacent sub-pixel rows, the first data line 21 and the first power signal line 41 are widened to a greater degree. Consequently, the line widths of the first data line 21 and the first power signal line 41 in the first region A1 are relatively large. This design allows the pixel circuits to be bypassed while simultaneously ensuring signal transmission quality and thus achieves a suitable spatial arrangement.

[0207] Fig. 6 and Fig. Figure 7 shows schematic representations of the structures of two further display panels according to an embodiment of the present innovation. With reference to Fig. 2, Fig. 3, Fig. 6 and Fig. In some embodiments, 7 may be specified that (W11 - W12) × (W21 - W22) ≥ 0.

[0208] (W11 - W12) × (W21 - W22) > 0, which is considered the situation in the Fig. 2 and Fig. 3 shown embodiments can be understood to mean that W11 > W12 and simultaneously W21 > W22. (W11 - W12) × (W21 - W22) = 0, which can be understood to mean that one of the first data line 21 and the first power signal line 41 has the same line width in the first region A1 and the second region A2, while the other signal line has different line widths. As exemplified in Fig. 6 and Fig. As shown in Figure 7, the line width of the first data line 21 can be set the same in the first region A1 and the second region A2, such that W11 - W12 = 0, while the first power signal line 41 has different line widths in the first region A1 and the second region A2. Thus, (W11 - W12) × (W21 - W22) = 0. In this embodiment, the line width of the first power signal line 41 is set larger in the first region A1 than in the second region A2, while the line width of the first data line 21 is the same in both regions. This is because the first power signal line 41 essentially delivers the first power signal to several sub-pixel rows 10 in the same column simultaneously.The larger the linewidth of the first power signal line 41, the lower the impedance and voltage drop, allowing the sub-pixel rows 10 in the same column to receive first power signals with smaller differences, resulting in better display uniformity. Therefore, when further defining the linewidth of the first power signal line 41 based on the spatial allocation in the first region A1, i.e., the gap region between pixel circuits 11 in the column direction, a relatively large linewidth can be set, while in the second region A2, i.e., the region where the pixel circuits 11 are located, a relatively narrow linewidth can be set to achieve adequate bypass. Thus, a balance between signal transmission quality and spatial allocation is achieved for the first power signal line 41.The first data line 21 typically delivers data signals to the sub-pixel rows 10 connected to it with a time delay, so its influence on display uniformity is relatively small. The need to set different line widths in the first region A1 and the second region A2 is also relatively low, so the same line width can be used.

[0209] With continued reference to Fig. 2 and Fig. In an optional embodiment, 3 may further specify that W21 - W22 > W11 - W12.

[0210] Similarly, the first power signal line 41 has a greater influence on display uniformity compared to the first data line 21. Therefore, when designing the line widths of the first data line 21 and the first power signal line 41, the line width of the first power signal line 41 can be chosen to be relatively large, and the difference in line widths between the first region A1 and the second region A2 can be relatively significant, resulting in a relatively large W21 - W22. The line width of the first data line 21 is relatively small, and although different settings can also be made between the first region A1 and the second region A2, the degree of differentiation is relatively low due to the already small line width, so W11 - W12 is relatively small. Thus, W21 - W22 > W11 - W12.In this case, both the first power signal line 41 and the first data line 21 can achieve adapted line widths as well as a differentiated line width design that adapts to the spatial allocation.

[0211] With continued reference to Fig. 2, Fig. 3, Fig. 6 and Fig. In an optional embodiment, it may be provided that in the first region A1 the distance between the first data line 21 and the first power signal line 41, which are adjacent to each other, is D11, and in the second region A2 the distance between the first data line 21 and the first power signal line 41, which are adjacent to each other, is D12, where D11 < D12.

[0212] First, the in Fig. 6 and Fig. The 7 examples shown are used. If the linewidth of the first data line 21 in the first region A1 and the second region A2 is the same, the distance between the first power signal line 41 and the first data line 21 is relatively small due to the relatively large linewidth of the first power signal line 41 in the first region A1. Since the linewidth of the first power signal line 41 is relatively small in the second region A2, the distance between the first power signal line 41 and the first data line 21 is relatively large. Thus, D11 < D12. In the Fig. 2 and Fig. In the three embodiments shown, the linewidth of the first data line 21 is relatively large in the first region A1 and relatively small in the second region A2. However, since the first power signal line 41 has a greater influence on the display uniformity, the difference in linewidths of the first data line 21 in the first region A1 can be chosen to be smaller than the difference in linewidths of the first power signal line 41 in the first region A2. Therefore, it can be understood that the distance between the first power signal line 41 and the first data line 21 in the first region A1 is still smaller than in the second region A2, i.e., D11 < D12. Likewise, in this case, both the first power signal line 41 and the first data line 21 can achieve adapted linewidths as well as a differentiated linewidth design that adapts to the spatial allocation.

[0213] Fig. 8 and Fig. Figure 9 shows schematic representations of the structures of two further display panels according to an embodiment of the present innovation. With reference to Fig. 8 and Fig. In the second region A2, the first data line 21 comprises a first winding section 211, and the first power signal line 41 comprises a second winding section 411. At least one first winding section 211 has the same winding direction as at least one second winding section 411, or at least one first winding section 211 has a winding direction opposite to that of a second winding section 411.

[0214] In the second region A2, a first winding section 211 is provided on the first data line 21, and a second winding section 411 is provided on the first power signal line 41 in the second region A2. This is mainly because the first region A1 and the second region A2 have different requirements for the arrangement positions of the signal lines. On the one hand, due to differences in the light emission efficiency of the light-emitting elements 12 and differences in the proportions required for color mixing, the areas of the light-emitting elements 12 in adjacent sub-pixel rows 10 can differ. If these two signal lines are arranged in the first region A1, it is necessary to bypass the light-emitting elements 12 as much as possible, which results in a non-equally spaced arrangement of these two signal lines in the first region A1.On the other hand, to prevent the first data line 21 or the first power signal line 41 from being located closer to the pixel circuit of one sub-pixel row 10 and further away from the pixel circuit of the other sub-pixel row 10—which would lead to obvious brightness differences between the two sub-pixel rows 10 after a longer cumulative operating time—it is necessary to arrange the two signal lines in the second region A2 so that they have a balanced distance with respect to the different sub-pixel rows 10 to be connected. In other words, the two signal lines must be arranged at equal intervals. Based on this, suitable winding positions must be designed when arranging the first data line 21 and the first power signal line 41.At the transition from the second region A2 to the first region A1, the first winding section 211 and the second winding section 411 must be provided to ensure that they pass through the gap between two adjacent pixel circuits in the row direction and are centered relative to these two pixel circuits. In this case, the first data line 21 and the first power signal line 41 can be connected uniformly to the pixel circuits to be connected, and differences in the provided signals, which would lead to display non-uniformity, are avoided. Furthermore, the influence of components in the sub-pixel rows on the signal lines can be reduced as much as possible, parasitic capacitances in the row and column directions can be avoided, and an appropriate design of the line width, position, and winding direction of the signal lines can be achieved.

[0215] With continued reference to Fig. 2 and Fig. In some embodiments, 3 may be specified that (W11 - W12) × (W31 - W32) ≥ 0.

[0216] (W11 - W12) × (W31 - W32) > 0, which is considered the situation in the Fig. 2 and Fig. 3 shown embodiments can be understood to mean that W11 > W12 and simultaneously W31 > W32. (W11 - W12) × (W31 - W32) = 0, which can be understood to mean that one of the first data lines 21 and the initialization signal line 50 has the same line width in the first region A1 and the second region A2, while the other signal line has different line widths. As exemplified in Fig. 6 and Fig. As shown in Figure 7, the line width of the first data line 21 can be set the same in the first region A1 and the second region A2, such that W11 - W12 = 0, while the initialization signal line 50 has different line widths in the first region A1 and the second region A2. Thus, (W11 - W12) × (W31 - W32) = 0. In this embodiment, the line width of the initialization signal line 50 is set larger in the first region A1 than in the second region A2, while the line width of the first data line 21 is the same in both regions. This is because the initialization signal line 50 essentially provides initialization signals to multiple sub-pixel rows 10 in the same column simultaneously.The larger the linewidth of the initialization signal line 50, the lower the impedance and voltage drop, allowing the sub-pixel rows 10 in the same column to receive initialization signals with smaller differences, resulting in better display uniformity. Therefore, when further designing the linewidth of the initialization signal line 50 based on the spatial allocation, a relatively large linewidth can be set in the first region A1, i.e., the gap region between pixel circuits in the column direction, while a relatively narrow linewidth can be set in the second region A2, i.e., the region where the pixel circuits are located, to achieve adequate bypass. Thus, a balance between signal transmission quality and spatial allocation is achieved for the initialization signal line 50.

[0217] With continued reference to Fig. 2 and Fig. In an optional embodiment, 3 may be specified that W31 > W32.

[0218] This embodiment essentially involves appropriately reducing the magnification of the initialization signal line 50 in the second region A2, namely the region where the pixel circuits 11 are located in the sub-pixel rows, while the initialization signal line 50 is widened to a greater degree in the first region A1, namely the gap region between the pixel circuits 11 in adjacent sub-pixel rows. Consequently, the line width of the initialization signal line 50 in the first region A1 is relatively large. This design allows the pixel circuits to be bypassed while simultaneously ensuring signal transmission quality and thus achieves a suitable spatial arrangement.

[0219] With continued reference to Fig. 2 and Fig. In an optional embodiment, 3 may further specify that W31 - W32 > W11 - W12.

[0220] Similarly, the initialization signal line 50 has a greater influence on display uniformity compared to the first data line 21. Therefore, when designing the line widths of the first data line 21 and the initialization signal line 50, the line width of the initialization signal line 50 can be chosen to be relatively large, and the difference in line widths between the first region A1 and the second region A2 can be relatively significant, resulting in a relatively large W31 - W32. The line width of the first data line 21 is relatively small, and although different settings can also be made between the first region A1 and the second region A2, the degree of differentiation is relatively low due to the already small line width, so W11 - W12 is relatively small. Therefore, W31 - W32 > W11 - W12.In this case, both the initialization signal line 50 and the first data line 21 can achieve adapted line widths as well as a differentiated line width design that adapts to the spatial allocation.

[0221] With continued reference to Fig. 2, Fig. 3, Fig. 6 and Fig. In an optional embodiment, it may be provided that in the first region A1 the distance between the first data line 21 and the initialization signal line 50, which are adjacent to each other, is D21, and in the second region A2 the distance between the first data line 21 and the initialization signal line 50, which are adjacent to each other, is D22, where D21 < D22.

[0222] Similarly, it applies that in the Fig. 6 and Fig. In the embodiments shown in Figure 7, the line width of the first data line 21 is the same in the first region A1 and the second region A2, while the line width of the initialization signal line 50 in the first region A1 is relatively large, so that the distance between the initialization signal line 50 and the first data line 21 is relatively small. Since the line width of the initialization signal line 50 is relatively small in the second region A2, the distance between the initialization signal line 50 and the first data line 21 is relatively large. Thus, D21 < D22. In the embodiments shown in Fig. 2 and Fig. In the three embodiments shown, the line width of the first data line 21 is relatively large in the first region A1 and relatively small in the second region A2. However, since the initialization signal line 50 has a greater influence on the display uniformity, the difference in line widths of the first data line 21 in the first region A1 can be chosen to be smaller than the difference in line widths of the initialization signal line 50 in the first region A1. Therefore, it can be understood that the distance between the initialization signal line 50 and the first data line 21 in the first region A1 is still smaller than in the second region A2, i.e., D21 < D22. Likewise, in this case, both the initialization signal line 50 and the first data line 21 can achieve adapted line widths as well as a differentiated line width design that adapts to the spatial allocation.

[0223] With continued reference to Fig. 8 and Fig. In the second region A2, the first data line 21 comprises a first winding section 211, and the initialization signal line 50 comprises a third winding section 501. The display panel fulfills at least one of the following characteristics: at least one first winding section 211 has the same winding direction as at least one third winding section 501, or at least one first winding section 211 has a winding direction opposite to that of a third winding section 501.

[0224] Similarly, when arranging the first data line 21 and the initialization signal line 50, suitable winding positions must be designed. At the transition from the second region A2 to the first region A1, the first winding section 211 and the third winding section 501 must be provided to ensure that they pass through the gap between two adjacent pixel circuits 11 in the row direction and are centered relative to these two pixel circuits 11. In this case, the first data line 21 and the initialization signal line 50 can be connected uniformly to the pixel circuits to be connected, and differences in the provided signals, which would lead to display non-uniformity, are avoided.Furthermore, the influence of components in the sub-pixel rows on the signal lines can be reduced as much as possible, parasitic capacitances in the row and column directions can be avoided, and an appropriate design of line width, position and winding direction can be achieved.

[0225] With continued reference to Fig. 3 and Fig. In some embodiments, it may be specified that (W21 - W22) × (W31 - W32) ≥ 0. In some embodiments, it may be specified that W31 - W32 > W21 - W22. In some embodiments, it may further be specified that |W21 - W31| + |W22 - W32| ≠ 0.

[0226] Based on the operating principle of the pixel circuits, the first power signal line 41 is compared with the initialization signal line 50. The initialization signal provided by the initialization signal line 50 influences the potential of the anode of the light-emitting element 12 during the light emission phase, which affects the brightness of the light-emitting element 12 to some extent. The first power signal PVDD provided by the first power signal line 41 directly determines the inrush current of the light-emitting element 12 during the light emission phase and therefore has a significantly stronger influence on the brightness of the light-emitting element 12.Therefore, in the actual design of these two signal lines, the linewidth of the first power signal line 41 must be chosen to be relatively large to ensure that the impedance and voltage drop on the first power signal line 41 are low, thus avoiding significant brightness differences in the sub-pixel rows 10 connected to the first power signal line 41 in the column direction and improving display uniformity. Therefore, when considering a differentiated linewidth design for the two signal lines in different regions, the first power signal line 41 is prioritized; that is, a larger linewidth is set in the first region A1 and a smaller linewidth in the second region A2. Furthermore, the first power signal line 41 can be designed with more pronounced linewidth differences compared to the initialization signal line 50.This means that in the first region A1, the linewidth of the first power signal line 41 is greater than that of the initialization signal line 50. Thus, the following can be achieved: (W21 - W22) × (W31 - W32) ≥ 0. Alternatively, W31 - W32 > W21 - W22. Alternatively, |W21 - W31| + |W22 - W32| ≠ 0. In this embodiment, both the first power signal line 41 and the initialization signal line 50 can achieve adapted linewidths as well as a differentiated linewidth design that adapts to the spatial allocation, which will not be described again here.

[0227] With continued reference to Fig. 3 and Fig. In some embodiments, it may be specified that (W11 - W12) × (W21 - W22) × (W31 - W32) ≥ 0. In some embodiments, it may be specified that W11 - W12 ≠ W21 - W22 ≠ W31 - W32. In some embodiments, it may further be specified that W11 - W12 < W21 - W22 < W31 - W32. In some embodiments, (W31 - W32) - (W21 - W22) > (W21 - W22) - (W11 - W12). In some embodiments, W21 ≥ W31 > W11 or W22 > W32 ≥ W12.

[0228] As described above, since the signals provided by the first data line 21, the first power signal line 41, and the initialization signal line 50 are different, their functions in the pixel circuit control process and their effects on the display effect also differ. Therefore, when widening the line widths of these three signal lines, the priority order should be as follows: first the first power signal line 41, then the initialization signal line 50, and finally the first data line 21. Specifically, the line widths of the first power signal line 41, the initialization signal line 50, and the first data line 21 should decrease sequentially, namely W21 > W31 > W11 or W22 > W32 > W12.Furthermore, taking into account that the first region A1 has a relatively larger space compared to the second region A2, the initialization signal line 50 and the first power signal line 41 can be designed with a relatively large linewidth so that they have the same linewidth in the first region A1, namely W21 = W31, so that the initialization signal line 50 can also have a relatively large linewidth in the first region A1 in order to fully utilize the space of the first region A1 and reduce the impedance of the initialization signal line 50.Furthermore, since the second region A2 has relatively less space compared to the first region A1, the initialization signal line 50 can be designed so that it has the same line width in the second region A2 as the first data line 21 with a relatively narrow line width, namely W32 = W12, so that the initialization signal line 50 also has a relatively narrow line width in the second region A2, thereby saving space in the second region A2, avoiding pixel circuits and preventing interference with components in the pixel circuits and the like.

[0229] Furthermore, if a differentiated linewidth design is implemented for these three signal lines in the first region A1 and the second region A2, at least one of the first data line 21, the first power signal line 41, and the initialization signal line 50 should be configured to have different linewidths in the first region A1 and the second region A2, namely (W11 - W12) × (W21 - W22) × (W31 - W32) ≥ 0 or W11 - W12 ≠ W21 - W22 ≠ W31 - W32. Additionally, the linewidth difference of the first data line 21, the first power signal line 41, and the initialization signal line 50 should increase sequentially in the first region A1 and the second region A2, namely W11 - W12 < W21 - W22 < W31 - W32.Furthermore, compared to the first data line 21, both the first power signal line 41 and the initialization signal line 50, since they each simultaneously deliver corresponding signals to several sub-pixel rows 10 arranged along the column direction, have a more similar effect on the display, and the line width requirements for these two signal lines should be relatively greater. Therefore, if different line widths are set in the first region A1 and the second region A2, the line width difference of the initialization signal line 50 is significantly larger than that of the first power signal line 41. In other words, if different line widths are set in the first region A1 and the second region A2, the line width differences between the first power signal line 41 and the first data line 21 are not pronounced.Thus, (W31 - W32) - (W21 - W22) > (W21 - W22) - (W11 - W12).

[0230] Among the various embodiments described above, the first data line 21, the first power signal line 41 and the initialization signal line 50 can each achieve adapted line widths as well as a differentiated line width design that adapts to the spatial allocation, which is not described again here.

[0231] With continued reference to Fig. 3 and Fig. In some embodiments, in the second region A2, the first data line 21 comprises a first winding section 211, the first power signal line 41 comprises a second winding section 411, and the initialization signal line 50 comprises a third winding section 501. At least two of the first winding sections 211, second winding sections 411, and third winding sections 501 have opposite winding directions.

[0232] In this case, the first data line 21, the first power signal line 41, and the initialization signal line 50 can each be connected equally to the pixel circuits to be connected, thus avoiding differences in the provided signals that would lead to display non-uniformity. Furthermore, the influence of components in the sub-pixel rows on the signal lines can be minimized, parasitic capacitances in the row and column directions can be avoided, and an appropriate design of the line width, position, and winding direction of the signal lines can be achieved.

[0233] Fig. 10 and Fig. Figures 11 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. With reference to Fig. 10 and Fig. In one embodiment, the sub-pixel rows 10 further comprise a third sub-pixel row 103. The third sub-pixel row 103 comprises a third pixel circuit 113 and a third light-emitting element 123. The light-emitting color of the first light-emitting element 121, the light-emitting color of the second light-emitting element 122, and the light-emitting color of the third light-emitting element 123 are different. The data lines 20 comprise a second data line 22, and the second data line 22 is connected to the third pixel circuit 113. With reference to Fig. In one embodiment, the sub-pixel rows 10 further comprise a fourth sub-pixel row 104. The fourth sub-pixel row 104 comprises a fourth pixel circuit 114 and a fourth light-emitting element 124. The light-emitting color of the first light-emitting element 121, the light-emitting color of the second light-emitting element 122, the light-emitting color of the third light-emitting element 123, and the light-emitting color of the fourth light-emitting element 124 are different. The second data line 22 is connected to the fourth pixel circuit 114.

[0234] In the Fig. In the embodiment shown in Figure 10, the light-emitting color of the first light-emitting element 121 can optionally be red, the light-emitting color of the second light-emitting element 122 can be green, and the light-emitting color of the third light-emitting element 123 can be blue. Alternatively, the light-emitting color of the first light-emitting element 121 can be red, the light-emitting color of the second light-emitting element 122 can be blue, and the light-emitting color of the third light-emitting element 123 can be green. Alternatively, the light-emitting color of the first light-emitting element 121 can be green, the light-emitting color of the second light-emitting element 122 can be blue, and the light-emitting color of the third light-emitting element 123 can be red.

[0235] In the Fig. In the embodiment shown in Figure 11, the light-emitting color of the first light-emitting element 121 can optionally be red, the light-emitting color of the second light-emitting element 122 can be green, the light-emitting color of the third light-emitting element 123 can be blue, and the light-emitting color of the fourth light-emitting element 124 can be white. Alternatively, the light-emitting color of the first light-emitting element 121 can be red, the light-emitting color of the second light-emitting element 122 can be blue, the light-emitting color of the third light-emitting element 123 can be green, and the light-emitting color of the fourth light-emitting element 124 can be white.Alternatively, the light-emitting color of the first light-emitting element 121 can be red, the light-emitting color of the second light-emitting element 122 can be white, the light-emitting color of the third light-emitting element 123 can be green, and the light-emitting color of the fourth light-emitting element 124 can be blue. Alternatively, the light-emitting color of the first light-emitting element 121 can be blue, the light-emitting color of the second light-emitting element 122 can be white, the light-emitting color of the third light-emitting element 123 can be red, and the light-emitting color of the fourth light-emitting element 124 can be green.Alternatively, the light-emitting color of the first light-emitting element 121 can be green, the light-emitting color of the second light-emitting element 122 can be white, the light-emitting color of the third light-emitting element 123 can be red, and the light-emitting color of the fourth light-emitting element 124 can be blue. Alternatively, the light-emitting color of the first light-emitting element 121 can be green, the light-emitting color of the second light-emitting element 122 can be blue, the light-emitting color of the third light-emitting element 123 can be red, and the light-emitting color of the fourth light-emitting element 124 can be white.

[0236] From the comparison of Fig. 10 with Fig. 11 It is evident that in these two embodiments the sub-pixel rows 10 in the same sub-pixel row can comprise three sub-pixel rows 10 of different colors or four sub-pixel rows 10 of different colors. In the embodiment with three different colors of sub-pixel rows, essentially one data line 20, namely the first data line 21, is provided for two color sub-pixel rows 10, namely the first sub-pixel row 101 and the second sub-pixel row 102, and one data line 20, namely the second data line 22, is provided separately for the remaining color component of the sub-pixel rows 10, namely the third sub-pixel row 103. For the first sub-pixel row 101 and the second sub-pixel row 102, the first data line 21 works together with two sub-scan lines, namely the first sub-scan line 311 and the second sub-scan line 312, to provide data signals for control at different times.For the third sub-pixel row 103, the second data line 22 can directly provide a data signal. A separate sampling line can be provided for the third sub-pixel row 103, or the third sub-pixel row 103 can be directly connected to at least one of the first sub-sampling lines 311 and the second sub-sampling line 312. In this way, sampling lines can be shared to save space in the column direction. When a Scan1 sampling signal is provided on the first sub-sampling line 311 or the second sub-sampling line 312, the data write transistor in the third pixel circuit 113 is switched on synchronously, namely the one in [reference missing]. Fig. 4 shown first transistor T1, and the second data line 22 synchronously provides a data signal to realize the writing of the data signal.

[0237] In the embodiment with four different colors of sub-pixel rows, essentially one data line 20, namely the first data line 21, is provided for two color sub-pixel rows 10, namely the first sub-pixel row 101 and the second sub-pixel row 102, and one data line 20, namely the second data line 22, is provided for the remaining two color sub-pixel rows 10, namely the third sub-pixel row 103 and the fourth sub-pixel row 104. Similar to the first sub-pixel row 101 and the second sub-pixel row 102, the third sub-pixel row 103 and the fourth sub-pixel row 104 can also be supplied with data signals for control, albeit with a time delay, via the second data line 22 in conjunction with two sub-scan lines.Furthermore, separate sub-scan lines can be provided for the third sub-pixel row 103 and the fourth sub-pixel row 104, or the first sub-scan line 311 and the second sub-scan line 312 can be directly shared. That is, the third sub-pixel row 103 is connected to the first sub-scan line 311, and the fourth sub-pixel row 104 is connected to the second sub-scan line 312. In this way, the first sub-pixel row 101 and the third sub-pixel row 103 can be controlled for the data write process by the first sub-scan line 311, and the second sub-pixel row 102 and the fourth sub-pixel row 104 can be controlled for the data write process by the second sub-scan line 312. Of course, the third sub-pixel row 103 can also be connected to the second sub-scanning line 312 and the fourth sub-pixel row 104 to the first sub-scanning line 311, which is not limited here.

[0238] Likewise, in the Fig. 10 and Fig. In the embodiments shown in Figure 11, since two data lines 20 are provided simultaneously, a suitable widening design for one of the two data lines 20 is implemented based on the dual-gate-line control scheme. The arrangement of the data lines 20 in this embodiment is described in more detail below.

[0239] With continued reference to Fig. 10 and Fig. In one embodiment, the line width of the second data line 22 W41 can be in the first region A1 and the line width of the second data line 22 W42 can be in the second region A2, where |W11 - W12| + |W41 - W42| ≠ 0. Alternatively, in one embodiment, it can be specified that (W11 - W12) × (W41 - W42) ≥ 0.

[0240] Taking into account the spatial arrangement requirements, the two data lines 20 can be designed with different line widths in different regions along the column. That is, the difference in line widths of the first data line 21 in the first region A1 and the second region A2 is not zero, or the difference in line widths of the second data line 22 in the first region A1 and the second region A2 is not zero. Thus, |W11 - W12| + |W41 - W42| ≠ 0. As described above, at least one data line 20 can be designed with a larger line width in the first region A1, namely the gap region between pixel circuits 11 along the column, and with a narrower line width in the second region A2, namely the region where the pixel circuits 11 are located. Thus, (W11 - W12) × (W41 - W42) ≥ 0.In this case, both the first data line 21 and the second data line 22 can achieve adapted line widths as well as a differentiated line width design that adapts to the spatial arrangement.

[0241] With continued reference to Fig. In one embodiment, it may further be specified that W11 - W12 ≠ W41 - W42.

[0242] Since the first data line 21 is connected to the first sub-pixel 101 and the second sub-pixel 102, and the second data line 22 is connected to the third sub-pixel 103, the number and types of sub-pixels connected to the two data lines 20 differ, and the loads they carry are also different. Therefore, considering the need to increase the line width, reduce the impedance, and improve signal transmission quality, the first data line 21 and the second data line 22 can be designed with different line widths. For example, the second data line 22, which is connected to the third sub-pixel 103, carries a larger load compared to the second data line 22, resulting in a relatively larger voltage drop during signal transmission. Therefore, the first data line 21 can be designed with a larger line width.In the gap region between pixel circuits 11 in the column direction, namely the first region A1, the line width of the first data line 21 can be larger than that of the second data line 22. In the region where the pixel circuits 11 are located in the column direction, namely the second region A2, the first data line 21 and the second data line 22 can have the same or similar line widths. Thus, W11 - W12 ≠ W41 - W42.

[0243] With continued reference to Fig. 10 and Fig. In one embodiment, it may further be specified that |(W31 - W32) - (W21 - W22)1 > |(W11 - W12) - (W41 - W42)|.

[0244] Compared to the first power signal line 41 and the initialization signal line 50, the first data line 21 and the second data line 22 have a lesser impact on the display effect of the sub-pixels. Therefore, the line widths of the two data lines 20 can be smaller than those of the first power signal line 41 and the initialization signal line 50. If different line widths are set for the same signal line in the first region A1 and the second region A2, the difference for the first power signal line 41 and the initialization signal line 50 can be relatively large, while the difference for the two data lines 20 is relatively similar. Thus, |(W31 - W32) - (W21 - W22)| > |(W11 - W12) - (W41 - W42)|.In this case, the first data line 21, the second data line 22, the first power signal line 41 and the initialization signal line 50 can each achieve adapted line widths as well as differentiated line width designs that adapt to the spatial arrangement.

[0245] Fig. Figure 12 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. With reference to Fig. In one embodiment, the first power signal line 41 extends along the second direction Y. In the second region A2, the first data line 21 comprises a first winding section 211, the first power signal line 41 comprises a second winding section 411, and the second data line 22 comprises a fourth winding section 221. At least two of the first winding sections 211, second winding sections 411, and fourth winding sections 221 have opposite winding directions. Alternatively, in one embodiment, the initialization signal line 50 extends along the second direction Y. In the second region A2, the first data line 21 comprises a first winding section 211, the initialization signal line 50 comprises a third winding section 501, and the second data line 22 comprises a fourth winding section 221.At least two of the first winding sections 211, third winding sections 501 and fourth winding sections 221 have opposite winding directions.

[0246] Similarly, when providing three or four sub-pixels 10, the areas of the light-emitting elements in each sub-pixel can differ due to variations in the light emission efficiency of the light-emitting elements and variations in the proportions required for color mixing. If signal lines are placed in the first region A1, the light-emitting elements must be bypassed as much as possible, resulting in a non-equally spaced arrangement of the signal lines. Furthermore, in the second region A2, to compensate for the distances between the signal lines and the pixel circuits to be connected, the signal lines must typically be centered, resulting in an equidistant arrangement of the signal lines. Based on this, as described in Fig. Figure 12 shows that when two data lines 20 and a first power signal line 41 or an initialization signal line 50 are provided, it is necessary to set up windings in the second region A2 to achieve a centered arrangement of the signal lines relative to the pixel circuits. In this case, the first data line 21, the second data line 22, and the third signal line can each be connected equally to the pixel circuits to be connected, and differences in the provided signals that would lead to display non-uniformity are avoided. Furthermore, the influence of components in the sub-pixels on the signal lines can be reduced as much as possible, parasitic capacitances in the row and column directions can be avoided, and an appropriate design of line width, position, and winding direction can be achieved.

[0247] Fig. Figure 13 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. With reference to Fig. In one embodiment, both the first power signal line 41 and the initialization signal line 50 extend along the second direction Y. In the second region A2, the first data line 21 comprises a first winding section 211, the first power signal line 41 comprises a second winding section 411, the initialization signal line 50 comprises a third winding section 501, and the second data line 22 comprises a fourth winding section 221. At least two of the first winding sections 211, second winding sections 411, third winding sections 501, and fourth winding sections 221 have opposite winding directions.

[0248] Similarly, if both the first power signal line 41 and the initialization signal line 50 are arranged to extend along the column direction, the four signal lines, including the first data line 21 and the second data line 22, can be provided with suitable winding positions in accordance with the requirements of the first region A1 and the second region A2 in the column direction. Winding sections are provided to ensure a centered arrangement through the gap between pixel circuits in the row direction, while bypassing the light-emitting elements in the gap regions between pixel circuits along the column direction, thereby reducing parasitic capacitances and achieving an appropriate design of line width, position, and winding direction.

[0249] Optionally, two of the first winding sections 211, second winding sections 411, third winding sections 501, and fourth winding sections 221 have winding directions that are opposite to the winding directions of the other two winding sections. For example, the first winding section 211 has a winding direction opposite to the winding direction of the fourth winding section 221, and the second winding section 411 has a winding direction opposite to the winding direction of the third winding section 501.

[0250] As exemplified in Fig. As shown in Figure 13, in a pixel unit composed of four sub-pixel rows 10 adjacent along the line direction, the first data line 21, the first power signal line 41, the second data line 22, and the initialization signal line 50 can be arranged sequentially. In the first sub-pixel row 101, the second sub-pixel row 102, the third sub-pixel row 103, and the fourth sub-pixel row 104, the areas of the two middle sub-pixel rows, namely the second sub-pixel row 102 and the third sub-pixel row 103, can be set smaller than the areas of the two outermost sub-pixels, namely the first sub-pixel 101 and the fourth sub-pixel 104.Consequently, in the row direction, the first power signal line 41, located between the first sub-pixel 101 and the second sub-pixel 102, and the second data line 22, located between the second sub-pixel 102 and the third sub-pixel 103, can be arranged with reduced spacing in the gap region between pixel circuits 11 in the column direction, namely the second region A2. Conversely, the second winding section 411 of the first power signal line 41 must be routed to the left in the first region A1, while the fourth winding section of the second data line 22 must be routed to the right in the first region A1, so that the two have opposite winding directions.Due to the reduced distance between the first power signal line 41 and the second data line 22 in the second region A2, the distance between the first data line 21 and the initialization signal line 50 in the second region A2 can also be further reduced. Similarly and conversely, the first winding section 211 of the first data line 21 in the first region A1 must also be routed to the left, and the third winding section of the initialization signal line 50 in the first region A1 must be routed to the right, so that the two have opposite winding directions.

[0251] Fig. 14 and Fig. Figure 15 shows schematic representations of the structures of two further display panels according to an embodiment of the present innovation. First, as shown in Fig. As shown in Figure 14, it may optionally be provided that the display panel is equipped with the first power signal line 41 or the initialization signal line 50, which extends along the second direction Y. As shown in Fig. As shown in Figure 15, optionally both the first power signal line 41 and the initialization signal line 50 can extend along the second direction Y in the display panel.

[0252] With continued reference to Fig. 14 and Fig. In an optional embodiment, the display panel 15 can comprise sub-pixel rows. Each sub-pixel row comprises several sub-pixels 10 arranged along the first direction X. Along the second direction Y, a preset region is provided between the first sub-scanning line 311 and the second sub-scanning line 312, which are closest to each other. The first region A1 includes the preset region, and the second region A2 does not include the preset region.

[0253] The display panel fulfills at least one of the following characteristics: The first power signal line 41 extends along the second direction Y; in the first region A1, the line width of the first power signal line 41 is W21, and in the second region A2, the line width of the first power signal line 41 is W22, where |W11 - W12| + |W21 - W22| ≠ 0. Alternatively, the initialization signal line 50 extends along the second direction Y; in the first region A1, the line width of the initialization signal line 50 is W31, and in the second region A2, the line width of the initialization signal line 50 is W32, where |W11 - W12| + |W31 - W32| ≠ 0.Alternatively, both the first power signal line 41 and the initialization signal line 50 extend along the second direction Y; in the first region A1, the line width of the first power signal line 41 is W21 and the line width of the initialization signal line 50 is W31, and in the second region A2, the line width of the first power signal line 41 is W22 and the line width of the initialization signal line 50 is W32, where |W11 - W12|+ |W21 - W22| + |W31 - W32| ≠ 0.

[0254] In this embodiment, the first region A1 can be understood, in simplified terms, as the gap region between the first sub-scanning line 311 and the second sub-scanning line 312, which are relatively close together, and the second region A2 can be understood, in simplified terms, as the region that does not include the gap between the first sub-scanning line 311 and the second sub-scanning line 312, which are not relatively close together.Since the first sub-scanning line 311 and the second sub-scanning line 312 are each responsible for delivering scanning signals to the first sub-pixel 101 and the second sub-pixel 102, respectively, the distance between these two signal lines and the first sub-pixel 101 and the second sub-pixel 102 in the column direction should be as small as possible to prevent differences in the scanning signals received by the two sub-pixels due to positional differences of the sub-scanning lines, which would impair the uniformity of the light emission of the two sub-pixels. Given this requirement, it must be considered that signal lines running in the column direction must continuously cross these two closely spaced sub-scanning lines, and the continuous height differences at the intersections can lead to a risk of breakage for the signal lines extending along the column direction.In this embodiment, therefore, for the first data line 21, the first power signal line 41, and the initialization signal line 50, which extend along the column direction, at least one of these signal lines has different line widths in the gap area (i.e., in the first region A1) between the two sub-scan lines and in the non-gap area (i.e., in the second region A2). This arrangement avoids breaks at the intersections of the signal lines extending along the column direction, thus ensuring normal signal transmission and preventing display deviations in the panel. It should be noted that in this embodiment, the first region A1 can encompass not only the gap region between the first sub-scan line 311 and the second sub-scan line 312, but also a region that extends outwards to some extent from this gap region.The second region A2 can refer to a specific region or to all regions except the first region A1.

[0255] With continued reference to Fig. 14 and Fig. In an optional embodiment, the display panel can fulfill at least one of the following features: W11 > W12. Alternatively, the first power signal line 41 extends along the second direction Y and W21 > W22 applies. Alternatively, the initialization signal line 50 extends along the second direction Y and W31 > W32 applies.

[0256] This embodiment essentially relates to widening the line width of one of the signal lines running along the column direction, namely the first data line 21, the first power signal line 41, or the initialization signal line 50, in the first region A1; that is, the line width in the first region A1 is greater than in the second region A2. Consequently, this signal line can have a greater line width at the point where it crosses the first sub-scan line 311 and the second sub-scan line 312, thereby reducing the risk of breakage at this point.

[0257] It should also be noted that, as in Fig. 14 and Fig. Figure 15 shows the two sub-scan lines connected to the same sub-pixel array, namely the first sub-scan line 311 and the second sub-scan line 312, both arranged on the top side of the sub-pixel array. This arrangement is only one embodiment of the present innovation. In other embodiments of the present innovation, the two sub-scan lines can optionally be arranged simultaneously on the underside of the sub-pixel array to which the sub-scan lines are connected, or the two sub-scan lines can optionally be arranged one on the top side and the other on the underside of the sub-pixel array to which the sub-scan lines are connected.

[0258] Fig. 16 and Fig. Figure 17 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. With reference to Fig. 16 and Fig. 17 In a further embodiment of the present innovation, the first sub-scanning line 311 and the second sub-scanning line 312, which are connected to the same sub-pixel array, are arranged on the top and bottom surfaces of the sub-pixel array, respectively, and the first sub-scanning line 311 and the second sub-scanning line 312 are arranged alternately in the column direction. In comparison, in the Fig. 14 and Fig. In the arrangement shown in Figure 15, the two sub-scan lines connected to the same sub-pixel row are relatively close together, and the first region A1 can be understood as the region between the two sub-scan lines connected to the same sub-pixel row. In the Fig. 16 and Fig. In the arrangement shown in Figure 17, the two sub-scan lines connected to the same sub-pixel row are relatively far apart, while the first sub-scan line 311 and the second sub-scan line 312, connected to different sub-pixel rows, are relatively close together. In this case, the first region A1 can be understood as the region between the two sub-scan lines, each connected to two adjacent sub-pixel rows.

[0259] Fig. 18 and Fig. Figure 19 shows schematic representations of the structures of two further display panels according to an embodiment of the present innovation. With reference to Fig. 18 and Fig. In one embodiment, the first sub-scan line 311 can be provided with at least one first annular structure 01. The display panel fulfills at least one of the following features: The first power signal line 41 extends along the second direction Y; in the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects at least one of the projections of the first data line 21 or the projection of the first power signal line 41. Alternatively, the initialization signal line 50 extends along the second direction Y; in the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects at least one of the projections of the first data line 21 or the projection of the initialization signal line 50.

[0260] In addition to the first data line 21, which extends along the column direction, the exemplary panel in Fig. 18 the first power signal line 41 or the initialization signal line 50, which extend along the column direction, and the exemplary panel in Fig. 19 comprises both the first power signal line 41 and the initialization signal line 50, which extend along the column direction. Based on this, in this embodiment, the first annular structure 01 is arranged on the first sub-scan line 311 such that the overlap position between the first sub-scan line 311 and the signal lines extending along the column direction is the first annular structure 01. This arrangement essentially concerns a special structural design at the overlap positions between the first sub-scan line 311 and the signal lines extending along the column direction. Those skilled in the art can understand that the overlap positions of signal lines extending in different directions are relatively special. The first sub-scan line 311, extending along the row direction, is usually arranged in the lower layer.When signal lines extending along the gap direction are produced in the upper layer, an insulating layer and the signal lines must be produced at the positions where the first sub-scanning line 311 overlaps with these insulating layers and signal lines. Furthermore, the first sub-scanning line 311 is essentially in an elevated state, which can easily lead to damage at the overlap positions during deposition, etching, and other processes for producing the insulating layer and the signal lines, creating a risk of breakage. In embodiments of the present innovation, the first annular structure 01 is provided at the overlapping positions of the first sub-scanning line 311.On the one hand, this arrangement can increase the line width in the column direction, improve the response to height differences, and prevent damage to the first sub-scan line 311 during the fabrication of the signal lines in the upper layer. On the other hand, two parallel paths are formed. Even if one path is damaged and interrupted, the other path can still transmit the scanning signal, thus preventing a complete break in the first sub-scan line 311, which would prevent effective transmission of the scanning signal, cause the sub-pixels to fail to illuminate, and lead to display deviations in the panel.

[0261] It should be noted that, as in Fig. 18 and Fig. Figure 19 shows that for a group consisting of the first data line 21, the first power signal line 41, and the initialization signal line 50, only one common first annular structure 01 is provided on the first sub-scanning line 311. In other embodiments of the present innovation, a first annular structure 01 can optionally be provided separately for each signal line, or a common first annular structure 01 can be provided for certain multiple signal lines, which is not limited here. Additionally, annular structures can also be provided for the second sub-scanning line 312 in the same manner as for the first sub-scanning line 311 to avoid breaks at positions that overlap with signal lines extending along the column direction and to ensure error-free transmission of the scanning signals. This is not described in detail here.Based on the design scheme for the first sub-scanning line in this embodiment, identical or similar improvements applied to the second sub-scanning line 312 also fall within the scope of protection of the present innovation.

[0262] Fig. Figure 20 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. With reference to Fig. In one embodiment, the first power signal line 41 extends along the second direction Y. The first sub-scan line 311 also includes a second annular structure 02. In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, and the projection of the second annular structure 02 intersects the projection of the first power signal line 41.

[0263] In this embodiment, both the first data line 21 and the first power signal line 41 extend along the column direction. Based on this, at the positions where these two signal lines overlap with the first sub-scanning line 311 in the column direction, annular structures, namely the first annular structure 01 and the second annular structure 02, can be provided separately on the first sub-scanning line 311 to prevent breaks in the first sub-scanning line 311 at the overlap positions with these two signal lines.

[0264] With continued reference to Fig. 20 can furthermore be the length of the first ring-shaped structure 01 La1 and the length of the second ring-shaped structure 02 La2 along the first direction X; along the second direction Y, the width of the first ring-shaped structure 01 Wa1 and the width of the second ring-shaped structure 02 Wa2 can be. The display panel satisfies at least one of the following characteristics: La1 ≠ La2. Alternatively, Wa1 ≠ Wa2. For example, the display panel satisfies at least one of the following characteristics: La1 < La2. Alternatively, Wa1 < Wa2.

[0265] As described above, the first data line 21 and the first power signal line 41 have different functions in the pixel circuit drive process. The first power signal line 41 is responsible for providing the initial power signal to the pixel circuits during the light emission phase. This directly determines the magnitude of the drive current for the light-emitting elements and thus influences the light emission brightness. Therefore, compared to the first data line 21, the line width of the first power signal line 41 can be wider to avoid excessive voltage drop across it, which would cause large variations in the initial power signals and thus result in display non-uniformity.Therefore, when designing ring-shaped structures on the first sub-scanning line 311, the size of the second ring-shaped structure 02, corresponding to the first power signal line 41, should be chosen to be larger in order to adapt to the line widths of the first data line 21 and the first power signal line 41 and to improve breakup problems of the first sub-scanning line 311 at the overlap positions with different signal lines. The size of the ring-shaped structure can refer to its length along the row direction or its width along the column direction; this is not restricted here.

[0266] With continued reference to Fig. In one embodiment, the initialization signal line 50 extends along the second direction Y. The first sub-scan line 311 also includes a third annular structure 03. In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, and the projection of the third annular structure 03 intersects the projection of the initialization signal line 50.

[0267] In this embodiment, both the first data line 21 and the initialization signal line 50 extend along the column direction. Based on this, at the positions where these two signal lines overlap with the first sub-scanning line 311 in the column direction, ring-shaped structures, namely the first ring-shaped structure 01 and the third ring-shaped structure 03, can be provided separately on the first sub-scanning line 311 to prevent breaks in the first sub-scanning line 311 at the overlap positions with these two signal lines.

[0268] With continued reference to Fig. 20 can furthermore be the length of the first ring-shaped structure 01 La1 and the length of the third ring-shaped structure 03 La3 along the first direction X; along the second direction Y, the width of the first ring-shaped structure 01 Wa1 and the width of the third ring-shaped structure 03 Wa3 can be. The display panel satisfies at least one of the following characteristics: La1 ≠ La3. Alternatively, Wa1 ≠ Wa3. For example, the display panel satisfies at least one of the following characteristics: La1 < La3. Alternatively, Wa1 < Wa3.

[0269] Similarly, the first data line 21 and the initialization signal line 50 have different functions in the pixel circuit control process. During the initialization phase, the initialization signal line 50 supplies an initialization signal to the anode of the light-emitting element. This directly affects the brightness of the light-emitting element in each sub-pixel connected to the initialization signal line and can cause display inconsistencies. Therefore, to avoid excessive voltage drop on the initialization signal line 50, which would cause display inconsistencies, the line width of the initialization signal line 50 can be wider compared to the first data line 21.Therefore, when designing ring-shaped structures on the first sub-scanning line 311, the size of the third ring-shaped structure 03, which corresponds to the initialization signal line 50, should be chosen to be larger in order to adapt to the line widths of the first data line 21 and the initialization signal line 50 and to improve breakup problems of the first sub-scanning line 311 at the overlap positions with different signal lines.

[0270] Fig. Figure 21 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. With reference to Fig. In one embodiment, both the first power signal line 41 and the initialization signal line 50 extend along the second direction Y. The first sub-scan line 311 also comprises a second annular structure 02 and a third annular structure 03. In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, the projection of the second annular structure 02 intersects the projection of the first power signal line 41, and the projection of the third annular structure 03 intersects the projection of the initialization signal line 50.

[0271] In this embodiment, the first data line 21, the first power signal line 41, and the initialization signal line 50 all extend along the column direction. Based on this, ring-shaped structures, namely the first ring-shaped structure 01, the second ring-shaped structure 02, and the third ring-shaped structure 03, can be provided separately on the first sub-scanning line 311 at the positions where these three signal lines overlap with the first sub-scanning line 311 in the column direction, in order to prevent breaks in the first sub-scanning line 311 at the corresponding overlap positions.

[0272] With continued reference to Fig. 20 can furthermore be the length of the first ring-shaped structure 01 La1, the length of the second ring-shaped structure 02 La2, and the length of the third ring-shaped structure 03 La3 along the first direction X; along the second direction Y, the width of the first ring-shaped structure 01 Wa1, the width of the second ring-shaped structure 02 Wa2, and the width of the third ring-shaped structure 03 Wa3 can be. The display panel satisfies at least one of the following characteristics: At least two of La1, La2, and La3 are unequal. Alternatively, at least two of Wa1, Wa2, and Wa3 are unequal. For example, the display panel satisfies at least one of the following characteristics: La1 < La3 ≤ La2. Alternatively, Wa1 < Wa3 ≤ Wa2.

[0273] Similarly, the first data line 21, the first power signal line 41, and the initialization signal line 50 have different functions in the pixel control process. Both the first power signal line 41 and the initialization signal line 50 directly influence the brightness of the light-emitting elements and cause display non-uniformity. Furthermore, the first power signal line 41 directly determines the brightness of the light-emitting elements and thus has a greater impact. Therefore, for the three signal lines extending along the column direction, the first power signal line 41 and the initialization signal line 50 can have relatively large line widths, and the line widths of the first power signal line 41 and the initialization signal line 50 can be the same, or the first power signal line 41 can be even wider.Therefore, when designing ring-shaped structures on the first sub-scanning line 311, the size of the second ring-shaped structure 02, which corresponds to the first power signal line 41, should be chosen to be the largest, followed by the size of the third ring-shaped structure 03, which corresponds to the initialization signal line 50, while the size of the first ring-shaped structure 01, which corresponds to the first data line 21, should be the smallest in order to adapt to the line widths of the three signal lines extending along the column direction and to improve breakup problems of the first sub-scanning line 311 at the overlap positions with different signal lines.

[0274] With continued reference to Fig. 18 and Fig. In one embodiment, the first region A1 can optionally include a region within the first annular structure 01, and the second region A2 can optionally not include the region within the first annular structure 01. Furthermore, the display panel fulfills at least one of the following features: In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, where W11 > W12. Alternatively, the first power signal line 41 extends along the second direction Y, and in the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first power signal line 41, where W21 > W22.Alternatively, the initialization signal line 50 extends along the second direction Y and in the direction perpendicular to the substrate of the display panel, the projection of the first ring-shaped structure 01 intersects the projection of the initialization signal line 50, where W31 > W32.

[0275] In this embodiment, the first region A1 is the region inside the first annular structure 01 on the first sub-scan line 311, and the second region A2 is the region outside the first annular structure 01. Based on this, the projection of the first data line 21 intersects the projection of the first annular structure 01. W11 > W12 means that the linewidth of the section of the first data line 21 inside the first annular structure 01 is greater than the linewidth of the section outside the first annular structure 01. The projection of the first power signal line 41 intersects the projection of the first annular structure 01. W21 > W22 means that the linewidth of the section of the first power signal line 41 inside the first annular structure 01 is greater than the linewidth of the section outside the first annular structure 01.The projection of the initialization signal line 50 intersects the projection of the first annular structure 01. W31 > W32 means that the linewidth of the section of the initialization signal line 50 inside the first annular structure 01 is greater than the linewidth of the section outside the first annular structure 01. As these three signal lines extend along the column direction, they overlap with the first sub-scan line 311 at the first annular structure 01. In this embodiment, at least one of the signal lines extending along the column direction is configured to have different linewidths in the first region A1 and the second region A2, as described above.This design ensures that the signal line has a larger line width at the position where it crosses the first sub-scanning line 311, thereby avoiding breaks due to height differences at the overlap position when crossing the first sub-scanning line 311 and preventing display deviations due to faulty signal transmission.

[0276] With continued reference to Fig. 20 and Fig. In one embodiment, the display panel optionally fulfills at least one of the following features: The first power signal line 41 extends along the second direction Y, the first sub-scan line 311 further comprises a second annular structure 02, and in the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, and the projection of the second annular structure 02 intersects the projection of the first power signal line 41, wherein W11 - W12 > W21 - W22 ≥ 0.Alternatively, the initialization signal line 50 extends along the second direction Y, the first sub-scan line 311 further includes a third annular structure 03, and in the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, and the projection of the third annular structure 03 intersects the projection of the initialization signal line 50, where W11 - W12 > W31 - W32 ≥ 0.

[0277] Compared to the first data line 21, the first power signal line 41 and the initialization signal line 50 have a significantly stronger influence on the control process of the same sub-pixel and easily cause differences in the light emission brightness of the sub-pixels connected to the first power signal line 41 and the initialization signal line 50, resulting in display non-uniformity. Therefore, in embodiments of the present innovation, the line widths of the first power signal line 41 and the initialization signal line 50 can optionally be set wider, while the line width of the first data line 21 is set relatively narrow. This makes a break more likely for the first data line 21 with the narrowest line width if the first data line 21 overlaps the first annular structure 01 on the first sub-scan line 311.Therefore, the first data line 21 must be significantly widened in the area of ​​overlap with the first ring-shaped structure 01, i.e., in the first region A1, resulting in a large linewidth difference of the first data line 21 between the first region A1 and the second region A2. For the first power signal line 41 and the initialization signal line 50, which have wider linewidths, appropriate widening or even no widening can be performed in the areas where they overlap with the second ring-shaped structure 02 and the third ring-shaped structure 03, respectively, i.e., in the first region A1. Consequently, the linewidth differences of the first power signal line 41 and the initialization signal line 50 between the first region A1 and the second region A2 are relatively small or equal to zero. Thus, W11 - W12 > W21 - W22 ≥ 0 and W11 - W12 > W31 - W32 ≥ 0.In this case, the first data line 21, the first power signal line 41 and the initialization signal line 50 can each adjust their line widths and be appropriately widened at the overlap positions with the first sub-scan line, thereby avoiding breaks and preventing display deviations.

[0278] With continued reference to Fig. In one embodiment, optionally both the first power signal line 41 and the initialization signal line 50 extend along the second direction Y. The first sub-scan line 311 also comprises a second annular structure 02 and a third annular structure 03. In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, the projection of the second annular structure 02 intersects the projection of the first power signal line 41, and the projection of the third annular structure 03 intersects the projection of the initialization signal line 50. W11 - W12 > W31 - W32 ≥ W21 - W22 ≥ 0.

[0279] Since the first power signal line 41 directly determines the brightness of the light-emitting elements and consequently has a greater impact, its linewidth can be wider than that of the initialization signal line 50. Therefore, for the first data line 21, which has the narrowest linewidth, a break is most likely when it overlaps the first annular structure 01. Consequently, the first data line 21 must be significantly widened in the first region A1, where it overlaps the first annular structure 01, resulting in the greatest linewidth difference between the first region A1 and the second region A2. For the initialization signal line 50, which has a medium linewidth, appropriate widening or even no widening at all is permissible in the first region A1, where it overlaps the third annular structure 03.For the first power signal line 41, which has the largest line width, the smallest possible widening, or even no widening at all, can be applied in the first region A1, where it overlaps with the second ring-shaped structure 02. Consequently, the line width difference of the initialization signal line 50 between the first region A1 and the second region A2 is medium, and the line width difference of the first power signal line 41 is the smallest or zero. Thus, W11 - W12 > W31 - W32 ≥ W21 - W22 ≥ 0. In this case, the first data line 21, the first power signal line 41, and the initialization signal line 50 can each adjust their line widths and be appropriately widened at the overlap positions with the first sub-scan line, thereby avoiding breaks and preventing display deviations.

[0280] Fig. 22 and Fig. 23 are schematic representations of the structures of two further display panels according to an embodiment of the present innovation. With reference to Fig. 22 and Fig. In one embodiment, the sub-pixels 10 further comprise a third sub-pixel 103. The third sub-pixel 103 comprises a third pixel circuit 113 and a third light-emitting element 123. The light-emitting color of the first light-emitting element 121, the light-emitting color of the second light-emitting element 122, and the light-emitting color of the third light-emitting element 123 are different. The data lines 20 comprise a second data line 22, and the second data line 22 is connected to the third pixel circuit 113. With reference to Fig. In one embodiment, the sub-pixels 10 further comprise a fourth sub-pixel 104. The fourth sub-pixel 104 comprises a fourth pixel circuit 114 and a fourth light-emitting element 124. The light-emitting color of the first light-emitting element 121, the light-emitting color of the second light-emitting element 122, the light-emitting color of the third light-emitting element 123, and the light-emitting color of the fourth light-emitting element 124 are different. The second data line 22 is connected to the fourth pixel circuit 114.

[0281] In the Fig. In the embodiment shown in Figure 22, the light-emitting color of the first light-emitting element 121 can optionally be red, the light-emitting color of the second light-emitting element 122 can be green, and the light-emitting color of the third light-emitting element 123 can be blue. Alternatively, the light-emitting color of the first light-emitting element 121 can be red, the light-emitting color of the second light-emitting element 122 can be blue, and the light-emitting color of the third light-emitting element 123 can be green. Alternatively, the light-emitting color of the first light-emitting element 121 can be green, the light-emitting color of the second light-emitting element 122 can be blue, and the light-emitting color of the third light-emitting element 123 can be red.

[0282] In the Fig. In the embodiment shown in Figure 23, the light-emitting color of the first light-emitting element 121 can optionally be red, the light-emitting color of the second light-emitting element 122 can be green, the light-emitting color of the third light-emitting element 123 can be blue, and the light-emitting color of the fourth light-emitting element 124 can be white. Alternatively, the light-emitting color of the first light-emitting element 121 can be red, the light-emitting color of the second light-emitting element 122 can be blue, the light-emitting color of the third light-emitting element 123 can be green, and the light-emitting color of the fourth light-emitting element 124 can be white.Alternatively, the light-emitting color of the first light-emitting element 121 can be red, the light-emitting color of the second light-emitting element 122 can be white, the light-emitting color of the third light-emitting element 123 can be green, and the light-emitting color of the fourth light-emitting element 124 can be blue. Alternatively, the light-emitting color of the first light-emitting element 121 can be blue, the light-emitting color of the second light-emitting element 122 can be white, the light-emitting color of the third light-emitting element 123 can be red, and the light-emitting color of the fourth light-emitting element 124 can be green.Alternatively, the light-emitting color of the first light-emitting element 121 can be green, the light-emitting color of the second light-emitting element 122 can be white, the light-emitting color of the third light-emitting element 123 can be red, and the light-emitting color of the fourth light-emitting element 124 can be blue. Alternatively, the light-emitting color of the first light-emitting element 121 can be green, the light-emitting color of the second light-emitting element 122 can be blue, the light-emitting color of the third light-emitting element 123 can be red, and the light-emitting color of the fourth light-emitting element 124 can be white.

[0283] With continued reference to Fig. 22 and Fig. In one embodiment, optionally both the first power signal line 41 and the initialization signal line 50 extend along the second direction Y. The first sub-scan line 311 further comprises a second annular structure 02, a third annular structure 03, and a fourth annular structure 04. In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, the projection of the second annular structure 02 intersects the projection of the first power signal line 41, the projection of the third annular structure 03 intersects the projection of the initialization signal line 50, and the projection of the fourth annular structure 04 intersects the projection of the second data line 22.

[0284] Furthermore, the second sub-scan line 312 can optionally include a fifth annular structure 05, a sixth annular structure 06, a seventh annular structure 07, and an eighth annular structure 08. In the direction perpendicular to the substrate of the display panel, the projection of the fifth annular structure 05 intersects the projection of the first data line 21, the projection of the sixth annular structure 06 intersects the projection of the first power signal line 41, the projection of the seventh annular structure 07 intersects the projection of the initialization signal line 50, and the projection of the eighth annular structure 08 intersects the projection of the second data line 22.

[0285] This embodiment is based on the arrangement of three differently colored sub-pixels or four differently colored sub-pixels in the sub-pixel row, corresponding to two data lines 20, namely the first data line 21 and the second data line 22. The control principle can be based on the content of the in Fig. 10 and Fig. The embodiments shown in Figure 11 are described in detail and are not repeated here. The three or four sub-pixels can share the first sub-scan line 311 and the second sub-scan line 312. Accordingly, if four signal lines, including the two data lines 20, the first power signal line 41, and the initialization signal line 50, are all arranged to extend along the column direction, a ring-shaped structure must be provided on each of the first sub-scan line 311 and the second sub-scan line 312. This prevents breaks in the first sub-scan line 311 and the second sub-scan line 312 at the positions where they overlap with these four signal lines, thus preventing display deviations.

[0286] With continued reference to Fig. 22 and Fig. In one embodiment, the length of the first annular structure 01 La1, the length of the second annular structure 02 La2, the length of the third annular structure 03 La3, and the length of the fourth annular structure 04 La4 can optionally be along the first direction X; along the second direction Y, the width of the first annular structure 01 Wa1, the width of the second annular structure 02 Wa2, the width of the third annular structure 03 Wa3, and the width of the fourth annular structure 04 Wa4 can be. The display panel fulfills at least one of the following features: At least two of La1, La2, La3, and La4 are unequal. Alternatively, at least two of Wa1, Wa2, Wa3, and Wa4 are unequal. For example, the display panel fulfills at least one of the following features: La1 = La4. Alternatively, La2 = La3. Alternatively, Wa1 = Wa4. Alternatively, Wa2 = Wa3.

[0287] It is understandable that the first power signal line 41 and the initialization signal line 50 serve to provide fixed voltage signals and directly influence the light emission brightness of the sub-pixels. Compared to the first data line 21 and the second data line 22, the first power signal line 41 and the initialization signal line 50 can be designed with relatively large linewidths. Therefore, when designing the ring-shaped structures on the first sub-scan line 311 corresponding to the first power signal line 41 and the initialization signal line 50, i.e., the second ring-shaped structure 02 and the third ring-shaped structure 03, the dimensions of the first power signal line 41 and the initialization signal line 50 can be chosen to be larger relative to the first ring-shaped structure 01 and the fourth ring-shaped structure 04.In other words, at least two of the four ring-shaped structures on the first sub-scanning line 311 should have different dimensions. Furthermore, both the first data line 21 and the second data line 22 are used for transmitting data signals, and their line widths can be identical. Therefore, when designing the ring-shaped structures on the first sub-scanning line 311, corresponding to the first data line 21 and the second data line 22 (i.e., the first ring-shaped structure 01 and the fourth ring-shaped structure 04), the dimensions of the two ring-shaped structures can be chosen to be the same. That is, La1 = La4 and Wa1 = Wa4. The first power signal line 41 and the initialization signal line 50 are both used to provide fixed voltage signals, and their line widths can also be different.Therefore, when designing the ring-shaped structures on the first sub-scanning line 311 corresponding to the first power signal line 41 and the initialization signal line 50, i.e., the second ring-shaped structure 02 and the third ring-shaped structure 03, the sizes of the two ring-shaped structures can be chosen to be the same. That is, La2 = La3 and Wa2 = Wa3.

[0288] With continued reference to Fig. 22 and Fig. 23 In one embodiment, the length of the first annular structure 01 La1, the length of the second annular structure 02 La2, the length of the third annular structure 03 La3, and the length of the fourth annular structure 04 La4 may optionally be along the first direction X; the length of the fifth annular structure 05 La5, the length of the sixth annular structure 06 La6, the length of the seventh annular structure 07 La7, and the length of the eighth annular structure 08 La8 may be along the first direction X; the width of the first annular structure 01 Wa1, the width of the second annular structure 02 Wa2, the width of the third annular structure 03 Wa3, and the width of the fourth annular structure 04 Wa4 may be along the second direction Y;Along the second direction Y, the width of the fifth ring-shaped structure can be 05 Wa5, the width of the sixth ring-shaped structure 06 Wa6, the width of the seventh ring-shaped structure 07 Wa7, and the width of the eighth ring-shaped structure 08 Wa8. The display panel fulfills at least one of the following characteristics: La1 = La5 and Wa1 = Wa5. Alternatively, La2 = La6 and Wa2 = Wa6. Alternatively, La3 = La7 and Wa3 = Wa7. Alternatively, La4 = La8 and Wa4 = Wa8.

[0289] In this embodiment, if ring-shaped structures are provided on the first sub-scanning line 311 and the second sub-scanning line 312 corresponding to the signal lines extending along the column direction, ring-shaped structures of the same size can be selected. Specifically, the sizes of the first ring-shaped structure 01 and the fifth ring-shaped structure 05, which are provided on the first sub-scanning line 311 and the second sub-scanning line 312 respectively corresponding to the first data line 21, can be selected to be the same. That is, La1 = La5 and Wa1 = Wa5. The sizes of the second ring-shaped structure 02 and the sixth ring-shaped structure 06, which are provided on the first sub-scanning line 311 and the second sub-scanning line 312 respectively corresponding to the first power signal line 41, can be selected to be the same. That is, La2 = La6 and Wa2 = Wa6.The dimensions of the third ring structure 03 and the seventh ring structure 07, located on the first sub-scan line 311 and the second sub-scan line 312 respectively, corresponding to the initialization signal line 50, can be chosen to be the same. That is, La3 = La7 and Wa3 = Wa7. The dimensions of the fourth ring structure 04 and the eighth ring structure 08, located on the first sub-scan line 311 and the second sub-scan line 312 respectively, corresponding to the second data line 22, can be chosen to be the same. That is, La4 = La8 and Wa4 = Wa8.

[0290] With continued reference to Fig. 22 and Fig. In one embodiment, both the first power signal line 41 and the initialization signal line 50 extend along the second direction Y. The first sub-scan line 311 further comprises a second annular structure 02, a third annular structure 03, and a fourth annular structure 04. In the direction perpendicular to the substrate of the display panel, the projection of the first annular structure 01 intersects the projection of the first data line 21, the projection of the second annular structure 02 intersects the projection of the first power signal line 41, the projection of the third annular structure 03 intersects the projection of the initialization signal line 50, and the projection of the fourth annular structure 04 intersects the projection of the second data line 22.In the first region A1, the line width of the second data line is 22 W41, and in the second region A2, the line width of the second data line is 22 W42, where |W11 - W12| + |W41 - W42| ≠ 0.

[0291] Considering that breaks can easily occur at overlapping positions, the two data lines 20 can be designed such that they have different line widths within the ring-shaped structures, i.e., in the first region A1, and outside the ring-shaped structures, i.e., in the second region A2. That is, the difference in line widths of the first data line 21 in the first region A1 and the second region A2 is not zero, or the difference in line widths of the second data line 22 in the first region A1 and the second region A2 is not zero. Thus, |W11 - W12| + |W41 - W42| ≠ 0.

[0292] With continued reference to Fig. 22 and Fig. 23 applies in one embodiment |(W31 - W32) - (W21 - W22)| > |(W11 - W12) - (W41 - W42)|.

[0293] Compared to the first power signal line 41 and the initialization signal line 50, the first data line 21 and the second data line 22 have a lesser impact on the display effect of the sub-pixels. Therefore, the line widths of the two data lines 20 can be smaller than those of the first power signal line 41 and the initialization signal line 50. If different line widths are set for the same signal line in the first region A1 and the second region A2, the difference for the first power signal line 41 and the initialization signal line 50 can be relatively large, while the difference for the two data lines 20 is relatively similar. Thus, |(W31 - W32) - (W21 - W22)| > |(W11 - W12) - (W41 - W42)|.In this case, the first data line 21, the second data line 22, the first power signal line 41 and the initialization signal line 50 can each adjust their line widths and be appropriately widened at the overlap positions with the first sub-scan line 311, thereby avoiding breaks and preventing display deviations.

[0294] The in Fig. The pixel circuit shown in Figure 4 is merely one example of the present innovation. The embodiments of the present innovation are applicable to several types of pixel circuits; examples are given below. Fig. Figure 24 is a schematic representation of the structure of another pixel circuit according to an embodiment of the present innovation. With reference to Fig. 24 In one embodiment, the scanning lines further comprise a second scanning line 32. The second scanning line 32 is connected to the first pixel circuit 111, and the second scanning line 32 is also connected to the second pixel circuit 112. Specifically, the pixel circuit, as shown in Fig. Figure 24 shows a first transistor T1 and a second transistor T2. The first scanning line 31 is connected to the first transistor T1, and the second scanning line 32 is connected to the second transistor T2.

[0295] The first scanning line 31 is responsible for supplying the Scan1 signal to the gate of the first transistor T1, the data write transistor, to control its switching on and off. The second scanning line 32 is responsible for supplying the Scan1 signal to the gate of the second transistor T2, the anode reset transistor, to initialize the anode of the light-emitting element 12. The two transistors can be switched on or off independently. This pixel circuit is essentially an external compensation 3T1C pixel circuit. Because the first transistor T1 and the second transistor T2 can be controlled independently in this pixel circuit, the actual control process can also include a compensation mode. Fig. 25 is a control timing diagram of the in Fig. The 24-pixel circuit shown. With reference to Fig. 24 and Fig. 25. The compensation mode can be executed before leaving the factory or at regular intervals. In compensation mode, the threshold voltage of the third transistor T3, i.e., the drive transistor, in the pixel can be detected and stored. Thus, in display mode, the stored threshold voltage can be used to compensate for the data signal Data, and the compensated data signal Data can be written to the pixel circuit. In this way, the influence on the drive transistor's threshold voltage during the drive and light emission process can be compensated. Specifically, the compensation mode includes an initialization phase tc, a pre-charge phase td, a discharge phase te, and a sampling phase tf. In the initialization phase tc, the first transistor T1 and the second transistor T2 are switched on.A data voltage is applied to the gate of the third transistor T3, i.e., the first node N1, and the initialization signal Vrefl is applied to the anode of the light-emitting element 12, i.e., the second node N2. In this case, the third transistor T3 is switched on, and a voltage Vdata - Vth is built up between the first node N1 and the second node N2 via the first capacitor C1. During the pre-charge phase td, the second transistor T2 is switched off, and a preset voltage signal Vpre is applied to the initialization signal line 50. During the discharge phase te, the second transistor T2 is switched on again. In this case, the initialization signal line 50 can receive the voltage Vdata - Vth from the second node N2. During the sampling phase tf, the first transistor T1 and the second transistor T2 are switched off. The driver chip can detect the voltage Vdata - Vth on the initialization signal line 50.Based on the known written data signal Data, the threshold voltage Vth of the third transistor T3 can be obtained and stored.

[0296] Fig. 26 and Fig. Figures 27 are schematic representations of the structures of two further pixel circuits according to an embodiment of the present innovation. With reference to Fig. 26 and Fig. The pixel circuit comprises at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The sixth transistor T6, the third transistor T3, and the seventh transistor T7 are connected in series between the first power signal line 41 and the light-emitting element 12. The first transistor T1 is connected between the data line 20 and a first electrode of the third transistor T3. The second transistor T2 is connected between the initialization signal line 50 and the light-emitting element 12. The fourth transistor T4 is connected to the gate of the third transistor T3. The fifth transistor T5 is connected between a second electrode of the third transistor T3 and the gate of the third transistor T3.The first capacitor C1 is located between the gate of the third transistor T3 and the first power signal line 41 (as shown in . Fig. 26) connected or the first capacitor C1 is connected between the gate of the third transistor T3 and the light-emitting element 12 (as shown in Fig. (shown in 27). The gate of the first transistor T1 is connected to the first scanning line 31.

[0297] Additionally, the display panel includes a second sampling line 32, a second power signal line, a light emission control signal line, and a reset signal line. The cathode of the light-emitting element 12 is connected to the second power signal line. The gates of the sixth transistor T6 and the seventh transistor T7 are connected to the light emission control signal line. The fourth transistor T4 is connected between the reset signal line and the gate of the third transistor T3. The gates of the first transistor T1 and the fifth transistor T5 are both connected to the first sampling line 31. The gates of the second transistor T2 and the fourth transistor T4 are both connected to the second sampling line 32.

[0298] These two types of pixel circuits are essentially 7T1CPixel circuits, which are internal compensation circuits that implement threshold voltage compensation directly through internal transistors. Specifically, the first transistor, T1, is a data write transistor, and the fifth transistor, T5, is a threshold voltage compensation transistor. During the data write phase, the first transistor, T1, and the fifth transistor, T5, are switched on. The data signal, Data, is written via the first transistor, T1, the third transistor, T3, and the fifth transistor, T5, to the gate of the third transistor, T3, and stored by the first capacitor, C1. During this process, the data signal passes through the third transistor, T3, which compensates for the threshold voltage of the third transistor. That is, the data signal actually written to the gate of the third transistor, T3, is Vdata - Vth.Thus, in the light emission phase, the threshold voltage can also be eliminated from the drive current equation, which means that by compensating the threshold voltage Vth during data writing, the drive current is prevented from being influenced by the threshold voltage.

[0299] It should be noted that the pixel circuits described above are also only examples of the innovation at hand. Fig. Figure 4 is used as an example. The transistors are implemented as N-channel transistors for illustrative purposes, but a person skilled in the art can optionally use P-channel transistors. The in Fig. 26 and Fig. The 27 pixels shown are also used as examples. The scheme in which transistor gates are connected to the same sampling line is an optional prior art scheme, and the person skilled in the art can optionally provide separate sampling lines for each transistor to supply sampling signals. In summary, based on the above pixel circuits, the person skilled in the art can make appropriate modifications or select different pixel circuit designs as needed, all of which fall within the scope of protection of the present innovation.

[0300] In embodiments of the present innovation, multiple scanning lines can also be provided adaptively depending on the configuration of the pixel circuits. Accordingly, the line widths of the signal lines extending along the second direction Y, i.e., the column direction, can be designed adaptively based on the arrangement of the scanning lines. The following serve as an example: Fig. 2 and Fig. 3 embodiments shown, in which the first region A1 is the gap region between pixel circuits in adjacent sub-pixel rows and the second region A2 is the region in which the pixel circuits are located in the sub-pixel rows, to illustrate by way of example the line width design scheme for signal lines extending along the second direction Y, i.e. the gap direction, when providing multiple scanning lines or sub-scanning lines.

[0301] Fig. Figure 28 is a schematic representation of the structure of another display panel according to an embodiment of the present innovation. With reference to Fig. 24 and Fig. 26 to Fig. 28 In other embodiments of the present innovation, if the sampling lines comprise a first sampling line 31 and a second sampling line 32, since the first sub-pixel 101 and the second sub-pixel 102, which are adjacent in the line direction, are connected to the same first data line 21, i.e., based on the dual-gate-line drive technology, each sampling line must actually be implemented as two sub-sampling lines in order to supply sampling signals to the two sub-pixels, respectively. Accordingly, the second sampling line 32 can also comprise a third sub-sampling line 323 and a fourth sub-sampling line 324. The third sub-sampling line 323 is connected to the first pixel circuit 111, and the fourth sub-sampling line 324 is connected to the second pixel circuit 112.

[0302] Based on this, in further embodiments of the present innovation, the line widths of signal lines extending along the column direction can be adaptively adjusted. For example, in the Fig. The display panel shown in Figure 28 contains the first data line 21, the first power signal line 41, the initialization signal line 50, and the second data line 22, all running along the column direction. Different line widths can be set for these four signal lines in the first region A1 and the second region A2, namely a larger line width in the first region A1 and a smaller line width in the second region A2. In this way, customized line widths and a differentiated line width design can be obtained that adapts to the spatial arrangement.

[0303] Fig. Figure 29 is a schematic representation of the structure of another display panel according to one embodiment of the present innovation. Further embodiments of the present innovation comprise, with reference to Fig. 29 the sub-pixel 10 further a third sub-pixel 103. The third sub-pixel 103 comprises a third pixel circuit 113 and a third light-emitting element 123. The light-emitting color of the first light-emitting element 121, the light-emitting color of the second light-emitting element 122 and the light-emitting color of the third light-emitting element 123 are different. The first data line 21 is connected to the third pixel circuit 113. The first sampling line 31 comprises a fifth sub-sampling line 315, and the fifth sub-sampling line 315 is connected to the third pixel circuit 113.

[0304] If the first sampling line 31 is configured to include three sub-sampling lines, namely the first sub-sampling line 311, the second sub-sampling line 312, and the fifth sub-sampling line 315, the line widths of the signal lines extending along the column direction can be adjusted accordingly and adaptively. Similarly, and by way of example, in the Fig. In the display panel shown in Figure 29, the first data line 21, the first power signal line 41, the initialization signal line 50, and the second data line 22 all run along the column direction. Different line widths can be set for these four signal lines in the first region A1 and the second region A2, a point which will not be discussed further here. In this case, an optimized line width design can be achieved, and customized line widths as well as differentiated line width designs that adapt to the spatial allocation can be obtained in this embodiment.

[0305] Fig. Figure 30 is a schematic representation of the structure of another display panel according to one embodiment of the present innovation. Further embodiments of the present innovation comprise, with reference to Fig. Sub-pixels 10 and a fourth sub-pixel 104 are also included. The fourth sub-pixel 104 comprises a fourth pixel circuit 114 and a fourth light-emitting element 124. The light-emitting color of the first light-emitting element 121, the light-emitting color of the second light-emitting element 122, the light-emitting color of the third light-emitting element 123, and the light-emitting color of the fourth light-emitting element 124 are different. The first data line 21 is connected to the fourth pixel circuit 114. The first sampling line 31 comprises a sixth sub-sampling line 326, and the sixth sub-sampling line 326 is connected to the fourth pixel circuit 114.

[0306] Similarly, if the first sampling line 31 is configured to include four sub-sampling lines, namely the first sub-sampling line 311, the second sub-sampling line 312, the fifth sub-sampling line 315, and the sixth sub-sampling line 326, the line widths of the signal lines extending along the column direction can be adjusted accordingly and adaptively. Likewise, and by way of example, in the Fig. In the display panel shown in Figure 30, the first data line 21, the first power signal line 41, the initialization signal line 50, and the second data line 22 all run along the column direction. Different line widths can be set for these four signal lines in the first region A1 and the second region A2, a point which will not be discussed further here. In this case, an optimized line width design can also be achieved, and customized line widths as well as differentiated line width designs that adapt to the spatial allocation can be obtained in this embodiment.

[0307] It is evident that the in Fig. 28 to Fig. The embodiments shown in Figure 30 merely illustrate the line width design scheme for signal lines extending along the column direction, where the first region A1 is the gap region between pixel circuits in adjacent sub-pixel rows and the second region A2 is the region in which the pixel circuits are located in the sub-pixel rows.Based on the specific implementations of the aforementioned embodiments of the present innovation, if the first region A1 is the gap region between closely spaced sub-scanning lines and the second region A2 is the region outside this gap, or if the first region A1 is the region within the first annular structure on the first sub-scanning line and the second region A2 is the region outside the first annular structure, differentiated line widths can also be set for the signal lines extending along the gap direction in these two regions. All variants achieved on this basis fall within the scope of protection of the present innovation.

[0308] Based on the same conceptual foundation, embodiments of the present innovation also provide a display device. Fig. Figure 31 is a schematic representation of the structure of a display device according to an embodiment of the present innovation. As shown in Fig. As shown in Figure 31, the display device comprises the display panel 1 according to any embodiment of the present innovation. Thus, the display device provided by the embodiments of the present innovation exhibits the corresponding advantageous effects of the display panel provided by the embodiments of the present innovation, which will not be discussed again here. For example, the display device may be a mobile phone, a smart wearable device (such as a smartwatch), a vehicle-mounted display device, a computer, a television, or any other electronic device, which is not limited in the embodiments of the present innovation.

[0309] It should be noted that the foregoing merely describe preferred embodiments of the present innovation and the technical principles employed therein. Those skilled in the art will understand that the present innovation is not limited to the embodiments described herein. Various obvious modifications, adaptations, combinations, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present innovation. Therefore, although the present innovation has been described in detail with reference to the foregoing embodiments, it is not limited to these embodiments and may include further equivalent embodiments without departing from the concept of the present innovation. The scope of protection of the present innovation is determined by the scope of the appended claims.

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