Display substrate and display device

Abstract

A display substrate includes a substrate, a plurality of first circuit groups, at least one first connection line group and at least one second connection line group. The substrate includes a display area and a binding area located at one side of the display area. The plurality of first circuit groups, the at least one first connection line group and the at least one second connection line group are located in the binding area. The plurality of first circuit groups are arranged along a first direction. At least two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a first connection line group and a second connection line group. In the first connection line group and the second connection line group, the first connection lines and the second connection lines transmitting the same signal are connected in parallel, and the at least one second connection line group is located at a side of the at least one first connection line group close to the display area.

Description

TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. SUMMARY

[0003] The following is an overview of subject matter of the detailed description herein. This overview is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] In one aspect, the present embodiments provide a display substrate, comprising: a substrate, a plurality of first circuit groups, at least one group of first connection lines and at least one group of second connection lines. The substrate comprises a display area and a binding area located at one side of the display area. The plurality of first circuit groups, the at least one group of first connection lines and the at least one group of second connection lines are located in the binding area. The plurality of first circuit groups are arranged along a first direction. At least two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a group of first connection lines and a group of second connection lines. In the group of first connection lines and the group of second connection lines, the first connection lines and the second connection lines transmitting the same signal are connected in parallel, and the at least one group of second connection lines is located at a side of the at least one group of first connection lines close to the display area.

[0006] In some example embodiments, two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a group of first connection lines and a group of second connection lines.

[0007] In some example embodiments, any two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a group of first connection lines and a group of second connection lines.

[0008] In some example embodiments, the binding area comprises: a first sub-area, a bending area and a second sub-area arranged in sequence along a direction away from the display area. The plurality of first circuit groups and the at least one group of first connection lines are located in the second sub-area, and the at least one group of second connection lines is located in the first sub-area.

[0009] In some example embodiments, the bending region comprises a plurality of bending transition lines, and each of the second connection lines is electrically connected to a corresponding first connection line of the first connection lines via a bending transition line.

[0010] In some example embodiments, in a direction perpendicular to the display substrate, the plurality of bending transition lines are located on a side of the at least one first connection line and the at least one second connection line away from the substrate.

[0011] In some example embodiments, the first sub-region further comprises a plurality of groups of first fan-out wires arranged along the first direction, and a second connection line is arranged between two adjacent groups of first fan-out wires, and a projection of the second connection line on the substrate does not overlap with projections of the two adjacent groups of first fan-out wires on the substrate.

[0012] In some example embodiments, at least one of the first connection lines comprises a first wire segment, a second wire segment, and a third wire segment electrically connected in sequence, the second wire segment extends along the first direction, the first wire segment is electrically connected to one of the first circuit groups, and the third wire segment is electrically connected to another of the first circuit groups.

[0013] In some example embodiments, the second sub-region further comprises a plurality of first electrostatic discharge circuits, the first wire segment, the second wire segment, and the third wire segment of at least one of the first connection lines are each electrically connected to one of the first electrostatic discharge circuits, the first electrostatic discharge circuit electrically connected to the first wire segment is located on a side of the first wire segment close to the third wire segment, the first electrostatic discharge circuit electrically connected to the second wire segment is located on a side of the second wire segment close to the bending region, and the first electrostatic discharge circuit electrically connected to the third wire segment is located on a side of the third wire segment close to the first wire segment.

[0014] In some example embodiments, at least one of the second connection lines comprises a fourth wire segment, a fifth wire segment, and a sixth wire segment electrically connected in sequence, the fifth wire segment extends along the first direction, the fourth wire segment and the sixth wire segment are located on a side of the fifth wire segment away from the display region, and a length of the fifth wire segment along the first direction is less than a shortest distance between the first wire segment and the third wire segment of the first connection line electrically connected by the second connection line.

[0015] In some example embodiments, the display substrate further comprises a buffer layer located on a side of the substrate away from the plurality of first circuit groups; at least one set of second connection lines electrically connected to at least one set of first connection lines partially overlap in the projection of the substrate.

[0016] In some example embodiments, the display substrate further comprises a plurality of binding pin groups located in the binding area, the plurality of binding pin groups located on a side of the plurality of first circuit groups away from the display area and electrically connected to the plurality of first circuit groups.

[0017] In some example embodiments, the display substrate further comprises a plurality of driving chip pin groups located in the binding area, the plurality of driving chip pin groups located on a side of the plurality of first circuit groups away from the display area and located on a side of the plurality of binding pin groups close to the display area.

[0018] In some example embodiments, the display area comprises a plurality of sub-pixels and a plurality of data lines electrically connected to the plurality of sub-pixels. At least one first circuit group of the plurality of first circuit groups comprises a plurality of test circuits connected to the plurality of data lines and configured to provide test data signals to the plurality of data lines in a test phase.

[0019] In another aspect, the present embodiment provides a display device comprising the display substrate as described above.

[0020] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of one or more components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0022] Figure 1 FIG. 1 is a structural schematic diagram of a display device;

[0023] Figure 2 FIG. 2 is a plan schematic diagram of a display substrate;

[0024] Figure 3 FIG. 3 is a partial cross-sectional structural schematic diagram of a display area of a display substrate;

[0025] Figure 4 FIG. 4 is a schematic diagram of a binding area of a display substrate;

[0026] Figure 5 This is a schematic diagram of the display substrate after the bending process;

[0027] Figure 6 This is a schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0028] Figure 7A This is an example diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 7B for Figure 7A A partial schematic diagram of the binding area in the diagram;

[0030] Figure 8 This is a partial schematic diagram of the binding area according to at least one embodiment of the present disclosure;

[0031] Figure 9 An equivalent circuit diagram of a test circuit according to at least one embodiment of this disclosure;

[0032] Figure 10 This is a plan view of a test circuit according to at least one embodiment of the present disclosure;

[0033] Figure 11 This is a schematic diagram showing the connection positions of a first circuit group and a set of first connecting lines according to at least one embodiment of the present disclosure;

[0034] Figure 12 for Figure 11 A magnified view of a portion of the central region U1;

[0035] Figure 13 This is a schematic diagram showing the connection position of the first and second traces of the first connecting line according to at least one embodiment of the present disclosure;

[0036] Figure 14 This is a schematic diagram showing the connection position between the fourth trace of the second connecting line and the bent connecting line in at least one embodiment of this disclosure;

[0037] Figure 15A for Figure 14 A schematic diagram of the first gate metal layer in the diagram;

[0038] Figure 15B for Figure 14 A schematic diagram of the second gate metal layer in the diagram;

[0039] Figure 16 This is another schematic diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure. Detailed Implementation

[0040] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. The embodiments can be implemented in various different forms. It is to be understood that the embodiments and features of the present disclosure can be arbitrarily combined with each other unless otherwise specified and limited. Thus, the present disclosure should not be construed as being limited to only the following embodiments.

[0041] In the drawings, the size, the thickness or the region of one or more constituent elements or layers is sometimes exaggerated for clarity. Thus, one embodiment of the present disclosure should not be construed as being limited to the size, the shape or the relative arrangement of the components illustrated in the drawings. The same reference numerals in different drawings denote the same or similar components.

[0042] In the present specification, the ordinal numbers such as "first", "second" and "third" are used to avoid confusion among constituent elements, and are not used to constitute a limitation on the number thereof in the specification. "A plurality of" in the present disclosure means two or more.

[0043] In the present specification, the words "over", "above", "under", "below", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like used to describe the positional relationship of the constituent elements with reference to the drawings are used to explain the positional relationship of the constituent elements in the drawings, and are merely used only for the convenience of describing the present specification and simplifying the description, and thus cannot be understood as indicating or implying that a particular orientation, configuration and operation of the devices or elements are necessary, and therefore cannot be understood as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Thus, the words described in the specification are not limited, and can be appropriately replaced according to the situation.

[0044] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements. Those skilled in the art can understand the meaning of the above terms in the present disclosure according to the situation.

[0045] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as the transmission of an electrical signal between the elements to be connected is possible. Examples of the element having a certain electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having a variety of functions, and the like.

[0046] In this specification, a transistor means an element including a gate, a drain, and a source. The transistor has a channel region between the drain (a drain electrode terminal, a drain region, or a drain electrode) and the source (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region means a region where current flows mainly.

[0047] In this specification, the first terminal can be a drain and the second terminal can be a source, or the first terminal can be a source and the second terminal can be a drain. The functions of the "source" and the "drain" are sometimes interchangeable with each other in this specification, depending on the direction in which current flows. Therefore, the "source" and the "drain" can be interchanged with each other in this specification. In addition, the gate can also be referred to as a control terminal.

[0048] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0049] In this specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can include some small deformations due to a tolerance, such as a fillet, a rounded corner, and a deformation.

[0050] In this specification, "about" and "approximately" mean that a certain range is not strictly limited, and a range within a process and measurement error is allowed. In this specification, "substantially the same" means that the difference between numerical values is within 10 %.

[0051] In the present disclosure, A extends along a direction of B means that A can include a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment or a bar-shaped body, the main portion stretches along the direction of B, and the length of the main portion stretching along the direction of B is greater than the length of the secondary portion stretching along other directions. In the present disclosure, A extending along the direction of B refers to A main portion extending along the direction of B.

[0052] Figure 1 A structural schematic diagram of a display device. In some examples, as shown in Figure 1 The display device can include a timing controller 21, a data driver 22, a scan driving circuit 23, a light emitting driving circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 can include a plurality of sub-pixels PX arranged regularly. The scan driving circuit 23 can be configured to provide a scan signal to the sub-pixels PX along a scan line; the data driver 22 can be configured to provide a data voltage to the sub-pixels PX along a data line; the light emitting driving circuit 24 can be configured to provide a light emitting control signal to the sub-pixels PX along a light emitting control line; and the timing controller 21 can be configured to control the scan driving circuit 23, the light emitting driving circuit 24 and the data driver 22.

[0053] In some examples, as shown in Figure 1As shown, the timing controller 21 can provide grayscale values and control signals suitable for the specifications of the data driver 22 to the data driver 22; the timing controller 21 can provide a scan clock signal, a scan start signal, and the like suitable for the specifications of the scan driving circuit 23 to the scan driving circuit 23; the timing controller 21 can provide a light emission clock signal, a light emission start signal, and the like suitable for the specifications of the light emission driving circuit 24 to the light emission driving circuit 24. The data driver 22 can generate data voltages to be provided to the data lines D1 to Di using the grayscale values and the control signals received from the timing controller 21. For example, the data driver 22 can sample the grayscale values using the clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Di in units of sub-pixels. The scan driving circuit 23 can generate scan signals to be provided to the scan lines S1 to Sj by the scan clock signal, the scan start signal, and the like received from the timing controller 21. For example, the scan driving circuit 23 can sequentially provide scan signals having on-pulse to the scan lines. In some examples, the scan driving circuit 23 can include a shift register, and can generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the scan clock signal. The light emission driving circuit 24 can generate light emission control signals to be provided to the light emission control lines E1 to Eo by the light emission clock signal, the light emission start signal, and the like received from the timing controller 21. For example, the light emission driving circuit 24 can sequentially provide light emission control signals having off-pulse to the light emission control lines. The light emission driving circuit 24 can include a shift register to generate the light emission control signals in a manner that sequentially transfers the light emission start signal provided in the form of an off-pulse to a next stage circuit under the control of the clock signal. Here, i, j, and o are all natural numbers.

[0054] In some examples, the display apparatus can include a display substrate. The sub-pixel array, the scan driving circuit, and the light emission driving circuit can be directly disposed on the display substrate. For example, the scan driving circuit can be disposed at a left bezel of the display substrate, and the light emission driving circuit can be disposed at a right bezel of the display substrate; or, the scan driving circuit and the light emission driving circuit can be disposed at both the left bezel and the right bezel of the display substrate. In some examples, the scan driving circuit and the light emission driving circuit can be formed together with the sub-pixels in a process of forming the sub-pixels.

[0055] In some examples, the data driver can be disposed on a separate chip or printed circuit board. For example, the data driver can be formed in a chip on glass, a chip on plastic, a chip on film, or the like, and disposed at a lower bezel of the display substrate to be connected to driving chip pins. The timing controller can be disposed separately from the data driver or integrally with the data driver. However, the present embodiment is not limited thereto.

[0056] Figure 2This is a planar schematic diagram of a display substrate. In some examples, such as... Figure 2 As shown, the display substrate may include: a display area AA, a bonding area B1 located on one side of the display area AA, and a border area B2 located on the other sides of the display area AA. The bonding area B1 may be, for example, the bottom border of the display substrate, and the border area B2 may include the top border, left border, and right border of the display substrate. In some examples, the display area AA may be a flat area comprising multiple sub-pixels PX forming a pixel array, the multiple sub-pixels PX being configured to display moving or still images. The display area may be referred to as the effective area. In some examples, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0057] In some examples, the border region B2 may include a circuit region, a power line region, a crack dam region, and a cutting region arranged sequentially along the direction of the display region AA. The circuit region may be connected to the display region AA and may include at least multiple cascaded gate drive circuits electrically connected to multiple gate lines in the display region AA. The power line region is connected to the circuit region and may include at least low-level power lines extending parallel to the edge of the display region and connected to the cathode of the display region. The crack dam region may be connected to the power line region and may include at least multiple cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least cutting grooves formed on the composite insulating layer. These cutting grooves can be configured to cut along the cutting grooves after all film layers of the display substrate have been prepared.

[0058] In some examples, the binding area B1 and the border area B2 can be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam can extend along a direction parallel to the edge of the display area to form a ring structure around the display area AA. The edge of the display area is the edge of the display area closer to the binding area B1 or the border area B2.

[0059] In some examples, such as Figure 2As shown, the display region AA can include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL can extend along a first direction X, and the plurality of data lines DL can extend along a second direction Y. The orthogonal projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate substrate cross to form a plurality of sub-pixel regions, and one sub-pixel PX is arranged in each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines DL can extend to the bonding region B1. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL can be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals can include scan signals and light-emitting control signals.

[0060] In some examples, as shown in FIG. 1A, the first direction X can be the extension direction (row direction) of the gate lines GL in the display region AA, and the second direction Y can be the extension direction (column direction) of the data lines DL in the display region AA. The first direction X and the second direction Y can be perpendicular to each other. Figure 2

[0061] In some examples, one pixel unit of the display region AA can include three sub-pixels, which are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, the present embodiments are not limited thereto. In some examples, one pixel unit can include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.

[0062] In some examples, the shape of a sub-pixel can be rectangular, rhombic, pentagonal, or hexagonal. When one pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner. When one pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner. However, the present embodiments are not limited thereto.

[0063] In some examples, one sub-pixel can include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor, for example, a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0064] ​In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiment is not limited thereto.

[0065] Figure 3 A schematic diagram of a partial cross-sectional structure of a display area of a display substrate. Figure 3 The structure of three sub-pixels of the display substrate is illustrated. In some examples, as shown in Figure 3 In the direction perpendicular to the display substrate, the display substrate can include a substrate 101, and a circuit structure layer 102, a light emitting structure layer 103, an encapsulation structure layer 104, and an encapsulation cover plate 200 arranged in sequence on the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a spacer, a touch structure layer, etc., which are not limited in the present disclosure.

[0066] In some examples, the substrate 101 can be a rigid substrate, for example, a glass substrate. However, the present embodiment is not limited thereto. For example, the substrate can be a flexible substrate, for example, prepared from an insulating material such as resin. In addition, the substrate can be a single-layer structure or a multi-layer structure. When the substrate is a multi-layer structure, for example, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be disposed between multiple layers in a single layer or multiple layers.

[0067] In some examples, the circuit structure layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel circuit, Figure 3The illustration uses an example of each sub-pixel containing a transistor and a storage capacitor. In some possible implementations, the circuit structure layer 102 of each sub-pixel may include: an active layer disposed on a substrate 101; a first insulating layer 11 (or a first gate insulating layer) covering the active layer; a first gate metal layer (e.g., including the gate electrode and first capacitor electrode of a transistor) disposed on the first insulating layer 11; a second insulating layer 12 (or a second gate insulating layer) covering the first gate metal layer; a second gate metal layer (e.g., including a second capacitor electrode) disposed on the second insulating layer 12; a third insulating layer 13 (or an interlayer insulating layer) covering the second gate metal layer, wherein a plurality of first vias are formed on the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13, and the plurality of first vias can expose the active layer; a first source / drain metal layer (e.g., including the source electrode and drain electrode of a transistor) disposed on the third insulating layer 13, wherein the source electrode and drain electrode can be connected to the active layer through the first vias respectively; and a first planarization layer 14 covering the aforementioned structure, wherein a second via is formed on the first planarization layer 14, and the second via can expose the drain electrode. The active layer, gate electrode, source electrode, and drain electrode can form a transistor 105, and the first capacitor electrode and the second capacitor electrode can form a storage capacitor 106.

[0068] In some examples, such as Figure 3 As shown, the light-emitting structure layer 103 may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer may include the anode of the light-emitting element, which may be disposed on the first planarization layer 14 and electrically connected to the drain electrode of the transistor of the pixel circuit through a second via formed in the first planarization layer 14; the pixel definition layer is disposed on the anode layer and the first planarization layer, and the pixel definition layer has a pixel opening that exposes at least a portion of the surface of the anode; the organic light-emitting layer is at least partially disposed within the pixel opening and is connected to the anode; the cathode is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer; the organic light-emitting layer emits light of the corresponding color under the drive of the anode and the cathode.

[0069] In some examples, such as Figure 3 As shown, the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0070] In some examples, the organic light-emitting layer can include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode. In some examples, the hole injection layer of all the sub-pixels can be a common layer connected together, the hole transport layer of all the sub-pixels can be a common layer connected together, the light-emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the hole blocking layer can be a common layer connected together. However, the present embodiments are not limited thereto.

[0071] Figure 4 A schematic view of a binding area of a display substrate. Figure 4 A schematic view of a display substrate before a bending process is performed. In some examples, as shown in FIG. 1A, the display substrate can include a display area AA and a binding area B1. The display area AA can include a plurality of sub-pixels. The binding area B1 can be located on a side of the display area AA. The binding area B1 can be configured to be bent to a back side of the display area AA. Figure 4 As shown, the binding area B1 of the display substrate can include a first fan-out region B11, a bending region B12, a second fan-out region B13, a first circuit region B14, a third fan-out region B15, a driving chip region B16, and a binding pin region B10 arranged in sequence along a direction away from the display area AA. The first fan-out region B11 can be connected to the display area AA. The first fan-out region B11 can include at least a first power line, a second power line, and a plurality of data lines, and the plurality of data lines can be configured to extend in a fan-out wiring manner from the data lines of the display area AA. The first power line of the first fan-out region B11 can be configured to connect a high-level power line of the display area, and the second power line can be configured to connect a low-level power line of the frame area. The bending region B12 is connected between the first fan-out region B11 and the second fan-out region B13, and can be configured to bend the binding area B1 to the back side of the display area AA. The first circuit region B14 can include at least a plurality of first circuit groups 41. The plurality of first circuit groups 41 can be arranged side by side along the first direction X. Each first circuit group 41 can include a plurality of test circuits, and the test circuits can be configured to be electrically connected to the plurality of data lines of the display area AA and provide test data signals to the plurality of data lines of the display area AA in a test stage. The driving chip region B16 can include a plurality of driving chip pin groups 42. The plurality of driving chip pin groups 42 can be electrically connected to the plurality of data lines and configured to be bound with at least one driving chip (IC, Integrated Circuit). For example, each driving chip pin group 42 can be configured to be bound with one driving chip. The driving chip can be configured to generate a driving signal required for driving the sub-pixel and provide the driving signal to the data line of the display area. For example, the driving signal can be a data signal for driving the sub-pixel. The binding pin region B10 can include a plurality of binding pin groups 43, and each binding pin group 43 can include a plurality of binding pins arranged in sequence along the first direction X. Each binding pin group 43 can be configured to be bound and connected with a corresponding at least one circuit board (for example, a flexible printed circuit (FPC)).

[0072] Figure 5 This is a schematic diagram of the display substrate after the bending process. In some examples, such as... Figure 5 As shown, after the display substrate undergoes a bending process, the area of ​​the bending region away from the display area AA (e.g., including the first circuit area, the third fan-out area, the driver chip area, and the bonding pin area) can be bent to the back side of the display area AA. In this way, the orthographic projection of the first circuit group 41, the driver chip pin group 42, and the bonding pin group 43 onto the substrate can overlap with the display area AA. Figure 5 The shaded area of ​​the bonding region B1 indicates the location of the foam. In the bending process of the display substrate, attaching foam to the back of the substrate provides support, thereby improving its bending resistance. The inventors of this application have discovered that in the bending process of medium-to-large-sized narrow-bezel display substrates, multi-segment foam is used, with a gap F1 between each segment. The length of gap F1 along the first direction X is approximately 1 millimeter (mm). After bending, the bonding region of the display substrate lacks support at the corresponding gap F1 position, posing a risk of breakage to the traces on the bonding region at this gap F1 position, thus affecting the yield of the display substrate.

[0073] This embodiment provides a display substrate, including: a substrate, a plurality of first circuit groups, at least one set of first connecting lines, and at least one set of second connecting lines. The substrate includes a display area and a bonding area located on one side of the display area. The plurality of first circuit groups, at least one set of first connecting lines, and at least one set of second connecting lines are located in the bonding area. The plurality of first circuit groups are arranged along a first direction. At least two adjacent first circuit groups are electrically connected through a set of first connecting lines and a set of second connecting lines. In the set of first connecting lines and the set of second connecting lines, the first connecting lines and the second connecting lines that transmit the same signal are connected in parallel, and the at least one set of second connecting lines is located on the side of the at least one set of first connecting lines closer to the display area.

[0074] The display substrate provided in this embodiment can provide double protection for signal transmission between adjacent first circuit groups by setting a first connecting line and a second connecting line connected in parallel between adjacent first circuit groups. By ensuring that at least one of the first connecting line and the second connecting line is conductive, the yield loss of the display substrate caused by the breakage of the bonding area during the bending process can be effectively avoided.

[0075] In this embodiment, the parallel connection of A and B can represent a connection in which the beginnings of A and B are connected together, and the end-to-end connections are also connected.

[0076] In some example embodiments, two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a set of first connection lines and a set of second connection lines. In this example, the two adjacent first circuit groups can be connected by the first connection lines and the second connection lines, and the remaining adjacent first circuit groups can be connected by the first connection lines only. This example can be applicable to a case where two sections of foam are used (i.e., only one foam gap exists).

[0077] In some example embodiments, any two adjacent first circuit groups in the plurality of first circuit groups can be electrically connected by a set of first connection lines and a set of second connection lines. In this example, all adjacent first circuit groups are connected by the first connection lines and the second connection lines. This example can be applicable to a case where multiple sections of foam are used (e.g., multiple foam gaps exist).

[0078] In some example embodiments, the binding area can include a first sub-area, a bending area, and a second sub-area arranged in sequence in a direction away from the display area. The plurality of first circuit groups and the at least one set of first connection lines can be located in the second sub-area, and the at least one set of second connection lines can be located in the first sub-area. For example, the first sub-area can include a first fan-out area, and the second sub-area can include a second fan-out area, a first circuit area, a third fan-out area, a driving chip area, and a binding pin area. However, the present embodiments are not limited thereto. In this example, by arranging the second connection lines in the first sub-area, the second connection lines can not be bent to the back of the display area in the bending process, and the second connection lines can be attached to the cover plate, thereby being free from the influence of the foam gap to ensure signal transmission of the second connection lines.

[0079] In some example embodiments, the display area includes a plurality of sub-pixels and a plurality of data lines, and the plurality of data lines are electrically connected to the plurality of sub-pixels. At least one first circuit group in the plurality of first circuit groups can include a plurality of test circuits, and the plurality of test circuits can be electrically connected to the plurality of data lines and configured to provide test data signals to the plurality of data lines in a test phase.

[0080] The scheme of the present embodiments is illustrated below by some examples.

[0081] Figure 6 A schematic diagram of a display substrate of at least one embodiment of the present disclosure is shown. In some examples, as shown in FIG. 1, the display substrate includes a display area 100, a binding area 200, and a bending area 300. The display area 100 includes a plurality of sub-pixels 110 and a plurality of data lines 120. The plurality of data lines 120 are electrically connected to the plurality of sub-pixels 110. The binding area 200 includes a plurality of first circuit groups 210 and a plurality of second circuit groups 220. The plurality of first circuit groups 210 are electrically connected to the plurality of second circuit groups 220. The bending area 300 is arranged between the display area 100 and the binding area 200. Figure 6As shown, the binding area B1 of the display substrate can include, in sequence along the direction away from the display area AA, a first fan-out area B11, a bending area B12, a second fan-out area B13, a first circuit area B14, a third fan-out area B15, a driving chip area B16, and a binding pin area B10. The first circuit area B14 can include a plurality of first circuit groups (for example, including four first circuit groups 41a, 41b, 41c, and 41d). The four first circuit groups 41a, 41b, 41c, and 41d can be arranged in sequence along the first direction X. The driving chip area B16 can include a plurality of driving chip pin groups (for example, including four driving chip pin groups 42a, 42b, 42c, and 42d). The four driving chip pin groups 42a, 42b, 42c, and 42d can be arranged in sequence along the first direction X. The binding pin area B10 can include a plurality of binding pin groups (for example, including four binding pin groups 43a, 43b, 43c, and 43d). The four binding pin groups 43a, 43b, 43c, and 43d can be arranged in sequence along the first direction X. In the present example, the number of first circuit groups, driving chip pin groups, and binding pin groups can be the same. One first circuit group corresponds to one driving chip pin group, one first circuit group corresponds to one binding pin group, and one driving chip pin group corresponds to one binding pin group. For example, the first circuit group 41a, the driving chip pin group 42a, and the binding pin group 43a correspond to each other, the first circuit group 41b, the driving chip pin group 42b, and the binding pin group 43b correspond to each other, the first circuit group 41c, the driving chip pin group 42c, and the binding pin group 43c correspond to each other, and the first circuit group 41d, the driving chip pin group 42d, and the binding pin group 43d correspond to each other.

[0082] In some examples, as shown in FIG. 6, the first circuit groups can be electrically connected through the first connection lines, thereby ensuring consistency of signal transmission and further ensuring uniformity of the display area. For example, the first circuit group 41a and the first circuit group 41b can be electrically connected through the first connection line 51a, the first circuit group 41b and the first circuit group 41c can be electrically connected through the first connection line 51b, and the first circuit group 41c and the first circuit group 41d can be electrically connected through the first connection line 51c. The first circuit group 41b and the first circuit group 41c can also be electrically connected through the second connection line 52b. The present example can be applicable to the case shown in FIG. 5, and the case of wire breakage caused by the foam gap F1 can be improved by providing the second connection line 52b. Figure 6 Figure 5 In some examples, as shown in FIG. 6, the first circuit groups can be electrically connected through the first connection lines, thereby ensuring consistency of signal transmission and further ensuring uniformity of the display area. For example, the first circuit group 41a and the first circuit group 41b can be electrically connected through the first connection line 51a, the first circuit group 41b and the first circuit group 41c can be electrically connected through the first connection line 51b, and the first circuit group 41c and the first circuit group 41d can be electrically connected through the first connection line 51c. The first circuit group 41b and the first circuit group 41c can also be electrically connected through the second connection line 52b. The present example can be applicable to the case shown in FIG. 5, and the case of wire breakage caused by the foam gap F1 can be improved by providing the second connection line 52b. Figure 5 Figure 6 ​​As shown, a buffer layer (e.g., foam) can be provided on the back side of the substrate. The orthographic projections of the second connection line 52b and the first connection line 51b on the substrate can partially overlap with the buffer layer. The orthographic projection of the first connection line 51b on the substrate is not completely covered by the buffer layer. Due to the foam gap F1 in the buffer layer, the trace may break. By setting the second connection line 52b in the first fan-out area B11, the second connection line 52b does not need to be bent to the back side of the display area and does not need to be supported by the buffer layer, which can ensure the stability of signal transmission and thus improve the yield of the display substrate.

[0083] In some examples, such as Figure 6 As shown, the second connecting line 52b and the first connecting line 51b can be connected in parallel. The second connecting line 52b can be located in the first fan-out area B11, and the first connecting line 51b can be located on the side of the bending area B12 away from the display area AA. The first connecting line 51b can be located between the first circuit groups 41b and 41c in the first direction X. One end of the second connecting line 52b can be electrically connected to one end of the first connecting line 51b through a bent connecting line 53a, and the other end of the second connecting line 52b can be electrically connected to the other end of the first connecting line 51b through another bent connecting line 53b, thus realizing the parallel connection of the first connecting line 51b and the second connecting line 52b that transmit the same signal.

[0084] Figure 7A This is an example diagram of the bonding area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 7B for Figure 7A A partial schematic diagram of the binding region. In some examples, such as... Figure 7A and Figure 7B As shown, the first fan-out area B11 further includes multiple sets of first fan-out traces 61. These multiple sets of first fan-out traces 61 can be arranged along a first direction X. Each set of first fan-out traces 61 can include multiple first fan-out traces, which can include data extensions of multiple data lines within the display area to the binding area. The multiple first fan-out traces within each set of first fan-out traces 61 extend towards the middle position of the corresponding first circuit group. The second connecting line 52b can be located between two adjacent sets of first fan-out traces, for example, between two sets of first fan-out traces electrically connected to first circuit groups 41b and 41c. The orthographic projection of the second connecting line 52b onto the substrate does not overlap with the orthographic projections of the two adjacent sets of first fan-out traces onto the substrate.

[0085] In some examples, such as Figure 7A and Figure 7BAs shown, the binding area B1 can include a plurality of first power lines PL1 and a plurality of second power lines PL2. One binding pin group (e.g., the binding pin group 43b) in the binding pin area B10 can be electrically connected with two second power lines PL2 and one first power line PL1, the first power line PL1 can be located between the two second power lines PL2 in the first direction X. For example, the first power line PL1 can be electrically connected with a first power pin of the binding pin group in the binding pin area B10, and the second power line PL2 can be electrically connected with a second power pin in the binding pin group. In some examples, the first power line PL1 and the second power line PL2 can be single-layer wires, for example, can be located in the first source-drain metal layer or the second source-drain metal layer; or, the first power line PL1 and the second power line PL2 can be double-layer wires, for example, can be a laminated structure wire of the first source-drain metal layer and the second source-drain metal layer. The present embodiment is not limited thereto.

[0086] As shown in FIG. 1, the driving chip 10 can include a plurality of driving chip pin groups 41, and the binding area 11 can include a plurality of binding pin groups 43. In some examples, the driving chip pin groups 41 and the binding pin groups 43 can be arranged in a one-to-one correspondence manner. Figure 7A and Figure 7B As shown, the pins in the driving chip pin group can be electrically connected with the pins in the corresponding binding pin group through the pin connection lines. The pin connection lines can extend substantially along the second direction Y, and can be arranged in sequence along the first direction X. The present embodiment is not limited thereto.

[0087] Figure 6 to Figure 7B The first connection line and the second connection line are illustrated by taking one signal transmission between adjacent first circuit groups as an example in FIG. 3. Figure 8 A partial view of the binding area of at least one embodiment of the present disclosure. Figure 8 A group of first connection lines and a group of second connection lines between adjacent first circuit groups are illustrated in FIG. 3. The group of first connection lines can include a plurality of first connection lines 51b with substantially the same extension direction, and the group of second connection lines can include a plurality of second connection lines 52b with substantially the same extension direction. In some examples, the first connection lines 51b and the second connection lines 52b can be arranged in sequence along the first direction X. Figure 8 The first connection line and the second connection line are illustrated by taking the labels of one first connection line and one second connection line as an example in FIG. 3.

[0088] As shown in FIG. 1, the driving chip 10 can include a plurality of driving chip pin groups 41, and the binding area 11 can include a plurality of binding pin groups 43. In some examples, the driving chip pin groups 41 and the binding pin groups 43 can be arranged in a one-to-one correspondence manner. Figure 8As shown, one first connection line 51b can include a first wire segment 511, a second wire segment 512 and a third wire segment 513 connected in sequence. The second wire segment 512 can extend along the first direction X, and two ends of the second wire segment 512 can be electrically connected with the first wire segment 511 and the third wire segment 513 respectively. For example, the second wire segment 512 can be electrically connected with the first wire segment 511 through a first jumper, and can be electrically connected with the third wire segment 513 through a second jumper. The first wire segment 511 can include a first extension segment and a second extension segment electrically connected with each other; the first extension segment can extend along the second direction Y and be electrically connected with the second connection line 52b through a bending adapter 53a; and the second extension segment can extend at least along the first direction X and be electrically connected with one first circuit group. The third wire segment 513 can include a third extension segment and a fourth extension segment electrically connected with each other; the third extension segment can extend along the second direction Y and be electrically connected with the second connection line 52b through a bending adapter 53b; and the fourth extension segment can extend at least along the first direction X and be electrically connected with another first circuit group. In some examples, the first wire segment 511, the second wire segment 512 and the third wire segment 513 of one first connection line 51b can be in the same layer structure, for example, in the first gate metal layer or the second gate metal layer. The first jumper and the second jumper can be in the same layer structure, for example, in the first source-drain metal layer.

[0089] In some examples, as Figure 8As shown, one second connection line 52b can include fourth, fifth and sixth wire segments 521, 522 and 523 connected in sequence. The fifth wire segment 522 can extend along the first direction X and be located at one side of the fourth and sixth wire segments 521 and 523 close to the display area. The fourth and sixth wire segments 521 and 523 are located at one side of the fifth wire segment 522 close to the bending area B12. The extension direction of the fourth wire segment 521 can be substantially the same as that of the adjacent first fan-out wire, and the extension direction of the sixth wire segment 523 can be substantially the same as that of the adjacent first fan-out wire. The fourth and sixth wire segments 521 and 523 can be substantially symmetrical about the middle line of the fifth wire segment 522 along the first direction X. One end of the fourth wire segment 521 can be electrically connected with the bending connection line 53a, and the other end can be electrically connected with one end of the fifth wire segment 522; one end of the sixth wire segment 523 can be electrically connected with the bending connection line 53b, and the other end can be electrically connected with the other end of the fifth wire segment 522. In some examples, the length of the fifth wire segment 522 of the second connection line 52b along the first direction X can be less than the shortest distance between the first and third wire segments 511 and 513 of the first connection line 51b to which the second connection line 52b is electrically connected. In some examples, the fourth, fifth and sixth wire segments 521, 522 and 523 of one second connection line 52b can be an integral structure, for example, located in the first gate metal layer or the second gate metal layer. However, the present embodiment is not limited thereto.

[0090] In some examples, as Figure 8As shown, the binding area can further include a plurality of first electrostatic discharge circuit groups (e.g., first electrostatic discharge circuit groups 581, 582, and 583). The first electrostatic discharge circuit groups 581, 582, and 583 can be located on a side of the bending area B12 away from the display area. Each first electrostatic discharge circuit group can include a plurality of first electrostatic discharge circuits. For example, the plurality of first electrostatic discharge circuits in the first electrostatic discharge circuit group 581 can be respectively electrically connected to the second wire segments 512 of the plurality of first connection lines 51b and configured to discharge static electricity of the second wire segments 512, the first electrostatic discharge circuits electrically connected to the second wire segments 512 can be located on a side of the second wire segments 512 close to the bending area B12; the plurality of first electrostatic discharge circuits in the first electrostatic discharge circuit group 582 can be respectively electrically connected to the first wire segments 511 of the plurality of first connection lines 51b, the first electrostatic discharge circuits electrically connected to the first wire segments 511 can be located on a side of the first wire segments 511 close to the third wire segments 513; and the plurality of first electrostatic discharge circuits in the first electrostatic discharge circuit group 583 can be respectively electrically connected to the third wire segments 513 of the plurality of first connection lines 51b, the first electrostatic discharge circuits electrically connected to the third wire segments 513 can be located on a side of the third wire segments 513 close to the first wire segments 511. The position setting manner of the first electrostatic discharge circuits in the present example can avoid affecting the arrangement of the first connection lines and is conducive to improving the space utilization. The present example is not limited to the number and position of the first electrostatic discharge circuits. The present example is conducive to discharging static electricity of the first connection lines and the second connection lines by setting a plurality of first electrostatic discharge circuit groups, thereby avoiding static electricity interference.

[0091] Figure 9 Equivalent circuit diagram of the test circuit of at least one embodiment of the present disclosure. In some examples, the first circuit group of the binding area can include a plurality of test circuits 40. The test circuit 40 can include a plurality of test transistors (e.g., including a first test transistor 44a, a second test transistor 44b, and a third test transistor 44c). As shown, the first test transistor 44a can be electrically connected to the second test transistor 44b and the third test transistor 44c. Figure 9As shown, the gate of the first test transistor 44a, the gate of the second test transistor 44b and the gate of the third test transistor 44c are connected to the same test control signal line 45. The first pole of the first test transistor 44a is connected to the first test data line 46-1, the first pole of the second test transistor 44b is connected to the second test data line 46-2, and the first pole of the third test transistor 44c is connected to the third test data line 46-3. The second poles of the first test transistor 44a, the second test transistor 44b and the third test transistor 44c are respectively connected to different data lines DL in the display area. That is, the second pole of the first test transistor 44a is connected to one data line DL, the second pole of the second test transistor 44b is connected to another data line DL, and the second pole of the third test transistor 44c is connected to yet another data line DL. In this way, the conduction of the three test transistors in the test circuit 40 can be controlled by the test control signal line 45, and the signal of different test data lines can be written to different data lines DL. When testing, by providing a conduction signal to the test control signal line 45 and providing the required test data signal to the plurality of test data lines respectively, the plurality of data lines in the display area can obtain the test data signal, and the detection can be realized.

[0092] In some examples, the color of the sub-pixels connected by each data line can be the same, and the same test data signal can be provided to the data line corresponding to the sub-pixels of the same color during testing, so that the same display can be performed on these sub-pixels. By determining the color of the display image, whether there is a sub-pixel with a defect can be determined, and the sub-pixel with a defect can be located.

[0093] Figure 10 A planar schematic diagram of the test circuit of at least one embodiment of the present disclosure. Figure 10 Two test circuits arranged along the first direction X are shown. In some examples, as shown in FIG. 4, the test circuit 40 is arranged in the display area 10. The test circuit 40 is arranged in the display area 10, and the test circuit 40 is arranged in the display area 10. Figure 10As shown, the first test transistor 44a, the second test transistor 44b and the third test transistor 44c of the test circuit can be arranged in sequence along the second direction Y. The test control signal line 45, the first test data line 46-1, the second test data line 46-2 and the third test data line 46-3 can be arranged in sequence along the second direction Y and extend at least along the first direction X. The test control signal line 45, the first test data line 46-1, the second test data line 46-2 and the third test data line 46-3 can be located in the first source-drain metal layer. The active layers of the three test transistors of the test circuit and the active layers of the transistors of the pixel circuit of the sub-pixel can be in a same-layer structure. The gate of the first test transistor 44a, the gate of the second test transistor 44b and the gate of the third test transistor 44c of one test circuit can be in an integrated structure and located in the first gate metal layer, and can also be electrically connected to the test control signal line 45 located in the first source-drain metal layer. The first electrode of one first test transistor 44a can be electrically connected to the first test data line 46-1 located in the first source-drain metal layer, and the second electrode can be electrically connected to one data line DL3 located in the second gate metal layer through the connection electrode located in the first source-drain metal layer. The first electrode of one second test transistor 44b can be electrically connected to the second test data line 46-2 located in the first source-drain metal layer, and the second electrode can be electrically connected to one data line DL2 located in the first gate metal layer through the connection electrode located in the first source-drain metal layer. The first electrode of one third test transistor 44c can be electrically connected to the third test data line 46-3 located in the first source-drain metal layer, and the second electrode can be electrically connected to one data line DL1 located in the second gate metal layer through the connection electrode located in the first source-drain metal layer. The three test transistors of another test circuit can be electrically connected to the data lines DL4, DL5 and DL6 respectively.

[0094] In some examples, the test control signal line 45 and the three test data lines (e.g., the first test data line 46-1, the second test data line 46-2 and the third test data line 46-3) electrically connected to the test circuit in the first circuit group can each be electrically connected to the test circuit in the adjacent first circuit group through the first connection line (or the first connection line and the second connection line).

[0095] Figure 11 A partial schematic view of the connection positions of the first circuit group and the set of first connection lines of at least one embodiment of the present disclosure. Figure 11 A partial schematic view of the connection positions of the first circuit group and the set of first connection lines of at least one embodiment of the present disclosure. Figure 7B A partial enlarged schematic view of the middle region U0. Figure 12 A partial enlarged schematic view of the middle region U0. Figure 11 A partial enlarged schematic view of the middle region U1. Figure 13 A partial schematic view of the connection positions of the first connection line and the second connection line of at least one embodiment of the present disclosure, Figure 13 A partial schematic view of the connection positions of the first connection line and the second connection line of at least one embodiment of the present disclosure, Figure 8A partial enlarged view of the middle region U2. Figure 14 A schematic view of a connection position of a fourth routing segment of a second connection line and a bending connection line of at least one embodiment of the present disclosure, Figure 14 A schematic view of a first gate metal layer in the Figure 8 A partial enlarged view of the middle region U3. Figure 15A A schematic view of a second gate metal layer in the Figure 14 A schematic view of a first gate metal layer in the Figure 15B A schematic view of a second gate metal layer in the Figure 14 A schematic view of a second gate metal layer in the Figure 11 to Figure 15B A connection structure between a first circuit group, a first routing segment of a first connection line, and a fourth routing segment of a second connection line is illustrated. The connection structure between a sixth routing segment of the second connection line, a third routing segment of the first connection line, and another first circuit group is similar to the connection structure between the fourth routing segment of the second connection line, the first routing segment of the first connection line, and the first circuit group, and thus is not described here again. In Figure 11 to Figure 15B In the

[0096] In some examples, as shown in Figure 11 and Figure 12 The first circuit group 41a can include a plurality of test circuits 40, a plurality of second electrostatic discharge circuits 481, and a plurality of detection circuits 482. The plurality of second electrostatic discharge circuits 481 can be arranged in sequence along the first direction X, and the plurality of test circuits 40 can be arranged along the first direction X. The plurality of detection circuits 482 can be arranged in sequence along the first direction X. In the second direction Y, the plurality of test circuits 40 can be located on a side of the plurality of second electrostatic discharge circuits 481 away from the display region, and the plurality of detection circuits 482 can be located on a side of the plurality of test circuits 40 away from the display region. The detection circuit 481 can be configured to provide a signal required for picture detection to the plurality of data lines.

[0097] In some examples, as shown in Figure 11 and Figure 12 The test control signal line 45, the first test data line 46-1, the second test data line 46-2, and the third test data line 46-3 electrically connected to the plurality of test circuits 40 can each be electrically connected to the first routing segment 511 of the corresponding first connection line 51b. The test control signal line 45, the first test data line 46-1, the second test data line 46-2, and the third test data line 46-3 can extend substantially along the second direction Y to the bonding pad region and be electrically connected to the corresponding bonding pad in the bonding pad region.

[0098] In some examples, as shown in Figure 11 and Figure 12As shown, a plurality of second electrostatic discharge circuits 481 can be electrically connected with the first voltage line 471, the second voltage line 472, and the third voltage line 473. For example, the first voltage line 471 and the third voltage line 473 can be electrically connected and configured to transmit high potential voltage, and the second voltage line 472 can be configured to transmit low potential voltage. The second voltage line 472 can be located between the first voltage line 471 and the third voltage line 473 in the second direction Y. The first voltage line 471, the second voltage line 472, and the third voltage line 473 can all be located in the first source-drain metal layer. For example, the first voltage line 471 and the third voltage line 473 can be electrically connected with the second conductive line 4712 located in the first source-drain metal layer through the first conductive line 4711 and 4731 located in the first gate metal layer, respectively, and electrically connected with a corresponding first connection line 51b through the second conductive line 4712, such as the second conductive line 4712 can be electrically connected with the first trace segment 511 located in the second gate metal layer of a corresponding first connection line 51b. The second voltage line 472 can be electrically connected with the fourth conductive line 4722 located in the first source-drain metal layer and extending in the second direction Y through the third conductive line 4721 located in the first gate metal layer, and electrically connected with a corresponding first connection line 51b through the fourth conductive line 4722, such as the fourth conductive line 4722 can be electrically connected with the first trace segment 511 located in the second gate metal layer of a corresponding first connection line 51b. The second conductive line 4712 located in the first source-drain metal layer electrically connected with the first voltage line 471 and the third voltage line 473, and the fourth conductive line 4722 located in the first source-drain metal layer electrically connected with the second voltage line 472 can extend to the binding pin area in the second direction Y and be electrically connected with a corresponding binding pin in the binding pin area.

[0099] In some examples, as shown in Figure 11 and Figure 12 As shown, a plurality of detection circuits 482 can be electrically connected with a plurality of panel detection lines (for example, including: a first panel detection line 474, a second panel detection line 475, and a third panel detection line 476). The plurality of panel detection lines can be configured to transmit signals required by the detection circuit. The first panel detection line 474, the second panel detection line 475, and the third panel detection line 476 can be located in the first source-drain metal layer and each electrically connected with the first trace segment 511 of a corresponding first connection line 51b. The first panel detection line 474, the second panel detection line 475, and the third panel detection line 476 can extend to the binding pin area in the second direction Y and be electrically connected with a corresponding binding pin in the binding pin area.

[0100] In some examples, as shown in Figure 11 and Figure 12As shown, the first routing segment 511 of the plurality of first connection lines 51b can extend substantially along the first direction X through the region where the first power line PL1 and the second power line PL2 are located after being electrically connected to the signal line of the first circuit group 41a, and then extend along the second direction Y to the bending region. The extension of the first routing segment 511 along the second direction Y can be electrically connected to the corresponding second routing segment 512.

[0101] In some examples, as shown in FIG. 6, the first routing segment 511 of the plurality of first connection lines 51b of the first set of connection lines can be electrically connected to the second routing segment 512 through the first jumper 55 respectively. The plurality of second routing segments 512 can be arranged in sequence along the second direction Y, and all extend along the first direction X. Figure 13

[0102] In some examples, as shown in FIG. 6, the fourth routing segment 521 of the second connection line 52b can be electrically connected to the bending connection line 53a. The bending connection line 53a can be located in the first source-drain metal layer. The second connection line 52b can be a double-layer routing. For example, the fourth routing segment 521 of the second connection line 52b can include a first sub-routing 521a and a second sub-routing 521b stacked. The second sub-routing 521b can be located in the first gate metal layer, and the first sub-routing 521a can be located in the second gate metal layer. The second connection line of the present example adopts a double-layer routing, which can reduce the routing resistance. The first fan-out routing 61 can also adopt a double-layer routing, for example, can include sub-routings located in the first gate metal layer and the second gate metal layer. The present embodiment is not limited in this regard. Figure 14 to Figure 15B

[0103] In some examples, as shown in FIG. 6, the fourth routing segment 521 of the second connection line 52b and the adjacent first fan-out routing 61 can not overlap in the orthographic projection of the substrate. The extension direction of the fourth routing segment 521 and the adjacent routing segment of the first fan-out routing 61 can be consistent, for example, intersecting with both the first direction X and the second direction Y. Figure 14 to Figure 15B The display substrate provided by the present embodiment can provide a double-insurance path for signal transmission by connecting the first connection line and the second connection line in parallel between adjacent first circuit groups, so as to ensure at least one transmission path, thereby effectively avoiding the yield loss of the display substrate caused by the disconnection of the bending region in the bending process.

[0104]

[0105] Another schematic view of the binding region of the display substrate of at least one embodiment of the present disclosure is shown in FIG. 6. In some examples, as shown in FIG. 6, the first routing segment 511 of the plurality of first connection lines 51b of the first set of connection lines can be electrically connected to the second routing segment 512 through the first jumper 55 respectively. The plurality of second routing segments 512 can be arranged in sequence along the second direction Y, and all extend along the first direction X. Figure 16 Figure 16 ​​​As shown, the binding area B1 of the display substrate can include: the first fan-out area B11, the bending area B12, the second fan-out area B13, the first circuit area B14, the third fan-out area B15, the driving chip area B16 and the binding pin area B10 arranged in sequence along the direction away from the display area AA. The adjacent first circuit groups can be electrically connected through the first connecting lines, thereby ensuring the consistency of signal transmission and further ensuring the uniformity of the display area. For example, the first circuit group 41a and 41b can be electrically connected through the first connecting line 51a, the first circuit group 41b and 41c can be electrically connected through the first connecting line 51b, and the first circuit group 41c and 41d can be electrically connected through the first connecting line 51c. The adjacent first circuit groups can also be electrically connected through the second connecting lines. For example, the first circuit group 41a and 41b can be electrically connected through the second connecting line 52a, the first circuit group 41b and 41c can be electrically connected through the second connecting line 52b, and the first circuit group 41c and 41d can be electrically connected through the second connecting line 52c. The first connecting line 51a and the second connecting line 52a transmitting the same signal can be connected in parallel, the first connecting line 51b and the second connecting line 52b transmitting the same signal can be connected in parallel, and the first connecting line 51c and the second connecting line 52c transmitting the same signal can be connected in parallel. The remaining structure of the display substrate of the present embodiment can refer to the description of the foregoing embodiments, and will not be described here.

[0106] The display device can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame or navigator.

[0107] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures can refer to the general design. The features in the embodiments of the present disclosure, i.e. the embodiments, can be combined with each other to obtain new embodiments without conflict. Those skilled in the art should understand that the technical solutions of the present disclosure can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be covered in the scope of the claims of the present application.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a bonding area located on one side of the display area; A plurality of first circuit groups, at least one set of first connecting lines, and at least one set of second connecting lines are located in the bonding area; the plurality of first circuit groups are arranged along a first direction. At least two adjacent first circuit groups are electrically connected by a set of first connecting lines and a set of second connecting lines. In the set of first connecting lines and the set of second connecting lines, the first connecting lines and the second connecting lines that transmit the same signal are connected in parallel, and the at least one set of second connecting lines is located on the side of the at least one set of first connecting lines closer to the display area.

2. The display substrate according to claim 1, characterized in that, Two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a set of first connecting lines and a set of second connecting lines.

3. The display substrate according to claim 1, characterized in that, Any two adjacent first circuit groups in the plurality of first circuit groups are electrically connected by a set of first connecting lines and a set of second connecting lines.

4. The display substrate according to any one of claims 1 to 3, characterized in that, The binding area includes: a first sub-area, a bend area, and a second sub-area, which are sequentially arranged along a direction away from the display area; The plurality of first circuit groups and the at least one set of first connecting lines are located in the second sub-region, and the at least one set of second connecting lines are located in the first sub-region.

5. The display substrate according to claim 4, characterized in that, The bending area includes: multiple bending adapter wires, and each end of each of the second connecting wires in a group of second connecting wires is electrically connected to the first connecting wire in the corresponding group of first connecting wires through a bending adapter wire.

6. The display substrate according to claim 5, characterized in that, In a direction perpendicular to the display substrate, the plurality of bent adapter lines are located on the side of the at least one set of first connecting lines and at least one set of second connecting lines away from the substrate.

7. The display substrate according to claim 4, characterized in that, The first sub-region further includes: multiple sets of first fan-out traces arranged along the first direction; a set of second connecting lines disposed between two adjacent sets of first fan-out traces, wherein the orthographic projection of the set of second connecting lines on the substrate does not overlap with the orthographic projection of the two adjacent sets of first fan-out traces on the substrate.

8. The display substrate according to claim 4, characterized in that, At least one of the first connecting lines in a group includes: a first trace segment, a second trace segment, and a third trace segment that are electrically connected in sequence, the second trace segment extending along the first direction, the first trace segment being electrically connected to a first circuit group, and the third trace segment being electrically connected to another first circuit group.

9. The display substrate according to claim 8, characterized in that, The second sub-region further includes: a plurality of first electrostatic discharge circuits; a first trace segment, a second trace segment, and a third trace segment of at least one of the at least one set of first connecting lines are each electrically connected to a first electrostatic discharge circuit; the first electrostatic discharge circuit electrically connected to the first trace segment is located on the side of the first trace segment closer to the third trace segment, the first electrostatic discharge circuit electrically connected to the second trace segment is located on the side of the second trace segment closer to the bending area, and the first electrostatic discharge circuit electrically connected to the third trace segment is located on the side of the third trace segment closer to the first trace segment.

10. The display substrate according to claim 8, characterized in that, At least one of the second connecting lines in a set includes: a fourth line segment, a fifth line segment, and a sixth line segment that are electrically connected in sequence, the fifth line segment extending along the first direction, the fourth line segment and the sixth line segment located on the side of the fifth line segment away from the display area, and the length of the fifth line segment along the first direction being less than the shortest distance between the first line segment and the third line segment of the first connecting line electrically connected by the second connecting line.

11. The display substrate according to claim 1, characterized in that, The display substrate further includes: a buffer layer located on the side of the substrate away from the plurality of first circuit groups; and the orthographic projection of at least one set of first connection lines electrically connected to at least one set of second connection lines on the substrate overlaps with the orthographic projection portion of the buffer layer on the substrate.

12. The display substrate according to claim 1, characterized in that, The display substrate further includes: a plurality of bonding pin groups located in the bonding area, the plurality of bonding pin groups being located on the side of the plurality of first circuit groups away from the display area and being electrically connected to the plurality of first circuit groups.

13. The display substrate according to claim 12, characterized in that, The display substrate further includes: a plurality of driver chip pin groups located in the bonding area, wherein the plurality of driver chip pin groups are located on the side of the plurality of first circuit groups away from the display area and on the side of the plurality of bonding pin groups close to the display area.

14. The display substrate according to claim 1, characterized in that, The display area includes multiple sub-pixels and multiple data lines, and the multiple data lines are electrically connected to the multiple sub-pixels; At least one of the plurality of first circuit groups includes a plurality of test circuits connected to the plurality of data lines and configured to provide test data signals to the plurality of data lines during the testing phase.

15. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 14.

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