Devices and methods for single-ended sense amplifiers

Abstract

Apparatus, systems, and methods for single-ended sense amplifiers. A memory device may include multiple sense amplifiers for reading the voltage of memory cells along digital lines. A double-ended sense amplifier is coupled to two digital lines. A single-ended sense amplifier is coupled to a single digital line. The memory cells on the edge word lines of a memory array may be alternately coupled to either a single-ended or double-ended sense amplifier. The use of a single-ended sense amplifier reduces the footprint required for a given number of memory cells in the array.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. More specifically, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Background Technology

[0002] Information can be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells. During access, the memory cell can be coupled to a digital line (or bit line), which in turn can be coupled to a sense amplifier. Along with the digital line coupled to the memory cell, a second complementary digital line can also be coupled to the sense amplifier. The use of complementary digital lines can be used to provide a reference voltage level to better distinguish values ​​read from / written to the memory cell. However, this may require, for example, the use of dedicated reference digital lines at the edges of the memory array, which could increase the size of the memory array. There is a growing need for smaller memory devices. Summary of the Invention

[0003] In one aspect, this application provides an apparatus comprising: a digital line; a first intermolecular node; a second intermolecular node; a first transistor coupled between a first voltage line and the first intermolecular node, wherein a gate is coupled to the digital line; a second transistor coupled between a second voltage line and the first intermolecular node, wherein a gate is coupled to the digital line; a third transistor coupled between a third voltage line and the second intermolecular node, wherein a gate is coupled to the first intermolecular node; a fourth transistor coupled between a fourth voltage line and the second intermolecular node, wherein a gate is coupled to the first intermolecular node; and a fifth transistor coupled between the digital line and the first intermolecular node, wherein a gate is coupled to a control signal.

[0004] In another aspect, this application provides an apparatus comprising: a memory array including a first word line and a second word line, each word line including a plurality of corresponding memory cells, wherein the first word line is positioned along an edge of the memory array; a plurality of dual-ended sensing amplifiers, each coupled to a memory cell along the first word line and coupled to a memory cell along the second word line; and a plurality of single-ended sensing amplifiers, each coupled to a memory cell along the first word line.

[0005] In another aspect, this application provides a single-ended sense amplifier, comprising: a first inverter circuit having an input coupled to a digital line; and an output coupled to a first node; a second inverter circuit having an input coupled to the first node and an output coupled to a second node; and a transistor configured to selectively couple the digital line to the first node. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 This is a block diagram of a memory array according to some embodiments of the present disclosure.

[0008] Figures 3A to 3B This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure.

[0009] Figure 4 This is a diagram of example sensing operations according to some embodiments of the present disclosure.

[0010] Figure 5 This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure.

[0011] Figure 6 This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure.

[0012] Figure 7 This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure.

[0013] Figures 8A to 8D Pull-up and pull-down drivers according to some embodiments of the present disclosure are shown.

[0014] Figure 9 This is a schematic diagram of a dual-ended sense amplifier and a single-ended sense amplifier according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and to specific embodiments in which the described systems and methods can be practiced, illustrated by means of the description. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized, and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be elaborated where they would be obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is defined only by the appended claims.

[0016] A memory device may include a memory array comprising a plurality of memory cells, each of which can store information. For example, each memory cell may store a single bit of information. Memory cells may be located at the intersection of word lines (rows) and digital lines (bit lines / columns). Each word line may be associated with a row address, and each digital line may be associated with a column address. Thus, a memory cell may be specified by its row and column addresses. When a memory cell is accessed (e.g., during a read or write operation), the memory cell may be coupled to a sense amplifier via the bit lines. For example, during a read operation, the value stored in the memory cell (e.g., as capacitive charge) may change the voltage on the bit lines. The sense amplifier may detect this change, amplify the voltage to a system level (e.g., a voltage representing logic high or logic low), and then provide these voltages to the read / write amplifier along the local input / output (LIO) and global input / output (GIO) lines, thereby sending the voltage to the data terminals of the memory. During instance write operations, the process is typically reversible (e.g., from GIO to LIO, to the sense amplifier to the bit line to the memory cell).

[0017] In conventional memory devices, the sense amplifier can use a complementary dual-ended architecture. In this architecture, the sense amplifier is coupled to a first digital line and a second digital line, the first digital line being coupled to the memory cell being accessed. The second digital line can be used as a reference. The use of complementary digital lines can be used to distinguish different voltages (e.g., by comparing complementary values). The dual-ended sense amplifier can be coupled between a pair of adjacent word lines, where the two coupled digital lines are coupled to the corresponding memory cells of the two word lines. During operation, one word line can be activated to read data from the activated memory cell along the first digital line, while the second digital line can act as a reference. However, this can cause problems along the edges of the memory array because the first and last rows do not have another row along the outer edge. In conventional memory, this can result in word lines along the outer edge having half memory cells. Due to the increasing demand for smaller memory devices, having a single-ended sense amplifier can be useful, for example, to allow for increased density of memory cells in edge word lines.

[0018] This disclosure relates to apparatus, systems, and methods for a single-ended sense amplifier. A conventional dual-ended sense amplifier may have two input terminals, one coupled to a digital line carrying a voltage based on data stored in a memory cell, and the other coupled to a reference (e.g., along a digital line coupled to a reference voltage). A single-ended sense amplifier may have a single input terminal coupled to a digital line carrying a voltage based on data. The single-ended sense amplifier may include a first inverter having an input coupled to the digital line and an output coupled to a first inverting node. The first inverting node may be coupled to an input of a second inverter having an output node coupled to a second inverting node. The second inverting node is coupled to an input of the first inverter. The single-ended sense amplifier may have a metastable state subject to voltage disturbances along the digital line. Based on how the metastable state is disturbed, the single-ended sense amplifier may drive the digital line to a voltage representing a high or low logic level. The digital line may then be coupled to a local input / output (LIO) line to indicate a value read from a memory cell.

[0019] In a typical application, the memory array may include first and second word lines, where the first word line is the edge word line of the memory array. A set of dual-ended sense amplifiers may be disposed between the first and second word lines. Each of the dual-ended sense amplifiers has a pair of input terminals, one input terminal coupled to a memory cell on the first word line and the second input coupled to a memory cell on the second word line. A set of single-ended sense amplifiers may be disposed adjacent to the first word line (e.g., but not adjacent to the second word line). Each single-ended sense amplifier may each have a single input terminal coupled to a memory cell along the first word line. Therefore, each memory cell along the first word line may be coupled to a single-ended or dual-ended sense amplifier (e.g., alternately along the word line). The same number of memory cells may be present along the first word line as along the second word line.

[0020] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0021] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as containing multiple memory banks. Figure 1 In one embodiment, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BLT, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BLT. The selection of word lines WL is performed by row decoder 108, and the selection of bit lines BLT is performed by column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines (BLTs) are coupled to corresponding sense amplifiers (SAMPs). Read data from the bit lines (BLTs) is amplified by the sense amplifiers (SAMPs) and passed to the read / write amplifier 120 via the local data line (LIO), the transmission gate (TG), and the global data line (GIO). Conversely, write data output from the read / write amplifier 120 is passed to the sense amplifiers (SAMPs) via the complementary master data line (GIO), the transmission gate (TG), and the complementary local data line (LIO), and written to the memory cell (MC) coupled to the bit line (BLT).

[0022] Memory device 100 may include a hybrid of single-ended and dual-ended sense amplifiers, wherein the single-ended sense amplifier is coupled to a single bit line or digital line BLT, and the dual-ended sense amplifier is coupled to two digital lines BLT and BLB. Examples of different types of sense amplifiers and their arrangement in the memory device are described in more detail herein.

[0023] The semiconductor device 100 may employ, for example, a plurality of external terminals, including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses; a clock terminal for receiving clock CK and / CK; a data terminal DQ coupled to a data bus to provide data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0024] An external clock CK and / or CK is supplied to the clock terminals, and this external clock is provided to input circuitry 112. The external clocks are complementary. Input circuitry 112 generates an internal clock ICLK based on the CK and / or CK clocks. The ICLK clock is provided to command decoder 106 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. An internal data clock LCLK is provided to input / output circuitry 122 to time the operation of circuits contained within input / output circuitry 122, for example, to a data receiver to time the reception of written data. Input / output circuitry 122 may include multiple interface connections, each of which may be coupled to one of the DQ pads (e.g., pads that may act as external connections to device 100).

[0025] The C / A terminal can be supplied with a memory address. The memory address supplied to the C / A terminal is passed to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The column decoder 110 can provide a column select signal CS, which can activate the selected sense amplifier in the sense amplifier SAMP. The address decoder 104 can also supply a decoded bank address BADD, which indicates the bank of memory in the memory array 118 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD for indicating the memory cell to be accessed.

[0026] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0027] Device 100 can receive access commands as read commands. When a read command is received and the memory bank address, row address, and column address are supplied in a timely manner along with the read command, read data is read from the memory cells corresponding to the row and column addresses in the memory array 118. The read command is received by command decoder 106, which provides an internal command causing the read data to be provided from the memory array 118 to the read / write amplifier 120. The read data is provided along the data bus and output to the outside via input / output circuitry 122 from the data terminal DQ.

[0028] Device 100 can receive access commands as write commands. When a write command is received and the bank address, row address, and column address are supplied in a timely manner along with the write command, write data is supplied to the data terminal DQ along the data bus and written to the memory cells in memory array 118 corresponding to the row and column addresses. The write command is received by command decoder 106, which provides an internal command causing the write data to be received by the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal for timing the data receiver in input / output circuit 122 to receive the write data. The write data is supplied via input / output circuit 122 to read / write amplifier 120 and from read / write amplifier 120 to memory array 118 to be written to memory cells MC.

[0029] The memory 100 may include single-ended sense amplifiers, each having an input terminal coupled to a digital line BLT carrying a voltage based on the memory cell. The single-ended sense amplifiers also have multiple terminals coupled to various control signals that the row decoder 108 and / or column decoder 110 can provide to operate the sense amplifiers during various operations. The memory array 118 may also include dual-ended sense amplifiers.

[0030] The device 100 may also receive commands to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, a self-refresh mode command may be issued externally to the memory device 100. In some embodiments, the self-refresh mode command may be generated periodically by a component of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF may be a pulse signal activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated immediately after the command input and may thereafter be activated cyclically according to desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during the self-refresh mode. Therefore, refresh operations may continue automatically. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and return it to an idle state.

[0031] A refresh signal AREF is supplied to refresh control circuitry 116. Refresh control circuitry 116 supplies a refresh row address RXADD to row decoder 108, which refreshes one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, refresh address RXADD may represent a single word line. In some embodiments, refresh address RXADD may represent multiple word lines, which may be refreshed sequentially or simultaneously by row decoder 108. In some embodiments, the number of word lines represented by refresh address RXADD may vary from one refresh address to another. Refresh control circuitry 116 can control the timing of the refresh operation and can generate and provide refresh address RXADD. Refresh control circuitry 116 can be controlled to change details of refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or can operate based on internal logic.

[0032] Power potentials VDD and VSS are supplied to the power terminals. The power potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power potentials VDD and VSS supplied to the power terminals.

[0033] Power potentials VDDQ and VSSQ are also supplied to the power terminals. These power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used in the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0034] Figure 2 This is a block diagram of a memory array according to some embodiments of the present disclosure. In some embodiments, the memory array 200 may be included in... Figure 1 In memory array 118. Memory array 200 shows a simplified view of a memory array with four word lines WLA to WLD, each of which contains eight memory cells 210. It should be understood that the memory array may contain more word lines and / or memory cells per word line. Although Figure 2 The embodiments illustrate a hybrid example of single-ended and double-ended sense amplifiers arranged in a specific pattern; however, it should be understood that other embodiments may include other methods of using and arranging single-ended sense amplifiers in memory arrays.

[0035] Memory array 200 has four word lines WLA, WLB, WLC, and WLD. Word lines WLA and WLD are edge word lines of memory array 200, each being the first (or last) word line of the array and having only one adjacent word line. For example, word line WLA is adjacent to word line WLB and word line WLD is adjacent to word line WLC. Word lines WLB and WLC are inner word lines of memory array 200, each of which is adjacent to two other word lines (e.g., word line WLC is adjacent to WLD and WLB, and word line WLB is adjacent to WLC and WLA). Each word line has a plurality of memory cells 210 disposed along the word line at the intersection of the word line and the digital line 212.

[0036] Groups of dual-ended sense amplifiers 206 are positioned between adjacent word lines. Groups of single-ended sense amplifiers 204 are positioned adjacent to individual word lines (e.g., to edge word lines WLA and WLD). Bit lines 212 couple each memory cell to a sense amplifier, either a single-ended sense amplifier 204 or a dual-ended sense amplifier 206.

[0037] Each dual-ended sense amplifier 206 is coupled to two digital lines, one of which is coupled to a memory cell 210 in each of the two word lines between which the sense amplifier 206 is located. During an access operation, one digital line can be used to read data, while the other digital line can be used as a reference. All memory cells 210 are coupled to dual-ended sense amplifiers 206 along the inner word lines WLB and WLC. Along the word lines, memory cells may alternately couple to which adjacent group of dual-ended sense amplifiers. For example, along word line WLC, a first memory cell is coupled to sense amplifier 206, which is also coupled to a first memory cell in WLB, a second memory cell is coupled to sense amplifier 206, which is also coupled to a second memory cell in WLD, and so on.

[0038] Each single-ended sense amplifier 204 is coupled to a single digital line 212 of a memory cell 210 in an edge row of the memory array 200. Therefore, along the edge row, the memory cell 210 may alternately be coupled to either a single-ended sense amplifier or a dual-ended sense amplifier 206. For example, a first memory cell along the WLD is coupled to a single-ended sense amplifier 204, a second memory cell along the WLD is coupled to a dual-ended sense amplifier 206, which is also coupled to a second memory cell along the WLC, and so on.

[0039] Since no specific bit lines need to be reserved to serve as permanent reference digital lines for the single-ended sense amplifier, each edge row memory (e.g., WLA and WLD) can have the same number of memory cells as inner rows (e.g., if half the bit lines are reserved for reference instead of half the memory cells). Therefore, using Figure 2 The memory array layout shown may contain a smaller row for the same number of memory cells.

[0040] exist Figures 3A to 8B An example single-ended sense amplifier that can be used as a single-ended sense amplifier 204 is described in more detail below. Figure 9 Examples of dual-ended sense amplifiers that can be used as dual-ended sense amplifier 206 are described in more detail below. In some embodiments, any dual-ended sense amplifier known in the art may be used as dual-ended sense amplifier 206.

[0041] Figures 3A to 3B This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure. In some embodiments, the single-ended sense amplifier 300 may be included in... Figure 1 In the sense amplifier SAMP and / or Figure 2 One of the sensing amplifiers 204. Figure 3A and 3B Different layouts of the same single-ended sense amplifier 300 are shown. Figure 3A and 3B The view differs from the guide only in layout to more easily depict the operation of the circuit. Therefore, for simplicity, the two figures use the same reference numerals and will be described together.

[0042] The sense amplifier 300 is shown coupled to system voltage lines ACT and RNL, which can be charged with a supply voltage to activate the amplifier. For example, during access operations, voltage line ACT can be charged to a system voltage such as VDD, representing a high logic level, while voltage line RNL can be charged to a ground voltage such as VSS.

[0043] The sense amplifier 300 includes a first inverter circuit comprising two transistors 310 and 312. The first inverter has an input coupled to a digital line (denoted here as digitA) and an output node coupled to a first inductor node digit_gutA. The first transistor 310 has a source coupled to ACT, a drain coupled to digit_gutA, and a gate coupled to digitA. The first transistor 310 may be a p-type transistor. The second transistor 312 has a source coupled to RNL, a drain coupled to digit_gutA, and a gate coupled to digitA. The second transistor 312 may be an n-type transistor. Therefore, when the signal digitA is at a sufficiently high voltage, transistor 312 will be activated and transistor 310 will be deactivated, thereby coupling digit_gutA to RNL through transistor 312. When the signal digitA is at a sufficiently low voltage, transistor 312 may be deactivated, while transistor 310 may be activated, thereby coupling digit_gutA to ACT through transistor 310.

[0044] The sense amplifier 300 includes a second inverter comprising two transistors 320 and 322. The second inverter may generally be similar to the first inverter, except that its input node is coupled to digit_gutA and its output node is coupled to digit_gutB. The second inverter includes a third transistor 320 having a source coupled to ACT, a drain coupled to digit_gutB, and a gate coupled to digit_gutA. The third transistor 320 may be a p-type transistor. A fourth transistor 322 has a source coupled to RNL, a drain coupled to digit_gutB, and a gate coupled to digit_gutA. The fourth transistor 322 may be an n-type transistor. Therefore, when the signal digit_gutA is at a sufficiently high voltage, transistor 322 will be activated and transistor 320 will be deactivated, thereby coupling digit_gutB to RNL through transistor 322. When the signal digit_gutA is at a sufficiently low voltage, transistor 322 may be inactive while transistor 320 may be activated, thereby coupling digit_gutB to ACT through transistor 320.

[0045] The sensing amplifier 300 also has two additional transistors coupled to control signals BLCP and ISO, respectively, which can be used to operate the sensing amplifier 300 during sensing operation. Figure 4 The instance sensing operation is described in more detail.

[0046] The fifth transistor 306 has a source coupled to digitA, a drain coupled to digit_gutA, and a gate coupled to the BLCP. The fifth transistor can be an n-type transistor. Therefore, when the BLCP is activated, transistor 306 is activated, and the transistor can couple digitA to digit_gutA.

[0047] The sixth transistor 304 has a source coupled to digit_gutB, a drain coupled to digitA, and a gate coupled to the isolation signal ISO. The sixth transistor 304 can be an n-type transistor. Therefore, when ISO is activated, transistor 304 is activated and can couple digit_gutB to digitA.

[0048] An additional column select transistor (not shown) couples the digital line digitA to the local / input / output line LIO (and from there to the global input / output and DQ pads of the memory). When the column select signal CS (e.g., by...) is activated... Figure 1 When the column decoder 110 is activated, the column selection transistor can be activated and couple the voltage on the digital line digitA to LIO.

[0049] Figure 4 This is a diagram illustrating example sensing operations according to some embodiments of the present disclosure. Figure 400 shows, for example... Figures 3A to 3B The single-ended sense amplifier 300 is shown as an example of operation. Figure 400 is representative and not drawn to scale, and the different traces shown may not be drawn to the same scale. Figure 400 shows time along the horizontal axis and voltage along the vertical axis, where low voltage typically represents logic low and high voltage represents logic high.

[0050] Before the initial time t0, signals ISO and BLCP are activated (e.g., at a high logic level), while signals ACT, RNL, digit_gutA, digit_gutB, and digitA are all held at a precharge level between logic high and logic low voltages (e.g., approximately halfway between VDD and VSS). Since ISO and BLCP are both active, transistors 304 and 306 in Figure 3 are activated, which can short digitA, digit_gutA, and digit_gutB together.

[0051] At the initial time t0, the activation signal ISO is deactivated (e.g., driven to a low logic level), and signals ACT and RNL can be driven to a high voltage (e.g., VDD) and a low voltage (e.g., VSS), respectively. This puts the single-ended sense amplifier into a metastable state. Since signal BLCP is still active, digitA can still be coupled to digit_gutA. However, since ISO is now deactivated, digit_gutB is no longer directly coupled to digit A.

[0052] At the first time t1, the signal BLCP can be deactivated (e.g., to decouple digitA and digit_gutA), which puts the sense amplifier in a sense or pre-sense mode. At t1, the word line coupled to the memory cell, digitA, is activated. This causes the memory cell to activate and drive the voltage of digitA based on the logic value stored in the memory cell. In this case, the instance memory cell remains at a high logic level (e.g., a high voltage). Therefore, after t1, the voltage on the digital line digitA can increase. This, in turn, causes the gut voltage digit_gutA to decrease (e.g., due to its inversion from digitA). The decrease in gut voltage digit_gutA may be greater than the positive swing of digitA because the voltages ACT and RNL differ significantly from the voltage driven by the memory cell along digitA. The decrease in digit_gutA can also cause digit_gutB to rise because digit_gutB inverts from digit_gutA. Since ISO is not activated, this can create feedback that continues to drive the voltage digitA to rise.

[0053] At the second time t2, the sensing amplifier can enter latching or sensing mode, in which the signal ISO is activated. This "freezes" the operation of the circuit, thereby locking in the higher voltage along digitA and digit_gutB and the lower voltage along digit_gutA. At this time, information along the digital line digitA can be latched or otherwise sensed. For example, the column select transistor can be activated, and the voltage along digitA can be coupled to the LIO line as part of a read operation.

[0054] At the third time t3, the sense amplifier can enter equalization mode, deactivate the word line, reactivate the signal BLCP, and drive the voltages ACT and RNL to the midpoint voltage (e.g., between VDD and VSS). This resets the sense amplifier and prepares it for the next sensing operation.

[0055] Figure 5 This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure. In some embodiments, a single-ended sense amplifier 500 may be included as... Figure 2 One of the single-ended sense amplifiers 204. The single-ended sense amplifier 500 can generally be similar to... Figures 3A to 3B The sensing amplifier 300. For the sake of brevity, features, components and operations similar to those described with respect to sensing amplifier 300 will not be repeated with respect to sensing amplifier 500.

[0056] The sensing amplifier 500 can be similar to Figures 3A to 3B The sense amplifier 300 differs from the sense amplifier 500 in that it has separate power signals for the two inverter circuits, instead of allowing the two inverters to share ACT and RNL. For example, transistor 510 has a source coupled to signal ACT1, and transistor 512 has a source coupled to signal RNL1. Meanwhile, transistor 520 has a source coupled to ACT2, and transistor 522 has a source coupled to signal RNL2. For example, if the signal on digitA is high, voltage RNL1 can be applied to digit_gutA, which in turn allows voltage ACT2 to be applied to digit_gutB.

[0057] The use of different signals ACT1 and ACT2, and RNL1 and RNL2, allows the inverters to operate at different voltage levels. Voltage ACT1 can be different from ACT2, and voltage RNL1 can be different from voltage RNL2. This allows the two inverter circuits to have different amplification levels. For example, if the difference between voltages ACT2 and RNL2 is greater than the difference between ACT1 and RNL2, the second inverter will have a greater amplification than the first inverter. In some embodiments, different sets of voltages can be activated at different times to control the operation of the circuit with more precise control. For example, Figure 7 An embodiment is described in which the transistor 504 is eliminated by controlled operation of voltages ACT1, ACT2, RNL1, and RNL2.

[0058] Figure 6 This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure. In some embodiments, a single-ended sense amplifier 600 may be included as... Figure 2 One of the single-ended sense amplifiers 204. The single-ended sense amplifier 600 can generally be similar to... Figures 3A to 3B The sensing amplifier 300 and / or Figure 5 The sensing amplifier 500. For the sake of brevity, features, components and operations similar to those described with respect to sensing amplifiers 300 and 500 will not be repeated with respect to sensing amplifier 600.

[0059] The single-ended sense amplifier 600 can typically be similar to Figure 5The single-ended sense amplifier 500 differs from the sense amplifier 600 in that transistors 610 and 620 are adjustable. Transistors 610 and 620 may have a voltage NW applied to their substrate, which controls the leakage current Ioff of transistors 610 and 620. The voltage NW can be dynamically adjusted (e.g., by...). Figure 1 (and some other control circuitry of the column decoder 110 and / or sense amplifier 600) to reduce leakage current Ioff when voltages ACT1, ACT2, RNL1, and RNL2 are off. Figures 8A to 8D The pull-up and pull-down devices that can provide voltages ACT1, ACT2, RNL1 and / or RNL2 are described in more detail.

[0060] Similar to Figure 5 The sensing amplifier 500 Figure 6 The sense amplifier 600 is shown having separate voltage lines for each of the inverters 610, 612, 620, and 622 (e.g., ACT1 and ACT2 are different, and RNL1 and RNL2 are different). However, in some embodiments, similar to the embodiments of Figures 3 and 4, transistors 610 and 620 and transistors 612 and 622 may be co-coupled to a single voltage rail (e.g., a single ACT and RNL, respectively).

[0061] Figure 7 This is a schematic diagram of a single-ended sense amplifier according to some embodiments of the present disclosure. In some embodiments, a single-ended sense amplifier 700 may be included as... Figure 2 One of the single-ended sense amplifiers 204. The single-ended sense amplifier 700 can generally be similar to... Figures 3A to 3B Sensing amplifier 300, Figure 5 500 and / or Figure 6 For the sake of brevity, features, components, and operations similar to those described with respect to sense amplifiers 300, 500, and / or 600 will not be repeated relative to sense amplifier 700.

[0062] Sensing amplifier 700, similar to sensing amplifiers 500 and 600, has different voltages coupled to each of the two inverters (e.g., ACT1 and ACT2 and RNL1 and RNL2). However, compared to sensing amplifiers 300, 500, and 600, sensing amplifier 700 eliminates the signal ISO and its corresponding transistor (e.g., in amplifier 700, the signal digit_gutB is directly coupled to the gates of transistors 710 and 712, rather than coupled through transistors).

[0063] Voltages ACT1, ACT2, RNL1, and RNL2 can be controlled independently during sensing operation. For example, instead of the activation signal ISO to couple the gut node digit_gutB to the digital line digitA, the voltages can be used to turn two inverters (e.g., 710 / 712 and 720 / 722) on and off at different times. For example, the first inverter (e.g., transistors 710 and 712) can be turned on at the first time, with voltage line ACT1 coupled to the system voltage VD and voltage line RNL1 coupled to the ground voltage VS, while the second inverter (e.g., transistors 720 and 722) is off, allowing voltage lines ACT2 and RNL2 to float. Similarly, at other times, the second inverter can be turned on (e.g., ACT2 coupled to VD and RNL2 coupled to VS), while the first inverter is off (e.g., ACT1 and RNL1 float). At other times, both inverters may be active or inactive. For example, during instance sensing operation, when the signal BLCP becomes inactive, the first inverter can be activated, and then instead of activating the ISO signal, the second transistor can be activated to latch the data in the sensing amplifier.

[0064] Similar to Figure 6 The sense amplifier 600 and sense amplifier 700 are shown as including transistors 710 and 720, which have an adjustable leakage current controlled by a voltage NW. However, the adjustable transistors 710 and 720 are optional, and in some embodiments, the voltage NW can be eliminated and transistors 710 and 720 can be operated with a fixed leakage current (e.g., similar to amplifier 300 of FIG3). Figure 5 (of 500).

[0065] Figures 8A to 8D Pull-up and pull-down leakage control circuitry according to some embodiments of the present disclosure is illustrated. In some embodiments, the pull-up and pull-down leakage control circuitry can be used to control leakage current from drivers (not shown) of voltages ACT, RNL, ACT1, ACT2, RNL1, and / or RNL2 in any of Figures 3, 4, 5, 6, and / or 7. Leakage control circuitry 800A to 800D may be transistors configured in a diode manner to limit current leakage between sense amplifiers and drivers that provide voltages to operate those sense amplifiers.

[0066] Leakage control circuits 800A and 800B demonstrate leakage control circuits that can be used to couple ground voltage VS to voltage lines RNL, RNL1, and / or RNL2. Embodiment 800A uses n-type transistors, while embodiment 800B uses p-type transistors, each coupled in a diode configuration. Drivers 800C and 800D demonstrate leakage control circuits that can be used to couple system voltage VD to voltage lines ACT, ACT1, and / or ACT2. Embodiment 800C uses n-type transistors, while embodiment 800D uses p-type transistors, each coupled in a diode configuration. For simplicity, the labels RNL and ACT will be used to indicate RNL, RNL1, and / or RNL2, and ACT, ACT1, and / or ACT2, respectively.

[0067] The driver 800A includes an n-type transistor with a source coupled to VS, a drain coupled to RNL, and a gate coupled to RNL. Therefore, when RNL has a higher voltage than VS, the transistor is activated and couples the voltage line RNL to VS. When RNL has a lower voltage (e.g., VS), the transistor is deactivated, thereby clamping the voltage across RNL and decoupling RNL from VS to prevent leakage.

[0068] The driver 800B includes a p-type transistor with a drain coupled to VS, a source coupled to RNL, and a gate coupled to VS. Therefore, when VS is at a voltage lower than RNL, the transistor is activated and couples VS to RNL. When RNL is at a voltage similar to or lower than VS, the transistor deactivates, and the voltage line RNL decouples from VS to prevent leakage.

[0069] The driver 800C includes an n-type transistor with a drain coupled to the system voltage VD, a source coupled to ACT, and a gate coupled to VD. The transistor is activated when VD is higher than ACT. When the voltage on ACT is sufficiently close to (or higher than) VD, the transistor is deactivated, thereby decoupling ACT and VD to prevent leakage.

[0070] The driver 800D includes a p-type transistor with a source coupled to VD, a drain coupled to ACT, and a gate coupled to ACT. When the voltage on ACT is lower than VD, the transistor is activated, thereby coupling VD to ACT. When the voltage on ACT is close to (or higher than) VD, the transistor is deactivated, thereby decoupling VD from ACT to prevent leakage.

[0071] The use of leakage control circuits 800A, 800B, 800C, and / or 800D can help save power by reducing the power lost through leakage current Ioff. In some embodiments, leakage control circuits 800A, 800B, 800C, and / or 800D may be coupled to embodiments using transistors with adjustable leakage current (e.g., controlled by voltage NW) to further reduce power loss via leakage current.

[0072] Figure 9 These are schematic diagrams of dual-ended and single-ended sense amplifiers according to some embodiments of the present disclosure. (As relative to...) Figure 2 As described, the memory array may include single-ended sense amplifiers and dual-ended sense amplifiers (e.g., respectively). Figure 2 A mixture of 204 and 206). Any of the previously described sense amplifiers (e.g., Figures 3, 4, 6, 7 and / or 8) can be used to implement the single-ended sense amplifier 950. In some embodiments, Figure 9 The dual-ended sense amplifier 900 can be used to implement a dual-ended sense amplifier (e.g., Figure 2 (206). In other example embodiments, other dual-ended sense amplifiers may be used, such as any dual-ended sense amplifier known in the art.

[0073] The dual-ended sense amplifier 900 and the single-ended sense amplifier 950 are shown coupled along word lines WL1 and WL2 to the corresponding memory cells 952, 954, and 956. The layout may be similar to... Figure 2 However, for illustrative purposes, with Figure 2 Unlike other chip layouts, the sense amplifier 900 is not shown positioned between two word lines (although it may be positioned in this manner in some chip layouts). Word line WL1 may represent the edge word line of the memory array (e.g., Figure 2 (WLA or WLD). Memory cell 954 is adjacent to memory cell 952 along word line WL1. Memory cells 952 and 956 are coupled to dual-ended sense amplifier 900, while memory cell 954 is coupled to single-ended sense amplifier 950.

[0074] A dual-ended sense amplifier can typically be similar to Figures 3A to 3B The single-ended sense amplifier 300. For the sake of simplicity, it will not be compared to... Figure 9 Repeat the previous relative Figures 3A to 3BThe operation and components are described. In the dual-ended sense amplifier 900, there are two input terminals coupled to a first digital line digitA and a second digital line digitB, which are coupled along word line WL1 to a corresponding memory cell 952 and along word line WL2 to 956. During access operations, one of the digital lines can be used to carry data (e.g., coupled along the active word line to the memory cell), while the other digital line can carry a reference voltage. For example, if memory cell 952 is accessed, digitA can carry data, while digitB can carry a reference voltage.

[0075] The second digital line digitB is coupled to the input of the second inverter (e.g., coupled to the gates of transistors 920 and 922). The second digital line is also coupled to the second node digit_gutB via transistor 905. Transistor 905 has a source coupled to digitB, a drain coupled to digit_gutB, and a gate coupled to the signal BLCP. Transistor 905 may be an n-type transistor. The digital line digitB is also coupled to the first node digit_gutA via transistor 903. Transistor 903 has a source coupled to digit_gutA, a drain coupled to digitB, and a gate coupled to the isolation signal ISO. Transistor 903 may also be an n-type transistor.

[0076] During instance sensing operation, two digital lines, digitA and digitB, are initially driven to a reference voltage (e.g., halfway between the voltage representing a high logic level and the voltage representing a low logic level). One of the digital lines may be coupled to a memory cell along an active word line, while the other digital line remains as a reference. When a read charge from a memory cell disturbs its coupled digital line, it will drive that digital line in one direction and another digital line in the other direction. For example, if digitA is coupled to a memory cell that holds a high logic value, the voltage of digitA (and digit_gutB) will increase, while the voltage of digitB (and digit_gutA) will decrease.

[0077] In some embodiments, the dual-ended sense amplifier 900 may include offset cancellation by splitting signal lines and power lines so that they are not jointly controlled. For example, similar to Figure 7 For ACT1 / ACT2 and RNL1 / RNL2, voltage ACT can be divided into ACT_A and ACT_B, and voltage RNL can be divided into RNLA_A and RNL_B. Similarly, signals ISO and BLCP can be divided into ISO_A of operating transistor 903, ISO_B of operating transistor 904, BLCP_A of operating transistor 906, and BLCP_B of operating transistor 905.

[0078] In some embodiments, additional transistors (not shown) may act as switches between the dual-ended sense amplifier 900 and memory cells 952 and 956. These transistors may have gates coupled to corresponding array isolation signals ArrayISO_A and ArrayISO_B. The array isolation signals may be used to isolate the dual-ended sense amplifier from one or both of the coupled digital lines digitA and digitB.

[0079] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the present invention.

[0080] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. An apparatus comprising: Digital line; First intestinal node; Second intestinal node; A first transistor is coupled between a first voltage line and a first intermolecular node, wherein the gate is coupled to the digital line; A second transistor is coupled between a second voltage line and the first intestinal node, wherein the gate is coupled to the digital line; A third transistor is coupled between a third voltage line and a second intestinal node, wherein the gate is coupled to the first intestinal node; A fourth transistor is coupled between a fourth voltage line and the second intestinal node, wherein the gate is coupled to the first intestinal node; A fifth transistor is coupled between the digital line and the first intestinal node, wherein the gate is coupled to the first control signal; A sixth transistor is coupled between the second intestinal node and the digital line, wherein the gate is coupled to the second control signal; and A controller configured to not activate the second control signal at a first time, not activate the first control signal at a second time, and activate the first control signal at a third time.

2. The device according to claim 1, wherein the first voltage line and the third voltage line are coupled to a first voltage, and wherein the second voltage line and the fourth voltage line are coupled to a second voltage.

3. The device of claim 1, wherein the first transistor and the third transistor are p-type transistors, and wherein the second transistor and the fourth transistor are n-type transistors.

4. The device of claim 1, wherein the device is not coupled to a second digital line.

5. An apparatus comprising: Digital line; First intestinal node; Second intestinal node; A first transistor is coupled between a first voltage line and a first intermolecular node, wherein the gate is coupled to the digital line; A second transistor is coupled between a second voltage line and the first intestinal node, wherein the gate is coupled to the digital line; A third transistor is coupled between a third voltage line and a second intestinal node, wherein the gate is coupled to the first intestinal node; A fourth transistor, coupled between a fourth voltage line and the second intestinal node, wherein its gate is coupled to the first intestinal node; and A fifth transistor, coupled between the digital line and the first intestinal node, wherein its gate is coupled to a control signal. The first transistor and the third transistor have adjustable leakage current.

6. An apparatus comprising: A memory array including a first word line and a second word line, each word line including a plurality of corresponding memory cells, wherein the first word line is positioned along the edge of the memory array; Multiple dual-ended sensing amplifiers, each coupled to a memory cell along the first word line and coupled to a memory cell along the second word line; Multiple single-ended sense amplifiers, each coupled to a memory cell along the first word line. Each of the plurality of single-ended sense amplifiers comprises: First intestinal node; Second intestinal node; A first transistor is coupled between a first voltage line and a first intermolecular node, wherein the gate is coupled to a digital line, the digital line being coupled along the first word line to a corresponding one of the plurality of memory cells; A second transistor is coupled between a second voltage line and the first intestinal node, wherein the gate is coupled to the digital line; A third transistor is coupled between a third voltage line and a second intestinal node, wherein the gate is coupled to the first intestinal node; A fourth transistor is coupled between a fourth voltage line and the second intestinal node, wherein the gate is coupled to the first intestinal node; A fifth transistor, coupled between the digital line and the first intestinal node, wherein its gate is coupled to a control signal; and A sixth transistor is coupled between the second intestinal node and the digital line, wherein the gate is coupled to a second control signal.

7. The device of claim 6, wherein the first word line and the second word line each comprise the same number of memory cells.

8. The device of claim 6, wherein the plurality of memory cells along the first word line are alternately coupled to one of the plurality of single-ended sense amplifiers or one of the plurality of dual-ended sense amplifiers.

9. The device of claim 6, wherein the first voltage line and the third voltage line are coupled to a first voltage, and wherein the second voltage line and the fourth voltage line are coupled to a second voltage.

10. A single-ended sensing amplifier, comprising: The first inverter circuit has an input coupled to a digital line; and the output coupled to the first node; The second inverter circuit has an input coupled to the first node and an output coupled to the second node; and A transistor configured to selectively couple the digital line to the first node. The first inverter circuit includes a transistor with adjustable leakage current, and the second inverter circuit includes another transistor with adjustable leakage current.

11. The single-ended sense amplifier of claim 10, further comprising a second transistor configured to selectively couple the second node to the digital line.

12. The single-ended sensing amplifier of claim 10, wherein the digital line is coupled to a first memory cell, and wherein a second memory cell adjacent to the first memory cell is coupled to a double-ended sensing amplifier.

13. The single-ended sensing amplifier of claim 10, wherein the first inverter circuit and the second inverter circuit are coupled together to the first voltage and the second voltage.

14. The single-ended sense amplifier of claim 10, wherein the first inverter circuit is coupled to a first voltage and a second voltage, and the second inverter circuit is coupled to a third voltage and a fourth voltage.

15. A single-ended sensing amplifier, comprising: The first inverter circuit has an input coupled to a digital line; and the output coupled to the first node; The second inverter circuit has an input coupled to the first node and an output coupled to the second node; and A transistor configured to selectively couple the digital line to the first node. At least one of the first inverter circuit or the second inverter circuit is coupled to a leakage control circuit, the leakage control circuit comprising a transistor having a drain shorted to its gate.

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