Active pixel sensor, display panel, display device and flat panel detection device

Abstract

The embodiment of the present application provides an active pixel sensor, a display panel, a display device and a flat panel detection device, wherein the active pixel sensor comprises: a plurality of pixel circuits arranged in an array, each pixel circuit comprises a first transistor and a pixel sensing unit for generating a pixel signal, the pixel sensing unit is connected to the first electrode of the first transistor, and the gate of the first transistor is used to connect to a gate control voltage; a plurality of common circuits, corresponding one to one to a plurality of columns of pixel circuits, the second electrode of the first transistor in each column of pixel circuits is connected to the corresponding common circuit, and the common circuit also has a read control voltage terminal, and the read control voltage terminal is used to connect to a read control voltage; when the gate control voltage and the read control voltage meet a first preset condition, the pixel signal of the current frame is sampled for the first time and the second time. The technical solution of the embodiment of the present application may not be limited by the pixel size and may be compatible with a photoconductive detector.

Description

Technical Field

[0001] The present application relates to the field of sensing technology, and in particular to an active pixel sensor, a display panel, a display device and a flat panel detection device. Background Art

[0002] Currently, the application of active pixel sensors (APS) is becoming more and more common. The pixel driving circuit of an active pixel sensor is usually arranged in the pixel area, and the pixel driving circuit usually includes three semiconductor transistors and a storage capacitor. However, this pixel driving circuit is limited by the pixel size, and the pixel driving circuit is not compatible with a photoconductive detector. Summary of the invention

[0003] Embodiments of the present application provide an active pixel sensor, a display panel, a display device, and a flat panel detection device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present application, an embodiment of the present application provides an active pixel sensor, comprising: a plurality of pixel circuits arranged in an array, each pixel circuit comprising a first transistor and a pixel sensing unit for generating a pixel signal, the pixel sensing unit being connected to a first electrode of the first transistor, wherein a gate of the first transistor is used to connect to a gate control voltage; a plurality of common circuits corresponding one-to-one to a plurality of columns of pixel circuits, a second electrode of the first transistor in each column of pixel circuits being connected to the common circuit corresponding to the column of pixel circuits, the common circuit also having a read control voltage terminal, the read control voltage terminal being used to connect to a read control voltage; wherein, when the gate control voltage and the read control voltage satisfy a first preset condition, a first sampling and a second sampling are performed on the pixel signal of a current frame.

[0005] In one implementation, the number of resets of the pixel sensing unit between the first sampling and the second sampling is zero.

[0006] In one embodiment, the shared circuit includes: a second transistor, the gate of the second transistor is connected to the second electrode of the first transistor, and the first electrode of the second transistor is used to connect to the power supply voltage of the active pixel sensor; a third transistor, the gate of the third transistor is used to connect to the read control voltage, the first electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the third transistor is used to connect to the readout circuit that reads out the current frame pixel signal; a first resistor, one end of the first resistor is used to connect to the power supply voltage, and the other end of the first resistor is connected to the gate of the second transistor.

[0007] In one embodiment, the power supply voltage includes a first power supply voltage and a second power supply voltage, the first resistor is connected to the first power supply voltage, and the first electrode of the second transistor is connected to the second power supply voltage, wherein the first power supply voltage is less than or equal to the second power supply voltage.

[0008] In one embodiment, the shared circuit also includes: a second resistor, one end of the second resistor is used to connect to the bias voltage, and the other end of the second resistor is connected to the gate of the second transistor, wherein the resistance of the second resistor is equal to the resistance of the pixel sensing unit in a non-light-sensitive state.

[0009] In one embodiment, when the gate control voltage is at a low level and the read control voltage is at a high level, the current frame pixel signal is sampled for the first time; when the gate control voltage is at a high level and the read control voltage is at a high level, the current frame pixel signal is sampled for the second time.

[0010] In one embodiment, the common circuit also has a reset control voltage terminal, which is used to connect a reset control voltage, wherein when the gate control voltage and the read control voltage meet a first preset condition and the reset control voltage meets a second preset condition, the current frame pixel signal is sampled for the first time and the second time.

[0011] In one embodiment, the shared circuit includes: a fourth transistor, the gate of the fourth transistor is connected to the second electrode of the first transistor, and the first electrode of the fourth transistor is used to connect to the power supply voltage; a fifth transistor, the first electrode of the fifth transistor is used to connect to the power supply voltage, the second electrode of the fifth transistor is connected to the gate of the fourth transistor, and the gate of the fifth transistor is used to connect to the reset control voltage; a sixth transistor, the gate of the sixth transistor is used to connect to the read control voltage, the first electrode of the sixth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the sixth transistor is connected to a readout circuit for reading out a pixel signal of a current frame; a third resistor, one end of the third resistor is used to connect to a bias voltage, and the other end of the third resistor is connected to the gate of the fourth transistor.

[0012] In one embodiment, when the gate control voltage is at a low level, the read control voltage is at a high level, and the reset control voltage is at a high level, the current frame pixel signal is sampled for the first time; when the gate control voltage is at a high level, the read control voltage is at a high level, and the reset control voltage is at a low level, the current frame pixel signal is sampled for a second time.

[0013] In one embodiment, the common circuit includes: a seventh transistor, the gate of the seventh transistor is connected to the second electrode of the first transistor, and the first electrode of the seventh transistor is used to connect to the power supply voltage; an eighth transistor, the first electrode of the eighth transistor is used to connect to the power supply voltage, the second electrode of the eighth transistor is connected to the gate of the seventh transistor, and the gate of the eighth transistor is used to connect to the reset control voltage; a ninth transistor, the gate of the ninth transistor is used to connect to the read control voltage, the first electrode of the ninth transistor is connected to the second electrode of the seventh transistor, and the second electrode of the ninth transistor is connected to a readout circuit for reading out a pixel signal of a current frame; a storage capacitor, one end of the storage capacitor is used to connect to a bias voltage, and the other end of the storage capacitor is connected to the gate of the seventh transistor.

[0014] In one embodiment, the shared circuit includes: a tenth transistor, wherein the gate of the tenth transistor is used to connect to a read control voltage, and the first electrode of the tenth transistor is connected to a readout circuit for reading out a pixel signal of a current frame; a transimpedance amplifier, wherein the first input terminal of the transimpedance amplifier is connected to the second electrode of the first transistor, the second input terminal of the transimpedance amplifier is used to connect to a reference voltage, and the output terminal of the transimpedance amplifier is connected to the second electrode of the tenth transistor.

[0015] As a second aspect of an embodiment of the present application, an embodiment of the present application provides a display panel, comprising an active pixel sensor according to any implementation of the first aspect of the present application.

[0016] As a third aspect of the embodiments of the present application, the embodiments of the present application provide a display device, including a display panel according to the embodiment of the second aspect of the present application.

[0017] As a fourth aspect of an embodiment of the present application, an embodiment of the present application provides a flat-panel detection device, comprising an active pixel sensor according to any implementation of the first aspect of the present application.

[0018] The embodiment of the present application adopts the above technical solution to enable the common circuit to be arranged outside the pixel area, without being restricted by the pixel size, and can be compatible with photoconductive detectors.

[0019] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0021] Figure 1 A schematic diagram showing the circuit structure of an active pixel sensor in the related art is shown;

[0022] Figure 2 A control timing diagram of an active pixel sensor in the related art is shown;

[0023] Figure 3 A schematic diagram of the circuit structure of an active pixel sensor according to an embodiment of the present application is shown;

[0024] Figure 4 A schematic diagram showing the circuit structure of an active pixel sensor according to a first embodiment of the present application is shown;

[0025] Figure 5 A control timing diagram of an active pixel sensor according to a first embodiment of the present application is shown;

[0026] Figure 6 A schematic diagram showing the circuit structure of an active pixel sensor according to a second embodiment of the present application is shown;

[0027] Figure 7 FIG. 1 shows a control timing diagram of an active pixel sensor according to a second embodiment of the present application;

[0028] Figure 8 A schematic diagram showing the circuit structure of an active pixel sensor according to a third embodiment of the present application is shown;

[0029] Fig. 9 FIG. 1 shows a control timing diagram of an active pixel sensor according to a third embodiment of the present application;

[0030] Fig.10 An equivalent circuit diagram of an active pixel sensor according to a third embodiment of the present application is shown;

[0031] Fig.11 A schematic diagram showing the circuit structure of an active pixel sensor according to a fourth embodiment of the present application is shown;

[0032] Fig.12 FIG. 1 shows a control timing diagram of an active pixel sensor according to a fourth embodiment of the present application;

[0033] Fig.13 A schematic diagram showing the circuit structure of an active pixel sensor according to a fifth embodiment of the present application is shown;

[0034] Fig.14 FIG. 1 shows a control timing diagram of an active pixel sensor according to a fifth embodiment of the present application;

[0035] Fig.15A schematic diagram of the circuit structure of an active pixel sensor according to a sixth embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0037] Figure 1 FIG. 1 is a schematic diagram showing a circuit structure of an active pixel sensor in the related art. Figure 1 As shown in the related art, the circuit structure of the active pixel sensor generally includes three thin film transistors (T1, T2 and T3) located in the pixel area and a storage capacitor C Pix However, this circuit structure is limited by the pixel size, and since the responsivity of the photoconductive detector is related to the voltage across it, if the circuit structure of the active pixel sensor in the related art is adopted, the voltage across the photoconductive detector will change with the accumulation of the light signal, causing the photoconductive detector to have a nonlinear light response problem. Therefore, the circuit structure of the active pixel sensor in the related art is not compatible with the photoconductive detector, and it is impossible to effectively read out the pixel signal generated by the photoconductive detector.

[0038] Figure 2 FIG. 2 shows a control timing diagram of an active pixel sensor in the related art. Figure 2 As shown, there is a reset between the first sampling CDS1 and the second sampling CDS2 of the active pixel sensor in the related art, so that the correlation between the first sampling and the second sampling has a large difference. Moreover, an exposure time is required between the first sampling and the second sampling, and the pixel signals of other rows need to be sampled during the interval.

[0039] Combine the following Figure 3-Figure 15 An active pixel sensor 10 according to an embodiment of the first aspect of the present application is described.

[0040] Figure 3 FIG. 1 is a schematic diagram showing a circuit structure of an active pixel sensor 10 according to an embodiment of the present application. Figure 3 As shown, the active pixel sensor 10 includes a plurality of pixel circuits 100 arranged in an array and a plurality of common circuits 200. In the description of the present application, "plurality" means two or more.

[0041] Each pixel circuit 100 includes a first transistor 110 and a pixel sensing unit 120, wherein the pixel sensing unit 120 is used to generate a pixel signal, and the pixel sensing unit 120 is connected to the first electrode of the first transistor 110, wherein the gate of the first transistor 110 is used to connect the gate control voltage V Ex .

[0042] For example, in Figure 3 In the example of FIG. 1 , the pixel region 130 includes 16 pixel circuits 100 arranged in a 4-row 4-column array. The gates of the first transistors 110 of the pixel circuits 100 in each row are respectively connected to the corresponding gate control voltage V Ex Specifically, the gates of the first transistors 110 of the four pixel circuits 100 in the first row are all connected to V Ex-1 The gates of the first transistors 110 of the four pixel circuits 100 in the second row are all connected to V Ex-2 The gates of the first transistors 110 of the four pixel circuits 100 in the third row are all connected to V Ex-3 The gates of the first transistors 110 of the four pixel circuits 100 in the fourth row are all connected to V Ex-4 In each pixel circuit 100, one end of the pixel sensing unit 120 may be connected to the first electrode of the first transistor 110, and the other end of the pixel sensing unit 120 may be used to connect to the first bias voltage V Bias1 .

[0043] Optionally, the pixel sensing unit 120 may be a photoconductive detector such as a resistor. Compared with the circuit structure of an active pixel sensor including three thin film transistors and a storage capacitor in the related art, the voltage across the pixel sensing unit 120 will not change due to the accumulation of the light signal, and the nonlinear problem of light response of the pixel sensing unit 120 such as a photoconductive detector can be avoided.

[0044] The plurality of common circuits 200 correspond to the plurality of columns of pixel circuits 100 one by one. The second electrodes of the first transistors 110 in each column of pixel circuits 100 are connected to the common circuit 200 corresponding to the column of pixel circuits 100. The common circuit 200 also has a read control voltage terminal, which is used to connect the read control voltage V Read Therefore, the common circuit 200 can be disposed outside the pixel region 130 and is not limited by the pixel size.

[0045] For example, in Figure 3In the example of , four common circuits 200 are shown, and the four common circuits 200 correspond to the four columns of pixel circuits 100 one by one, and the four common circuits 200 are all located outside the pixel area 130. Among them, the second electrodes of the first transistors 110 in the four pixel circuits 100 in the first column are all connected to the first common circuit 200; the second electrodes of the first transistors 110 in the four pixel circuits 100 in the second column are all connected to the second common circuit 200; the second electrodes of the first transistors 110 in the four pixel circuits 100 in the third column are all connected to the third common circuit 200; and the second electrodes of the first transistors 110 in the four pixel circuits 100 in the fourth column are all connected to the fourth common circuit 200. Among them, one of the first electrode and the second electrode is a source electrode, and the other of the first electrode and the second electrode is a drain electrode.

[0046] Figure 3 16 pixel circuits 100 and 4 common circuits 200 are shown for illustrative purposes, but after reading the technical solution of the present application, ordinary technicians can obviously understand that the solution can be applied to the technical solution of other numbers of pixel circuits 100 and common circuits 200, which also falls within the protection scope of the present application.

[0047] The gate control voltage V Ex and read the control voltage V Read When the first preset condition is met, the current frame pixel signal is sampled for the first time and for the second time.

[0048] Exemplarily, the first sampling and the second sampling may be two samplings in Correlated Double Sample (CDS). The first sampling may sample the reset level of the pixel signal of the current frame, and the second sampling may sample the signal level of the pixel signal of the current frame, so that the noise voltages of the first sampling and the second sampling are substantially equal, and the interference of the reset noise may be substantially eliminated by subtracting the second sampling value from the first sampling value, and the actual effective amplitude of the signal level may be obtained, thereby effectively reading the pixel signal of the current frame.

[0049] The first preset condition corresponding to the first sampling and the first preset condition corresponding to the second sampling may be different. Ex is low and reads the control voltage V Read When the gate control voltage V Ex is low and reads the control voltage V Read is high level. At the gate control voltage V Ex is high and reads the control voltage V ReadWhen the gate control voltage V Ex is high and reads the control voltage V Read is high level.

[0050] In one embodiment, reference Figure 3 , Figure 5 , Figure 7 and Fig. 9 , the number of resets of the pixel sensing unit 120 between the first sampling and the second sampling is zero. Such a setting can effectively reduce the correlation difference between the first sampling and the second sampling, realize true correlation sampling, and thus effectively reduce the readout noise. Moreover, there is no need for an interval exposure time between the first sampling and the second sampling, which can effectively reduce the time interval between the first sampling and the second sampling, greatly compress the time required for each frame, and realize an ultra-high frame rate, so that the active pixel sensor 10 can be applied to the field of high-speed detection.

[0051] In one embodiment, if Figure 4 and Figure 5 As shown, the common circuit 200 includes a second transistor 210, a third transistor 220 and a first resistor 230. The gate of the second transistor 210 is connected to the second electrode of the first transistor 110, and the first electrode of the second transistor 210 is used to connect the power supply voltage V DD The gate of the third transistor 220 is used to connect the read control voltage V Read The first electrode of the third transistor 220 is connected to the second electrode of the second transistor 210, and the second electrode of the third transistor 220 is used to connect to the read-out integrated circuit (ROIC) 300 for reading out the pixel signal of the current frame. One end of the first resistor 230 (for example, Figure 4 The upper end of the DD , the other end of the first resistor 230 (eg, Figure 4 The lower end of the transistor 210 is connected to the gate of the second transistor 210.

[0052] Exemplarily, the second transistor 210 and the first resistor 230 may form an amplifier circuit. The gate of the second transistor 210 and the second electrode of the first transistor 110 may be connected via a connecting branch. The connection point between the first resistor 230 and the connecting branch is point G, and the potential at point G is the gate potential of the second transistor 210. One end of the pixel sensing unit 120, such as a photoconductive detector, may be connected to the first electrode of the first transistor 110, and the other end of the photoconductive detector may be used to connect the first bias voltage V Bias1 .

[0053] The specific working process can be: first, the gate control voltage V Ex The low level is turned on to turn off the first transistor 110. At this time, the pixel sensing unit 120, such as the photoconductive detector and the common circuit 200, can be isolated, and the potential of the G point is reset to the initial potential V DD , that is, V G =V DD During the G point potential reset process, read the control voltage V Read Turn on the high level and sample the pixel signal of the current frame for the first time CDS1 as the reference signal. After the G point potential is reset, the gate control voltage V Ex The high level is turned on to turn on the first transistor 110, and the pixel signal of the current frame is sampled for the second time CDS2 as the pixel sensing signal. G-signal The resistance R of the photoconductive detector in the light-sensitive state and the on-state resistance R of the first transistor 110 are determined by T1-on , the resistance Rc of the first resistor 230 and the first bias voltage V Bias1 With the power supply voltage V DD The potential difference,

[0054] In order to ensure that the leakage current of the photoconductive detector is less than 1pA (10 -12 A), the resistance R of the photoconductive detector is greater than 10 12 Ω. The on-state resistance R of the first transistor 110 T1-on Greater than or equal to 10 6 Ω less than 10 7 Ω. Moreover, the resistance Rc of the first resistor 230 is much smaller than the resistance R of the photoconductive detector. Therefore, Rc and R T1-on The sum is much smaller than R, and the potential of point G mentioned above in, is the photocurrent I of the photoconductive detector at a fixed voltage p ,Right now Where A is the current response coefficient of the photoconductive detector, and Q is the amount of light signal. Therefore, the signal difference between the first sampling and the second sampling is ΔV G =A·Q·R C The above process is repeated to read the pixel information of subsequent rows.

[0055] The readout circuit 300 may include a capacitive feedback transimpedance amplifier, a low pass filter (LPF), a correlated double sampling (CDS) chip, an analog-to-digital converter (ADC), a data converter (Data Processing) and a low voltage differential signal (LVDS) interface. The capacitive feedback transimpedance amplifier may include a capacitor C FB and amplifier AMP, C FB Accumulate charge and output voltage signal Vout. LPF is used to filter out high-frequency noise. CDS chip is used to perform the first sampling and the second sampling, and calculate the signal difference ΔV between the first sampling and the second sampling. G ADC is used to convert analog voltage signals into digital voltage signals. Data Processing is used to convert parallel data into serial data. LVDS is used to output signals.

[0056] In this embodiment, by setting the second transistor 210, the third transistor 220 and the first resistor 230, the pixel signal generated by the pixel sensing unit 120, such as a photoconductive detector, can be effectively read, thereby solving the nonlinear problem of the photoconductive detector.

[0057] In the above example, the power supply voltage V DD The signal is used as an example for explanation. Of course, the present application is not limited to this. In another embodiment, refer to Figure 6 and Figure 7 Combined with Figure 3 , power supply voltage V DD The first power supply voltage V DR and the second power supply voltage V DS , the first resistor 230 is connected to the first power supply voltage V DR , the first electrode of the second transistor 210 is connected to the second power supply voltage V DS , where the first power supply voltage V DR Less than or equal to the second power supply voltage V DS Therefore, the power supply voltage V DD The signal is split into the first power supply voltage V DR signal and second power supply voltage V DS Signal, at this time, the pixel signal generated by the pixel sensing unit 120, such as a photoconductive detector, can also be effectively read, solving the nonlinear problem of the photoconductive detector.

[0058] In one embodiment, reference Figure 8 and Fig. 9 The shared circuit 200 further includes a second resistor 240, one end of the second resistor 240 (eg, Figure 8 The lower end of the second resistor 240 is used to connect the bias voltage, and the other end of the second resistor 240 (for example, Figure 8 The upper end of the resistor 240 is connected to the gate of the second transistor 210, wherein the resistance value of the second resistor 240 is R C2 The resistance value R of the pixel sensing unit 120 in the non-light-sensitive state dark equal.

[0059] For example, in Figure 8 and Fig. 9 In the example, one end of the photoconductive detector can be connected to the first electrode of the first transistor 110, and the other end of the photoconductive detector can be used to connect the first bias voltage V Bias1 One end of the second resistor 240 is used to connect the second bias voltage V Bias2 , the other end of the second resistor 240 is connected to point G. At this time, the working process can be: first, the gate control voltage V Ex The low level is turned on to turn off the first transistor 110. At this time, the pixel sensing unit 120, such as the photoconductive detector and the common circuit 200, can be isolated, and the potential of the G point is reset to the initial potential V G-dark , V G-dark =V DR -I dark R C During the G point potential reset process, read the control voltage V Read Turn on the high level, sample the pixel signal of the current frame for the first time CDS1 as the reference signal, and the reference signal includes the leakage current signal of the photoconductive detector. Similar to the above embodiment, Rc and R T1-on The sum is much smaller than R. is the photocurrent of the photoconductive detector under a fixed voltage, that is, I dark It is the dark current of the photoconductive detector, that is, the current when the photoconductive detector is not exposed to light.

[0060] After the G point potential is reset, the gate control voltage V Ex The high level is turned on to turn on the first transistor 110, and the pixel signal of the current frame is sampled for the second time CDS2 as the pixel sensing signal. Fig.10 As shown, the potential at point G is V G-signal =V DR -(I p +I dark )R C =V DR -(A·Q+2Idark )R C In the correlated double sampling, the multiplication factor 2 is introduced, and the signal difference between the first sampling and the second sampling ΔV G =V G-signal -2V G-dark =A·Q·R C The above process is repeated to read the pixel information of subsequent rows.

[0061] In this embodiment, by setting the above-mentioned second resistor 240, the influence of the dark current of the pixel sensing unit 120, such as the photoconductive detector, can be fully considered, while reducing the influence of the first resistor 230 on the photoconductive detector, ensuring that the reference signal sampled for the first time can be the initial signal of the photoconductive detector, thereby effectively reducing the readout noise.

[0062] In one embodiment, in combination Figure 3 , Fig.11 and Fig.12 The common circuit 200 may also have a reset control voltage terminal, which is used to connect the reset control voltage V RST , where the gate control voltage V Ex and read the control voltage V Read The first preset condition is met and the control voltage V is reset RST When the second preset condition is met, the pixel signal of the current frame is sampled for the first time and for the second time.

[0063] For example, the first preset condition corresponding to the first sampling and the first preset condition corresponding to the second sampling may be different, and the second preset condition corresponding to the first sampling and the second preset condition corresponding to the second sampling may be different. Ex Low level, read control voltage V Read is high and resets the control voltage V RST When the gate control voltage V Ex is low and reads the control voltage V Read is high level; the second preset condition corresponding to the first sampling is: reset control voltage V RST is high level.

[0064] The gate control voltage V Ex High level, read control voltage V Read is high and resets the control voltage V RST When the gate control voltage V Exis high and reads the control voltage V Read is high level; the second preset condition corresponding to the second sampling is: reset control voltage V RST is low level.

[0065] Therefore, the gate control voltage V Ex , read the control voltage V Read and reset control voltage V RST Correlated double sampling is performed on the pixel signal of the current frame, so that the actual effective amplitude of the signal level can be obtained, and the pixel signal of the current frame can be effectively read out.

[0066] In one embodiment, if Fig.11 and Fig.12 As shown, the common circuit 200 includes a fourth transistor 250, a fifth transistor 260, a sixth transistor 270 and a third resistor 280. Specifically, the gate of the fourth transistor 250 is connected to the second electrode of the first transistor 110, and the first electrode of the fourth transistor 250 is used to connect the power supply voltage V DD The first electrode of the fifth transistor 260 is used to connect the power supply voltage V DD The second electrode of the fifth transistor 260 is connected to the gate of the fourth transistor 250, and the gate of the fifth transistor 260 is used to connect the reset control voltage V RST The gate of the sixth transistor 270 is used to connect the read control voltage V Read The first electrode of the sixth transistor 270 is connected to the second electrode of the fourth transistor 250, and the second electrode of the sixth transistor 270 is connected to the readout circuit 300 for reading out the pixel signal of the current frame. One end of the third resistor 280 (for example, Fig.11 The lower end of the bias voltage is used to connect a bias voltage such as a second bias voltage V Bias2 , the other end of the third resistor 280 (eg, Fig.11 The upper end of the transistor 250 is connected to the gate of the fourth transistor 250.

[0067] Exemplarily, the fourth transistor 250 and the fifth transistor 260 may form a source follower circuit. The gate of the fourth transistor 250 and the second electrode of the fifth transistor 260 may be connected via a connecting branch. The connection point between the third resistor 280 and the connecting branch is point G, and the potential of point G is the gate potential of the fourth transistor 250. One end of the photoconductive detector may be connected to the first electrode of the first transistor 110, and the other end of the photoconductive detector may be used to connect the first bias voltage V Bias1 .

[0068] The specific working process can be: first, the gate control voltage V ExThe low level is turned on to disconnect the first transistor 110. At this time, the pixel sensing unit 120, such as the photoconductive detector and the common circuit 200, can be isolated, and the control voltage V RST The high level is turned on to turn on the fifth transistor 260, and the potential of the G point is reset to the initial potential V G . V G Depends on the on-state resistance R of the fifth transistor 260 T2-on , the resistance value Rc of the third resistor 280 and the power supply voltage V DD With the second bias voltage V Bias2 The potential difference, Among them, V Bias2 ≤V DD To simplify the calculation, V Bias2 =V DD Take this as an example. G =V Bias2 =V DD During the G point potential reset process, read the control voltage V Read Turn on the high level and sample the current frame pixel signal for the first time CDS1 as the reference signal.

[0069] After the G point potential is reset, reset the control voltage V RST The low level is turned on to turn off the fifth transistor 260, and the gate control voltage V Ex The high level is turned on, the first transistor 110 is turned on, and then the pixel signal of the current frame is sampled for the second time CDS2 as the pixel sensing signal. At this time, the potential V G-signal The resistance R of the photoconductive detector after being exposed to light and the on-state resistance R of the first transistor 110 are determined by T1-on , the resistance Rc of the third resistor 280 and the first bias voltage V Bias1 With the second bias voltage V Bias2 The potential difference, Similarly, since Rc is related to R T1-on The sum of is much smaller than R, then in, is the photocurrent I of the photoconductive detector at a fixed voltage p ,Right now Therefore, the signal difference between the first sampling and the second sampling is ΔV G =A·Q·R C The above process is repeated to read the pixel information of subsequent rows.

[0070] In this embodiment, by setting the fourth transistor 250, the fifth transistor 260, the sixth transistor 270 and the third resistor 280, the pixel signal generated by the pixel sensing unit 120, such as a photoconductive detector, can also be effectively read, thereby solving the nonlinear problem of the photoconductive detector.

[0071] In one embodiment, if Fig.13 and Fig.14 As shown, the common circuit 200 includes a seventh transistor 20a, an eighth transistor 20b, a ninth transistor 20c and a storage capacitor 20d. Specifically, the gate of the seventh transistor 20a is connected to the second electrode of the first transistor 110, and the first electrode of the seventh transistor 20a is used to connect to the power supply voltage V DD The first electrode of the eighth transistor 20b is used to connect the power supply voltage V DD The second electrode of the eighth transistor 20b is connected to the gate of the seventh transistor 20a, and the gate of the eighth transistor 20b is used to connect the reset control voltage V RST The gate of the ninth transistor 20c is used to connect the read control voltage V Read The first electrode of the ninth transistor 20c is connected to the second electrode of the seventh transistor 20a, and the second electrode of the ninth transistor 20c is connected to the readout circuit 300 for reading out the pixel signal of the current frame. One end of the storage capacitor 20d (for example, Fig.13 The lower end of the bias voltage is used to connect a bias voltage such as a second bias voltage V Bias2 , the other end of the storage capacitor 20d (for example, Fig.13 The upper end of the transistor 20a is connected to the gate of the seventh transistor 20a.

[0072] For example, in Fig.13 and Fig.14 In the example, first the gate control voltage V Ex The low level is turned on to disconnect the first transistor 110. At this time, the pixel sensing unit 120, such as the photoconductive detector and the common circuit 200, can be isolated, and the control voltage V RST The high level is turned on to turn on the eighth transistor 20b, and the potential at point G is reset to the initial potential. After the potential at point G is reset, the control voltage V Read Turn on the high level and sample the pixel signal of the current frame for the first time CDS1 as the reference signal. Then, the gate control voltage V Ex The high level is turned on to turn on the first transistor 110 and maintain the preset time (ie, the exposure time T EX ). Then the gate control voltage V Ex The low level is turned on to turn off the first transistor 110, and the pixel signal of the current frame is sampled for the second time CDS2 as a pixel sensing signal. The above process is repeated to read the pixel information of the subsequent rows.

[0073] In this embodiment, by setting the above-mentioned seventh transistor 20a, eighth transistor 20b, ninth transistor 20c and storage capacitor 20d, since the storage capacitor 20d is located outside the pixel unit, there can be a larger space for placing a sufficiently large storage capacitor 20d, and the size of the storage capacitor 20d is no longer limited by the pixel size, so that it can better cooperate with the large amount of charge read out by the flat-panel detection device, reduce the signal-to-noise ratio of the signal read out by the flat-panel detection device, and then improve the imaging quality.

[0074] In one embodiment, if Fig.15 As shown, the common circuit 200 includes a tenth transistor 20e and a trans-impedance amplifier 20f (TIA). The gate of the tenth transistor 20e is used to connect the read control voltage V Read , the first electrode of the tenth transistor 20e is connected to the readout circuit 300 for reading out the pixel signal of the current frame. The first input terminal of the transimpedance amplifier 20f is connected to the second electrode of the first transistor 110, the second input terminal of the transimpedance amplifier 20f is used to connect the reference voltage Vref1, and the output terminal of the transimpedance amplifier 20f is connected to the second electrode of the tenth transistor 20e. For example, the transimpedance amplifier 20f can be a capacitive feedback transimpedance amplifier (CTIA) 20f. The transimpedance amplifier 20f can include a capacitor C FD and amplifier AMP, capacitor C FD The tenth transistor 20e can control the connection and isolation between the common circuit 200 and the readout circuit 300, thereby controlling the readout of the pixel signal.

[0075] Therefore, by providing the tenth transistor 20 e and the transimpedance amplifier 20 f , it is also possible to effectively read the pixel signal generated by the pixel sensing unit 120 , such as a photoconductive detector.

[0076] The display panel according to the embodiment of the second aspect of the present application includes an active pixel sensor 10 according to any implementation of the first aspect of the present application.

[0077] A display device according to an embodiment of the third aspect of the present application includes a display panel according to an embodiment of the second aspect of the present application.

[0078] The flat-panel detection device according to the embodiment of the fourth aspect of the present application includes an active pixel sensor 10 according to any implementation of the first aspect of the present application.

[0079] Other structures of the display panel, the display device and the flat panel detection device in the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0080] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0081] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0082] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0083] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0084] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0085] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An active pixel sensor, characterized in that: include: A plurality of pixel circuits arranged in an array, each of the pixel circuits comprising a first transistor and a pixel sensing unit for generating a pixel signal, the pixel sensing unit being connected to a source of the first transistor, wherein a gate of the first transistor is used to connect to a gate control voltage; A plurality of common circuits corresponding to the plurality of columns of pixel circuits one by one, the drains of the first transistors in each column of pixel circuits are connected to the common circuit corresponding to the column of pixel circuits, the common circuit further comprising a read control voltage terminal, the read control voltage terminal being used to connect a read control voltage; The common circuit further has a reset control voltage terminal, and the reset control voltage terminal is used to connect a reset control voltage. The common circuit includes: a fourth transistor, wherein a gate of the fourth transistor is connected to a drain of the first transistor, and a source of the fourth transistor is used to be connected to a power supply voltage; a fifth transistor, wherein a source of the fifth transistor is connected to the power supply voltage, a drain of the fifth transistor is connected to the gate of the fourth transistor, and a gate of the fifth transistor is connected to the reset control voltage; a sixth transistor, wherein the gate of the sixth transistor is used to connect to the read control voltage, the source of the sixth transistor is connected to the drain of the fourth transistor, and the drain of the sixth transistor is connected to a readout circuit for reading out a pixel signal of a current frame; A third resistor, one end of the third resistor is used to connect the bias voltage, and the other end of the third resistor is connected to the gate of the fourth transistor; Wherein, when the gate control voltage and the read control voltage meet a first preset condition, and the reset control voltage meets a second preset condition, the pixel signal of the current frame is sampled for the first time and the second time.

2. The active pixel sensor according to claim 1, characterized in that: The number of resets of the pixel sensing unit between the first sampling and the second sampling is zero.

3. The active pixel sensor according to claim 1, characterized in that: When the gate control voltage is at a low level, the read control voltage is at a high level, and the reset control voltage is at a high level, sampling the current frame pixel signal for the first time; When the gate control voltage is at a high level, the read control voltage is at a high level, and the reset control voltage is at a low level, the current frame pixel signal is sampled for a second time.

4. The active pixel sensor according to claim 1, characterized in that: The shared circuit comprises: a seventh transistor, wherein a gate of the seventh transistor is connected to the drain of the first transistor, and a source of the seventh transistor is used to be connected to a power supply voltage; an eighth transistor, wherein a source of the eighth transistor is connected to the power supply voltage, a drain of the eighth transistor is connected to the gate of the seventh transistor, and a gate of the eighth transistor is connected to the reset control voltage; a ninth transistor, wherein the gate of the ninth transistor is used to connect to the read control voltage, the source of the ninth transistor is connected to the drain of the seventh transistor, and the drain of the ninth transistor is connected to a readout circuit for reading out the pixel signal of the current frame; A storage capacitor, one end of which is used to connect to a bias voltage, and the other end of which is connected to the gate of the seventh transistor.

5. A display panel, characterized in that: Comprising an active pixel sensor according to any one of claims 1-4.

6. A display device, characterized in that: Comprising the display panel according to claim 5.

7. A flat panel detection device, characterized in that: Comprising an active pixel sensor according to any one of claims 1-4.

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