Source driving circuit, display device, and data driving method

Abstract

A source driver circuit includes: an interpolation circuit (1) and an auxiliary circuit (2); the interpolation circuit (1) is connected to a first reference voltage input terminal (IN1), a second reference voltage input terminal (IN2), a grayscale voltage output terminal (OUT-VG), and a control signal input terminal (CG), and is configured to perform interpolation processing between a first reference voltage (VL) provided by the first reference voltage input terminal (IN1) and a second reference voltage (VH) provided by the second reference voltage input terminal (IN2) in response to the control of an interpolation control signal provided by the control signal input terminal (CG), and write the target grayscale voltages (V2, V4) obtained by the interpolation processing to the grayscale voltage output terminal (OUT-VG), the first reference voltage (VL) being less than the second reference voltage (VH); the auxiliary circuit (2) is connected to the first reference voltage input terminal (IN1), the second reference voltage input terminal (IN2), and the grayscale voltage output terminal (OUT-VG), and is configured to charge the grayscale voltage output terminal (OUT-VG) when the voltage at the grayscale voltage output terminal (OUT-VG) is less than the first reference voltage (VL), and discharge the grayscale voltage output terminal (OUT-VG) when the voltage at the grayscale voltage output terminal (OUT-VG) is greater than the second reference voltage (VH).

Description

Technical Field

[0001] The present invention relates to the field of displays, and particularly to a source driver circuit, a display device, and a data driving method. Background Art

[0002] Compared with the traditional passive matrix pixel driving technology, the currently commonly used active matrix pixel driving technology has the advantages of high efficiency, low power consumption, easy colorization, high brightness, and high resolution.

[0003] The specific feature of active array pixel driving is to perform progressive scanning to drive each row of pixels row by row. However, with the gradual increase in the resolution of the display device, the number of pixel rows in the display device increases, resulting in a shorter row scanning time. At this time, the response speed requirement for the source driver circuit is more stringent. If the response speed is too slow, it will limit the further improvement of the resolution, becoming a major problem in the design of high-performance source driver circuits. Summary of the Invention

[0004] The present invention provides a source driver circuit, a display device, and a data driving method.

[0005] In a first aspect, the present invention provides a source driver circuit, including:

[0006] An interpolation circuit, connected to a first reference voltage input terminal, a second reference voltage input terminal, a grayscale voltage output terminal, and a control signal input terminal, configured to perform interpolation processing between the first reference voltage provided by the first reference voltage input terminal and the second reference voltage provided by the second reference voltage input terminal in response to the control of the interpolation control signal provided by the control signal input terminal, and write the target grayscale voltage obtained by the interpolation processing to the grayscale voltage output terminal, where the first reference voltage is less than the second reference voltage;

[0007] An auxiliary circuit, connected to the first reference voltage input terminal, the second reference voltage input terminal, and the grayscale voltage output terminal, configured to charge the grayscale voltage output terminal when the voltage at the grayscale voltage output terminal is less than the first reference voltage, and discharge the grayscale voltage output terminal when the voltage at the grayscale voltage output terminal is greater than the second reference voltage.

[0008] In some embodiments, the auxiliary circuit includes: a first feedback circuit, a second feedback circuit, and a first output circuit;

[0009] The first feedback circuit is configured with a first input terminal, a second input terminal, and a first output terminal. The first input terminal is connected to the first reference voltage input terminal, the second input terminal is connected to the grayscale voltage output terminal, the first output terminal is connected to the first output circuit, and the first feedback circuit is configured to output a first control signal in an active level state to the first output circuit when the voltage at the grayscale voltage output terminal is less than the first reference voltage;

[0010] The second feedback circuit is configured with a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is connected to the second reference voltage input terminal, the fourth input terminal is connected to the grayscale voltage output terminal, the second output terminal is connected to the first output circuit, and the second feedback circuit is configured to output a second control signal in an active level state to the first output circuit when the voltage at the grayscale voltage output terminal is greater than the second reference voltage;

[0011] The first output circuit is connected to the grayscale voltage output terminal, and the grayscale voltage output terminal is configured to charge the grayscale voltage output terminal in response to the control of the first control signal in an active level state, and discharge the grayscale voltage output terminal in response to the control of the second control signal in an active level state.

[0012] In some embodiments, the first feedback circuit includes: a first comparator circuit;

[0013] The first input terminal is the inverting input terminal of the first comparator circuit, the second input terminal is the non-inverting input terminal of the first comparator circuit, and the first output terminal is the output terminal of the first comparator circuit.

[0014] In some embodiments, the first feedback circuit includes: a first comparator circuit and a first inverter circuit, and the output terminal of the first comparator circuit is connected to the input terminal of the first inverter circuit;

[0015] The first input terminal is the non-inverting input terminal of the first comparator circuit, the second input terminal is the inverting input terminal of the first comparator circuit, and the first output terminal is the output terminal of the first comparator circuit.

[0016] In some embodiments, the second feedback circuit includes: a second comparator circuit;

[0017] The third input terminal is the inverting input terminal of the second comparator circuit, the fourth input terminal is the non-inverting input terminal of the second comparator circuit, and the second output terminal is the output terminal of the second comparator circuit.

[0018] In some embodiments, the second feedback circuit includes: a second comparator circuit and a second inverter circuit, and an output terminal of the second comparator circuit is connected to an input terminal of the second inverter circuit;

[0019] The third input terminal is a non-inverting input terminal of the second comparator circuit, the fourth input terminal is an inverting input terminal of the second comparator circuit, and the second output terminal is an output terminal of the second comparator circuit.

[0020] In some embodiments, at least one of the comparator circuit in the first feedback circuit and the comparator circuit in the second feedback circuit includes: a first bias circuit, an amplification stage circuit, and a second output circuit;

[0021] The first bias circuit is connected to the amplification stage circuit and the second output circuit, and the first bias circuit is configured to provide a bias voltage to the amplification stage circuit and the second output circuit;

[0022] The amplification stage circuit is configured with two input terminals and serves as the non-inverting input terminal and the inverting input terminal of the comparator circuit respectively. An output terminal of the amplification stage circuit is connected to the second output circuit, and the amplification stage circuit is configured to amplify the difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal and output it;

[0023] The second output circuit is configured to receive the voltage output by the amplification stage circuit and perform secondary amplification to output a corresponding high-level signal or low-level signal.

[0024] In some embodiments, the first output circuit includes: a charging circuit and a discharging circuit

[0025] The charging circuit is connected to the first output terminal, the grayscale voltage output terminal, and the first power supply terminal. The charging circuit is configured to charge the grayscale voltage output terminal through the first power supply terminal under the control of the first control signal in an active level state;

[0026] The discharging circuit is connected to the second output terminal, the grayscale voltage output terminal, and the second power supply terminal. The discharging circuit is configured to discharge the grayscale voltage output terminal through the second power supply terminal under the control of the second control signal in an active level state.

[0027] In some embodiments, the charging circuit includes: a first transistor;

[0028] A control electrode of the first transistor is connected to the first output terminal, a first electrode of the first transistor is connected to the first power supply terminal, and a second electrode of the first transistor is connected to the grayscale voltage output terminal.

[0029] In some embodiments, the first control signal in the active level state is a low-level signal, and the first transistor is a P-type transistor.

[0030] In some embodiments, the discharge circuit includes: a second transistor;

[0031] The control electrode of the second transistor is connected to the second output terminal, the first electrode of the second transistor is connected to the grayscale voltage output terminal, and the second electrode of the second transistor is connected to the second power supply terminal.

[0032] In some embodiments, the second control signal in the active level state is a high-level signal, and the second transistor is an N-type transistor.

[0033] In some embodiments, the interpolation circuit is a linear interpolation circuit.

[0034] In some embodiments, the linear interpolation circuit includes: a programmable current circuit, a voltage-current conversion circuit, and a third output circuit. The output terminal of the programmable current circuit, the output terminal of the voltage-current conversion circuit, and the input terminal of the third output circuit are connected to each other;

[0035] The programmable current circuit is connected to the first reference voltage input terminal, the second reference voltage input terminal, and the control signal input terminal. The programmable current circuit is configured to use the first reference voltage and the second reference voltage as input operating voltages and output corresponding currents in response to the control of the interpolation control signal;

[0036] The non-inverting input terminal of the voltage-current conversion circuit is connected to the output terminal of the third output circuit, the inverting input terminal of the voltage-current conversion circuit is connected to the first reference voltage input terminal, and the output terminal of the voltage-current conversion circuit is connected to the input terminal of the third output circuit. The voltage-current conversion circuit is configured to convert the voltage difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal into a corresponding current;

[0037] The output terminal of the third output circuit is connected to the grayscale voltage output terminal. The third output circuit is configured to receive, through the input terminal, the current formed by the superposition of the current output by the programmable current circuit and the current output by the voltage-current conversion circuit, and output the corresponding target grayscale voltage according to the received current.

[0038] In some embodiments, the linear interpolation circuit further includes: a frequency compensation circuit;

[0039] The frequency compensation circuit is connected to the input end and the output end of the third output circuit, and the frequency compensation circuit is configured to perform frequency compensation on the third output circuit.

[0040] In some embodiments, the linear interpolation circuit further includes: a second bias circuit;

[0041] The second bias circuit is connected to the programmable current circuit, the voltage-current conversion circuit, and the third output circuit, and the second bias circuit is configured to provide a bias voltage to the programmable current circuit, the voltage-current conversion circuit, and the third output circuit.

[0042] In a second aspect, an embodiment of the present invention further provides a display device, including: a display area and a non-display area located outside the display area, and the source driver circuit provided in the first aspect as described above is disposed in the non-display area.

[0043] In a third aspect, an embodiment of the present invention further provides a data driving method, based on the source driver circuit provided in the first aspect, the data driving method includes:

[0044] The interpolation circuit responds to the interpolation control signal provided by the control signal input end, performs interpolation processing between the first reference voltage and the second reference voltage, and writes the target gray-scale voltage obtained by the interpolation processing to the gray-scale voltage output end; wherein, when the voltage at the gray-scale voltage output end is less than the first reference voltage, the auxiliary circuit charges the gray-scale voltage output end, and when the voltage at the gray-scale voltage output end is greater than the second reference voltage, the auxiliary circuit discharges the gray-scale voltage output end. Description of the Drawings

[0045] Figure 1 It is a schematic circuit structure diagram of a source driver circuit provided by an embodiment of the present invention;

[0046] Figure 2 It is a schematic diagram comparing the charging timing waveforms of the source driver circuit provided by the present invention and the traditional source driver circuit;

[0047] Figure 3 It is a schematic diagram comparing the discharging timing waveforms of the source driver circuit provided by the present invention and the traditional source driver circuit;

[0048] Figure 4 It is a schematic circuit structure diagram of another source driver circuit provided by an embodiment of the present invention;

[0049] Figure 5 It is a schematic circuit structure diagram of yet another source driver circuit provided by an embodiment of the present invention;

[0050] Figure 6 It is a schematic diagram of a circuit structure of a comparator circuit in an embodiment of the present invention;

[0051] Figure 7 It is a schematic diagram of a circuit structure of an interpolation circuit in an embodiment of the present invention;

[0052] Figure 8 It is another schematic diagram of a circuit structure of an interpolation circuit in an embodiment of the present invention. Detailed implementation manners

[0053] To enable those skilled in the art to better understand the technical solutions of the present invention, a source driving circuit, a display device, and a data driving method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0054] Figure 1 It is a schematic diagram of a circuit structure of a source driving circuit provided by an embodiment of the present invention. As Figure 1 shown, the source driving power supply includes: an interpolation circuit 1 and an auxiliary circuit 2.

[0055] Among them, the interpolation circuit 1 is connected to a first reference voltage input terminal IN1, a second reference voltage input terminal IN2, a grayscale voltage output terminal OUT_VG, and a control signal input terminal CG. The interpolation circuit 1 is configured to perform interpolation processing between the first reference voltage provided by the first reference voltage input terminal IN1 and the second reference voltage provided by the second reference voltage input terminal IN2 in response to the control of the interpolation control signal provided by the control signal input terminal CG, and write the target grayscale voltage obtained by the interpolation processing to the grayscale voltage output terminal OUT_VG. The first reference voltage is less than the second reference voltage.

[0056] The auxiliary circuit 2 is connected to the first reference voltage input terminal IN1, the second reference voltage input terminal IN2, and the grayscale voltage output terminal OUT_VG. The auxiliary circuit 2 is configured to charge the grayscale voltage output terminal OUT_VG when the voltage at the grayscale voltage output terminal OUT_VG is less than the first reference voltage, and discharge the grayscale voltage output terminal OUT_VG when the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage.

[0057] In the embodiment of the present invention, a plurality of different reference voltages are pre-configured. By performing interpolation processing on two adjacent reference voltages in terms of magnitude, a plurality of target grayscale voltages between the two adjacent reference voltages in terms of magnitude can be output (taking the case where the interpolation control signal samples 3 bits as an example, there are 2 3 = 8 kinds of interpolation control signals, and the interpolation circuit 1 can perform 2 3= 8 different interpolation processes). As an example, if the reference voltage is represented by 7 bits and the interpolation control signal is represented by 3 bits, then there are 2 7 + 1 = 129 types (specifically including 128 reference voltages with non-zero voltage magnitudes generated by the external circuit in response to the 7-bit control signal and 1 reference voltage with a voltage magnitude of 0V directly provided by the power supply). Since there are 8 different interpolation processes between every two adjacent reference voltages, the interpolation circuit 1 can actually output (129 - 1) × 8 = 1024 types of target gray-scale voltages.

[0058] During the actual data driving process, by providing the first reference voltage, the second reference voltage, and the corresponding interpolation control signal corresponding to the target gray-scale voltage to be output to the interpolation circuit 1, the interpolation circuit 1 can be controlled to output the corresponding gray-scale circuit.

[0059] The source driving circuit provided by the embodiment of the present invention has three working states: a stable working state, a fast charging state, and a fast discharging state.

[0060] When the voltage at the gray-scale voltage output terminal OUT_VG is greater than or equal to the first reference voltage and less than or equal to the second reference voltage, the source driving circuit is in a stable working state. At this time, the auxiliary circuit 2 neither charges nor discharges the gray-scale voltage output terminal OUT_VG, and only the interpolation circuit 1 writes the target gray-scale voltage to the gray-scale voltage output terminal OUT_VG.

[0061] When the voltage at the gray-scale voltage output terminal OUT_VG is less than the first reference voltage, the source driving circuit is in a fast charging state. At this time, the auxiliary circuit 2 charges the gray-scale voltage output terminal OUT_VG, and at the same time, the interpolation circuit 1 writes the target gray-scale voltage to the gray-scale voltage output terminal OUT_VG (the target gray-scale voltage is greater than the first reference voltage. When the voltage at the gray-scale voltage output terminal OUT_VG is less than the first reference voltage, it can be regarded as the interpolation circuit 1 charging the gray-scale voltage output terminal OUT_VG), that is, the auxiliary circuit 2 and the interpolation circuit 1 charge the gray-scale voltage output terminal OUT_VG at the same time, and the voltage at the gray-scale voltage output terminal OUT_VG will rise rapidly.

[0062] When the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage, the source driver circuit is in a fast discharge state. At this time, the auxiliary circuit 2 discharges the grayscale voltage output terminal OUT_VG, and at the same time, the interpolation circuit 1 writes the target grayscale voltage to the grayscale voltage output terminal OUT_VG (the target grayscale voltage is less than the second reference voltage. When the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage, it can be regarded as the interpolation circuit 1 discharging the grayscale voltage output terminal OUT_VG), that is, the auxiliary circuit 2 and the interpolation circuit 1 discharge the grayscale voltage output terminal OUT_VG at the same time, and the voltage at the grayscale voltage output terminal OUT_VG will drop rapidly.

[0063] The fast charging and fast discharging processes of the source driver circuit of the present invention will be described in detail below with specific examples. Among them, the magnitude of the first reference voltage is denoted as VL, and the magnitude of the second reference voltage is denoted as VH.

[0064] Figure 2 It is a schematic diagram comparing the charging timing waveforms of the source driver circuit provided by the present invention and the traditional source driver circuit. As Figure 2 shown, the initial voltage (the target grayscale voltage output by the source driver circuit last time) is V1, the target grayscale voltage is V2, and V1 < VL < V2 < VH is satisfied, that is, it is necessary to charge the voltage at the grayscale voltage output terminal OUT_VG from V1 to V2.

[0065] The source driver circuit provided by the present invention divides the process of charging the voltage at the grayscale voltage output terminal OUT_VG from V1 to V2 into two stages: the fast charging stage from t1 to t2 and the stable charging stage from t2 to t3. Among them, in the fast charging stage from t1 to t2, the interpolation circuit 1 and the auxiliary circuit 2 charge the grayscale voltage output terminal OUT_VG at the same time, and the voltage at the grayscale voltage output terminal OUT_VG rapidly increases from V1 to VL. In the stable charging stage from t2 to t3, the voltage at the grayscale voltage output terminal OUT_VG is very close to the target grayscale voltage. At this time, the auxiliary circuit 2 stops working, and only the interpolation circuit 1 charges the grayscale voltage output terminal OUT_VG to charge the voltage at the grayscale voltage output terminal OUT_VG to the target grayscale voltage. The time required for the source driver circuit provided by the present invention to charge the voltage at the grayscale voltage output terminal OUT_VG from V1 to V2 is t3 - t1.

[0066] During the process of charging the voltage at the grayscale voltage output terminal OUT_VG from V1 to V2 by the conventional source driver circuit, only the interpolation circuit 1 charges the grayscale voltage output terminal OUT_VG. The time required for the conventional source driver circuit to charge the voltage at the grayscale voltage output terminal OUT_VG from V1 to V2 is t4 - t1. Since t3 < t4, the source driver circuit provided by the present invention has a faster charging speed.

[0067] Figure 3 It is a schematic diagram comparing the discharge timing waveforms of the source driver circuit provided by the present invention and the conventional source driver circuit. As Figure 3 shown, the initial voltage (the target grayscale voltage output by the source driver circuit last time) is V3, the target grayscale voltage is V4, and VL < V4 < VH < V3 is satisfied, that is, it is necessary to discharge the voltage at the grayscale voltage output terminal OUT_VG from V3 to V4.

[0068] The process of discharging the voltage at the grayscale voltage output terminal OUT_VG from V3 to V4 by the source driver circuit provided by the present invention is divided into two stages: a fast discharge stage from t5 to t6 and a stable discharge stage from t6 to t7. Among them, in the fast discharge stage from t5 to t6, the interpolation circuit 1 and the auxiliary circuit 2 discharge the grayscale voltage output terminal OUT_VG at the same time, and the voltage at the grayscale voltage output terminal OUT_VG rapidly drops from V3 to VH. In the stable discharge stage from t6 to t7, the voltage at the grayscale voltage output terminal OUT_VG is very close to the target grayscale voltage. At this time, the auxiliary circuit 2 stops working, and only the interpolation circuit 1 discharges the grayscale voltage output terminal OUT_VG to discharge the voltage at the grayscale voltage output terminal OUT_VG to the target grayscale voltage. The time required for the source driver circuit provided by the present invention to discharge the voltage at the grayscale voltage output terminal OUT_VG from V3 to V4 is t7 - t5.

[0069] During the process of discharging the voltage at the grayscale voltage output terminal OUT_VG from V3 to V4 by the conventional source driver circuit, only the interpolation circuit 1 discharges the grayscale voltage output terminal OUT_VG. The time required for the conventional source driver circuit to discharge the voltage at the grayscale voltage output terminal OUT_VG from V3 to V4 is t8 - t5. Since t7 < t8, the source driver circuit provided by the present invention has a faster discharge speed.

[0070] It should be noted that when both the initial voltage and the target gray-scale voltage are between the first reference voltage and the second reference voltage, the duration for the source driver circuit provided by the present invention to charge / discharge the voltage at the gray-scale voltage output terminal OUT_VG from the initial voltage to the target gray-scale voltage is equal to the duration for the conventional source driver circuit to charge / discharge the voltage at the gray-scale voltage output terminal OUT_VG from the initial voltage to the target gray-scale voltage. Since both the initial voltage and the target gray-scale voltage are between the first reference voltage and the second reference voltage, the initial voltage and the target gray-scale voltage are close, and thus the required charge / discharge time is relatively short.

[0071] Based on the foregoing analysis, it can be seen that, compared with the conventional source driver circuit, the source driver circuit provided by the present invention can improve the charge / discharge speed of the gray-scale voltage output terminal OUT_VG when there is a large difference between the initial voltage and the target gray-scale voltage, so that the voltage at the gray-scale voltage output terminal OUT_VG can quickly reach the target gray-scale voltage; in addition, the auxiliary circuit 2 operates under the control of the voltage at the gray-scale voltage output terminal OUT_VG and forms a negative feedback with the gray-scale voltage output terminal OUT_VG (which will be described exemplarily in combination with the specific circuit structure later), and this negative feedback can enhance the stability of the output at the gray-scale voltage output terminal. Therefore, the source driver circuit provided by the embodiment of the present invention can achieve a stable output while having a fast charge / discharge speed.

[0072] Figure 4 FIG. is a schematic circuit diagram of another source driver circuit provided by an embodiment of the present invention, as Figure 4 shown, Figure 4 The shown source driver circuit is a specific optional implementation scheme based on the Figure 1 shown source driver circuit. Among them, the auxiliary circuit 2 includes: a first feedback circuit 201, a second feedback circuit 202, and a first output circuit.

[0073] The first feedback circuit 201 is configured with a first input terminal, a second input terminal, and a first output terminal. The first input terminal is connected to the first reference voltage input terminal IN1, the second input terminal is connected to the gray-scale voltage output terminal OUT_VG, and the first output terminal is connected to the first output circuit. The first feedback circuit 201 is configured to output a first control signal in an effective level state to the first output circuit when the voltage at the gray-scale voltage output terminal OUT_VG is less than the first reference voltage;

[0074] The second feedback circuit 202 is configured with a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is connected to the second reference voltage input terminal IN2, the fourth input terminal is connected to the grayscale voltage output terminal OUT_VG, and the second output terminal is connected to the first output circuit. The second feedback circuit 202 is configured to output a second control signal in an active level state to the first output circuit when the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage;

[0075] The first output circuit is connected to the grayscale voltage output terminal OUT_VG. The grayscale voltage output terminal OUT_VG is configured to perform a charging process on the grayscale voltage output terminal OUT_VG in response to the control of the first control signal in an active level state, and perform a discharging process on the grayscale voltage output terminal OUT_VG in response to the control of the second control signal in an active level state.

[0076] In some embodiments, the first feedback circuit 201 includes: a first comparator circuit 2011; the first input terminal is the inverting input terminal of the first comparator circuit 2011, the second input terminal is the non-inverting input terminal of the first comparator circuit 2011, and the first output terminal is the output terminal of the first comparator circuit 2011.

[0077] In some embodiments, the second feedback circuit 202 includes: a second comparator circuit 2021; the third input terminal is the inverting input terminal of the second comparator circuit 2021, the fourth input terminal is the non-inverting input terminal of the second comparator circuit 2021, and the second output terminal is the output terminal of the second comparator circuit 2021.

[0078] In the embodiments of the present invention, the "comparator circuit" is configured to perform differential amplification processing on the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal and then output.

[0079] In some embodiments, the first output circuit 203 includes: a charging circuit and a discharging circuit; wherein, the charging circuit is connected to the first output terminal, the grayscale voltage output terminal OUT_VG, and the first power supply terminal, and the charging circuit is configured to perform a charging process on the grayscale voltage output terminal OUT_VG through the first power supply terminal in response to the control of the first control signal in an active level state; the discharging circuit is connected to the second output terminal, the grayscale voltage output terminal OUT_VG, and the second power supply terminal, and the discharging circuit is configured to perform a discharging process on the grayscale voltage output terminal OUT_VG through the second power supply terminal in response to the control of the second control signal in an active level state.

[0080] In some embodiments, the charging circuit includes: a first transistor T1; a control electrode of the first transistor T1 is connected to a first output terminal, a first electrode of the first transistor T1 is connected to a first power supply terminal, and a second electrode of the first transistor T1 is connected to a grayscale voltage output terminal OUT_VG. Further optionally, the first control signal in an active level state is a low-level signal, and the first transistor T1 is a P-type transistor. Wherein, the first power supply terminal provides a first operating voltage VDD.

[0081] In some embodiments, the discharging circuit includes: a second transistor T2; a control electrode of the second transistor T2 is connected to a second output terminal, a first electrode of the second transistor T2 is connected to the grayscale voltage output terminal OUT_VG, and a second electrode of the second transistor T2 is connected to a second power supply terminal. Further optionally, the second control signal in an active level state is a high-level signal, and the second transistor T2 is an N-type transistor. Wherein, the second power supply terminal provides a second operating voltage VSS.

[0082] In the present invention, each transistor can be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. Wherein, the "control electrode" specifically refers to the gate of the transistor, the "first electrode" specifically refers to the source of the transistor, and the "second electrode" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "first electrode" and the "second electrode" can be interchanged, that is, the "first electrode" specifically refers to the drain of the transistor, and the "second electrode" specifically refers to the source of the transistor.

[0083] In addition, classified by transistor type, transistors can be divided into N-type transistors and P-type transistors; wherein, an N-type transistor is turned on when controlled by a high-level signal and turned off when controlled by a low-level signal; a P-type transistor is turned on when controlled by a low-level signal and turned off when controlled by a high-level signal.

[0084] When the voltage at the grayscale voltage output terminal OUT_VG is greater than or equal to a first reference voltage and less than or equal to a second reference voltage, in the auxiliary circuit 2, the first comparator circuit 2011 outputs a high-level signal (that is, the first feedback circuit 201 outputs a high-level signal), and the second comparator circuit 2021 outputs a low-level signal (that is, the second feedback circuit 202 outputs a low-level signal). Since the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, both the first transistor T1 and the second transistor T2 are turned off. That is, the auxiliary circuit 2 does not charge or discharge the grayscale voltage output terminal OUT_VG.

[0085] When the voltage at the grayscale voltage output terminal OUT_VG is less than the first reference voltage, in the auxiliary circuit 2, the first comparator circuit 2011 outputs a low-level signal (i.e., the first feedback circuit 201 outputs a low-level signal), and the second comparator circuit 2021 outputs a low-level signal (i.e., the second feedback circuit 202 outputs a low-level signal). Since the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first transistor T1 is turned on and the second transistor T2 is turned off. At this time, the first power supply terminal charges the grayscale voltage output terminal OUT_VG through the first transistor T1.

[0086] When the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage, in the auxiliary circuit 2, the first comparator circuit 2011 outputs a high-level signal (i.e., the first feedback circuit 201 outputs a high-level signal), and the second comparator circuit 2021 outputs a high-level signal (i.e., the second feedback circuit 202 outputs a high-level signal). Since the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first transistor T1 is turned off and the second transistor T2 is turned on. At this time, the second power supply terminal discharges the grayscale voltage output terminal OUT_VG through the second transistor T2.

[0087] In the embodiment of the present invention, the first feedback circuit 201 and the charging circuit form a first negative feedback regulation path, and the second feedback circuit 202 and the discharging circuit form a second negative feedback regulation path. When the voltage at the grayscale voltage output terminal OUT_VG is greater than or equal to the first reference voltage and less than or equal to the second reference voltage, both the first negative feedback regulation path and the second negative feedback regulation path do not work; when the voltage at the grayscale voltage output terminal OUT_VG is less than the first reference voltage, under the negative feedback regulation of the interpolation circuit 1 and the first negative feedback regulation path, the voltage at the grayscale voltage output terminal OUT_VG is quickly charged to the first reference voltage; when the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage, under the negative feedback regulation of the interpolation circuit 1 and the second negative feedback regulation path, the voltage at the grayscale voltage output terminal OUT_VG is quickly discharged to the second reference voltage.

[0088] Ideally, the outputs of the first / second comparator circuits 2011 and 2021 can only take two possible values: high level and low level. However, in practical applications, non-ideal situations often occur. When the voltage difference between the signals input to the two input terminals of the first / second comparator circuits 2011 and 2021 is very small, the voltage output by the first / second comparator circuits 2011 and 2021 is neither high level nor low level, but a certain voltage value between the high level and the low level. This voltage between the high level and the low level is input to the control electrodes of the first transistor T1 and the second transistor T2, which may cause both the first transistor T1 and the second transistor T2 to conduct. There is a conduction current between the first transistor T1 and the second transistor T2, which not only increases the static power consumption of the first output circuit 203, but also reduces the response speed of the entire source driver circuit due to the decrease in the current flowing to the gray-scale voltage output terminal OUT_VG.

[0089] To solve the above technical problems, the embodiments of the present invention provide corresponding solutions. Figure 5 A circuit structure diagram of another source driver circuit provided by an embodiment of the present invention is shown in Figure 5 as follows Figure 5 The source driver circuit shown is based on Figure 1 A specific optional implementation of the source driver circuit shown. Different from the situation shown in Figure 4 , in the solution shown in Figure 5 , the first feedback circuit 201 includes: a first comparator circuit 2011 and a first inverter circuit 2012, and the second feedback circuit 202 includes: a second comparator circuit 2021 and a second inverter circuit 2022.

[0090] Among them, the output terminal of the first comparator circuit 2011 is connected to the input terminal of the first inverter circuit 2012; the first input terminal is the non-inverting input terminal of the first comparator circuit 2011, the second input terminal is the inverting input terminal of the first comparator circuit 2011, and the first output terminal is the output terminal of the first comparator circuit 2011.

[0091] The output terminal of the second comparator circuit 2021 is connected to the input terminal of the second inverter circuit 2022; the third input terminal is the non-inverting input terminal of the second comparator circuit 2021, the fourth input terminal is the inverting input terminal of the second comparator circuit 2021, and the second output terminal is the output terminal of the second comparator circuit 2021.

[0092] In this embodiment, by arranging a first inverter circuit between the first comparator circuit 2011 and the charging circuit, and arranging a second inverter circuit 2022 between the second comparator circuit 2021 and the discharging circuit, the first inverter circuit and the second inverter circuit 2022 can greatly suppress the influence caused by the non-ideal transfer characteristic curves of the first comparator circuit 2011 and the second comparator circuit 2021, so that the voltages input to the charging circuit (the first transistor T1) and the discharging circuit (the second transistor T2) are clamped at a high level or a low level, avoiding the situation where the first regulating transistor and the second regulating transistor are turned on simultaneously due to the existence of an intermediate level, thereby effectively ensuring the driving ability and reducing power consumption losses.

[0093] Among them, both the first / second inverter circuits 2012 and 2022 can be composed of one N-type transistor NMOS and one P-type transistor PMOS.

[0094] Next, Figure 5 the working processes of the auxiliary circuit 2 in the shown scheme under different conditions will be described in detail.

[0095] When the voltage at the grayscale voltage output terminal OUT_VG is greater than or equal to the first reference voltage and less than or equal to the second reference voltage, in the auxiliary circuit 2, the first comparator circuit 2011 outputs a low-level signal, the first inverter circuit 2012 outputs a high-level signal (i.e., the first feedback circuit 201 outputs a high-level signal), the second comparator circuit 2021 outputs a high-level signal, and the second inverter circuit 2022 outputs a low-level signal (i.e., the second feedback circuit 202 outputs a low-level signal). Since the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, both the first transistor T1 and the second transistor T2 are turned off. That is, the auxiliary circuit 2 does not charge or discharge the grayscale voltage output terminal OUT_VG.

[0096] When the voltage at the grayscale voltage output terminal OUT_VG is less than the first reference voltage, in the auxiliary circuit 2, the first comparator circuit 2011 outputs a high-level signal, the first inverter circuit 2012 outputs a low-level signal (i.e., the first feedback circuit 201 outputs a low-level signal), the second comparator circuit 2021 outputs a high-level signal, and the second inverter circuit 2022 outputs a low-level signal (i.e., the second feedback circuit 202 outputs a low-level signal). Since the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first transistor T1 is turned on and the second transistor T2 is turned off. At this time, the first power supply terminal charges the grayscale voltage output terminal OUT_VG through the first transistor T1.

[0097] When the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage, in the auxiliary circuit 2, the first comparator circuit 2011 outputs a low-level signal, the first inverter circuit 2012 outputs a high level (i.e., the first feedback circuit 201 outputs a high-level signal), the second comparator circuit 2021 outputs a low-level signal, and the second inverter circuit 2022 outputs a high level (i.e., the second feedback circuit 202 outputs a high-level signal). Since the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first transistor T1 is turned off and the second transistor T2 is turned on. At this time, the second power supply terminal discharges the grayscale voltage output terminal OUT_VG through the second transistor T2.

[0098] Figure 6 A circuit structure diagram of a comparator circuit in an embodiment of the present invention is shown in Figure 6 As shown, at least one of the first comparator circuit 2011 and the second comparator circuit 2021 in the embodiment of the present invention can adopt Figure 6 the comparator circuit 3 shown. The comparator circuit 3 includes: a first bias circuit 301, an amplification stage circuit 302, and a second output circuit 303.

[0099] Among them, the first bias circuit 301 is connected to the amplification stage circuit 302 and the second output circuit 303. The first bias circuit 301 is configured to provide a bias voltage to the amplification stage circuit 302 and the second output circuit 303. The amplification stage circuit 302 is configured with two input terminals IN_N and IN_P and serves as the positive-phase input terminal and the negative-phase input terminal of the comparator circuit 3 respectively. The output terminal of the amplification stage circuit 302 is connected to the second output circuit 303. The amplification stage circuit 302 is configured to amplify the difference between the voltage input at the positive-phase input terminal and the voltage input at the negative-phase input terminal and output it. The second output circuit 303 is configured to receive the voltage output by the amplification stage circuit 302 and perform secondary amplification to output a corresponding high-level signal or low-level signal through the output terminal OUT1.

[0100] See Figure 6 As shown, further optionally, the first bias circuit 301 includes 7 transistors (transistors M1 to M7) and 1 resistor. By changing the resistor R, the bias current flowing through the transistor M12 in the amplification stage circuit 302 and the transistor M14 in the second output circuit 303 can be adjusted. The amplification stage circuit 302 includes 5 transistors (transistors M8 to M12), and the transistors M8 to M12 form a basic differential amplifier. The second output circuit 303 includes 2 transistors (transistors M13 and M14), and the transistors M13 and M14 form a common-source amplifier for generating and outputting a high-level signal or a low-level signal.

[0101] Figure 7This is a schematic diagram of a circuit structure of the interpolation circuit 1 in an embodiment of the present invention. As Figure 7 shown, in some embodiments, the interpolation circuit 1 is a linear interpolation circuit, and the linear interpolation circuit can perform linear interpolation processing based on two reference voltages.

[0102] In some embodiments, the linear interpolation circuit 1 specifically includes: a programmable current circuit 101, a voltage-current conversion circuit 102, and a third output circuit 103. The output end of the programmable current circuit 101, the output end of the voltage-current conversion circuit 102, and the input end of the third output circuit 103 are connected to each other.

[0103] Among them, the programmable current circuit 101 is connected to the first reference voltage input terminal IN1, the second reference voltage input terminal IN2, and the control signal input terminal CG. The programmable current circuit 101 is configured to use the first reference voltage and the second reference voltage as input working voltages and output corresponding currents in response to the control of the interpolation control signal.

[0104] The non-inverting input terminal of the voltage-current conversion circuit 102 is connected to the output end of the third output circuit 103, the inverting input terminal of the voltage-current conversion circuit 102 is connected to the first reference voltage input terminal IN1, and the output end of the voltage-current conversion circuit 102 is connected to the input end of the third output circuit 103. The voltage-current conversion circuit 102 is configured to convert the voltage difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal into a corresponding current.

[0105] The output end of the third output circuit 103 is connected to the grayscale voltage output terminal OUT_VG. The third output circuit 103 is configured to receive, through the input end, the current formed by superimposing the current output by the programmable current circuit 101 and the current output by the voltage-current conversion circuit 102, and output a corresponding target grayscale voltage according to the received current.

[0106] Figure 8 This is another schematic diagram of a circuit structure of the interpolation circuit in an embodiment of the present invention. As Figure 8 shown, in some embodiments, the programmable current circuit 101 includes: a programmable control circuit 1011 and a current output circuit 1012; among them, the programmable control circuit 1011 is connected to the control signal input terminal CG and the bias current output circuit 1012; the current output circuit 1011 is configured with a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal is connected to the second reference voltage input terminal IN2, and the inverting input terminal is connected to the first reference voltage input terminal IN1. By the interpolation control signal provided by the control signal input terminal CG, the magnitude of the current output by the current output circuit can be changed. Taking a 3-bit interpolation control signal as an example, when the value of the interpolation control signal gradually increases from "000" to "111", the current output by the current output circuit also increases from the minimum to the maximum.

[0107] In some embodiments, the voltage - current conversion circuit 102 includes a differential amplifier. Its non - inverting input terminal is connected to the output terminal OUT2 of the third output circuit 103, its inverting input terminal is connected to the first reference voltage input terminal IN1, and its output terminal is connected to the input terminal of the third output circuit 103. The voltage - current conversion circuit 102 can convert the differentially - input voltage into a current and superimpose it on the current output by the programmable current circuit 101.

[0108] In some embodiments, the third output circuit 103 includes a common - source amplifier circuit, specifically including transistor M14 and transistor M15. The control electrode of transistor M14 serves as the input terminal of the third output circuit 103, and the control electrode of transistor M15 is used to receive the bias voltage Vb. The third output circuit 103 is used to amplify the received input signal and then output it. In addition, a capacitor CM can be provided between the control electrode and the drain electrode of the transistor. The capacitor CM can improve the phase margin of the interpolation circuit 1 and enhance the stability of the circuit operation.

[0109] In some embodiments, the linear interpolation circuit further includes: a frequency compensation circuit 104; the frequency compensation circuit 104 is connected to the input terminal and the output terminal of the third output circuit 103, and the frequency compensation circuit 104 is configured to perform frequency compensation on the third output circuit 103.

[0110] In the embodiments of the present invention, by setting the frequency compensation circuit 104, on the one hand, the high - frequency characteristics of the third output circuit 103 can be improved, and on the other hand, the phenomenon of self - excitation oscillation that may occur due to the introduction of negative feedback can be overcome, enabling the third output circuit 103 to operate stably. Among them, the frequency compensation method can be divided into lead compensation and lag compensation, mainly by connecting some resistive - capacitive elements to change the phase - frequency characteristics of the open - loop gain of the third output circuit 103 in the high - frequency band, for example, using a phase - locked loop for frequency compensation.

[0111] In some embodiments, the linear interpolation circuit further includes: a second bias circuit 105; the second bias circuit 105 is connected to the programmable current circuit 101, the voltage - current conversion circuit 102, and the third output circuit 103, and the second bias circuit 105 is configured to provide bias voltages to the programmable current circuit 101, the voltage - current conversion circuit 102, and the third output circuit 103.

[0112] Of course, the interpolation circuit 1 in the embodiments of the present invention can also adopt a non - linear interpolation circuit, which will not be described one by one here.

[0113] The performance parameters of the source driver circuit provided by the embodiments of the present invention are analyzed below. To simplify the analysis, the load at the grayscale voltage output terminal OUT_VG of the source driver circuit is equivalent to a load in which a resistor RL and a capacitor CL are connected in series. During one working cycle, the output of the source driver circuit can be regarded as a direct current, and the voltage across the load capacitor is the output voltage. According to the expression of the voltage-current relationship across the capacitor, the slew rate SR of the source driver circuit can be obtained:

[0114]

[0115] where SR is the slew rate, Vout is the output voltage, t represents time, and I 总 is the total charging or discharging current provided by the source driver circuit to the load.

[0116] When the voltage at the grayscale voltage output terminal OUT_VG is less than the first reference voltage, the total charging current at the grayscale voltage output terminal OUT_VG is I in =(I SD14 -I DS15 )+I SD1 ; where. I in is the total charging current, I SD14 is the current flowing from the source to the drain of the transistor M14 in the interpolation circuit 1 shown in Figure 8 , I DS15 is the current flowing from the drain to the source of the transistor M15 in the interpolation circuit 1 shown in Figure 8 , I SD14 -I DS15 is the charging current provided by the interpolation circuit 1 shown in Figure 8 , and I SD1 is the current flowing from the source to the drain of the first transistor T1, that is, the charging current provided by the auxiliary circuit 2.

[0117] When the voltage at the grayscale voltage output terminal OUT_VG is greater than the second reference voltage, the total discharging current at the grayscale voltage output terminal OUT_VG is I out =I DS15 +I SD2 ; where. I out is the total discharging current, I DS15 is the discharging current provided by the transistor M15 in the interpolation circuit 1 shown in Figure 8 , and I SD2 is the current flowing from the drain to the source of the second transistor T2, that is, the discharging current provided by the auxiliary circuit 2.

[0118] The slew rate of a circuit determines the response speed of the circuit. The larger the slew rate, the faster the response speed. As can be seen from the above analysis, when the load capacitance is constant, the larger the total driving current, the larger the slew rate. Due to the existence of the auxiliary circuit 2, an additional charging / discharging current is introduced into the total driving current based on the current output by the interpolation circuit 1, so that the charging / discharging speed of the gray-scale voltage output terminal OUT_VG for the load capacitance is faster and the response time is shorter.

[0119] See Figure 4 and Figure 5 As shown, in the embodiment of the present invention, the inverting input terminal in the interpolation circuit 1 can also be connected to the gray-scale voltage output terminal OUT_VG, so as to form a negative feedback between the interpolation circuit 1 and the gray-scale voltage output terminal OUT_VG.

[0120] The embodiment of the present invention provides a source driver circuit, which can improve the charging / discharging speed of the gray-scale voltage output terminal, so that the voltage at the gray-scale voltage output terminal quickly reaches the target gray-scale voltage; in addition, the auxiliary circuit is controlled to work according to the voltage at the gray-scale voltage output terminal OUT_VG and forms a negative feedback with the gray-scale voltage output terminal OUT_VG, and this negative feedback can enhance the stability of the output at the gray-scale voltage output terminal. Therefore, the source driver circuit provided by the embodiment of the present invention can achieve stable output while having a relatively fast charging / discharging speed.

[0121] Based on the same inventive concept, the embodiment of the present invention further provides a display device, which includes: a display area and a non-display area located outside the display area, and the source driver circuit provided in the above embodiment is arranged in the non-display area. For the specific description of this source driver circuit, reference can be made to the content in the previous embodiment, and details are not described here again.

[0122] The display device provided by the present invention can specifically be: any product or component with a display function such as an electronic paper, an LED panel, an OLED panel, a liquid crystal display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0123] The embodiment of the present invention further provides a data driving method, which is based on the source driver circuit provided in the previous embodiment. The data driving method includes: the interpolation circuit performs interpolation processing between a first reference voltage and a second reference voltage in response to the control of an interpolation control signal provided by a control signal input terminal, and writes the target gray-scale voltage obtained by the interpolation processing to the gray-scale voltage output terminal, wherein when the voltage at the gray-scale voltage output terminal is less than the first reference voltage, the auxiliary circuit charges the gray-scale voltage output terminal, and when the voltage at the gray-scale voltage output terminal is greater than the second reference voltage, the auxiliary circuit discharges the gray-scale voltage output terminal.

[0124] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A source driver circuit, wherein, Including: An interpolation circuit, connected to a first reference voltage input terminal, a second reference voltage input terminal, a grayscale voltage output terminal, and a control signal input terminal, configured to perform interpolation processing between the first reference voltage provided by the first reference voltage input terminal and the second reference voltage provided by the second reference voltage input terminal in response to the control of the interpolation control signal provided by the control signal input terminal, and write the target grayscale voltage obtained by the interpolation processing to the grayscale voltage output terminal, where the first reference voltage is less than the second reference voltage; An auxiliary circuit, connected to the first reference voltage input terminal, the second reference voltage input terminal, and the grayscale voltage output terminal, configured to charge the grayscale voltage output terminal when the voltage at the grayscale voltage output terminal is less than the first reference voltage, and discharge the grayscale voltage output terminal when the voltage at the grayscale voltage output terminal is greater than the second reference voltage; The auxiliary circuit includes: a first feedback circuit, a second feedback circuit, and a first output circuit; The first feedback circuit is configured with a first input terminal, a second input terminal, and a first output terminal. The first input terminal is connected to the first reference voltage input terminal, the second input terminal is connected to the grayscale voltage output terminal, and the first output terminal is connected to the first output circuit. The first feedback circuit is configured to output a first control signal in an active level state to the first output circuit when the voltage at the grayscale voltage output terminal is less than the first reference voltage; The second feedback circuit is configured with a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is connected to the second reference voltage input terminal, the fourth input terminal is connected to the grayscale voltage output terminal, and the second output terminal is connected to the first output circuit. The second feedback circuit is configured to output a second control signal in an active level state to the first output circuit when the voltage at the grayscale voltage output terminal is greater than the second reference voltage; The first output circuit is connected to the grayscale voltage output terminal. The grayscale voltage output terminal is configured to charge the grayscale voltage output terminal in response to the control of the first control signal in an active level state, and discharge the grayscale voltage output terminal in response to the control of the second control signal in an active level state.

2. The source driver circuit according to claim 1, wherein The first feedback circuit includes: a first comparator circuit; The first input terminal is the inverting input terminal of the first comparator circuit, the second input terminal is the non-inverting input terminal of the first comparator circuit, and the first output terminal is the output terminal of the first comparator circuit.

3. The source driver circuit according to claim 1, wherein The first feedback circuit includes: a first comparator circuit and a first inverter circuit. The output terminal of the first comparator circuit is connected to the input terminal of the first inverter circuit; The first input terminal is the non-inverting input terminal of the first comparator circuit, the second input terminal is the inverting input terminal of the first comparator circuit, and the first output terminal is the output terminal of the first comparator circuit.

4. The source driver circuit according to any one of claims 1 to 3, wherein, The second feedback circuit includes: a second comparator circuit; The third input terminal is the inverting input terminal of the second comparator circuit, the fourth input terminal is the non-inverting input terminal of the second comparator circuit, and the second output terminal is the output terminal of the second comparator circuit.

5. The source driver circuit according to any one of claims 1 to 3, wherein, The second feedback circuit includes: a second comparator circuit and a second inverter circuit, and the output terminal of the second comparator circuit is connected to the input terminal of the second inverter circuit; The third input terminal is the non-inverting input terminal of the second comparator circuit, the fourth input terminal is the inverting input terminal of the second comparator circuit, and the second output terminal is the output terminal of the second comparator circuit.

6. The source driver circuit according to claim 1, wherein, At least one of the comparator circuit in the first feedback circuit and the comparator circuit in the second feedback circuit includes: a first bias circuit, an amplification stage circuit, and a second output circuit; The first bias circuit is connected to the amplification stage circuit and the second output circuit, and the first bias circuit is configured to provide a bias voltage to the amplification stage circuit and the second output circuit; The amplification stage circuit is configured with two input terminals and serves as the non-inverting input terminal and the inverting input terminal of the comparator circuit respectively. The output terminal of the amplification stage circuit is connected to the second output circuit, and the amplification stage circuit is configured to amplify the difference between the voltage input at the non-inverting input terminal and the voltage input at the inverting input terminal and output it; The second output circuit is configured to receive the voltage output by the amplification stage circuit and perform secondary amplification to output a corresponding high-level signal or low-level signal.

7. The source driver circuit according to claim 1, wherein, The first output circuit includes: a charging circuit and a discharging circuit The charging circuit is connected to the first output terminal, the grayscale voltage output terminal, and the first power supply terminal. The charging circuit is configured to charge the grayscale voltage output terminal through the first power supply terminal in response to the control of the first control signal in an active level state; The discharging circuit is connected to the second output terminal, the grayscale voltage output terminal, and the second power supply terminal. The discharging circuit is configured to discharge the grayscale voltage output terminal through the second power supply terminal in response to the control of the second control signal in an active level state.

8. The source driver circuit according to claim 7, wherein The charging circuit includes: a first transistor; The control electrode of the first transistor is connected to the first output terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the grayscale voltage output terminal.

9. The source driver circuit according to claim 8, wherein, The first control signal in an active level state is a low-level signal, and the first transistor is a P-type transistor.

10. The source driver circuit according to any one of claims 7 to 9, wherein, The discharging circuit includes: a second transistor; The control electrode of the second transistor is connected to the second output terminal, the first electrode of the second transistor is connected to the grayscale voltage output terminal, and the second electrode of the second transistor is connected to the second power supply terminal.

11. The source driver circuit according to claim 10, wherein, The second control signal in an active level state is a high-level signal, and the second transistor is an N-type transistor.

12. The source driver circuit according to claim 1, wherein, The interpolation circuit is a linear interpolation circuit.

13. The source driver circuit according to claim 12, wherein, The linear interpolation circuit includes: a programmable current circuit, a voltage-current conversion circuit, and a third output circuit. The output terminal of the programmable current circuit, the output terminal of the voltage-current conversion circuit, and the input terminal of the third output circuit are connected to each other. The programmable current circuit is connected to the first reference voltage input terminal, the second reference voltage input terminal, and the control signal input terminal. The programmable current circuit is configured to use the first reference voltage and the second reference voltage as input operating voltages and output corresponding currents in response to the control of the interpolation control signal. The non-inverting input terminal of the voltage-current conversion circuit is connected to the output terminal of the third output circuit. The inverting input terminal of the voltage-current conversion circuit is connected to the first reference voltage input terminal. The output terminal of the voltage-current conversion circuit is connected to the input terminal of the third output circuit. The voltage-current conversion circuit is configured to convert the voltage difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal into a corresponding current. The output terminal of the third output circuit is connected to the grayscale voltage output terminal. The third output circuit is configured to receive, through the input terminal, the current formed by superimposing the current output by the programmable current circuit and the current output by the voltage-current conversion circuit, and output the corresponding target grayscale voltage according to the received current.

14. The source driver circuit according to claim 13, wherein, The linear interpolation circuit further includes: a frequency compensation circuit. The frequency compensation circuit is connected to the input terminal and the output terminal of the third output circuit. The frequency compensation circuit is configured to perform frequency compensation on the third output circuit.

15. The source driver circuit according to claim 13 or 14, wherein, The linear interpolation circuit further includes: a second bias circuit. The second bias circuit is connected to the programmable current circuit, the voltage-current conversion circuit, and the third output circuit. The second bias circuit is configured to provide bias voltages to the programmable current circuit, the voltage-current conversion circuit, and the third output circuit.

16. A display device, wherein, It includes: a display area and a non-display area located outside the display area. The source driver circuit as described in any one of claims 1-15 is provided in the non-display area.

17. A data-driven method, wherein, Based on the source driver circuit as described in any one of claims 1-15, the data driving method includes: The interpolation circuit performs interpolation processing between the first reference voltage and the second reference voltage in response to the control of the interpolation control signal provided by the control signal input terminal, and writes the target grayscale voltage obtained by the interpolation processing to the grayscale voltage output terminal. Among them, when the voltage at the grayscale voltage output terminal is less than the first reference voltage, the auxiliary circuit charges the grayscale voltage output terminal, and when the voltage at the grayscale voltage output terminal is greater than the second reference voltage, the auxiliary circuit discharges the grayscale voltage output terminal.

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