Shift register, driving method thereof, gate driving circuit, and display device

Abstract

The present disclosure provides a shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an input sub-circuit, an output sub-circuit, and a node reset sub-circuit. The input sub-circuit is connected to an input terminal, a first clock signal terminal, and a pull-up node, and is configured to write an input signal to the pull-up node to control the level of the pull-up node when both the first clock signal and the input signal are at valid levels. The output sub-circuit is connected to the pull-up node, a second clock signal terminal, and an output terminal, and is configured to output the second clock signal to the output terminal under the control of the level of the pull-up node. The node reset sub-circuit is connected to the pull-up node and a first reset terminal, and is configured to reset the pull-up node in response to a reset signal received at the first reset terminal. Wherein, the first clock signal and the second clock signal have the same period, and the arrival time of the valid level of the first clock signal is earlier than the arrival time of the valid level of the second clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] One of the current trends in the development of electronic products is high refresh rates. Especially for gaming and competitive products, the design challenges for display products are also getting higher and higher. Among them, the voltage withstand of the GOA (Gate Driver On Array) circuit has been greatly tested. Especially when there are many clock signal lines, the reset transistors in the GOA circuit are prone to being broken down and burned due to long-term operation under a large voltage difference, resulting in the GOA circuit being unable to work properly, and thus causing defects such as horizontal stripes in the display screen, affecting the user experience. Therefore, it is particularly important to improve the voltage withstand characteristics of the GOA circuit. Summary of the Invention

[0003] Embodiments of the present disclosure provide a shift register, a driving method thereof, a gate driving circuit, and a display device.

[0004] In a first aspect, embodiments of the present disclosure provide a shift register, including:

[0005] An input sub-circuit, connected to an input terminal, a first clock signal terminal, and a pull-up node, configured to write the input signal to the pull-up node to control the level of the pull-up node when both the first clock signal and the input signal are at valid levels;

[0006] An output sub-circuit, connected to the pull-up node, a second clock signal terminal, and an output terminal, configured to output the second clock signal to the output terminal under the control of the level of the pull-up node;

[0007] A node reset sub-circuit, connected to the pull-up node and a first reset terminal, configured to reset the pull-up node in response to a reset signal received by the first reset terminal;

[0008] Wherein, the first clock signal and the second clock signal have the same period, and the arrival time of the valid level of the first clock signal is earlier than the arrival time of the valid level of the second clock signal.

[0009] Further, the input sub-circuit includes a first transistor and a second transistor,

[0010] A first pole of the first transistor is connected to the input terminal, and a second pole is connected to the pull-up node,

[0011] The gate of the second transistor is connected to the first clock signal terminal, the first pole is connected to the input terminal, and the second pole is connected to the gate of the first transistor.

[0012] Further, the node reset sub - circuit includes: a third transistor and a fourth transistor,

[0013] The gates of the third transistor and the fourth transistor are both connected to the first reset terminal;

[0014] The first pole of the third transistor is connected to the pull - up node, the second pole is respectively connected to the output terminal and the first pole of the fourth transistor, and the second pole of the fourth transistor is connected to the first voltage terminal.

[0015] Further, the output sub - circuit includes: a first output sub - circuit and a second output sub - circuit,

[0016] The first output sub - circuit is respectively connected to the pull - up node, the second clock signal terminal and the cascade signal output terminal, and is used for writing the second clock signal into the cascade signal output terminal under the control of the pull - up node;

[0017] The second output sub - circuit is respectively connected to the pull - up node, the second clock signal terminal and the scan signal output terminal, and is used for writing the second clock signal into the scan signal output terminal under the control of the pull - up node;

[0018] The second pole of the third transistor is connected to the cascade signal output terminal.

[0019] Further, the period when the first clock signal is at the effective level at least partially overlaps with the period when the input signal is at the effective level, and the first clock signal and the second clock signal alternately are at the effective level.

[0020] Further, the above - mentioned shift register further includes: a node noise reduction sub - circuit, which is connected to the pull - up node, the first noise reduction node and the second noise reduction node, and is used for reducing the noise of the pull - up node under the control of the level of the first noise reduction node or the level of the second noise reduction node.

[0021] Further, the above - mentioned shift register further includes: an output noise reduction sub - circuit, which is respectively connected to the first noise reduction node, the second noise reduction node and the output terminal, and is used for reducing the noise of the output terminal under the control of the level of the first noise reduction node or the level of the second noise reduction node.

[0022] Further, the above - mentioned shift register further includes: a first control sub - circuit and a second control sub - circuit,

[0023] The first control sub - circuit is respectively connected to the pull - up node and the first noise - reduction node, and is used to control the level of the first noise - reduction node under the control of the level of the pull - up node;

[0024] The second control sub - circuit is respectively connected to the pull - up node and the second noise - reduction node, and is used to control the level of the second noise - reduction node under the control of the level of the pull - up node.

[0025] Further, the above - mentioned shift register further includes: an output reset sub - circuit and a frame reset sub - circuit,

[0026] The output reset sub - circuit is respectively connected to the first reset terminal and the output terminal, and is used to reset the output terminal under the control of the reset signal received by the first reset terminal;

[0027] The frame reset sub - circuit is connected to the second reset terminal and the pull - up node, and is used to reset the pull - up node under the control of the frame reset signal received by the second reset terminal.

[0028] In a second aspect, an embodiment of the present disclosure provides a driving method for a shift register, and the method includes:

[0029] When the first clock signal and the input signal are both at valid levels, write the input signal to the pull - up node to control the level of the pull - up node;

[0030] Under the control of the level of the pull - up node, output the second clock signal to the output terminal, where the first clock signal and the second clock signal have the same period, and the arrival time of the valid level of the first clock signal is earlier than the arrival time of the valid level of the second clock signal;

[0031] Reset the pull - up node based on the reset signal.

[0032] In a third aspect, an embodiment of the present disclosure provides a gate driving circuit, including N - stage cascaded shift registers, where the shift register is the shift register provided in the first aspect above, and N is an integer greater than 2;

[0033] The input terminal of the first - stage shift register is connected to the frame input signal line;

[0034] The input terminal of the i - th stage shift register is connected to the output terminal of the (i - 1) - th stage shift register, and the output terminal of the i - th stage shift register is connected to the first reset terminal of the (i - 1) - th stage shift register, where 1 < i ≤ N;

[0035] The first reset terminal of the N - th stage shift register is connected to the frame reset signal line.

[0036] In a fourth aspect, an embodiment of the present disclosure provides a display device, including: the gate driving circuit provided in the third aspect above.

[0037] Further, the display device further includes: 2M clock signal lines and at least one frame input signal line for receiving a frame start signal, where M is an integer greater than or equal to 2;

[0038] Each stage of shift register in the gate driving circuit is respectively connected to a corresponding one of the 2M clock signal lines;

[0039] The input ends of the shift registers at the first stage in the gate driving circuit are connected to the same frame input signal line.

[0040] The technical solution provided in the embodiment of the present disclosure has at least the following technical effects or advantages:

[0041] The shift register provided in the embodiment of the present disclosure jointly controls the level of the pull-up node through the first clock signal and the input signal, and configures the first clock signal so that the arrival time of its effective level is earlier than the arrival time of the effective level of the second clock signal, so as to realize the time of the first level change (such as pull-up) of the pull-up node, which is beneficial to reducing the duration of the effective level of the pull-up node, thereby reducing the high-voltage difference working time of the reset transistor and improving the withstand voltage of the gate driving circuit.

[0042] The above description is only an overview of the technical solution of the embodiment of the present disclosure. In order to be able to understand the technical means of the embodiment of the present disclosure more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the embodiment of the present disclosure more obvious and understandable, the following specifically illustrates the specific implementation manners of the embodiment of the present disclosure. Description of the Drawings

[0043] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the embodiments of the present disclosure. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0044] Figure 1 It is a schematic structural diagram of an exemplary gate driving circuit;

[0045] Figure 2 It is a partial circuit diagram of an exemplary shift register;

[0046] Figure 3 For Figure 1An exemplary timing diagram of STV and CLK1 - CLK10;

[0047] Figure 4 For Figure 1 An exemplary timing diagram of STV and G1_PU - G10_PU;

[0048] Figure 5 The structural block diagram of the first exemplary shift register in the embodiments of the present disclosure;

[0049] Figure 6 An exemplary timing diagram of STV, CLK1 - CLK10 and G1_PU - G5_PU in the embodiments of the present disclosure;

[0050] Figure 7 The structural block diagram of the second exemplary shift register in the embodiments of the present disclosure;

[0051] Figure 8 The circuit structure diagram of an exemplary shift register in the embodiments of the present disclosure;

[0052] Figure 9 For Figure 2 And Figure 8 The source - drain waveform diagram of the reset transistor in;

[0053] Figure 10 For Figure 8 The timing diagram of the shift register shown;

[0054] Figure 11 The flowchart of a driving method of a shift register in the embodiments of the present disclosure. Detailed implementation manners

[0055] Generally speaking, the gate driving circuit in a display panel includes cascaded multi - stage shift registers. In display products with a large number of CLKs (high refresh frequency), there are usually multiple shift registers at the first stage. Considering circuit cost and border, the input ends of the shift registers at the first stage are connected to the same frame input signal line to receive the frame start signal STV input by this frame input signal line.

[0056] For example, taking Figure 1 The gate driving circuit with 10 CLKs (i.e., 10 clock signal lines are arranged) shown as an example, the 10 clock signal lines are respectively represented as CLK1 - CLK10. It should be noted that Figure 1 G1 - G5 at the first stage and G6 - G10 at the second stage are taken as examples, and the shift registers at other stages are not shown. Among them, G6 is cascaded at the next stage of G1, G7 is cascaded at the next stage of G2, G8 is cascaded at the next stage of G3, G9 is cascaded at the next stage of G4, and G10 is cascaded at the next stage of G1.

[0057] As shown Figure 1 in the figure, G1 can be connected to CLK1 and CLK6. The clock signal line CLK6 provides the first clock signal CLKB for it, and the clock signal line CLK1 provides the second clock signal CLK for it; G2 can be connected to CLK2 and CLK7. The clock signal line CLK7 provides the first clock signal CLKB for it, and the clock signal line CLK2 provides the second clock signal CLK for it; G3 can be connected to CLK3 and CLK8. The clock signal line CLK8 provides the first clock signal CLKB for it, and the clock signal line CLK3 provides the second clock signal CLK for it; G4 can be connected to CLK4 and CLK9. The clock signal line CLK9 provides the first clock signal CLKB for it, and the clock signal line CLK4 provides the second clock signal CLK for it; G5 can be connected to CLK5 and CLK10. The clock signal line CLK10 provides the first clock signal CLKB for it, and the clock signal line CLK5 provides the second clock signal CLK for it.

[0058] The inputs INPUT of G1 - G5 at the first stage are connected to the same frame input signal line, and the same frame start signal STV is input.

[0059] As shown Figure 2 in the figure, in some exemplary implementation manners, the shift register includes an input transistor T1 and a reset transistor T2. The first pole and the gate of the input transistor T1 are both connected to the input terminal INPUT, and the second pole is connected to the pull - up node PU to control the output waveform number of the output terminal by controlling the potential of the pull - up node PU. The gate of the reset transistor T2 is connected to the first reset terminal RST1, the first pole is connected to the pull - up node PU, and the second pole is connected to the first voltage terminal LVGL, and is configured to control the reset of the pull - up node PU. The source - drain voltage difference Vds of the reset transistor is usually 0V. Taking the input transistor T1 being turned on at high level as an example, in the input stage, when the signal input at the input terminal INPUT is at high level, the input transistor T1 is turned on, and the potential of the pull - up node PU is pulled up. Then, when the input signal is at low level, the input transistor T1 is turned off, and due to the bootstrap effect, the potential of the pull - up node PU is further pulled up. The source - drain voltage difference Vds of the reset transistor T2 also continuously increases as the potential of the pull - up node PU is pulled up. That is to say, in the stage where the potential of the pull - up node PU is pulled up twice continuously, the reset transistor T2 will continuously work in a high - voltage - difference state.

[0060] Applying the Figure 2 shift register shown Figure 1When showing the gate driving circuit, since the potential of the pull-up node PU in each shift register is only controlled by the input signal, for G1-G5, the input signal is the same frame start signal STV. When the frame start signal STV is at a high level, the potential of the pull-up node PU in G1-G5 will be pulled up simultaneously, and the holding time of the first pulled-up level increases sequentially.

[0061] Figure 3 An exemplary timing diagram of the frame start signal STV and CLK1-CLK10 is shown. Figure 4 Shown in Figure 3 Under the timing control in, the timing diagram of the pull-up nodes of G1-G10 is shown. G1_PU, G2_PU, G3_PU, G4_PU, G5_PU, G6_PU, G7_PU, G8_PU, G9_PU and G10_PU represent the waveforms of the pull-up nodes of G1-G10 in sequence. It can be seen from Figure 4 that the holding time of the first pulled-up level of the pull-up nodes of G1 to G5 increases sequentially. Compared with G1, G2 increases by ΔT2, G3 increases by ΔT3 compared with G1, G4 increases by ΔT4 compared with G1, and G5 increases by ΔT5 compared with G1, and ΔT2 < ΔT3 < ΔT4 < ΔT5. In this way, the too long high-voltage duration of the pull-up node in G2-G5, especially G5, will easily cause the reset transistor to burn out, which is not conducive to improving the breakdown voltage of the gate driving circuit.

[0062] Based on this, the embodiments of the present disclosure provide a shift register that can control the duration of the first pull-up of the pull-up node to improve the breakdown voltage of the gate driving circuit. As Figure 5 shown, the shift register 10 includes: an input sub-circuit 101, an output sub-circuit 102, and a node reset sub-circuit 103.

[0063] The input sub-circuit 101 is connected to the input terminal INPUT, the first clock signal terminal CK1, and the pull-up node PU. The input terminal INPUT is used to receive the input signal, and the first clock signal terminal CK1 is used to receive the first clock signal CLKB. The input sub-circuit 101 is used to write the input signal into the pull-up node PU when both the first clock signal CLKB and the input signal are at valid levels, so as to control the potential PU of the pull-up node. The output sub-circuit 102 is connected to the pull-up node PU, the second clock signal terminal CK2, and the output terminal OUTPUT. The second clock signal terminal CK2 is used to receive the second clock signal CLK. The output sub-circuit 102 is used to output the second clock signal CLK to the output terminal OUTPUT under the control of the potential of the pull-up node PU. The node reset sub-circuit 103 is connected to the pull-up node and the first reset terminal RST1, and is used to reset the pull-up node PU in response to the reset signal received by the first reset terminal RST1, so as to reset the output terminal OUTPUT.

[0064] Among them, the period of the first clock signal CLKB is the same as that of the second clock signal CLK, and the arrival time of the active level of the first clock signal CLKB is earlier than that of the active level of the second clock signal CLK. It should be noted that the above-mentioned active level refers to the working level, which can be a high level, or it can also be a low level, specifically determined according to the specific implementation manners of the input sub-circuit 101 and the output sub-circuit 102, and the embodiments of the present disclosure do not limit this. The active level of the first clock signal CLKB and the active level of the input signal can be the same, or they can also be different. For example, the active levels of the first clock signal CLKB, the second clock signal CLK, and the input signal INPUT can all be high levels.

[0065] In this way, the potential of the pull-up node PU is jointly controlled by the first clock signal CLKB and the input signal, so that the time of the first potential change (such as pulling up to a high level) and the duration of the pull-up node PU can be controlled by configuring the arrival time of the active level of the first clock signal CLKB of each shift register, which is beneficial to reducing the duration of the active level of the pull-up node PU, thereby reducing the high-voltage difference working time of the reset transistor and improving the voltage withstand of the gate driving circuit.

[0066] Still taking 10CLK as an example, Figure 6 An exemplary timing diagram provided by the embodiments of the present disclosure is shown. For G1-G5, assuming that the active levels of the first clock signal CLKB and the input signal are both high levels, the potential of the pull-up node PU will be pulled up when the frame start signal STV as the input signal is at a high level and the first clock signal CLKB is also at a high level. Taking G5 as an example, before the high level of the first clock signal CLKB provided by the clock signal line CLK10 arrives, although the frame start signal STV is already at a high level, the pull-up node PU still remains at a low level until the first clock signal CLKB is at a high level, effectively reducing the high-level duration of the pull-up node in G5. Similarly, the high-level duration of the pull-up node in G2-G4 can also be reduced to varying degrees. For example, by configuring the corresponding first clock signal CLKB, the high-level duration of the pull-up node in G2-G5 can be reduced to be the same as that of G1.

[0067] It should be noted that the time period when the first clock signal CLKB is at the active level and the time period when the input signal is at the active level overlap at least partially, so that when the first clock signal CLKB is at the active level, the active level of the input signal, such as a high level, is written into the pull-up node PU.

[0068] The duration of the active level of the first clock signal CLKB is less than the duration of the active level of the frame start signal STV. For example, taking the active level as the high level, the duration of the high level of the frame start signal STV is 9H, the clock periods of the first clock signal CLKB and the second clock signal CLK can be 10H, the duty cycle is 50%, and the duration of the high level of the first clock signal CLKB is 5H. Here, H represents the time for scanning one line, which is related to the resolution and the refresh rate. For example, when the resolution is 1920*1080 and the refresh rate is 60Hz, 1H = 1 / 60 / 1080 ≈ 15.4 μs.

[0069] In some examples, the first clock signal CLKB and the second clock signal CLK can alternately be in the active level. Taking the active level as the high level, when the first clock signal CLKB is at the high level, the second clock signal CLK is at the low level, and vice versa, when the second clock signal CLK is at the high level, the first clock signal CLKB is at the low level. For example, as Figure 6 shown, on the basis of the first clock signal CLKB illustrated in Figure 3 , the first clock signal CLKB can be turned on one clock cycle earlier, that is, adding one clock cycle in front.

[0070] Specifically, the input sub - circuit 101 responds to the first clock signal CLKB and writes the input signal to the pull - up node PU to control the level of the pull - up node PU. For example, the input sub - circuit 101 can, under the control of the first clock signal CLKB, electrically connect the pull - up node PU to the input terminal INPUT, so that the active level of the input signal can be input to the pull - up node, changing the potential of the pull - up node PU to control the output sub - circuit 102.

[0071] For example, if the active level of the input signal is the high level, the pull - up node PU is charged, causing the potential of the pull - up node PU to rise. Or, in other examples, the active level of the input signal can also be the low level, then the pull - up node PU is discharged, causing the potential of the pull - up node PU to drop to control the output sub - circuit 102. The control of the potential of the pull - up node PU (i.e., rising or dropping) can be determined according to the specific implementation of the output sub - circuit 102, and the embodiments of the present disclosure do not limit this.

[0072] Under the control of the level of the pull-up node, the output sub-circuit 102 outputs the second clock signal to the output terminal OUTPUT. For example, under the control of the level of the pull-up node PU, the output sub-circuit 102 can electrically connect the second clock signal terminal CK2 to the output terminal OUTPUT, so as to output the received second clock signal to the output terminal OUTPUT. The output terminal OUTPUT connected to the output sub-circuit 102 is used to output the gate driving signal and output the cascade signal to the previous stage (except the first-stage shift register) and the next stage (except the last-stage shift register).

[0073] In some examples, the output sub-circuit 102 may include: a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is respectively connected to the pull-up node PU, the second clock signal terminal CK2 and the cascade signal output terminal OUT_C, and is used to write the second clock signal CLK input from the second clock signal terminal CK2 to the cascade signal output terminal OUT_C under the control of the pull-up node PU. The second output sub-circuit is respectively connected to the pull-up node PU, the second clock signal terminal CK2 and the scan signal output terminal OUT_G, and is used to write the second clock signal CLK to the scan signal output terminal OUT_G under the control of the pull-up node PU.

[0074] The scan signal output terminal OUT_G is used to provide a gate driving signal for the corresponding gate line of the pixel circuit (pixel row) to drive the pixel unit connected to the gate line to turn on or off. The cascade signal output terminal OUT_C is used to provide a cascade signal for the first reset terminal RST1 of the previous-stage shift register and the input terminal INPUT of the next-stage shift register. By separating the scan signal output terminal OUT_G and the cascade signal output terminal OUT_C, it is beneficial to reduce the power consumption of the gate driving circuit.

[0075] Under the control of the reset signal received by the first reset terminal RST1, the node reset sub-circuit 103 writes the potential of the first voltage terminal LVGL to the pull-up node PU to reset the pull-up node PU. For example, the effective level of the input signal is high level, the pull-up node PU is pulled high, and the first voltage terminal LVGL is used to provide a first low-level signal to restore the pulled-high pull-up node PU to a low level. It should be noted that for the first to N-1 stage shift registers, the reset signal is provided by the scan signal output terminal OUT_G or the cascade signal output terminal OUT_C of the subsequent stage shift register.

[0076] Figure 7 Shows a structural block diagram of another exemplary shift register 20 provided by an embodiment of the present disclosure. As Figure 7As shown, in addition to the input sub-circuit 101, the output sub-circuit 102, and the node reset sub-circuit 103, the shift register 20 may further include: a node noise reduction sub-circuit 104. The node noise reduction sub-circuit 104 is connected to the pull-up node PU, the first noise reduction node PDA, and the second noise reduction node PDB, and is configured to perform noise reduction on the pull-up node PU under the control of the level of the first noise reduction node PDA or the level of the second noise reduction node PDB.

[0077] For example, the node noise reduction sub-circuit 104 may be connected to the pull-up node PU, the first noise reduction node PD1, the second noise reduction node PD2, and the first voltage terminal LVGL. Under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2, the pull-up node PU and the first voltage terminal LVGL are electrically connected, and the level of the pull-up node PU is reset to the voltage provided by the first voltage terminal LVGL, avoiding the noise caused by the level of the pull-up node PU during non-operation, thereby performing noise reduction (e.g., pulling down) on the pull-up node PU.

[0078] For example, by controlling the levels of the first noise reduction node PD1 and the second noise reduction node PD2, the first noise reduction node PD1 and the second noise reduction node PD2 can be alternately at an effective level (e.g., high level), so that the node noise reduction sub-circuit 104 alternately responds to the levels of the first noise reduction node PD1 and the second noise reduction node PD2 to perform noise reduction on the first node PU.

[0079] In some examples, as Figure 7 shown, the shift register 20 provided by the embodiments of the present disclosure may further include: an output noise reduction sub-circuit 105. The output noise reduction sub-circuit 105 is respectively connected to the first noise reduction node PDA, the second noise reduction node PDB, and the output terminal OUTPUT, and is configured to perform noise reduction on the output terminal OUTPUT under the control of the level of the first noise reduction node PDA or the level of the second noise reduction node PDB. For example, the output noise reduction sub-circuit 105 may be connected to the first voltage terminal LVGL and / or the second voltage terminal VGL, the output terminal OUTPUT, the first noise reduction node PDA, and the second noise reduction node PDB, and is configured to electrically connect the output terminal OUTPUT to the first voltage terminal LVGL and / or the second voltage terminal VGL under the control of the level of the first noise reduction node PDA or the level of the second noise reduction node PDB, for example, such that the voltage of the output terminal OUTPUT is equal to the voltage of the first voltage terminal LVGL and / or the second voltage terminal VGL, thereby performing noise reduction (e.g., pulling down) on the output terminal OUTPUT.

[0080] It should be noted that in some examples, when the output terminal OUTPUT includes a scan signal output terminal OUT_G and a cascade signal output terminal OUT_C, under the control of the level of the first noise reduction node PDA or the level of the second noise reduction node PDB, the output noise reduction sub-circuit 105 can electrically connect the cascade signal output terminal OUT_C to the first voltage terminal LVGL, write the first low-level signal of the first voltage terminal LVGL to the cascade signal output terminal OUT_C, and perform noise reduction on the cascade signal output terminal OUT_C; and, electrically connect the scan signal output terminal OUT_G to the second voltage terminal VGL, write the second low-level signal of the second voltage terminal VGL to the scan signal output terminal OUT_G, and perform noise reduction on the scan signal output terminal OUT_G.

[0081] In some examples, such as Figure 7 shown, the shift register 20 provided by the embodiment of the present disclosure may further include: a first control sub-circuit 106 and a second control sub-circuit 107. The first control sub-circuit 106 is respectively connected to the pull-up node PU and the first noise reduction node PDA, and is used to control the level of the first noise reduction node PDA under the control of the level of the pull-up node PU. The second control sub-circuit 107 is respectively connected to the pull-up node PU and the second noise reduction node PDB, and controls the level of the second noise reduction node PDB under the control of the level of the pull-up node PU.

[0082] In some examples, the first control sub-circuit 106 and the second control sub-circuit 107 may also be connected to the input terminal. At this time, the first control sub-circuit 106 controls the level of the first noise reduction node PD1 under the control of the input signal and the level of the pull-up node PU. The second control sub-circuit 107 also controls the level of the second noise reduction node PD1 under the control of the input signal and the level of the pull-up node PU.

[0083] The first control sub-circuit 106 and the second control sub-circuit 107 are set to alternately control the above-mentioned noise reduction sub-circuits, including the node noise reduction sub-circuit 104 and the output noise reduction sub-circuit 105. For example. The two groups of control sub-circuits respectively receive alternating DC high-level signals and DC low-level signals, and the DC signals received by the two groups of control sub-circuits are inverse-phase signals. For example, in one cycle, the first control sub-circuit 106 receives a DC high-level signal, the second control sub-circuit 107 receives a DC low-level signal, and each noise reduction sub-circuit in the shift register operates under the control of the first control sub-circuit 106; in the next cycle, the first control sub-circuit 106 receives a DC low-level signal, the second control sub-circuit 107 receives a DC high-level signal, and each noise reduction sub-circuit in the shift register operates under the control of the second control sub-circuit 107. This helps to avoid performance drift of the transistors in the shift register due to long-term conduction.

[0084] In some examples, such as Figure 7 shown, the shift register 20 provided by the embodiments of the present disclosure may further include: an output reset sub-circuit 108. The output reset sub-circuit 108 is respectively connected to the first reset terminal RST1 and the output terminal OUTPUT, and is configured to reset the output terminal OUTPUT under the control of a reset signal received by the first reset terminal RST1, so that the signal output by the output terminal OUTPUT quickly recovers from an effective level, such as a high level, to an invalid level, such as a low level.

[0085] For example, when the output terminal OUTPUT includes a scan signal output terminal OUT_G and a cascade signal output terminal OUT_C, the output reset sub-circuit 108 may specifically be connected to the scan signal output terminal OUT_G.

[0086] In some examples, such as Figure 7 shown, the shift register 20 provided by the embodiments of the present disclosure may further include: a frame reset sub-circuit 109. The frame reset sub-circuit 109 is connected to the second reset terminal RST2 and the pull-up node PU, and is configured to reset the pull-up node under the control of a frame reset signal received by the second reset terminal RST2. For example, the frame reset sub-circuit 109 may be connected to the second reset terminal RST2, the pull-up node PU, and the first voltage terminal LVGL. Under the control of a frame reset signal received by the second reset terminal RST2, the pull-up node PU is electrically connected to the first voltage terminal LVGL, and a first low-level signal of the first voltage terminal LVGL is written into the pull-up node PU, thereby resetting (for example, pulling down) the pull-up node PU. Wherein, the frame reset signal is a reset signal generated after scanning a frame, and is used to reset the pull-up nodes of each stage of the shift register after scanning a frame.

[0087] Figure 8 For Figure 7 is a circuit diagram of a specific implementation example of the shift register 20 shown in. It should be noted that in the following description, N-type transistors are taken as examples for each transistor, but this does not limit the embodiments of the present disclosure. In other examples, one or more transistors in the shift register may also be P-type transistors.

[0088] Such as Figure 8 shown, the input sub-circuit 101 may include a first transistor M1 and a second transistor M2. A first pole of the first transistor M1 is connected to the input terminal, a second pole is connected to the pull-up node PU, a gate of the second transistor M2 is connected to the first clock signal terminal CK1, a first pole is connected to the input terminal, and a second pole is connected to a gate of the first transistor M1.

[0089] For example, when the first clock signal CLKB is at a high level, the first transistor M1 is turned on, and the input signal is input to the gate of the second transistor M2. When the input signal is at a high level, the second transistor M2 is turned on, and the input signal charges the pull-up node PU, pulling it up to a high level.

[0090] In some examples, the node reset sub-circuit 103 may include: a third transistor M3 and a fourth transistor M4. The gates of the third transistor M3 and the fourth transistor M4 are both connected to the first reset terminal RST1. The first pole of the third transistor M3 is connected to the pull-up node PU, the second pole is respectively connected to the output terminal OUTPUT and the first pole of the fourth transistor M4, and the second pole of the fourth transistor M4 is connected to the first voltage terminal LVGL.

[0091] In some examples, the output terminal OUTPUT of the output sub-circuit 102 includes: a scan signal output terminal OUT_G and a cascade signal output terminal OUT_C. At this time, the second pole of the third transistor M3 may be connected to the cascade signal output terminal OUT_C among them.

[0092] For the sake of convenience of description, the connection node of the second pole of the third transistor M3, the first pole of the fourth transistor M4, and the output terminal OUTPUT is defined as the A node. When the pull-up node PU is pulled up by the input signal, since the cascade signal output terminal OUT_C is at a low level, the voltage of the A node remains low with the cascade signal output terminal OUT_C. When the pull-up node PU is further pulled up due to the bootstrap effect of the output sub-circuit 102, the cascade signal output terminal OUT_C outputs a high level, and the voltage of the A node is pulled up to a high level with the cascade signal output terminal OUT_C again.

[0093] For example, Figure 9 the (a) diagram in Figure 2 shows the potential diagram of the first and second poles of the reset transistor T2 in Figure 9 the (b) diagram in Figure 8 shows the potential diagram of the first and second poles of the third transistor M3 in Figure 9 the (c) diagram in Figure 8 shows the potential diagram of the first and second poles of the fourth transistor M4 in Figure 9 It can be seen from the (a), (b), and (c) diagrams in Figure 2 that the voltage difference between the first and second poles of the third transistor M3 and the fourth transistor M4, that is, the source-drain voltage difference Vds, is less than

[0094] shown in Figure 8 the source-drain voltage difference Vds of the reset transistor T2 shown in the exemplary embodiment. In order to more clearly understand the effect of the exemplary embodiment shown inFigure 8 In the shown shift register, the source-drain voltage difference Vds of the third transistor M3, the fourth transistor M4 and Figure 2 the reset transistor T2 in the shown shift register is compared. The comparison results are shown in Table 1. In this example, the high-level (VGH) voltage is 22V, the voltage of the first voltage terminal (LVGL) is -11V, the voltage after the pull-up node PU is lifted twice is 44V, the periods of the first clock signal CLKB and the second clock signal CLK are 10H, the duty cycle is 50%, the effective average voltages are high levels, and the high-level duration of the frame start signal STV is 9H.

[0095] Table 1

[0096]

[0097] It can be seen from the comparison results that in this example, compared with Figure 2 the reset transistor T2 in, the maximum value of the source-drain voltage difference Vds of the fourth transistor M4 drops from 55V to 33V, a decrease of 40%, and the high-voltage duration drops from 9H + 5H = 14H to 5H, a decrease of 64%. In addition, the maximum value of the source-drain voltage difference Vds of the fourth transistor M4 is also 33V, 40% lower than that of the reset transistor T2.

[0098] Therefore, by adding the third transistor M3, the source-drain voltage difference Vds of the reset transistor can be effectively reduced, the working environment of the reset transistor can be improved, so that Vds can meet the current process capabilities without being broken down and burned, which is beneficial to improving the breakdown voltage resistance of the gate drive circuit and improving the display abnormality problem caused by the breakdown and burning of the reset transistor due to excessive and long Vds.

[0099] In some examples, the output sub-circuit 102 may include: a fifth transistor M5, a sixth transistor M6 and a capacitor C. The gate of the fifth transistor M5 is connected to the pull-up node PU, the first pole is connected to the second clock signal terminal CK2, and the second pole is connected to the cascade signal output terminal OUT_C. The gate of the sixth transistor M6 is connected to the pull-up node PU, the first pole is connected to the second clock signal terminal CK2, and the second pole is connected to the scan signal output terminal OUT_G. One end of the capacitor C is connected to the pull-up node PU, and the other end is connected to the scan signal output terminal OUT_G.

[0100] When the first clock signal terminal CK1 inputs a high level and the input terminal INPUT also inputs a high level, the input terminal INPUT pre-charges the pull-up node PU, pulling up the voltage of the pull-up node PU to a high level, for example, equal to the high-level voltage of the input signal, so that the fifth transistor M5 and the sixth transistor M6 are pre-conducted. Next, the second clock signal terminal CK2 starts to input a high level. Due to the effect of the capacitor, the voltage of the pull-up node PU is further pulled up through the bootstrap effect, making the fifth transistor M5 and the sixth transistor M6 fully conductive, thereby writing the high level of the second clock signal terminal CK2 to the cascade signal output terminal OUT_C and the scan signal output terminal OUT_G, so that both the cascade signal output terminal OUT_C and the scan signal output terminal OUT_G output a high level.

[0101] Of course, in other examples, the output terminal OUTPUT can also be one, which is used to provide both the scan signal, i.e., the gate driving signal, and the cascade signal. At this time, the output sub-circuit 102 can only include the above-mentioned sixth transistor M6 and the capacitor C. Specifically, it can be set according to actual needs, and this embodiment does not limit this.

[0102] In some examples, the node noise reduction sub-circuit 104 can include: a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is connected to the first noise reduction node PDA, the first pole is connected to the pull-up node PU, and the second pole is connected to the first voltage terminal LVGL. The gate of the eighth transistor M8 is connected to the second noise reduction node PDB, the first pole is connected to the pull-up node PU, and the second pole is connected to the first voltage terminal LVGL.

[0103] When the potential of the first noise reduction node PDA or the potential of the second noise reduction node PDB is at a high level, the seventh transistor M7 or the eighth transistor M8 conducts, writing the first low-level signal provided by the first voltage terminal LVGL to the pull-up node PU, thereby reducing the noise of the pull-up node PU.

[0104] In some examples, the output noise reduction sub - circuit 105 may include: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The gate of the ninth transistor M9 is connected to the first noise reduction node PDA, the first pole is connected to the cascade signal output terminal OUT_C, and the second pole is connected to the first voltage terminal LVGL. The gate of the tenth transistor M10 is connected to the first noise reduction node PDA, the first pole is connected to the scan signal output terminal OUT_G, and the second pole is connected to the second voltage terminal VGL. The gate of the eleventh transistor M11 is connected to the second noise reduction node PDB, the first pole is connected to the cascade signal output terminal OUT_C, and the second pole is connected to the first voltage terminal LVGL. The gate of the twelfth transistor M12 is connected to the second noise reduction node PDB, the first pole is connected to the scan signal output terminal OUT_G, and the second pole is connected to the second voltage terminal VGL.

[0105] When the potential of the first noise reduction node PDA or the potential of the second noise reduction node PDB is at a high level, the ninth transistor M9 and the tenth transistor M10 are turned on, or the eleventh transistor M11 and the twelfth transistor M12 are turned on, writing the first low - level signal provided by the first voltage terminal LVGL to the cascade signal output terminal OUT_C and writing the second low - level signal provided by the second voltage terminal VGL to the scan signal output terminal OUT_G, thereby reducing noise for the cascade signal output terminal OUT_C and the scan signal output terminal OUT_G respectively.

[0106] In some examples, the first control sub - circuit 106 may include: a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The gate and the first pole of the thirteenth transistor M13 are both connected to the third voltage terminal VDDA, and the second pole is connected to the first noise reduction node PDA. The gate of the fourteenth transistor M14 is connected to the pull - up node PU, the first pole is connected to the first noise reduction node PDA, and the second pole is connected to the first voltage terminal LVGL. The gate of the fifteenth transistor M15 is connected to the input terminal INPUT, the first pole is connected to the first noise reduction node PDA, and the second pole is connected to the first voltage terminal LVGL.

[0107] When the third voltage terminal VDDA provides a high-level signal, the thirteenth transistor M13 conducts, and writes the high level of the third voltage terminal VDDA to the first noise reduction node PDA. When the input terminal INPUT inputs a high level and / or the pull-up node PU is at a high level, the fourteenth transistor M14 and / or the fifteenth transistor M15 conduct, and write the first low-level signal provided by the first voltage terminal LVGL to the first noise reduction node PDA. At this time, a high level and a low level are written simultaneously, and the potential of the first noise reduction node PDA cannot be pulled up. When the input terminal INPUT inputs a low level and the pull-up node PU is at a low level, the fourteenth transistor M14 and the fifteenth transistor M15 are turned off, and the first noise reduction node PDA is pulled up to a high level by the third voltage terminal VDDA.

[0108] Similarly, the second control sub-circuit 107 may include: a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The gate and the first pole of the sixteenth transistor M16 are both connected to the fourth voltage terminal VDDB, and the second pole is connected to the second noise reduction node PDB. The gate of the seventeenth transistor M17 is connected to the pull-up node PU, the first pole is connected to the second noise reduction node PDB, and the second pole is connected to the first voltage terminal LVGL. The gate of the eighteenth transistor M18 is connected to the input terminal INPUT, the first pole is connected to the second noise reduction node PDB, and the second pole is connected to the first voltage terminal LVGL. The specific principle can refer to the description of the first control sub-circuit 106, and will not be elaborated here.

[0109] It should be noted that the third voltage terminal VDDA and the fourth voltage terminal VDDB are configured to alternately provide a DC high-level signal. For example, the third voltage terminal VDDA and the fourth voltage terminal VDDB respectively provide an alternating DC high-level signal and a DC low-level signal, and the signals provided by the third voltage terminal VDDA and the fourth voltage terminal VDDB are anti-phase signals to each other.

[0110] The output reset sub-circuit 108 may include: a nineteenth transistor M19. The gate of the nineteenth transistor M19 is connected to the first reset terminal RST1, the first pole is connected to the scan signal output terminal OUT_G, and the second pole is connected to the second voltage terminal VGL. When the first reset terminal RST1 inputs a high level, the nineteenth transistor M19 conducts, and the second low-level signal provided by the second voltage terminal VGL is written to the scan signal output terminal OUT_G, resetting the scan signal output terminal OUT_G to a low level.

[0111] The frame reset sub - circuit 109 may include: a twentieth transistor M20. The gate of the twentieth transistor M20 is connected to a second reset terminal RST2, the first pole is connected to a pull - up node PU, and the second pole is connected to a first voltage terminal LVGL. When a high level is input to the second reset terminal RST2, the twentieth transistor M20 is turned on, and the first low - level signal provided by the first voltage terminal LVGL is written into the pull - up node PU, resetting the pull - up node PU to a low level.

[0112] Figure 10 shows Figure 8 An exemplary working timing sequence of the shift register shown in. Assume that the shift register is located in the first stage of the gate driving circuit, and the input signal INPUT is a frame start signal STV.

[0113] Then, at stage t1, both STV and CLKB are at high levels, M1 and M2 are turned on, and the high level of STV is written into the pull - up node PU, causing the potential of the pull - up node PU to be raised, and M5 and M6 are pre - turned on. At this time, the cascaded signal output terminal OUT_C still remains at a low level, and the A node is at a low level.

[0114] At stage t2, CLK is at a high level, and the potential of the pull - up node PU is further raised due to the bootstrap effect. M5 and M6 are turned on, and the high level of CLK is written into the scan signal output terminal OUT_G and the cascaded signal output terminal OUT_C, causing both OUT_G and OUT_C to output high levels, and the A node is at a high level.

[0115] At stage t3, the pull - up node is at a low level, both OUT_G and OUT_C output low levels, the A node is at a low level, the first noise reduction node PDA or the second noise reduction node PDB is at a high level, and M7, M9, and M10 are turned on, or M8, M11, and M12 are turned on to reduce noise for the pull - up node PU, the scan signal output terminal OUT_G, and the cascaded signal output terminal OUT_C.

[0116] It should be noted that the "high level" and "low level" in this article respectively refer to two logical states represented by a potential height range at a certain position. For example, the high level can specifically refer to a potential higher than the common - terminal voltage, and the low level can specifically refer to a potential lower than the common - terminal voltage. At the same time, the "high - level" potential at different positions may not be the same, and the "low - level" potential at different positions may also not be the same. It can be understood that the specific potential height range can be set according to needs in a specific application scenario, and this embodiment does not limit it.

[0117] In the description of the embodiments of the present disclosure, the pull - up node PU, the first noise reduction node PDA, the second noise reduction node PDB, and the A node do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram.

[0118] It should be noted that the transistors used in the embodiments of the present disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin-film transistors are taken as examples for illustration. The source and drain of the transistors used here can be symmetric in structure, so there can be no difference between the source and drain in terms of structure. In the embodiments of the present disclosure, in order to distinguish the two poles (i.e., the source and the drain) of the transistor other than the gate, one of the poles is described as the first pole and the other as the second pole.

[0119] The embodiments of the present disclosure also provide a driving method for a shift register, which is used to drive the shift register provided in the above embodiments. As Figure 11 shown, the method may include the following steps:

[0120] Step S101, when both the first clock signal and the input signal are at the effective level, write the input signal into the pull-up node to control the level of the pull-up node;

[0121] Step S102, under the control of the level of the pull-up node, output the second clock signal to the output terminal, where the first clock signal and the second clock signal have the same period, and the arrival time of the effective level of the first clock signal is earlier than the arrival time of the effective level of the second clock signal;

[0122] Step S103, based on the reset signal, reset the pull-up node.

[0123] It should be noted that the implementation processes of steps S101 to S103 can refer to the relevant descriptions above, and will not be elaborated here.

[0124] The embodiments of the present disclosure also provide a gate driving circuit, which includes N cascaded shift registers, where N is an integer greater than 2. Among them, the shift register used is the shift register provided in the embodiments of the present disclosure. The input terminal of the first-stage shift register is connected to the frame input signal line; the input terminal of the i-th stage shift register is connected to the output terminal of the (i - 1)-th stage shift register, and the output terminal of the i-th stage shift register is connected to the first reset terminal of the (i - 1)-th stage shift register, where 1 < i ≤ N; the first reset terminal of the N-th stage shift register is connected to the frame reset signal line.

[0125] Since the shift register included in the gate driving circuit introduced in the embodiments of the present disclosure has been described above, based on the shift register introduced in the embodiments of the present disclosure, those skilled in the art can understand the specific structure and effect principle of the gate driving circuit, so it will not be elaborated here. Any gate driving circuit including the shift register of the embodiments of the present disclosure falls within the scope of protection of the present disclosure.

[0126] Embodiments of the present disclosure also provide a display device, including the gate driving circuit provided in the above embodiments. In addition, the display device further includes: 2M clock signal lines and at least one frame input signal line for receiving a frame start signal, where M is a positive integer. Each stage of the shift register in the gate driving circuit is respectively connected to the corresponding clock signal line among the 2M clock signal lines.

[0127] In some scenarios, in order to increase the refresh rate of the display device, M is an integer greater than or equal to 2. For example, when M is 2, it is a 4CLK operating mode; when M is 3, it is a 6CLK operating mode; when M is 4, it is an 8CLK operating mode; when M is 5, it is a 10CLK operating mode. Further, considering circuit cost and the border, the frame input signal line can be one. At this time, the input ends of the shift registers in the first stage of the gate driving circuit are connected to the same frame input signal line.

[0128] For example, the display device can be a display panel, such as a liquid crystal display panel, an OLED (Organic Light-Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, etc., or it can also be any product or component with a display function, such as a television, a monitor, an electronic paper display device, a personal computer (PC), a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. Embodiments of the present disclosure do not limit this. The technical effects of the display device can refer to the corresponding descriptions of the shift register in the above embodiments and will not be elaborated here.

[0129] In the specification provided here, a large number of specific details are described. However, it can be understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0130] Similarly, it should be understood that in the above description of the exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting the intention that the claimed present disclosure requires more features than those expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all the features of the single embodiments disclosed above. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, where each claim itself serves as a separate embodiment of the present disclosure.

[0131] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0132] In addition, those skilled in the art can understand that the combination of features of different embodiments is within the scope of the present disclosure and forms different embodiments. The above embodiments are illustrative of the present disclosure rather than restrictive of the present disclosure, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A shift register, characterized in that, comprising: An input sub-circuit, connected to an input terminal, a first clock signal terminal, and a pull-up node, for writing the input signal to the pull-up node to control the level of the pull-up node when both the first clock signal and the input signal are at valid levels; An output sub-circuit, connected to the pull-up node, a second clock signal terminal, and an output terminal, for outputting the second clock signal to the output terminal under the control of the level of the pull-up node; A node reset sub-circuit, connected to the pull-up node and a first reset terminal, for resetting the pull-up node in response to a reset signal received by the first reset terminal; wherein, the period of the first clock signal is the same as that of the second clock signal, and the arrival time of the valid level of the first clock signal precedes the arrival time of the valid level of the second clock signal; The input sub-circuit includes a first transistor and a second transistor. The first pole of the first transistor is connected to the input terminal, the second pole is connected to the pull-up node, the gate of the second transistor is connected to the first clock signal terminal, the first pole is connected to the input terminal, and the second pole is connected to the gate of the first transistor.

2. The shift register according to claim 1, characterized in that, The node reset sub-circuit includes: a third transistor and a fourth transistor, The gates of the third transistor and the fourth transistor are both connected to the first reset terminal; The first pole of the third transistor is connected to the pull-up node, the second pole is respectively connected to the output terminal and the first pole of the fourth transistor, and the second pole of the fourth transistor is connected to a first voltage terminal.

3. The shift register according to claim 2, characterized in that, The output sub-circuit includes: a first output sub-circuit and a second output sub-circuit, The first output sub-circuit is respectively connected to the pull-up node, the second clock signal terminal, and a cascade signal output terminal, for writing the second clock signal to the cascade signal output terminal under the control of the pull-up node; The second output sub-circuit is respectively connected to the pull-up node, the second clock signal terminal, and a scan signal output terminal, for writing the second clock signal to the scan signal output terminal under the control of the pull-up node; The second pole of the third transistor is connected to the cascade signal output terminal.

4. The shift register according to claim 1, characterized in that, The time period during which the first clock signal is at a valid level at least partially overlaps with the time period during which the input signal is at a valid level, and the first clock signal and the second clock signal alternately are at the valid level.

5. The shift register according to claim 1, characterized in that, further comprising: A node noise reduction sub-circuit, connected to the pull-up node, a first noise reduction node, and a second noise reduction node, for reducing noise of the pull-up node under the control of the level of the first noise reduction node or the level of the second noise reduction node.

6. The shift register according to claim 1, characterized in that, further comprising: An output noise reduction sub - circuit, which is respectively connected to a first noise reduction node, a second noise reduction node and the output terminal, and is used to reduce the noise of the output terminal under the control of the level of the first noise reduction node or the level of the second noise reduction node.

7. The shift register according to claim 5 or 6, wherein, it further comprises: a first control sub - circuit and a second control sub - circuit, the first control sub - circuit is respectively connected to the pull - up node and the first noise reduction node, and is used to control the level of the first noise reduction node under the control of the level of the pull - up node; the second control sub - circuit is respectively connected to the pull - up node and the second noise reduction node, and is used to control the level of the second noise reduction node under the control of the level of the pull - up node.

8. The shift register according to claim 1, wherein, it further comprises: an output reset sub - circuit and a frame reset sub - circuit, the output reset sub - circuit is respectively connected to the first reset terminal and the output terminal, and is used to reset the output terminal under the control of the reset signal received by the first reset terminal; the frame reset sub - circuit is connected to the second reset terminal and the pull - up node, and is used to reset the pull - up node under the control of the frame reset signal received by the second reset terminal.

9. A driving method for a shift register, wherein, it is used to drive the shift register according to any one of claims 1 - 8, and the method includes: when the first clock signal and the input signal are both at the valid level, writing the input signal to the pull - up node to control the level of the pull - up node; under the control of the level of the pull - up node, outputting a second clock signal to the output terminal, wherein the first clock signal and the second clock signal have the same period, and the arrival time of the valid level of the first clock signal is earlier than the arrival time of the valid level of the second clock signal; resetting the pull - up node based on the reset signal.

10. A gate driving circuit, wherein, it includes N - stage cascaded shift registers, and the shift register is the shift register according to any one of claims 1 - 8, where N is an integer greater than 2; the input terminal of the first - stage shift register is connected to the frame input signal line. When each stage includes multiple shift registers and the first - stage shift registers are all connected to the same frame input signal line, the duration of the valid level of the first clock signal is less than the duration of the valid level of the frame start signal input by the frame input signal line; the input terminal of the i - th stage shift register is connected to the output terminal of the (i - 1) - th stage shift register, and the output terminal of the i - th stage shift register is connected to the first reset terminal of the (i - 1) - th stage shift register, where 1 < i ≤ N; the first reset terminal of the N - th stage shift register is connected to the frame reset signal line.

11. A display device, wherein, it includes: the gate driving circuit according to claim 10.

12. The display device according to claim 11, wherein, it further comprises: 2M clock signal lines and at least one frame input signal line for receiving a frame start signal, where M is an integer greater than or equal to 2; Each stage of shift register in the gate driving circuit is respectively connected to the corresponding clock signal line among the 2M clock signal lines; The input ends of the shift registers at the first stage in the gate driving circuit are connected to the same frame input signal line.

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