Display device and display driving method

Abstract

Embodiments of the present invention relate to a display device and a display driving method. The display device includes: a display panel including a light-emitting element, a driving transistor for providing a driving current to the light-emitting element, and a plurality of switching transistors for controlling the operation of the driving transistor; a gate driving circuit for providing a plurality of scan signals to the display panel; a data driving circuit for providing a plurality of data voltages to the display panel; and a timing controller for controlling the gate driving circuit and the data driving circuit, wherein a bias voltage is provided to the driving transistor during a first period of providing the data voltages to the display panel in a low-speed mode, wherein the display panel is driven at a predetermined speed frequency in the low-speed mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0124376 filed on September 16, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display device and a display driving method, which can reduce image quality defects occurring on a display panel during a process of changing a driving frequency. Background Art

[0004] With the development of the information society, the demand for various types of image display devices is increasing. In this regard, a series of display devices such as liquid crystal display devices and organic light emitting display devices have been widely used recently.

[0005] Among these display devices, organic light emitting display devices have excellent characteristics such as fast response speed, high contrast, high luminous efficiency, high brightness, and wide viewing angle because they use self-luminous organic light emitting diodes as light emitting elements.

[0006] Such an organic light emitting display device may include organic light emitting diodes (OLEDs) in a plurality of sub-pixels arranged in a display panel, and may control the organic light emitting diodes to emit light by controlling a voltage flowing through the OLEDs, thereby displaying an image while controlling the brightness of the sub-pixels.

[0007] In this case, the image data provided to the display device may be a still image or a moving image that changes at a constant speed, and even in the case of a moving image, there may be various types of images such as motion pictures, movies, or game images.

[0008] Furthermore, the display device may be switched to various operation modes according to a user's input or operation status.

[0009] On the other hand, the display device may change the driving frequency according to the type of input image data or the operation mode. In the process of changing the driving frequency, brightness deviation occurs, which causes image distortion or quality degradation such as flicker. Summary of the Invention

[0010] Therefore, the inventors of the present invention have invented a display device and a display driving method, which can reduce defects in image quality that occur during the process of changing the driving frequency.

[0011] Embodiments of the present invention provide a display device and a display driving method capable of reducing image quality defects by applying a bias voltage for preventing luminance degradation of a light-emitting element when a driving frequency changes from a high-speed driving frequency to a low-speed driving frequency.

[0012] Embodiments of the present invention provide a display device and a display driving method capable of reducing image quality defects by controlling the level of a stabilization voltage applied to a driving transistor when a driving frequency changes from a high-speed driving frequency to a low-speed driving frequency.

[0013] Embodiments of the present invention provide a display device and a display driving method capable of reducing image quality defects by controlling the level of a reset voltage applied to a light emitting element when a driving frequency changes from a high-speed driving frequency to a low-speed driving frequency.

[0014] Problems solved by the embodiments of the present invention described below are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0015] According to an embodiment of the present invention, a display device includes: a display panel, the display panel including a light-emitting element, a driving transistor for providing a driving current to the light-emitting element, and a plurality of switching transistors for controlling the operation of the driving transistor; a gate driving circuit for providing a plurality of scan signals to the display panel; a data driving circuit for providing a plurality of data voltages to the display panel; and a timing controller for controlling the gate driving circuit and the data driving circuit, wherein a bias voltage is provided to the driving transistor in a first period of time in which the data voltage is provided to the display panel in a low-speed mode, wherein the display panel is driven at a predetermined speed frequency in the low-speed mode.

[0016] In the display device according to an embodiment of the present invention, the plurality of switching transistors include: a first switching transistor, wherein a first scanning signal is supplied to a gate of the first switching transistor, a drain of the first switching transistor is connected to the gate of the driving transistor, and a source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein a second scanning signal is supplied to a gate of the second switching transistor, a data voltage or the bias voltage is supplied to a drain of the second switching transistor, and a source of the second switching transistor is connected to the drain of the driving transistor; a third switching transistor, wherein a light emitting signal is supplied to a gate of the third switching transistor, a high potential driving voltage is supplied to a drain of the third switching transistor, and a source of the third switching transistor is connected to a drain of the third switching transistor. a first switching transistor, wherein the light emitting signal is supplied to the gate of the fourth switching transistor, the drain of the fourth switching transistor is connected to the source of the driving transistor, and the source of the fourth switching transistor is connected to the anode of the light emitting element; a second switching transistor, wherein the third scanning signal is supplied to the gate of the fifth switching transistor, the stabilization voltage is supplied to the drain of the fifth switching transistor, and the source of the fifth switching transistor is connected to the gate of the driving transistor and a storage capacitor; and a third switching transistor, wherein the fourth scanning signal is supplied to the gate of the sixth switching transistor, the reset voltage is supplied to the drain of the sixth switching transistor, and the source of the sixth switching transistor is connected to the anode of the light emitting element.

[0017] In a display device according to an embodiment of the present invention, the plurality of switching transistors include: a first switching transistor, wherein a first scanning signal is supplied to a gate of the first switching transistor, a drain of the first switching transistor is connected to the gate of the driving transistor, and a source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein a second scanning signal is supplied to a gate of the second switching transistor, a data voltage is supplied to a drain of the second switching transistor, and a source of the second switching transistor is connected to the drain of the driving transistor; a third switching transistor, wherein a light emitting signal is supplied to a gate of the third switching transistor, a high potential driving voltage is supplied to a drain of the third switching transistor, and a source of the third switching transistor is connected to the drain of the driving transistor; a fourth switching transistor, wherein the light emitting signal is supplied to a gate of the fourth switching transistor a gate of the fourth switching transistor, the drain of the fourth switching transistor is connected to the source of the driving transistor, and the source of the fourth switching transistor is connected to the anode of the light-emitting element; a fifth switching transistor, wherein the third scanning signal is supplied to the gate of the fifth switching transistor, the stabilization voltage is supplied to the drain of the fifth switching transistor, and the source of the fifth switching transistor is connected to the gate of the driving transistor and a storage capacitor; a sixth switching transistor, wherein the fourth scanning signal is supplied to the gate of the sixth switching transistor, the reset voltage is supplied to the drain of the sixth switching transistor, and the source of the sixth switching transistor is connected to the anode of the light-emitting element; and a seventh switching transistor, wherein the fifth scanning signal is supplied to the gate of the seventh switching transistor, the bias voltage is supplied to the drain of the seventh switching transistor, and the source of the seventh switching transistor is connected to the drain of the driving transistor.

[0018] In the display device according to the embodiment of the present invention, the bias voltage is supplied between a compensation period for compensating the characteristic value of the driving transistor in the first period and a light emitting period of the light emitting element.

[0019] In the display device according to the embodiment of the present invention, the bias voltage is supplied to the driving transistor in a second period in which the data voltage is not supplied to the display panel after a first period in a low-speed mode in which the display panel is driven at a low-speed driving frequency.

[0020] In the display device according to the embodiment of the present invention, the bias voltage supplied in the first period and the bias voltage supplied in the second period have different levels.

[0021] In the display device according to an embodiment of the present invention, the level of the stabilization voltage or the reset voltage is controlled in a second period in which the data voltage is not supplied to the display panel after a first period in a low-speed mode in which the display panel is driven at a low-speed driving frequency.

[0022] In the display device according to the embodiment of the present invention, the stabilization voltage is determined according to a level or grayscale of a data voltage supplied to the display panel in the first period.

[0023] In the display device according to the embodiment of the present invention, the reset voltage is determined according to the level of the low-potential driving voltage supplied to the cathode of the light emitting element in the first period.

[0024] According to an embodiment of the present invention, a display driving method for driving a display panel is provided, wherein the display panel includes a light-emitting element, a driving transistor for providing a driving current to the light-emitting element, and a plurality of switching transistors for controlling the operation of the driving transistor. The display driving method includes: switching from a first mode of driving at a high-speed driving frequency to a second mode of driving at a low-speed driving frequency; providing a first bias voltage to the driving transistor in a first period, wherein a data voltage is provided to the display panel in the second mode during the first period; and providing a second bias voltage to the driving transistor in a second period after the first period, wherein the data voltage is not provided to the display panel during the second period.

[0025] According to the embodiments of the present invention, a display device and a display driving method can be provided, which can reduce image quality defects that occur during the process of changing the driving frequency.

[0026] In addition, according to an embodiment of the present invention, a display device and a display driving method can be provided, which can reduce image quality defects by applying a bias voltage for preventing brightness degradation of a light-emitting element when the driving frequency changes from a high-speed driving frequency to a low-speed driving frequency.

[0027] Furthermore, according to an embodiment of the present invention, a display device and a display driving method can be provided, which can reduce image quality defects by controlling the level of a stabilization voltage applied to a driving transistor when the driving frequency changes from a high-speed driving frequency to a low-speed driving frequency.

[0028] In addition, according to an embodiment of the present invention, a display device and a display driving method can be provided, which can reduce image quality defects by controlling the level of the reset voltage applied to the light-emitting element when the driving frequency changes from a high-speed driving frequency to a low-speed driving frequency.

[0029] The effects of the embodiments disclosed in the present invention are not limited to the above-mentioned effects. In addition, those skilled in the art will clearly understand from the following description that the embodiments disclosed in the present invention can achieve other effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the attached figure:

[0031] Figure 1 A schematic diagram showing a display device according to an embodiment of the present invention is shown.

[0032] Figure 2 A system diagram of a display device according to an embodiment of the present invention is shown.

[0033] Figure 3 A sub-pixel circuit diagram of a display device according to an embodiment of the present invention is shown.

[0034] Figure 4 FIG. 1 is a schematic diagram showing a driving mode based on frequency variation in a display device according to an embodiment of the present invention.

[0035] Figure 5 1 shows a driving timing in the second mode of driving at a low speed frequency in the display device according to the embodiment of the present invention.

[0036] Figure 6 A signal diagram showing brightness changes when the display device operates at a low driving frequency.

[0037] Figure 7 A signal diagram is shown in a case where luminance degradation is reduced by providing a bias voltage in a refresh frame in a display device according to an embodiment of the present invention.

[0038] Figure 8 A signal diagram is shown in a case where luminance degradation is reduced by providing a bias voltage in a skip frame in a display device according to an embodiment of the present invention.

[0039] Figure 9 A diagram showing a case where a luminance deviation in a frame skip is improved by performing a turn-on bias process in a refresh frame in a display device according to an embodiment of the present invention.

[0040] Figures 10 to 12 FIG. 4 shows changes in current flowing through a light-emitting element according to levels of a bias voltage, a stabilization voltage, and a reset voltage in a display device according to an embodiment of the present invention.

[0041] Figure 13 Another sub-pixel circuit diagram in a display device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] The advantages and features of the present invention and methods for achieving these advantages and features will become apparent through reference to the accompanying drawings and detailed description of the embodiments. However, the present invention should not be construed as limited to the embodiments set forth herein, but rather may be implemented in a variety of different forms. These embodiments are provided to make the disclosure of the present invention thorough and complete and to fully convey the scope of the present invention to those skilled in the art. The scope of the present invention is defined by the appended claims.

[0043] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing exemplary embodiments are merely examples, and the present invention is not limited to the embodiments shown in the drawings. The same reference numerals and symbols will be used throughout the application to refer to the same or similar components. In the following description of the present invention, detailed descriptions of known functions and components involved in the present invention will be omitted to avoid unnecessarily obscuring the subject matter of the present invention. It will be understood that the terms "including", "having" and "comprising" used herein and any variations thereof are intended to cover non-exclusive "including" unless otherwise expressly stated.

[0044] When analyzing an element, it should be understood that the element is interpreted as including a range of error even if not explicitly stated.

[0045] When spatially relative terms such as "on," "above," "below," "under," and "to the side of" are used to describe the relationship between one element or component and another element or component, one or more intervening elements or components may be present between the one element or component and the other element or component unless terms such as "directly" are used.

[0046] When time-relative terms such as "after," "subsequently," "following," and "before" are used to define a temporal relationship, discontinuous situations may be included unless the terms "immediately" or "directly" are used.

[0047] When describing signal transmission such as "a signal is sent from node A to node B," the signal may be sent from node A to node B via another node unless the term "immediately" or "directly" is used.

[0048] Furthermore, terms such as "first" and "second" may be used herein to describe various components. However, it should be understood that these components are not limited by these terms. These terms are merely used to distinguish one element or component from other elements or components. Therefore, within the spirit of the present invention, the first component mentioned below may also be the second component.

[0049] The features of the exemplary embodiments of the present invention may be combined or combined with each other in part or in whole, and may cooperate with each other or operate in various technical ways. In addition, each exemplary embodiment may be implemented independently of each other, or implemented in conjunction with other embodiments.

[0050] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 A schematic diagram showing a display device according to an embodiment of the present invention is shown.

[0052] Reference Figure 1 According to an embodiment of the present invention, a display device 100 may include: a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, in which a plurality of sub-pixels SP are arranged in rows and columns; a gate driving circuit 120 for supplying scan signals to the plurality of gate lines GL and a data driving circuit 130 for supplying data voltages to the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0053] The display panel 110 displays an image based on scan signals supplied from the gate driving circuit 120 via the plurality of gate lines GL and data voltages supplied from the data driving circuit 130 via the plurality of data lines DL.

[0054] In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates and can operate in any known mode such as a TN (twisted nematic) mode, a VA (vertical alignment) mode, an IPS (in-plane switching) mode, or an FFS (fringe field switching) mode. In the case of an organic light-emitting display device, the display panel 110 can be implemented in a top emission method, a bottom emission method, or a bi-directional emission method.

[0055] In the display panel 110, a plurality of pixels may be arranged in a matrix. Each pixel may be composed of sub-pixels SP of different colors, such as a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0056] The subpixel SP may include a thin film transistor (TFT) disposed in a region where the data line DL and the gate line GL cross each other, a light emitting element such as a light emitting diode that emits light according to a data voltage, and a storage capacitor for maintaining the data voltage by being electrically connected to the light emitting element.

[0057] For example, when the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white W, red R, green G, and blue B, 3840×4=15360 data lines can be provided by 2160 gate lines GL and 3840 data lines DL connected to the four sub-pixels WRGB, respectively. Each of the plurality of sub-pixels SP can be arranged in a region where the plurality of gate lines GL and the plurality of data lines DL overlap with each other.

[0058] The gate driving circuit 120 is controlled by the timing controller 140 , and controls the driving timing of the plurality of sub-pixels SP by sequentially supplying scan signals to the plurality of gate lines GL located in the display panel 110 .

[0059] In the display device 100 having a resolution of 2160×3840, the operation of sequentially supplying scan signals to 2160 gate lines from the first gate line GL1 to the 2160th gate line GL2160 may be referred to as a 2160-phase drive operation. On the other hand, the operation of sequentially supplying scan signals to every four gate lines GL, such as the case where the scan signal is sequentially supplied from the first gate line GL1 to the fourth gate line GL4 and then sequentially supplied from the fifth gate line GL5 to the eighth gate line GL8, may be referred to as a 4-phase drive operation. As described above, the operation of sequentially supplying scan signals to every N gate lines may be referred to as an N-phase drive operation.

[0060] The gate driver circuit 120 may include one or more gate driver integrated circuits (GDICs), which may be provided on one or both sides of the display panel 110 depending on the driving method. Alternatively, the gate driver circuit 120 may be implemented as a gate-in-panel (GIP) structure built into the bezel area of ​​the display panel 110.

[0061] The data driving circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. Then, the data driving circuit 130 supplies the analog data voltage to each data line DL at a time when a scan signal is supplied via the gate line GL, thereby causing each sub-pixel SP connected to the data line DL to emit light at a corresponding brightness corresponding to the analog data voltage.

[0062] Similarly, the data driver circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 via tape automated bonding (TAB) or chip on glass (COG), or may be directly mounted on the display panel 110.

[0063] In some cases, each source driver integrated circuit (SDIC) may be integrated with the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented using a chip on film (COF) structure. In this case, the source driver integrated circuit (SDIC) may be mounted on a circuit film to be electrically connected to the data line DL in the display panel 110 via the circuit film.

[0064] The timing controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to provide a scan signal in response to the timing achieved by the corresponding frame; on the other hand, the timing controller 140 transmits image data DATA from an external source to the data driving circuit 130.

[0065] Here, the timing controller 140 receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from the external host system 200 .

[0066] The host system 200 may be any one of a TV (television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0067] Therefore, the timing controller 140 generates control signals using various timing signals received from an external source and provides the control signals to the gate driving circuit 120 and the data driving circuit 130 .

[0068] For example, the timing controller 140 generates various gate control signals including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE to control the gate driver circuit 120. Here, the gate start pulse GSP is used to control the start timing of one or more gate driver integrated circuits (GDICs) of the gate driver circuit 120. In addition, the gate clock GCLK is a clock signal commonly provided to one or more gate driver integrated circuits (GDICs) to control the shift timing of the scan signal. The gate output enable signal GOE specifies the timing information of one or more gate driver integrated circuits (GDICs).

[0069] In addition, the timing controller 140 generates various data control signals, including a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE, to control the data driver circuit 130. The source start pulse SSP is used to control the start timing of data sampling for one or more source driver integrated circuits (SDICs) in the data driver circuit 130. The source sampling clock SCLK is a clock signal used to control the data sampling timing in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data driver circuit 130.

[0070] The display device 100 may further include a power management circuit 150 for providing or controlling various voltages or currents for the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 .

[0071] The power management circuit 150 generates necessary power required to drive the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 by controlling the DC input voltage Vin provided from the host system 200 .

[0072] The sub-pixel SP is located at a point where the gate line GL and the data line DL intersect each other, and a light-emitting element may be located in each sub-pixel SP. For example, an organic light-emitting display device may include a light-emitting element such as a light-emitting diode located in each sub-pixel SP, and may display an image by controlling a current flowing through the light-emitting element in response to a data voltage.

[0073] The display device 100 may be various devices such as a liquid crystal display, an organic light emitting display, and a plasma display panel.

[0074] Figure 2 A system diagram of a display device according to an embodiment of the present invention is shown.

[0075] As an example, Figure 2 It is shown that in the display device 100 according to the embodiment of the present invention, each source driver integrated circuit SDIC of the data driver circuit 130 and each gate driver integrated circuit GDIC of the gate driver circuit 120 are implemented using a COF type among various structures such as TAB, COG and COF.

[0076] One or more gate driver integrated circuits GDIC included in the gate driver circuit 120 may be mounted on the gate film GF, respectively, and one side of the gate film GF may be electrically connected to the display panel 110. In addition, wires may be provided on the gate film GF to electrically connect the gate driver integrated circuits GDIC and the display panel 110.

[0077] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits SDIC that may be mounted on the source film SF, respectively. A portion of the source film SF may be electrically connected to the display panel 110. In addition, wires may be provided on the source film SF to electrically connect the source driver integrated circuits SDIC and the display panel 110.

[0078] The display device 100 may include at least one source printed circuit board (SPCB) for connecting a plurality of source driver integrated circuits (SDIC) to other devices through circuits, and a control printed circuit board (CPCB) for mounting various control components and electrical elements.

[0079] The other portion of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. That is, one portion of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other portion of the source film SF may be electrically connected to the source printed circuit board SPCB.

[0080] The timing controller 140 and the power management circuit 150 may be mounted on the control printed circuit board (CPCB). The timing controller 140 may control the operation of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage and a driving current, or control the voltage and current for the data driving circuit 130 and the gate driving circuit 120.

[0081] The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be circuit-connected via at least one connecting member. For example, the connecting member may be a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like. In this case, the connecting member used to connect the at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may vary depending on the size and type of the display device 100. The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0082] In the display device 100 having the above configuration, the power management circuit 150 supplies the driving voltage required for display driving operation or characteristic value sensing operation to the source printed circuit board SPCB via the flexible printed circuit (FPC) or the flexible flat cable (FFC). The driving voltage supplied to the source printed circuit board SPCB is transmitted within the display panel 110 via the source driver integrated circuit (SDIC) to cause a specific sub-pixel SP to emit light or sense a specific sub-pixel SP.

[0083] Each sub-pixel SP arranged in the display panel 110 of the display device 100 may include an organic light emitting diode as a light emitting element and circuit elements such as a driving transistor for driving the light emitting element.

[0084] The type and number of circuit elements constituting each sub-pixel SP may be variously determined according to function, design, and the like.

[0085] Figure 3 A sub-pixel circuit diagram of a display device according to an embodiment of the present invention is shown.

[0086] Reference Figure 3 , the sub-pixel SP of the display device 100 according to the embodiment of the present invention includes first to sixth switching transistors T1 - T6 , a driving transistor DRT, a storage capacitor Cst, and a light emitting element ED.

[0087] Here, the light-emitting element ED may be, for example, a self-luminous element capable of emitting light by itself, such as an organic light-emitting diode OLED.

[0088] In the subpixel SP according to the embodiment of the present invention, the second to fourth switching transistors T2 - T4 , the sixth switching transistor T6 and the driving transistor DRT may be P-type transistors, and the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

[0089] P-type transistors are relatively more reliable than N-type transistors. P-type transistors have the advantage that, because their drains are fixed to a high-potential drive voltage VDD, the current flowing through the light-emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, current can be stably supplied.

[0090] For example, a P-type transistor may be connected to the anode of the light-emitting element ED. In this case, when the transistors T4 and T6 connected to the light-emitting element ED operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the light-emitting element ED. Therefore, reliability is relatively high.

[0091] In this sub-pixel SP structure, the N-type transistors T1 and T5 may include oxide transistors formed using semiconductor oxides (for example, transistors having channels formed of semiconductor oxides such as indium, gallium, zinc oxide, or IGZO), and the other P-type transistors DRT, T2-T4, and T6 may include silicon transistors formed of semiconductors such as silicon (for example, transistors having polysilicon channels formed by a low-temperature process such as LTPS or low-temperature polysilicon).

[0092] Oxide transistors have relatively lower leakage current than silicon transistors. Therefore, when implemented using oxide transistors, leakage current from the gate of the drive transistor DRT is reduced, which has the effect of reducing image quality defects such as flicker.

[0093] Meanwhile, the remaining P-type transistors DRT, T2 - T4 , and T6 excluding the first and fifth switching transistors T1 and T5 corresponding to N-type transistors may be formed of low-temperature polysilicon.

[0094] The first scan signal SCAN1 is provided to the gate of the first switch transistor T1. The drain of the first switch transistor T1 is connected to the gate of the drive transistor DRT.

[0095] The source of the first switching transistor T1 is connected to the source of the driving transistor DRT.

[0096] The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT using the high potential driving voltage VDD stored in the storage capacitor Cst.

[0097] The first switch transistor T1 may be formed by an N-type MOS transistor to constitute an oxide transistor. Since the N-type MOS transistor uses electrons as carriers, it has higher mobility and faster switching speed than the P-type MOS transistor.

[0098] The second scan signal SCAN2 is provided to the gate of the second switch transistor T2. The data voltage Vdata or the bias voltage VOBS may be provided to the drain of the second switch transistor T2. The source of the second switch transistor T2 is connected to the drain of the drive transistor DRT.

[0099] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata to the drain of the driving transistor DRT.

[0100] The light emitting signal EM is supplied to the gate of the third switch transistor T3, the high potential driving voltage VDD is supplied to the drain of the third switch transistor T3, and the source of the third switch transistor T3 is connected to the drain of the driving transistor DRT.

[0101] The third switch transistor T3 is turned on by the light emitting signal EM to provide the high potential driving voltage VDD to the drain of the driving transistor DRT.

[0102] The emission signal EM is provided to the gate of the fourth switch transistor T4. The drain of the fourth switch transistor T4 is connected to the source of the drive transistor DRT. The source of the fourth switch transistor T4 is connected to the anode of the light emitting element ED.

[0103] The fourth switching transistor T4 is turned on by the light emitting signal EM to provide a driving current to the anode of the light emitting element ED.

[0104] The third scan signal SCAN3 is provided to the gate of the fifth switching transistor T5.

[0105] Here, the third scan signal SCAN3 may be the first scan signal SCAN1 provided to the sub-pixel SP located at another position. For example, when the first scan signal SCAN1 is provided to the n-th gate line, the third scan signal SCAN3 may be the first scan signal SCAN1[n-9] provided to the (n-9)-th gate line. That is, depending on the driving phase of the display panel 110, the third scan signal SCAN3 may function as the first scan signal SCAN1 at another gate line GL.

[0106] A stabilization voltage Vini is supplied to the drain of the fifth switching transistor T5. A source of the fifth switching transistor T5 is connected to the gate of the driving transistor DRT and the storage capacitor Cst.

[0107] The fifth switch transistor T5 is turned on by the third scan signal SCAN3 to provide the stabilized voltage Vini to the gate of the driving transistor DRT.

[0108] The fourth scan signal SCAN4 is provided to the gate of the sixth switching transistor T6.

[0109] Here, the fourth scan signal SCAN4 may be the second scan signal SCAN2 provided to the sub-pixel SP located at another position. For example, when the second scan signal SCAN2 is provided to the n-th gate line, the fourth scan signal SCAN4 may be the second scan signal SCAN2[n-1] provided to the (n-1)-th gate line. That is, depending on the driving phase of the display panel 110, the fourth scan signal SCAN4 may function as the second scan signal SCAN2 at another gate line GL.

[0110] The reset voltage VAR is supplied to the drain of the sixth switch transistor T6. The source of the sixth switch transistor T6 is connected to the anode of the light emitting element ED.

[0111] The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 to provide the reset voltage VAR to the anode of the light emitting element ED.

[0112] The gate of the driving transistor DRT is connected to the drain of the first switching transistor T1 , the drain of the driving transistor DRT is connected to the source of the second switching transistor T2 , and the source of the driving transistor DRT is connected to the source of the first switching transistor T1 .

[0113] The driving transistor DRT is turned on by the voltage difference between the source and the drain of the first switching transistor T1 to supply the driving current to the light emitting element ED.

[0114] The high potential driving voltage VDD is supplied to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor DRT. The storage capacitor Cst stores the voltage of the gate of the driving transistor DRT.

[0115] The anode of the light emitting element ED is connected to the source of the fourth switching transistor T4 and the source of the sixth switching transistor T6. The low potential driving voltage VSS is supplied to the cathode of the light emitting element ED.

[0116] The light emitting element ED emits light with predetermined brightness according to a driving current controlled by the driving transistor DRT.

[0117] At this time, the stabilization voltage Vini is supplied to stabilize the change in capacitance formed at the gate of the driving transistor DRT, and the reset voltage VAR is supplied to reset the anode of the light emitting element ED.

[0118] When the reset voltage VAR is supplied to the anode of the light emitting element ED in a state in which the fourth switching transistor T4 is turned off, the anode of the light emitting element ED may be reset.

[0119] The sixth switching transistor T6 for providing the reset voltage VAR is connected to the anode of the light emitting element ED.

[0120] In order to separately perform the driving operation of the driving transistor DRT and the resetting operation of the anode of the light emitting element ED, the third scan signal SCAN3 for driving or resetting the driving transistor DRT and the fourth scan signal SCAN4 for controlling the supply of the reset voltage VAR to the anode of the light emitting element ED are separated from each other.

[0121] When the switching transistors T5 and T6 for providing the stabilization voltage Vini and the reset voltage VAR are turned on, the fourth switching transistor T4, which connects the source of the driving transistor DRT to the anode of the light-emitting element ED, can be turned off. As a result, the driving current of the driving transistor DRT is blocked from flowing to the anode of the light-emitting element ED, so that the anode is not affected by voltages other than the reset voltage VAR.

[0122] As described above, the sub-pixel SP including the seven transistors DRT, T1, T2, T3, T4, T5, and T6 and one capacitor Cst may be referred to as a 7T1C structure.

[0123] Here, a 7T1C structure is shown as an example of various types of sub-pixel SP circuits. The structure and number of transistors and capacitors constituting the sub-pixel SP may vary. At the same time, each of the plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures.

[0124] Figure 4FIG. 1 is a schematic diagram showing a driving mode based on frequency variation in a display device according to an embodiment of the present invention.

[0125] Reference Figure 4 According to an embodiment of the present invention, the display device 100 may include: a first mode Mode1, in which moving image data is displayed at a high-speed first frequency; and a second mode Mode2, in which still image data or low-speed image data is displayed at a low-speed second frequency (or a frequency of a predetermined speed).

[0126] For example, in the first mode Mode1, moving image data may be displayed in full color at a frequency of 120 Hz corresponding to the first frequency on the display panel 110. While the display device 100 operates in the first mode Mode1, the subpixels SP of the display panel 110 display moving image data transmitted from the timing controller 140 every 120 frame periods.

[0127] As described above, the period of continuously displaying image data on the display panel 110 at a high-speed driving frequency may be referred to as a refresh frame. For example, when the driving frequency is 120 Hz, all 120 frames within 1 second in the first mode Mode1 will be refresh frames for displaying image data.

[0128] Meanwhile, when the display device 100 operates in the second mode Mode2 for displaying still image data or low-speed image data, the display device 100 may display specified image data on the display panel 110 during an initial period of the second mode Mode2, and may not display image data on the display panel 110 during the remaining periods.

[0129] For example, when entering the second mode Mode2, the display device 100 may change the driving frequency from the first frequency of 120 Hz to the second frequency of 1 Hz. In this case, the image data displayed in the last period of the first mode Mode1 may be displayed on the display panel 110 in the second mode Mode2 with the frequency changed to 1 Hz.

[0130] For example, in the second mode Mode2 driven at 1 Hz, the display device 100 may display the image data displayed in the last frame of the first mode Mode1 on the display panel 110 once, and may not display the image data during the remaining time.

[0131] In this case, the subpixel SP may display image data once in the second mode Mode2, but may maintain the voltage stored in the storage capacitor Cst for the rest of the time. As described above, the period during which the voltage stored in the storage capacitor Cst is maintained and image data is not transmitted to the display panel 110 may be referred to as frame skipping. For example, when the driving frequency is 120 Hz, the first frame of the second mode Mode2 will be a refresh frame displaying image data, and the remaining frames will be skipped frames in which image data is not transmitted.

[0132] As described above, by not transmitting image data during a specific period (frame skipping) in the second mode Mode2 driven at a low speed frequency, power consumption can be reduced.

[0133] However, during the process of switching from the first mode Mode 1 driven at a high frequency to the second mode Mode 2 driven at a low frequency, a flicker phenomenon may occur due to brightness deviation.

[0134] Figure 5 1 shows a driving timing in the second mode of driving at a low speed frequency in the display device according to the embodiment of the present invention.

[0135] Reference Figure 5 In the display device 100 according to the embodiment of the present invention, the second mode Mode2 driven at a low speed frequency may include a first period and a second period divided from one frame period based on the synchronization signal SYNC.

[0136] The first period may be a refresh frame for displaying image data, and the second period may be a skip frame for not transmitting image data.

[0137] The data voltage Vdata, the stabilization voltage Vini, and the reset voltage VAR for driving the sub-pixel SP may be provided during the refresh frame.

[0138] The refresh frame is a period for initializing the voltage charged or retained in the storage capacitor Cst and the drive transistor DRT. The refresh frame can be partially set within the start period of each frame in the low-speed second mode Mode2. The effects of the data voltage Vdata and the drive voltage stored in the subpixel SP in the high-speed first mode Mode1 can be removed in the refresh frame.

[0139] After the refresh operation is completed within the refresh frame, the light emitting element ED may emit light according to the data voltage Vdata supplied to the sub-pixel SP.

[0140] Meanwhile, a sampling process Sampling (which may be referred to as a compensation period) for compensating a characteristic value (threshold voltage or mobility) of the driving transistor DRT may be performed within the refresh frame.

[0141] For example, when the first switching transistor T1 is turned on by the first scan signal SCAN1 to electrically connect the gate and source of the driving transistor DRT, the gate and source of the driving transistor DRT have substantially equal potentials. At this point, when the second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata, a current path is formed until the voltage difference Vgs between the gate and source of the driving transistor DRT reaches the threshold voltage of the driving transistor DRT. As a result, the gate and source voltages of the driving transistor DRT are charged.

[0142] That is, when the data voltage Vdata is supplied to the drain of the driving transistor DRT, the voltages of the gate and source of the driving transistor DRT rise to the voltage difference between the data voltage and the threshold voltage, thereby compensating for the threshold voltage of the driving transistor DRT.

[0143] As described above, the process of compensating the characteristic value of the driving transistor DRT through the sampling process may correspond to internal compensation.

[0144] The frame skipping is a period for charging or setting the data voltage Vdata and the driving voltage of each frame, and the frame skipping continues until the refresh frame of the next frame starts after the refresh frame of each frame is completed.

[0145] In the skip frame, the driving transistor DRT and the light emitting element ED are driven according to the scan signal SCAN and the light emitting signal EM. That is, the initialization operation and supply of the data voltage Vdata can be performed in the refresh frame of one frame period, and the light emitting element ED can emit light in the skip frame.

[0146] In the frame skipping, the anode of the light emitting element ED is reset to the reset voltage VAR. In this case, the anode of the light emitting element ED can be reset to a predetermined voltage to improve flicker generated while the frame skipping is continued by the low-speed driving operation in the frame skipping.

[0147] Specifically, the data voltage Vdata in the skipped frame is maintained at a low logic level L. At the same time, in order to reduce the hysteresis effect that may occur in the driving transistor DRT and improve the response characteristics, a bias voltage VOBS may be provided in the skipped frame. For example, the driving transistor DRT may be in an on-bias state, in which a large current flows between the drain and source of the driving transistor DRT by providing the peak white grayscale voltage to the gate of the driving transistor DRT.

[0148] On the other hand, the driving transistor DRT may be in an off-bias state in which no current flows between the drain and source of the driving transistor DRT by supplying the peak black grayscale voltage to the gate of the driving transistor DRT.

[0149] The peak white grayscale voltage refers to the voltage supplied to the gate of the driving transistor DRT so that the light-emitting element ED emits light at the peak white grayscale, and the peak black grayscale voltage refers to the voltage supplied to the gate of the driving transistor DRT so that the light-emitting element ED emits light at the peak black grayscale. For example, when the grayscale value is expressed as an 8-bit digital value, the peak black grayscale may represent the minimum value "0" and the peak white grayscale may represent the maximum value "255".

[0150] At this time, since sweep curves of the on-bias state and the off-bias state in the P-type driving transistor DRT are different, currents flowing between the drain and the source of the driving transistor DRT may be different at the same gray level.

[0151] At this time, during grayscale expression, due to the voltage deviation between the gate and source of the driving transistor DRT, the current characteristics flowing between the drain and source of the driving transistor DRT change between the on-bias state and the off-bias state. This phenomenon is called hysteresis, which can cause afterimages.

[0152] In addition, the driving current difference flowing through the drain and source of the driving transistor DRT makes the driving characteristics of the light emitting element ED unstable, which may cause brightness deviation.

[0153] In particular, when the operation mode of the display device 100 is changed from the first mode Mode1 driven at a high-speed driving frequency to the second mode Mode2 driven at a low-speed driving frequency, afterimages due to the hysteresis phenomenon may be easily recognized.

[0154] Therefore, while the display device 100 operates in the second mode Mode2 driven at a low speed driving frequency, on-bias processing OBS1 and OBS2 for setting the driving transistor DRT to an on-bias state may be performed before the start of the light emitting period in order to minimize afterimages recognized due to a hysteresis phenomenon.

[0155] To achieve the above purpose, the driving transistor DRT may be placed in an on-bias state by supplying a bias voltage VOBS to the drain or source of the driving transistor DRT before the light emitting period begins.

[0156] For example, in the frame skipping of the second mode Mode2 driven at a low speed driving frequency, the bias voltage VOBS may be supplied to the drain of the driving transistor DRT through the data line DL before the light emitting period begins.

[0157] Alternatively, in the frame skipping of the second mode Mode2 driven at a low speed driving frequency, the bias voltage VOBS may be supplied to the source of the driving transistor DRT through a separate bias voltage supply line before the light emitting period starts.

[0158] Here, as an example, a case is shown where the bias voltage VOBS is supplied to the drain of the driving transistor DRT through the data line DL before the light emitting period starts in the frame skipping of the second mode Mode2 driven at a low speed driving frequency.

[0159] During the frame skipping, the first scan signal SCAN1 and the third scan signal SCAN3 maintain a low logic level L, and the second scan signal SCAN2 and the fourth scan signal SCAN4 maintain a high logic level H.

[0160] Therefore, the data voltage Vdata is not provided during the frame skipping. In addition, the first switching transistor T1 and the fourth switching transistor T4 remain in the off state during the frame skipping.

[0161] The second and fourth scan signals SCAN2 and SCAN4 may be supplied to odd and even gate lines with a phase difference, and may maintain a low logic level L during a portion of the skip frame and a high logic level H during the remaining period.

[0162] The second switching transistor T2 is turned on during a period when the second scan signal SCAN2 maintains a low logic level L, and the sixth switching transistor T6 is turned on during a period when the fourth scan signal SCAN4 maintains a low logic level L.

[0163] During the frame skipping, the second switching transistor T2 in the on state provides the bias voltage VOBS to the driving transistor DRT, and the sixth switching transistor T6 in the on state provides the reset voltage VAR to the anode of the light emitting element ED.

[0164] The emission signal EM maintains a high logic level H during the skip frame. The third switching transistor T3 and the fourth switching transistor T4 are turned on during a period in which the emission signal EM maintains a low logic level L.

[0165] Since the luminescence signal EM maintains a high logic level H during the frame skipping, the third and fourth switching transistors T3 and T4 are turned off, so that the current of the driving transistor DRT can be cut off while the anode of the luminescence element ED is reset.

[0166] Figure 6 A signal diagram showing brightness changes when the display device operates at a low driving frequency.

[0167] Reference Figure 6 While executing the second mode Mode2 driven at a low speed driving frequency, the data voltage Vdata and the stabilization voltage Vini are provided in a state where the third switching transistor T3 and the fourth switching transistor T4 are turned off by the light emitting signal EM of the high logic level H during the refresh frame period.

[0168] After the stabilization voltage Vini and the data voltage Vdata are supplied, when the third and fourth switching transistors T3 and T3 are turned on by the emission signal EM of the low logic level L, the brightness of the sub-pixel SP increases as the light emitting element ED starts to emit light.

[0169] During the frame skipping period after the refresh frame ends, the luminance of the subpixel SP may gradually decrease. In particular, since the frame skipping is maintained longer than the refresh frame in the second mode Mode2 driven at a low speed driving frequency, the luminance degradation of the light emitting element ED may be large.

[0170] When the image data displayed by the display device 100 changes, for example, from black image data to white image data or from moving image data to still image data, such brightness variation may occur due to a change in the characteristic value of the driving transistor DRT. Therefore, during the second mode Mode2 driven at a low driving frequency, the brightness deviation between frames increases, and a flicker phenomenon may occur.

[0171] The display device 100 of the present invention can reduce defects such as flicker and improve image quality by reducing the brightness degradation that occurs when the operating mode is changed to a low-speed driving frequency. To achieve the above object, the display device 100 of the present invention can additionally provide a bias voltage during the refresh frame period to reduce the hysteresis of the drive transistor DRT in the second mode Mode2 operating at a low driving frequency.

[0172] Figure 7 A signal diagram is shown in a case where luminance degradation is reduced by providing a bias voltage in a refresh frame in a display device according to an embodiment of the present invention.

[0173] Reference Figure 7 According to an embodiment of the present invention, the display device 100 can perform a turn-on bias process OBS1 of pre-supplying a bias voltage in a refresh frame to reduce a flicker phenomenon caused by a brightness deviation between a refresh frame and a skipped frame in a second mode Mode2 driven at a low speed driving frequency.

[0174] The second mode Mode2 driven at a low-speed driving frequency may include a refresh frame for displaying image data and a skip frame for not transmitting image data.

[0175] In a refresh frame providing the data voltage Vdata, the stabilization voltage Vini, and the reset voltage VAR for driving the subpixel SP, an on-bias process OBS1 for providing the bias voltage VOBS may be additionally performed to set the driving transistor DRT to an on-bias state before the light emitting period begins.

[0176] Meanwhile, a sampling process Sampling for compensating a characteristic value (threshold voltage or mobility) of the driving transistor DRT may be performed within the refresh frame.

[0177] When the sampling process Sampling is performed, the on-bias process OBS1 may be performed in a period between the sampling process Sampling and the light emission period.

[0178] At this time, the on-bias process OBS1 within the refresh frame can be performed with the second switch transistor T2 turned on, and the remaining switch transistors, namely the first switch transistor T1, the third switch transistor T3, the third switch transistor T4, the fifth switch transistor T5 and the sixth switch transistor T6 are all turned off.

[0179] Therefore, during the on-bias process OBS1 in the refresh frame, the bias voltage VOBS may be supplied to the drain of the driving transistor DRT. At this time, when the driving transistor DRT is turned on by the voltage charged in the storage capacitor Cst, the bias voltage VOBS may be supplied to both the drain and source of the driving transistor DRT.

[0180] As a result, in the refresh frame of the second mode Mode2 driven at a low speed driving frequency, the hysteresis of the driving transistor DRT and the luminance deviation of the light emitting element ED can be reduced.

[0181] Figure 8 A signal diagram is shown in a case where luminance degradation is reduced by providing a bias voltage in a frame skip in a display device according to an embodiment of the present invention.

[0182] Reference Figure 8 , the display device 100 according to an embodiment of the present invention may provide a bias voltage VOBS to the drain or source of the driving transistor DRT one or more times to reduce the hysteresis of the driving transistor DRT in a skip frame in which image data is not transmitted to the display panel 110, and the voltage charged in the storage capacitor Cst is maintained after the refresh frame ends.

[0183] Here, the case where two on-bias processes OBS1 and OBS2 are performed in the frame skipping is exemplified. Figure 5 The operations shown are the same and further description will be omitted.

[0184] Figure 9 A diagram showing a case where a luminance deviation in a frame skip is improved by performing a turn-on bias process in a refresh frame in a display device according to an embodiment of the present invention.

[0185] Reference Figure 9 , the display device 100 according to the embodiment of the present invention can change the operation mode from the first mode Mode1 driven at a high-speed driving frequency to the second mode Mode2 driven at a low-speed driving frequency according to the type of input image data.

[0186] For example, the first mode Mode 1 may be driven at a frequency of 120 Hz, and the second mode Mode 2 may be driven at a frequency of 1 Hz.

[0187] While the display device 100 is operating in the second mode Mode2 driven at a low speed driving frequency, the data voltage Vdata and the stabilization voltage Vini are supplied in a state where the third switching transistor T3 and the fourth switching transistor T4 are turned off by the emission signal EM of a high logic level H during a refresh frame period. Therefore, the brightness of the sub-pixel SP can be instantaneously reduced.

[0188] On the other hand, when the sampling process Sampling for compensating the characteristic value of the driving transistor DRT is performed in the refresh frame, the voltage of the gate and source of the driving transistor DRT may increase to the voltage difference between the data voltage Vdata and the threshold voltage. As a result, an offset phenomenon may occur in which the operating area of ​​the driving transistor DRT moves.

[0189] Therefore, in the refresh frame of the second mode Mode2 driven at a low speed driving frequency, the bias voltage VOBS can be supplied to the drain or source of the driving transistor DRT before the start of the light emitting period and after the sampling process Sampling for compensating the characteristic value of the driving transistor DRT is terminated. As a result, the luminance degradation of the light emitting element ED can be reduced.

[0190] Meanwhile, during the frame skipping period after the refresh frame is terminated, the luminance of the sub-pixel SP may gradually decrease. In particular, since the frame skipping is maintained longer than the refresh frame in the second mode Mode2 driven at a low speed driving frequency, the luminance degradation of the light-emitting element ED may be large.

[0191] However, since the on-bias processes OBS1 and OBS2 of supplying the bias voltage VOBS to the drain or source of the driving transistor DRT can be performed within the skip frame, the luminance degradation of the light emitting element can be reduced.

[0192] At this time, the bias voltage VOBS supplied to the drain or source of the driving transistor DRT in the skip frame may have the same level as the bias voltage VOBS supplied to the drain of the driving transistor DRT in the refresh frame. Alternatively, they may have different levels.

[0193] As a result, the hysteresis of the driving transistor DRT is reduced during the frame skipping and refresh frames of the second mode Mode2 driven at a low drive frequency, and the luminance degradation of the light-emitting element ED can be reduced while undergoing the refresh frame and the frame skipping. Therefore, quality defects such as flicker that occur in the second mode Mode2 driven at a low drive frequency can be reduced.

[0194] At the same time, the display device 100 according to an embodiment of the present invention can further reduce the brightness degradation in the second mode Mode2 by providing a bias voltage VOBS in the refresh frame of the second mode Mode2 driven at a low-speed driving frequency, and at the same time, by controlling the level of the bias voltage VOBS, the stabilization voltage Vini or the reset voltage VAR provided in the skip frame.

[0195] Figures 10 to 12 FIG. 4 shows changes in current flowing through a light-emitting element according to levels of a bias voltage, a stabilization voltage, and a reset voltage in a display device according to an embodiment of the present invention.

[0196] Reference Figures 10 to 12 In the display device 100 according to the embodiment of the present invention, the current level flowing through the light emitting element ED may be different in the light emitting period based on the levels of the bias voltages VOBS1 to VOBS3, the stabilization voltages Vini1 to Vini3, and the reset voltages VAR1 to VAR3.

[0197] Therefore, by detecting the brightness deviation between the first mode Mode1 and the second mode Mode2, and by controlling the levels of the bias voltage VOBS, the stabilization voltage Vini and the reset voltage VAR provided in the first mode Mode1 or the second mode Mode2, the brightness deviation between the first mode Mode1 driven at a high-speed driving frequency and the second mode Mode2 driven at a low-speed driving frequency can be reduced.

[0198] In this case, the level of the bias voltage VOBS may be determined by reflecting the luminance degradation of the light emitting element ED according to the frequency variation.

[0199] Meanwhile, the stabilization voltage Vini may be determined according to a level or grayscale of a data voltage Vdata supplied through the data line DL in a refresh frame of the first mode Mode1 or the second mode Mde2.

[0200] In addition, the reset voltage VAR may be determined according to the level of the low potential driving voltage VSS of the sub-pixel SP in the refresh frame of the first mode Mode1 or the second mode Mde2.

[0201] In addition, the display device 100 according to the embodiment of the present invention can be applied to various structures of the sub-pixel SP.

[0202] Figure 13 Another sub-pixel circuit diagram in a display device according to an embodiment of the present invention is shown.

[0203] Reference Figure 13 , the sub-pixel SP of the display device 100 according to the embodiment of the present invention includes first to seventh switching transistors T1 - T7 , a driving transistor DRT, a storage capacitor Cst, and a light emitting element ED.

[0204] Here, the light-emitting element ED may be, for example, a self-luminous element capable of emitting light by itself, such as an organic light-emitting diode OLED.

[0205] In the subpixel SP according to the embodiment of the present invention, the second to fourth switching transistors T2 - T4 , the sixth switching transistor T6 , the seventh switching transistor T7 and the driving transistor DRT may be P-type transistors. In addition, the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

[0206] P-type transistors are relatively more reliable than N-type transistors. P-type transistors have the advantage that, because their drains are fixed to a high-potential drive voltage VDD, the current flowing through the light-emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, current can be stably supplied.

[0207] For example, a P-type transistor may be connected to the anode of the light-emitting element ED. In this case, when the transistors T4 and T6 connected to the light-emitting element ED operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the light-emitting element ED. Therefore, reliability is relatively high.

[0208] In this sub-pixel SP structure, the N-type transistors T1 and T5 may include oxide transistors formed using semiconductor oxides (for example, transistors having channels formed of semiconductor oxides such as indium, gallium, zinc oxide, or IGZO), and the other P-type transistors DRT, T2-T4, T6, and T7 may include silicon transistors formed of semiconductors such as silicon (for example, transistors having polysilicon channels formed by a low-temperature process such as LTPS or low-temperature polysilicon).

[0209] Oxide transistors have relatively lower leakage current than silicon transistors. Therefore, when implemented using oxide transistors, leakage current from the gate of the drive transistor DRT is reduced, which has the effect of reducing image quality defects such as flicker.

[0210] Meanwhile, the remaining P-type transistors DRT, T2 - T4 , T6 , and T7 excluding the first and fifth switching transistors T1 and T5 corresponding to N-type transistors may be formed of low-temperature polysilicon.

[0211] The first scan signal SCAN1 is provided to the gate of the first switch transistor T1. The drain of the first switch transistor T1 is connected to the gate of the drive transistor DRT. The source of the first switch transistor T1 is connected to the source of the drive transistor DRT.

[0212] The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT using the high potential driving voltage VDD stored in the storage capacitor Cst.

[0213] The first switch transistor T1 may be formed by an N-type MOS transistor to constitute an oxide transistor. Since the N-type MOS transistor uses electrons as carriers, it has higher mobility and faster switching speed than the P-type MOS transistor.

[0214] The second scan signal SCAN2 is provided to the gate of the second switching transistor T2. The data voltage Vdata is provided to the drain of the second switching transistor T2. The source of the second switching transistor T2 is connected to the drain of the driving transistor DRT.

[0215] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide the data voltage Vdata to the drain of the driving transistor DRT.

[0216] The light emitting signal EM is supplied to the gate of the third switch transistor T3, the high potential driving voltage VDD is supplied to the drain of the third switch transistor T3, and the source of the third switch transistor T3 is connected to the drain of the driving transistor DRT.

[0217] The third switch transistor T3 is turned on by the light emitting signal EM to provide the high potential driving voltage VDD to the drain of the driving transistor DRT.

[0218] The emission signal EM is provided to the gate of the fourth switch transistor T4. The drain of the fourth switch transistor T4 is connected to the source of the drive transistor DRT. The source of the fourth switch transistor T4 is connected to the anode of the light emitting element ED.

[0219] The fourth switching transistor T4 is turned on by the light emitting signal EM to provide a driving current to the anode of the light emitting element ED.

[0220] The third scan signal SCAN3 is provided to the gate of the fifth switching transistor T5.

[0221] Here, the third scan signal SCAN3 may be the first scan signal SCAN1 provided to the sub-pixel SP located at another position. For example, when the first scan signal SCAN1 is provided to the n-th gate line, the third scan signal SCAN3 may be the first scan signal SCAN1[n-9] provided to the (n-9)-th gate line. That is, depending on the driving phase of the display panel 110, the third scan signal SCAN3 may function as the first scan signal SCAN1 at another gate line GL.

[0222] The stabilized voltage Vini is supplied to the drain of the fifth switch transistor T5. The source of the fifth switch transistor T5 is connected to the gate of the drive transistor DRT and the storage capacitor Cst.

[0223] The fifth switch transistor T5 is turned on by the third scan signal SCAN3 to provide the stabilized voltage Vini to the gate of the driving transistor DRT.

[0224] The fourth scan signal SCAN4 is provided to the gate of the sixth switching transistor T6.

[0225] The reset voltage VAR is supplied to the drain of the sixth switch transistor T6. The source of the sixth switch transistor T6 is connected to the anode of the light emitting element ED.

[0226] The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 to provide the reset voltage VAR to the anode of the light emitting element ED.

[0227] The fifth scan signal SCAN5 is provided to the gate of the seventh switching transistor T7.

[0228] The bias voltage VOBS is provided to the drain of the seventh switch transistor T7. The source of the seventh switch transistor T7 is connected to the drain of the driving transistor DRT.

[0229] Here, the fifth scan signal SCAN5 may be the fourth scan signal SCAN4 having a different phase provided to a sub-pixel SP located at another position. For example, when the fourth scan signal SCAN4 is provided to the n-th gate line, the fifth scan signal SCAN5 may be the fourth scan signal SCAN4[n-1] provided to the (n-1)-th gate line. That is, depending on the driving phase of the display panel 110, the fifth scan signal SCAN5 may function as the fourth scan signal SCAN4 at another gate line GL.

[0230] Meanwhile, since the fifth scan signal SCAN5 is a signal for providing the bias voltage VOBS to the driving transistor DRT, it may be different from the second scan signal SCAN2 for providing the data voltage Vdata.

[0231] The gate of the driving transistor DRT is connected to the drain of the first switching transistor T1 , the drain of the driving transistor DRT is connected to the source of the second switching transistor T2 , and the source of the driving transistor DRT is connected to the source of the first switching transistor T1 .

[0232] The driving transistor DRT is turned on by the voltage difference between the source and the drain of the first switching transistor T1 to supply the driving current to the light emitting element ED.

[0233] The high potential driving voltage VDD is supplied to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor DRT. The storage capacitor Cst stores the voltage of the gate of the driving transistor DRT.

[0234] The anode of the light emitting element ED is connected to the source of the fourth switching transistor T4 and the source of the sixth switching transistor T6. The low potential driving voltage VSS is supplied to the cathode of the light emitting element ED.

[0235] The light emitting element ED emits light with predetermined brightness according to a driving current controlled by the driving transistor DRT.

[0236] At this time, the stabilization voltage Vini is supplied to stabilize the change in capacitance formed at the gate of the driving transistor DRT, and the reset voltage VAR is supplied to reset the anode of the light emitting element ED.

[0237] When the reset voltage VAR is supplied to the anode of the light emitting element ED in a state in which the fourth switching transistor T4 is turned off, the anode of the light emitting element ED may be reset.

[0238] The sixth switching transistor T6 for providing the reset voltage VAR is connected to the anode of the light emitting element ED.

[0239] In order to separately perform the driving operation of the driving transistor DRT and the resetting operation of the anode of the light emitting element ED, the third scan signal SCAN3 for driving or stabilizing the driving transistor DRT and the fourth scan signal SCAN4 for controlling the supply of the reset voltage VAR to the anode of the light emitting element ED are separated from each other.

[0240] When the switching transistors T5 and T6 for providing the stabilization voltage Vini and the reset voltage VAR are turned on, the fourth switching transistor T4, which connects the source of the driving transistor DRT to the anode of the light-emitting element ED, can be turned off. As a result, the driving current of the driving transistor DRT is blocked from flowing to the anode of the light-emitting element ED, so that the anode is not affected by voltages other than the reset voltage VAR.

[0241] As described above, the sub-pixel SP including the eight transistors DRT, T1, T2, T3, T4, T5, T6, and T7 and one capacitor Cst may be referred to as an 8T1C structure.

[0242] As previously described, an 8T1C structure is shown as an example of various types of sub-pixel SP circuits. The structure and number of transistors and capacitors constituting the sub-pixel SP may vary. At the same time, each of the plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures.

[0243] As described above, the display device 100 according to the embodiment of the present invention can reduce hysteresis and brightness degradation of the light emitting element ED by supplying the bias voltage VOBS to the drain or source of the driving transistor DRT in the refresh frame of the second mode Mode2 driven at a low speed driving frequency.

[0244] In addition, by controlling the level of the bias voltage VOBS, the stabilization voltage Vini, or the reset voltage VAR provided in the frame skipping of the second mode Mode2 driven at a low speed driving frequency, the brightness deviation occurring in the second mode Mode2 can be further reduced.

[0245] The above description and the accompanying drawings provide examples of the technical concepts of the present invention for the purpose of illustration only. Those skilled in the art of the present invention will recognize that various modifications and changes in form, such as combinations, separations, substitutions, and changes in structure, are possible without departing from the essential features of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate the scope of the technical concepts of the present invention, and the scope of the present invention is not limited to these embodiments. The scope of the present invention should be interpreted based on the appended claims as all technical concepts included in the scope equivalent to the claims belong to the present invention.

Claims

1. A display device comprising: a display panel including a light emitting element, a driving transistor for supplying a driving current to the light emitting element, and a plurality of switching transistors for controlling an operation of the driving transistor; a gate driving circuit for providing a plurality of scanning signals to the display panel; a data driving circuit for providing a plurality of data voltages to the display panel; as well as a timing controller for controlling the gate driving circuit and the data driving circuit, The bias voltage is supplied to the driving transistor in a first period when the data voltage is supplied to the display panel in a low-speed mode, wherein the display panel is driven at a frequency of a predetermined speed in the low-speed mode.

2. The display device according to claim 1 , wherein the plurality of switching transistors comprises: a first switching transistor, wherein a first scanning signal is supplied to a first gate of the first switching transistor, a first drain of the first switching transistor is connected to the gate of the driving transistor, and a first source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein a second scan signal is supplied to a second gate of the second switching transistor, a data voltage or the bias voltage is supplied to a second drain of the second switching transistor, and a second source of the second switching transistor is connected to the drain of the driving transistor; a third switching transistor, wherein a light emitting signal is supplied to a third gate of the third switching transistor, a high potential driving voltage is supplied to a third drain of the third switching transistor, and a third source of the third switching transistor is connected to the drain of the driving transistor; a fourth switching transistor, wherein the light emitting signal is provided to a fourth gate of the fourth switching transistor, a fourth drain of the fourth switching transistor is connected to the source of the driving transistor, and a fourth source of the fourth switching transistor is connected to the anode of the light emitting element; a fifth switching transistor, wherein the third scan signal is supplied to a fifth gate of the fifth switching transistor, a stabilization voltage is supplied to a fifth drain of the fifth switching transistor, and a fifth source of the fifth switching transistor is connected to the gate of the driving transistor and a storage capacitor; as well as a sixth switching transistor, wherein the fourth scan signal is supplied to a sixth gate of the sixth switching transistor, a reset voltage is supplied to a sixth drain of the sixth switching transistor, and a sixth source of the sixth switching transistor is connected to the anode of the light emitting element.

3. The display device according to claim 1 , wherein the plurality of switching transistors comprises: a first switching transistor, wherein a first scanning signal is supplied to a first gate of the first switching transistor, a first drain of the first switching transistor is connected to the gate of the driving transistor, and a first source of the first switching transistor is connected to the source of the driving transistor; a second switching transistor, wherein a second scan signal is supplied to a second gate of the second switching transistor, a data voltage is supplied to a second drain of the second switching transistor, and a second source of the second switching transistor is connected to the drain of the driving transistor; a third switching transistor, wherein a light emitting signal is supplied to a third gate of the third switching transistor, a high potential driving voltage is supplied to a third drain of the third switching transistor, and a third source of the third switching transistor is connected to the drain of the driving transistor; a fourth switching transistor, wherein the light emitting signal is provided to a fourth gate of the fourth switching transistor, a fourth drain of the fourth switching transistor is connected to the source of the driving transistor, and a fourth source of the fourth switching transistor is connected to the anode of the light emitting element; a fifth switching transistor, wherein the third scan signal is supplied to a fifth gate of the fifth switching transistor, a stabilization voltage is supplied to a fifth drain of the fifth switching transistor, and a fifth source of the fifth switching transistor is connected to the gate of the driving transistor and a storage capacitor; a sixth switching transistor, wherein the fourth scan signal is supplied to a sixth gate of the sixth switching transistor, a reset voltage is supplied to a sixth drain of the sixth switching transistor, and a sixth source of the sixth switching transistor is connected to the anode of the light emitting element; as well as a seventh switching transistor, wherein the fifth scan signal is supplied to a seventh gate of the seventh switching transistor, the bias voltage is supplied to a seventh drain of the seventh switching transistor, and a seventh source of the seventh switching transistor is connected to the drain of the driving transistor. 4 . The display device according to claim 1 , wherein the bias voltage is supplied between a compensation period for compensating a characteristic value of the driving transistor in the first period and a light emission period of the light emitting element. 5 . The display device according to claim 1 , wherein the bias voltage or another bias voltage is supplied to the driving transistor in a second period after the first period in the low speed mode during which the data voltage is not supplied to the display panel. 6 . The display device according to claim 5 , wherein the bias voltage supplied in the first period and the bias voltage supplied in the second period have different levels. 7 . The display device according to claim 2 , wherein a level of the stabilization voltage or the reset voltage is controlled in a second period after the first period in the low speed mode in which the data voltage is not supplied to the display panel. 8 . The display device of claim 7 , wherein the stabilization voltage is determined according to a level or a grayscale of a data voltage supplied to the display panel in the first period. 9 . The display device according to claim 7 , wherein the reset voltage is determined according to a level of a low-potential driving voltage supplied to a cathode of the light emitting element in the first period.

10. The display device according to claim 2 or 3, wherein the high potential driving voltage is supplied to one end of the storage capacitor, and the other end of the storage capacitor is connected to the gate electrode of the driving crystal.

11. The display device according to claim 2 , wherein each of the first switching transistor and the fifth switching transistor comprises an oxide transistor, Each of the driving transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the sixth switching transistor comprises a silicon transistor.

12. The display device according to claim 3, wherein each of the first switching transistor and the fifth switching transistor comprises an oxide transistor, and each of the driving transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the sixth switching transistor, and the seventh switching transistor comprises a silicon transistor.

13. The display device according to claim 2 or 3, wherein the third scan signal and the fourth scan signal are separated from each other. 14 . The display device according to claim 1 , wherein the level of the bias voltage is determined by reflecting luminance degradation of the light emitting element according to a change in a driving frequency of the display panel.

15. A display driving method for driving a display panel, the display panel comprising a light-emitting element, a driving transistor for providing a driving current to the light-emitting element, and a plurality of switching transistors for controlling an operation of the driving transistor, the method comprising: Switching from a first mode driven at a high-speed driving frequency to a second mode driven at a low-speed driving frequency; providing a first bias voltage to the driving transistor in a first period, wherein in the first period, a data voltage is provided to the display panel in the second mode; as well as A second bias voltage is supplied to the driving transistor in a second period after the first period, wherein the data voltage is not supplied to the display panel in the second period.

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