A functional verification device and system compatible with RAM read and write logic and ECC logic

Abstract

The present invention proposes a functional verification device that is compatible with RAM read-write logic and ECC logic, wherein the address generation module generates a full address, a first read-write enable signal, and data to be read and written; when the functional verification type of the RAM to be tested is read-write logic functional verification, the read-write logic conversion module performs full-address reading and writing on the RAM to be tested when the first read-write enable signal and the second read-write enable signal are both read enable signals or write enable signals; when the functional verification type of the RAM to be tested is ECC logic functional verification, the ECC error correction verification module performs ECC logic functional verification by random error injection; when the functional verification type of the RAM to be tested is read-write logic functional verification, the data comparison module performs read-write logic functional verification. The present invention also proposes a functional verification system that is compatible with RAM read-write logic and ECC logic, which effectively improves the efficiency of RAM memory functional verification.

Description

Technical Field

[0001] The present invention relates to the field of RAM function verification, and in particular to a function verification device and system compatible with RAM read-write logic and ECC logic. Background Art

[0002] In the era of big data, information is being transmitted and processed all the time. As a temporary data storage device within the system, RAM (Random Access Memory) has a fast read and write speed. However, how to improve data reliability is a key concern in the industry.

[0003] As industry demands evolve, the control logic integrated into chips becomes increasingly complex. Logic verification platforms, used to simulate logically implementable functions within chips, face significant challenges in rapidly implementing such a vast array of functionality. Logic verification platforms typically deliver stimuli to the logically implementable functions under test based on the stimulus requirements of the functions. They then receive the results of the logical processing and verify the correctness of the received data to verify the correctness of the logical processing. Furthermore, in industrial computers, aerospace electronics, and database center applications, equipment is required to maintain normal operation under harsh conditions such as all-weather, high loads, and complex electromagnetic environments.

[0004] In order to ensure data reliability, in the prior art, a data error correction module is generally built into the RAM controller. If there are no problems with the operation timing and circuit stability, a RAM error will generally not cause an error in the entire Bank (memory bank) or Page (page), but rather an error in one or several bits in the entire Page. The built-in data error correction module mainly uses a dedicated verification method ECC (Error Correcting Code) to correct single-bit errors and detect double-bit errors to ensure system operation; however, the data error correction module in the prior art can only implement ECC logic function verification, and cannot achieve compatibility between the RAM memory read and write logic and the ECC logic functional verification, which is not conducive to improving the efficiency of RAM memory functional verification. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, the present invention innovatively proposes a functional verification device and system that is compatible with RAM read and write logic and ECC logic, which effectively solves the problem of incompatibility between the functional verification of RAM memory read and write logic and ECC logic caused by the prior art, and effectively improves the efficiency of RAM memory functional verification.

[0006] The first aspect of the present invention provides a functional verification device compatible with RAM read-write logic and ECC logic, which is connected to the RAM in communication, including: an address generation module, a read-write logic conversion module, an ECC error correction verification module, and a data comparison module. The address generation module is used to generate all read or write addresses according to the number of bits of the RAM address to be tested, and generate a first read-write enable signal and data to be read and written for reading and writing the RAM to be tested according to the functional verification type of the RAM to be tested; the read-write logic conversion module is used to judge whether all the combined logic signals after the arrangement and combination of multiple read-write logic control signals are the second read-write enable signal respectively when the functional verification type of the RAM to be tested is the read-write logic function verification. If the combined logic signal is the second read-write enable signal , outputs a second read-write enable signal for reading and writing the RAM to be tested, and when the first read-write enable signal and the second read-write enable signal are both read enable signals or write enable signals, performs full-address reading and writing on the RAM to be tested; when the function verification type of the RAM to be tested is ECC logic function verification, the ECC error correction verification module reads and writes the RAM to be tested according to all the read or write addresses generated by the address generation module and the first read-write enable signal, and performs ECC logic function verification by random error injection; the data comparison module is used to judge the data for full-address reading and writing of the RAM to be tested and compare it with the data to be read and written sent by the address generation module when the function verification type of the RAM to be tested is read-write logic function verification, and perform read-write logic function verification.

[0007] Optionally, the address generation module is further configured to receive a user function verification request signal sent by a user via a communication bus, and determine a function verification type of the RAM to be tested according to the user function verification request signal.

[0008] Furthermore, determining the functional verification type of the RAM to be tested according to the user functional verification request signal is specifically: determining the functional verification type of the RAM to be tested according to the user functional verification request signal and a functional verification type database, wherein the functional verification type database stores the corresponding relationship between the user functional verification request signal and the functional verification type of the RAM to be tested.

[0009] Optionally, the read-write logic conversion module is further configured to, if the combinational logic signal is not the second read-write enable signal, perform judgment on the next combinational logic signal until all combinational logic signals are judged.

[0010] Optionally, the data to be read or written at each address generated by the address generation module corresponds to the same data at each address to be read or written.

[0011] Optionally, the ECC error correction verification module includes a data flip submodule, a random address generator, an ECC error correction function component, and a state controller. The ECC error correction function component is used to perform a full-address write operation on the RAM to be tested according to all the read or write addresses generated by the address generation module and the first read and write enable signal when the ECC error correction function is first enabled. After confirming that all addresses have data, when the ECC error correction function is enabled again, a full-address read operation is performed on the RAM to be tested. When it is detected that the data of the randomly generated error-noted address in the RAM to be tested is wrong and the write enable is valid, the error-corrected data is written back to the original randomly generated error-noted address. During the output process, the original randomly generated error-noted address is detected again. whether the data has been repaired; when the ECC error correction function is turned off, the random address generator obtains the number of input error-note addresses, and randomly generates a corresponding number of error-note addresses according to the number of input error-note addresses; the data flip submodule is used to flip the data in the randomly generated error-note addresses and write them into the randomly generated error-note addresses again; the state controller is used to pull down the ECC data completion signal and trigger the write enable to be valid when the ECC error correction function component detects that the data of the randomly generated error-note addresses in the RAM to be tested are wrong; when the ECC error correction function component detects that the data of the original randomly generated error-note addresses in the RAM to be tested have been repaired, pull up the ECC data completion signal and trigger the write enable to be invalid.

[0012] Furthermore, the ECC error correction verification module also includes an encoder and a decoder. The encoder is used to encode the data to be written generated by the address generation module and write it into the RAM to be tested; the decoder is used to decode the data to be read in the RAM to be tested and output the data to be read.

[0013] Optionally, the number of the input error-injected addresses obtained in the random address generator is 1 bit, 2 bits, or 3 bits.

[0014] Optionally, a clock reset module is further included, and the clock reset module is used to reset the clock of the functional verification device compatible with the RAM read and write logic and the ECC logic.

[0015] The second aspect of the present invention provides a functional verification system that is compatible with RAM read-write logic and ECC logic, including a functional verification device that is compatible with RAM read-write logic and ECC logic as described in the first aspect of the present invention, RAM, and an AXI bus. The functional verification device that is compatible with RAM read-write logic and ECC logic obtains a user functional verification request through the AXI bus, determines the functional verification type of the RAM to be tested according to the user functional verification request signal, and performs functional verification of the RAM read-write logic and ECC logic on the RAM to be tested according to the determined functional verification type of the RAM to be tested.

[0016] The technical solution adopted by the present invention includes the following technical effects:

[0017] 1. In the technical solution of the present invention, the address generation module is used to generate all read or write addresses, and generates a first read / write enable signal and data to be read / written for reading and writing the RAM to be tested according to the functional verification type of the RAM to be tested; the read / write logic conversion module is used to perform read / write logic function verification when the functional verification type of the RAM to be tested is read / write logic function verification; the ECC (Error Correcting Code) error correction verification module performs ECC logic function verification by random error injection when the functional verification type of the RAM to be tested is ECC logic function verification; the data comparison module is used to judge the data for full address reading and writing of the RAM to be tested and compare it with the data to be read / written sent by the address generation module when the functional verification type of the RAM to be tested is read / write logic function verification, and perform read / write logic function verification, thereby effectively solving the problem of incompatibility between the functional verification of the RAM memory read / write logic and the ECC logic caused by the prior art, and effectively improving the efficiency of the RAM memory functional verification.

[0018] 2. The address generation module in the technical solution of the present invention performs functional control by utilizing the User signal (user function verification request signal) of the AXI (Advanced eXtensible Interface) bus, and determines the function verification type of the RAM to be tested according to the user function verification request signal. This not only does not affect the normal communication bandwidth, but also can flexibly adjust the function verification type of the RAM to be tested according to user requests.

[0019] 3. In the technical solution of the present invention, the read-write logic conversion module judges whether all the combination logic signals after the arrangement and combination of multiple read-write logic control signals are the second read-write enable signal respectively. If the combination logic signal is the second read-write enable signal, the second read-write enable signal for reading and writing the RAM to be tested is output. If the combination logic signal is not the second read-write enable signal, the next combination logic signal is judged until all the combination logic signals are judged. By adding the integrity test of the read-write logic, the read-write failure caused by the abnormal combination of the read-write logic control signal is avoided, and the comprehensiveness of the RAM read-write logic function verification is improved.

[0020] 4. In the technical solution of the present invention, the data to be read and written at each address generated by the address generation module corresponds to the same address data to be read and written, which makes the data comparison module more convenient and improves the efficiency of the read and write logic function verification.

[0021] 5. The technical solution of the present invention not only adds the test of RAM full address, but also can simulate random RAM bit flipping according to the random address generator and the horizontal flip submodule during the ECC logic function verification. It has the characteristics of strong randomness and easy operation, thereby improving the reliability of ECC logic function verification.

[0022] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 This is a schematic structural diagram of a device in Example 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of verification of the read-write logic function in the device of Example 1 of the solution of the present invention;

[0026] Figure 3 Schematic diagram of ECC logic function verification in the device of Example 1 of the solution of the present invention;

[0027] Figure 4 Schematic diagram of the internal communication of the ECC error correction and verification module in the device of Example 1 of the solution of the present invention;

[0028] Figure 5 This is a schematic diagram of the structure of the system of Example 2 in the solution of the present invention. DETAILED DESCRIPTION

[0029] In order to clearly illustrate the technical features of this solution, the present invention is described in detail below through specific implementation methods and in conjunction with the accompanying drawings. The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. In addition, the present invention may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed. It should be noted that the components illustrated in the accompanying drawings are not necessarily drawn to scale. The present invention omits descriptions of well-known components and processing technologies and processes to avoid unnecessary limitations on the present invention.

[0030] Example 1

[0031] like Figure 1-Figure 3As shown, the present invention provides a functional verification device compatible with RAM read-write logic and ECC logic, which is connected to the RAM in communication, including: an address generation module, a read-write logic conversion module, an ECC error correction verification module, and a data comparison module. The address generation module is used to generate all read or write addresses according to the number of bits of the RAM address to be tested, and generate a first read-write enable signal and data to be read and written for reading and writing the RAM to be tested according to the functional verification type of the RAM to be tested; the read-write logic conversion module is used to judge whether all the combination logic signals after the arrangement and combination of multiple read-write logic control signals are the second read-write enable signal respectively when the functional verification type of the RAM to be tested is the read-write logic function verification; if the combination logic signal is the second read-write enable signal, the output Output a second read-write enable signal for reading and writing the RAM to be tested, and when the first read-write enable signal and the second read-write enable signal are both read enable signals or write enable signals, perform full-address reading and writing on the RAM to be tested; when the function verification type of the RAM to be tested is ECC logic function verification, the ECC error correction verification module reads and writes the RAM to be tested according to all the read or write addresses generated by the address generation module and the first read-write enable signal, and performs ECC logic function verification by random error injection; the data comparison module is used to judge when the function verification type of the RAM to be tested is read-write logic function verification, compare the data for full-address reading and writing of the RAM to be tested with the data to be read and written sent by the address generation module, and perform read-write logic function verification.

[0032] The address generation module may also be configured to receive a user function verification request signal (user signal or ram check) sent by the user via the communication bus (AXI bus), and determine the function verification type of the RAM to be tested according to the user function verification request signal.

[0033] Specifically, determining the functional verification type of the RAM to be tested according to the user functional verification request signal is: determining the functional verification type of the RAM to be tested according to the user functional verification request signal and a functional verification type database, wherein the functional verification type database stores the corresponding relationship between the user functional verification request signal and the functional verification type of the RAM to be tested.

[0034] For example, as shown in Table 1 below

[0035]

[0036]

[0037] Specifically, the address generation module is mainly used to: after receiving the request for logic check from the AXI bus (RAM check), according to the test RAM address bit number n, it is known that the maximum address of the RAM is 2 n-1; Generate all read or write addresses according to the number of address bits of the RAM to be tested, and generate the first read / write enable signal for reading and writing the RAM to be tested and the data to be read / written according to the functional verification type of the RAM to be tested (i.e., the user functional verification request signal, ramcheck). When the chip select signal is enabled, after entering a read / write logic state, determine whether the first read / write enable signal is valid. When the first read / write enable signal is valid for write enable, determine whether the current address is the maximum address value. If it is not the maximum address value, the address is accumulated from 0 until it stops when the address is equal to the maximum address value; when the first read / write enable signal is valid for read enable, determine whether the current address is 0. If it is not equal to 0, the address is accumulated from the maximum address value until it stops when the address is 0.

[0038] Among them, the read-write logic conversion module can calculate the maximum number of signal permutations and combinations based on the number x of read-write logic control signals (control signals used to control reading or writing). x . When the chip select signal is valid, the read-write logic control signal is set to all 0 as the initial state S_idle. The next step is to judge whether the multiple combination logic signals after the arrangement and combination of the multiple read-write logic control signals are valid. When the combination logic signal is valid (the second read-write enable signal), the second read-write enable signal for reading and writing the RAM to be tested is output, and when the first read-write enable signal and the second read-write enable signal are both read enable signals or write enable signals, the RAM to be tested is read and written at all addresses; if the combination logic signal is invalid (not the second read-write enable signal), data is recorded, and the current combination logic signal is recorded and marked as an invalid combination logic signal. After the marking is completed, jump to the next combination logic signal judgment until all combination logic signals have jumped. The integrity test of the read-write logic function verification is completed, and the test results of all combination logic signals are displayed.

[0039] The data comparison module: When the permuted and combined combination logic signal is valid (the second read / write enable signal), it performs continuous read and write operations from low to high according to the full address generated by the address generation module. For example, with a data width of 32 bits and an address width of 4 bits, the address range is 0x0–0xF. To facilitate data comparison, the corresponding "Write_data" for each address generated by the address generation module is set to the same as the address data to be read or written. That is, the corresponding "Write_data" for address 0x0 is also set to 0x0, and the data corresponding to address 0xF is incremented as the address increases. When reading data, the address is read from high to low. If the read address and the address data are inconsistent, it indicates a data anomaly. After counting 10 abnormal data points, the error data is recorded and the current read / write enable logic is marked. After marking, the module jumps to the next logical combination state. This process continues until all states have been transitioned. At this point, the logic integrity test is completed and the test results for all states are displayed.

[0040] Read / write logic verification typically involves performing certain logical operations on one or more read / write logic control signals, using the results as enable signals for the RAM read / write ports. These control signals are typically controlled by other modules in the digital circuit, such as DMA (direct memory access) and data cache units. When multiple modules need to access RAM, the logic access timing signals, read / write data, and addresses are transmitted to the RAM. Data detection components perform data comparison and verification. When confirming a logical access, the access logic is judged to be normal based on the access address and data.

[0041] Specifically, the user sends a request for a read / write test via the user function verification request signal ram check of the AXI bus; ram check[2:0] is identified according to the data in Table 1, and when ram check[2:0]=001 is detected, a read / write test is performed on the RAM to be tested;

[0042] When the first read / write enable signal sent by the address generation module is a write enable signal, the address is accumulated from 0 to the maximum address in the full address, and the full address and the data to be written at the corresponding address are sent to the data comparison module; when the first read / write enable signal sent by the address generation module is a read enable signal, the address is accumulated from the maximum address in the full address until the full address ends at 0, and the full address of the RAM to be tested is read;

[0043] After the selection signal is valid, the read-write logic conversion module chip sets the read-write logic control signal to all 0 as the initial state S_idle, and next determines whether the read-write enable signal is valid; all the combination logic signals after the arrangement and combination of multiple read-write logic control signals are judged in turn to be the second read-write enable signal; if the combination logic signal is the second read-write enable signal, the second read-write enable signal for reading and writing the RAM to be tested is output, and when the first read-write enable signal and the second read-write enable signal are both write enable signals, the RAM to be tested is fully written, and the full address data and the data to be written are sent to the data comparison module for comparison; and when the first read-write enable signal and the second read-write enable signal are both read enable signals, the RAM to be tested is fully read, and the full address data and the read data are sent to the data comparison module for comparison; if the combination logic signal is not the second read-write enable signal, data recording is performed, and the current combination logic signal is recorded and marked as an invalid combination logic signal; and the next combination logic signal is judged until all combination logic signals are judged.

[0044] The data comparison module compares the full address data and the data to be written sent by the address generation module with the full address data and the read data sent by the read-write logic conversion module. If the full address data and the data to be written sent by the address generation module are consistent with the full address data and the read data sent by the read-write logic conversion module (that is, the full address data sent by the address generation module is consistent with the full address data sent by the read-write logic conversion module, and the data to be written sent by the address generation module is consistent with the read data sent by the read-write logic conversion module), the test passes.

[0045] Among them, such as Figure 4 As shown, the ECC error correction and verification module includes a data flip submodule (level translator), a random address generator (Random_address), an ECC error correction function component (Ecc_check), a state controller (state_controller), and also includes the data input interface DATA_IN to be read and written, the number of flipped bits ERROR_BIT_CNT, the address ADDRESS, the read / write data bus WR, and the chip select CS port. The ECC error correction function component is used to, when the ECC error correction function (Ecc_check_en) is first enabled, perform a full address write operation on the RAM to be tested based on all read or write addresses (ADDRESS) and the first read / write enable signal (the first read / write enable signal is a write enable signal, i.e., WR bus) generated by the address generation module, and after confirming that all addresses have data, perform a full address read operation on the RAM to be tested when the ECC error correction function is enabled again. When it is detected that the data of the randomly generated error address in the RAM to be tested is wrong and the write enable is valid, the error-corrected data is written back to the original randomly generated error address. During the output process, it is again detected whether the data of the original randomly generated error address has been repaired. The random address generation module When the ECC error correction function is turned off, the device obtains the input number of error addresses (ERROR_BIT_CNT) and randomly generates a corresponding number of error addresses according to the input number of error addresses; the data flip submodule is used to flip the data in the randomly generated error addresses and write them into the randomly generated error addresses again; the state controller is used to pull down the ECC data completion signal (ECC_DATA_READY) and trigger the write enable to be valid when the ECC error correction function component detects that the data of the randomly generated error addresses in the RAM to be tested are wrong; when the ECC error correction function component detects that the data of the original randomly generated error addresses in the RAM to be tested have been repaired, the ECC data completion signal is pulled high to trigger the write enable to be invalid.

[0046] Furthermore, the ECC error correction verification module also includes an encoder (ECC_encoder) and a decoder (ECC_decoder). The encoder is used to encode the data to be written (DATA_IN) generated by the address generation module and write it into the RAM to be tested; the decoder is used to decode the data to be read (ram_data_out) in the RAM to be tested and output the data to be read (ECC_DATA_OUT).

[0047] The ECC logic function verification (ECC error correction function verification) will be tested after the read and write logic function test is completed and the data reading and writing are confirmed to be normal. The present invention can realize the following: after the ECC function is turned on, a RAM full address write operation is performed; after the ECC function is turned off, a random function generator is used as a random address generator to randomly generate an address that requires artificial error injection within the RAM address range, and the bit data level in the address is flipped; after the ECC function is turned on, the data is read out and the ECC function verification is performed.

[0048] Specifically, the system sends a request for ECC logic function test via the RAM check (user function verification request signal) of the AXI bus;

[0049] The address generation module identifies RAM check[2:0] according to the data in Table 1. When RAM check[2:0] = 010 is detected, the RAM ECC single-bit error correction function test is performed. After the chip select signal is enabled, the ECC function is enabled. After performing a full address write operation on the RAM to be tested and confirming that all addresses have data, the ECC error correction function component will generate a set of corresponding ECC check codes.

[0050] Disable the ECC error correction component, that is, disable ECC_check_start. The random address generator (Random_address) will randomly generate a corresponding number of addresses based on the number of error addresses entered (ERROR_BIT_CNT). After the data in the error address is flipped (level translator) (the number of flipped bits corresponds to the number of error addresses entered), it is written back to the error address.

[0051] Re-enable the ECC error correction component, that is, enable the ECC function again, and perform a full address read operation on the RAM under test. When a data error is detected in the RAM under test, the ECC_DATA_READY signal is pulled low, and the state controller sets the state_flag. When the write enable is valid, the corrected data correct_data is written back to the original address (the original randomly generated error address) and then output again.

[0052] During the output process, the ECC error correction function component will re-check whether the data is incorrect (whether the data of the original randomly generated erroneous address has been repaired, that is, whether the check code generated by the data is the same as the check code generated by the initial enable. If they are the same, the data of the original randomly generated erroneous address has been repaired, that is, the data is correct after re-detection; if they are different, the data of the original randomly generated erroneous address has not been repaired, that is, the data is incorrect after re-detection;). If the erroneous data has been repaired at this time, ECC_DATA_READY is valid, the state controller pulls state_flag high, and write enable is invalid, which proves that the bit flipping caused by accident in the RAM can be repaired when the number of error bits meets the error correction capability.

[0053] Specifically, the number of input incorrect addresses obtained in the random address generator is 1 bit, 2 bits, or 3 bits. The number of input incorrect addresses can be determined to be 1 bit, 2 bits, or 3 bits based on the user function verification request signal (ram check) and Table 1.

[0054] Furthermore, a functional verification device compatible with RAM read / write logic and ECC logic in the technical solution of the present invention also includes a clock reset module, which is used to reset the clock of the functional verification device compatible with RAM read / write logic and ECC logic.

[0055] It should be noted that the functional verification device compatible with RAM read-write logic and ECC logic in the technical solution of the present invention can be a hardware logic check chip (RTL chip), which integrates RAM read-write logic verification and ECC logic function verification into the verification platform on the logic check chip, so as to check whether the read-write access generated by the RTL internal logic is legal, whether there is a conflict in the read-write access, and whether the RAM access interface signal generates an indeterminate state. By utilizing the usersignal (user request signal) of the AXI bus, it is set as the RAM logic function check signal ram check (user function verification request signal) to select the function of the logic check, and the ECC function is verified by random error injection, thereby improving the logical integrity and data reliability of the RAM controller; the internal address generation module, read-write logic conversion module, ECC error correction verification module, data comparison module, and clock reset module can all be implemented by software function modules and / or hardware circuit modules, and the present invention is not limited here.

[0056] The technical solution of the present invention is used to generate all read or write addresses, and generate a first read / write enable signal and data to be read / written for reading and writing the RAM to be tested according to the functional verification type of the RAM to be tested; the read / write logic conversion module is used to perform read / write logic function verification when the functional verification type of the RAM to be tested is read / write logic function verification; the ECC (Error Correcting Code) error correction verification module performs ECC logic function verification by randomly injecting errors when the functional verification type of the RAM to be tested is ECC logic function verification; the data comparison module is used to judge when the functional verification type of the RAM to be tested is read / write logic function verification, compare the data for full address reading and writing of the RAM to be tested with the data to be read / written sent by the address generation module, and perform read / write logic function verification, thereby effectively solving the problem of incompatibility between the functional verification of the RAM memory read / write logic and the ECC logic caused by the prior art, and effectively improving the efficiency of the RAM memory functional verification.

[0057] The address generation module in the technical solution of the present invention performs function control by utilizing the User signal (user function verification request signal) of the AXI (Advanced eXtensible Interface) bus, and determines the function verification type of the RAM to be tested according to the user function verification request signal. This not only does not affect the normal communication bandwidth, but also can flexibly adjust the function verification type of the RAM to be tested according to user requests.

[0058] In the technical solution of the present invention, the read-write logic conversion module judges whether all the combination logic signals after the arrangement and combination of multiple read-write logic control signals are the second read-write enable signal respectively. If the combination logic signal is the second read-write enable signal, the second read-write enable signal for reading and writing the RAM to be tested is output. If the combination logic signal is not the second read-write enable signal, the next combination logic signal is judged until all the combination logic signals are judged. By adding the integrity test of the read-write logic, the read-write failure caused by the abnormal combination of the read-write logic control signal is avoided, and the comprehensiveness of the RAM read-write logic function verification is improved.

[0059] In the technical solution of the present invention, the data to be read and written at each address generated by the address generation module corresponds to the same address data to be read and written, which makes the comparison of the data comparison module more convenient and improves the efficiency of the verification of the read and write logic functions.

[0060] The technical solution of the present invention not only adds a test of the RAM full address, but also can simulate random RAM bit flipping according to the random address generator and the horizontal flip submodule during the ECC logic function verification. It has the characteristics of strong randomness and easy operation, thereby improving the reliability of the ECC logic function verification.

[0061] Example 2

[0062] like Figure 5 As shown, the technical solution of the present invention also provides a functional verification system for compatible RAM read and write logic and ECC logic, including a functional verification device compatible with RAM read and write logic and ECC logic (i.e., logic check unit), RAM, and AXI bus in embodiment one. The functional verification device compatible with RAM read and write logic and ECC logic obtains a user functional verification request sent by a user through an AXI master device (AXI master1) through the AXI bus, determines a functional verification type of the RAM to be tested according to the user functional verification request signal, and performs functional verification of the RAM read and write logic and ECC logic on the RAM to be tested respectively according to the determined functional verification type of the RAM to be tested.

[0063] Among them, the address generation module in a functional verification device compatible with RAM read and write logic and ECC logic can also be used to receive a user function verification request signal (user signal or ramcheck) sent by the user through a communication bus (AXI bus), and determine the functional verification type of the RAM to be tested according to the user function verification request signal.

[0064] Specifically, determining the functional verification type of the RAM to be tested according to the user functional verification request signal is: determining the functional verification type of the RAM to be tested according to the user functional verification request signal and a functional verification type database, wherein the functional verification type database stores the corresponding relationship between the user functional verification request signal and the functional verification type of the RAM to be tested.

[0065] Specifically, the address generation module is mainly used to: after receiving the request for logic check from the AXI bus (RAM check), according to the test RAM address bit number n, it is known that the maximum address of the RAM is 2 n-1 ; Generate all read or write addresses according to the number of address bits of the RAM to be tested, and generate the first read / write enable signal for reading and writing the RAM to be tested and the data to be read / written according to the functional verification type of the RAM to be tested (i.e., the user functional verification request signal, ramcheck). When the chip select signal is enabled, after entering a read / write logic state, determine whether the first read / write enable signal is valid. When the first read / write enable signal is valid for write enable, determine whether the current address is the maximum address value. If it is not the maximum address value, the address is accumulated from 0 until it stops when the address is equal to the maximum address value; when the first read / write enable signal is valid for read enable, determine whether the current address is 0. If it is not equal to 0, the address is accumulated from the maximum address value until it stops when the address is 0.

[0066] Among them, the read-write logic conversion module can calculate the maximum number of signal permutations and combinations based on the number x of read-write logic control signals (control signals used to control reading or writing). x . When the chip select signal is valid, the read-write logic control signal is set to all 0 as the initial state S_idle. The next step is to judge whether the multiple combination logic signals after the arrangement and combination of the multiple read-write logic control signals are valid. When the combination logic signal is valid (the second read-write enable signal), the second read-write enable signal for reading and writing the RAM to be tested is output, and when the first read-write enable signal and the second read-write enable signal are both read enable signals or write enable signals, the RAM to be tested is read and written at all addresses; if the combination logic signal is invalid (not the second read-write enable signal), data is recorded, and the current combination logic signal is recorded and marked as an invalid combination logic signal. After the marking is completed, jump to the next combination logic signal judgment until all combination logic signals have jumped. The integrity test of the read-write logic function verification is completed, and the test results of all combination logic signals are displayed.

[0067] The data comparison module: When the permuted and combined combination logic signal is valid (the second read / write enable signal), it performs continuous read and write operations from low to high according to the full address generated by the address generation module. For example, with a data width of 32 bits and an address width of 4 bits, the address range is 0x0–0xF. To facilitate data comparison, the corresponding "Write_data" for each address generated by the address generation module is set to the same as the address data to be read or written. That is, the corresponding "Write_data" for address 0x0 is also set to 0x0, and the data corresponding to address 0xF is incremented as the address increases. When reading data, the address is read from high to low. If the read address and the address data are inconsistent, it indicates a data anomaly. After counting 10 abnormal data points, the error data is recorded and the current read / write enable logic is marked. After marking, the module jumps to the next logical combination state. This process continues until all states have been transitioned. At this point, the logic integrity test is completed and the test results for all states are displayed.

[0068] Read / write logic verification typically involves performing certain logical operations on one or more read / write logic control signals, using the results as enable signals for the RAM read / write ports. These control signals are typically controlled by other modules in the digital circuit, such as DMA (direct memory access) and data cache units. When multiple modules need to access RAM, the logic access timing signals, read / write data, and addresses are transmitted to the RAM. Data detection components perform data comparison and verification. When confirming a logical access, the access logic is judged to be normal based on the access address and data.

[0069] Specifically, the user sends a request for a read / write test via the user function verification request signal ram check of the AXI bus; ram check[2:0] is identified according to the data in Table 1, and when ram check[2:0]=001 is detected, a read / write test is performed on the RAM to be tested;

[0070] When the first read / write enable signal sent by the address generation module is a write enable signal, the address is accumulated from 0 to the maximum address in the full address, and the full address and the data to be written at the corresponding address are sent to the data comparison module; when the first read / write enable signal sent by the address generation module is a read enable signal, the address is accumulated from the maximum address in the full address until the full address ends at 0, and the full address of the RAM to be tested is read;

[0071] After the selection signal is valid, the read-write logic conversion module chip sets the read-write logic control signal to all 0 as the initial state S_idle, and next determines whether the read-write enable signal is valid; all the combination logic signals after the arrangement and combination of multiple read-write logic control signals are judged in turn to be the second read-write enable signal; if the combination logic signal is the second read-write enable signal, the second read-write enable signal for reading and writing the RAM to be tested is output, and when the first read-write enable signal and the second read-write enable signal are both write enable signals, the RAM to be tested is fully written, and the full address data and the data to be written are sent to the data comparison module for comparison; and when the first read-write enable signal and the second read-write enable signal are both read enable signals, the RAM to be tested is fully read, and the full address data and the read data are sent to the data comparison module for comparison; if the combination logic signal is not the second read-write enable signal, data recording is performed, and the current combination logic signal is recorded and marked as an invalid combination logic signal; and the next combination logic signal is judged until all combination logic signals are judged.

[0072] The data comparison module compares the full address data and the data to be written sent by the address generation module with the full address data and the read data sent by the read-write logic conversion module. If the full address data and the data to be written sent by the address generation module are consistent with the full address data and the read data sent by the read-write logic conversion module (that is, the full address data sent by the address generation module is consistent with the full address data sent by the read-write logic conversion module, and the data to be written sent by the address generation module is consistent with the read data sent by the read-write logic conversion module), the test passes.

[0073] Among them, such as Figure 3As shown, the ECC error correction and verification module includes a data flip submodule (level translator), a random address generator (Random_address), an ECC error correction function component (Ecc_check), a state controller (state_controller), and also includes the data input interface DATA_IN to be read and written, the number of flipped bits ERROR_BIT_CNT, the address ADDRESS, the read / write data bus WR, and the chip select CS port. The ECC error correction function component is used to, when the ECC error correction function (Ecc_check_en) is first enabled, perform a full address write operation on the RAM to be tested based on all read or write addresses (ADDRESS) and the first read / write enable signal (the first read / write enable signal is a write enable signal, i.e., WR bus) generated by the address generation module, and after confirming that all addresses have data, perform a full address read operation on the RAM to be tested when the ECC error correction function is enabled again. When it is detected that the data of the randomly generated error address in the RAM to be tested is wrong and the write enable is valid, the error-corrected data is written back to the original randomly generated error address. During the output process, it is again detected whether the data of the original randomly generated error address has been repaired. The random address generation module When the ECC error correction function is turned off, the device obtains the input number of error addresses (ERROR_BIT_CNT) and randomly generates a corresponding number of error addresses according to the input number of error addresses; the data flip submodule is used to flip the data in the randomly generated error addresses and write them into the randomly generated error addresses again; the state controller is used to pull down the ECC data completion signal (ECC_DATA_READY) and trigger the write enable to be valid when the ECC error correction function component detects that the data of the randomly generated error addresses in the RAM to be tested are wrong; when the ECC error correction function component detects that the data of the original randomly generated error addresses in the RAM to be tested have been repaired, the ECC data completion signal is pulled high to trigger the write enable to be invalid.

[0074] Furthermore, the ECC error correction verification module also includes an encoder (ECC_encoder) and a decoder (ECC_decoder). The encoder is used to encode the data to be written (DATA_IN) generated by the address generation module and write it into the RAM to be tested; the decoder is used to decode the data to be read (ram_data_out) in the RAM to be tested and output the data to be read (ECC_DATA_OUT).

[0075] The ECC logic function verification (ECC error correction function verification) will be tested after the read and write logic function test is completed and the data reading and writing are confirmed to be normal. The present invention can realize the following: after the ECC function is turned on, a RAM full address write operation is performed; after the ECC function is turned off, a random function generator is used as a random address generator to randomly generate an address that requires artificial error injection within the RAM address range, and the bit data level in the address is flipped; after the ECC function is turned on, the data is read out and the ECC function verification is performed.

[0076] Specifically, the system sends a request for ECC logic function test via the RAM check (user function verification request signal) of the AXI bus;

[0077] The address generation module identifies RAM check[2:0] according to the data in Table 1. When RAM check[2:0] = 010 is detected, the RAM ECC single-bit error correction function test is performed. After the chip select signal is enabled, the ECC function is enabled. After performing a full address write operation on the RAM to be tested and confirming that all addresses have data, the ECC error correction function component will generate a set of corresponding ECC check codes.

[0078] Disable the ECC error correction component, that is, disable ECC_check_start. The random address generator (Random_address) will randomly generate a corresponding number of addresses based on the number of error addresses entered (ERROR_BIT_CNT). After the data in the error address is flipped (level translator) (the number of flipped bits corresponds to the number of error addresses entered), it is written back to the error address.

[0079] Re-enable the ECC error correction component, that is, enable the ECC function again, and perform a full address read operation on the RAM under test. When a data error is detected in the RAM under test, the ECC_DATA_READY signal is pulled low, and the state controller sets the state_flag. When the write enable is valid, the corrected data correct_data is written back to the original address (the original randomly generated error address) and then output again.

[0080] During the output process, the ECC error correction function component will re-check whether the data is incorrect (whether the data of the original randomly generated erroneous address has been repaired, that is, whether the check code generated by the data is the same as the check code generated by the initial enable. If they are the same, the data of the original randomly generated erroneous address has been repaired, that is, the data is correct after re-detection; if they are different, the data of the original randomly generated erroneous address has not been repaired, that is, the data is incorrect after re-detection;). If the erroneous data has been repaired at this time, ECC_DATA_READY is valid, the state controller pulls state_flag high, and write enable is invalid, which proves that the bit flipping caused by accident in the RAM can be repaired when the number of error bits meets the error correction capability.

[0081] Specifically, the number of input incorrect addresses obtained in the random address generator is 1 bit, 2 bits, or 3 bits. The number of input incorrect addresses can be determined to be 1 bit, 2 bits, or 3 bits based on the user function verification request signal (ram check) and Table 1.

[0082] Furthermore, a functional verification device compatible with RAM read / write logic and ECC logic in the technical solution of the present invention also includes a clock reset module, which is used to reset the clock of the functional verification device compatible with RAM read / write logic and ECC logic.

[0083] It should be noted that the functional verification device compatible with RAM read / write logic and ECC logic in the technical solution of the present invention can be a hardware logic check chip (RTL chip), which integrates RAM read / write logic verification and ECC logic function verification into the verification platform on the logic check chip. This is used to check whether the read / write access generated by the RTL internal logic is legal, whether there is a conflict in the read / write access, and whether the RAM access interface signal generates an indeterminate state. By utilizing the usersignal (user request signal) of the AXI bus, it is set as the RAM logic function check signal ramcheck (user function verification request signal) for selecting the logic check function and using random error injection to verify the ECC function, thereby improving the logical integrity and data reliability of the RAM controller.

[0084] The technical solution of the present invention is used to generate all read or write addresses, and generate a first read / write enable signal and data to be read / written for reading and writing the RAM to be tested according to the functional verification type of the RAM to be tested; the read / write logic conversion module is used to perform read / write logic function verification when the functional verification type of the RAM to be tested is read / write logic function verification; the ECC (Error Correcting Code) error correction verification module performs ECC logic function verification by randomly injecting errors when the functional verification type of the RAM to be tested is ECC logic function verification; the data comparison module is used to judge when the functional verification type of the RAM to be tested is read / write logic function verification, compare the data for full address reading and writing of the RAM to be tested with the data to be read / written sent by the address generation module, and perform read / write logic function verification, thereby effectively solving the problem of incompatibility between the functional verification of the RAM memory read / write logic and the ECC logic caused by the prior art, and effectively improving the efficiency of the RAM memory functional verification.

[0085] The address generation module in the technical solution of the present invention performs function control by utilizing the User signal (user function verification request signal) of the AXI (Advanced eXtensible Interface) bus, and determines the function verification type of the RAM to be tested according to the user function verification request signal. This not only does not affect the normal communication bandwidth, but also can flexibly adjust the function verification type of the RAM to be tested according to user requests.

[0086] In the technical solution of the present invention, the read-write logic conversion module judges whether all the combination logic signals after the arrangement and combination of multiple read-write logic control signals are the second read-write enable signal respectively. If the combination logic signal is the second read-write enable signal, the second read-write enable signal for reading and writing the RAM to be tested is output. If the combination logic signal is not the second read-write enable signal, the next combination logic signal is judged until all the combination logic signals are judged. By adding the integrity test of the read-write logic, the read-write failure caused by the abnormal combination of the read-write logic control signal is avoided, and the comprehensiveness of the RAM read-write logic function verification is improved.

[0087] In the technical solution of the present invention, the data to be read and written at each address generated by the address generation module corresponds to the same address data to be read and written, which makes the comparison of the data comparison module more convenient and improves the efficiency of the verification of the read and write logic functions.

[0088] The technical solution of the present invention not only adds a test of the RAM full address, but also can simulate random RAM bit flipping according to the random address generator and the horizontal flip submodule during the ECC logic function verification. It has the characteristics of strong randomness and easy operation, thereby improving the reliability of the ECC logic function verification.

[0089] Although the above describes the specific embodiments of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without any creative work are still within the scope of protection of the present invention.

Claims

1. A functional verification device compatible with RAM read / write logic and ECC logic, characterized in that: Communicates with the RAM and includes: an address generation module, a read-write logic conversion module, an ECC error correction verification module, and a data comparison module. The address generation module is used to generate all read or write addresses according to the number of bits of the RAM address to be tested, and to generate a first read-write enable signal and data to be read and written for reading and writing the RAM to be tested according to the functional verification type of the RAM to be tested; when the first read-write enable signal is valid for write enable, it is judged whether the current address is the maximum address value, if not, the address is accumulated from 0 until the address is equal to the maximum address value and stops; when the first read-write enable signal is valid for read enable, it is judged whether the current address is 0, if not, the address is accumulated from the maximum address value until the address is 0 and stops; the read-write logic conversion module is used to judge whether all combination logic signals after the arrangement and combination of multiple read-write logic control signals are the second read-write enable signal in sequence when the functional verification type of the RAM to be tested is read-write logic function verification, and if the combination logic signal is the second read-write enable signal, output for the RAM to be tested The second read-write enable signal for reading and writing, and when the first read-write enable signal and the second read-write enable signal are both read enable signals or write enable signals, the full-address reading and writing of the RAM to be tested is performed; when the functional verification type of the RAM to be tested is ECC logic function verification, the ECC error correction verification module reads and writes the RAM to be tested according to all the read or write addresses generated by the address generation module and the first read-write enable signal, and performs ECC logic function verification by random error injection; the data comparison module is used to judge the data for full-address reading and writing of the RAM to be tested and compare it with the data to be read and written sent by the address generation module when the functional verification type of the RAM to be tested is read-write logic function verification, and perform read-write logic function verification; the data to be read and written on each address generated by the address generation module is the same as the address data to be read and written. When reading data, the address is read from high to low. When the read address is inconsistent with the address data size, it means that the data is abnormal at this time. After continuously counting multiple abnormal data, the error data is recorded and the current read-write enable logic is marked.

2. The function verification device compatible with RAM read / write logic and ECC logic according to claim 1, characterized in that: The address generation module is further configured to receive a user function verification request signal sent by a user via a communication bus, and determine a function verification type of the RAM to be tested according to the user function verification request signal.

3. The function verification device compatible with RAM read / write logic and ECC logic according to claim 2, characterized in that: Determining the functional verification type of the RAM to be tested according to the user functional verification request signal is specifically: determining the functional verification type of the RAM to be tested according to the user functional verification request signal and the functional verification type database, wherein the functional verification type database stores the corresponding relationship between the user functional verification request signal and the functional verification type of the RAM to be tested.

4. The function verification device compatible with RAM read / write logic and ECC logic according to claim 1, characterized in that: The read-write logic conversion module is further configured to, if the combinational logic signal is not the second read-write enable signal, determine the next combinational logic signal until all combinational logic signals are determined.

5. The function verification device for compatible RAM read / write logic and ECC logic according to claim 1, characterized in that: The ECC error correction verification module includes a data flip submodule, a random address generator, an ECC error correction function component, and a state controller. The ECC error correction function component is used to, when the ECC error correction function is first enabled, perform a full address write operation on the RAM to be tested based on all read or write addresses generated by the address generation module and the first read and write enable signal, and after confirming that all addresses have data, perform a full address read operation on the RAM to be tested when the ECC error correction function is enabled again. When it is detected that the data of the randomly generated error address in the RAM to be tested is wrong and the write enable is valid, the error-corrected data is written back to the original randomly generated error address. During the output process, the data of the original randomly generated error address is detected again. The control module detects whether the data has been repaired; when the ECC error correction function is turned off, the random address generator obtains the number of input error addresses, and randomly generates a corresponding number of error addresses according to the number of input error addresses; the data flip submodule is used to flip the data in the randomly generated error addresses and write them into the randomly generated error addresses again; the state controller is used to pull down the ECC data completion signal and trigger the write enable to be valid when the ECC error correction function component detects that the data of the randomly generated error addresses in the RAM to be tested are wrong; when the ECC error correction function component detects that the data of the original randomly generated error addresses in the RAM to be tested have been repaired, pull up the ECC data completion signal and trigger the write enable to be invalid.

6. The function verification device compatible with RAM read / write logic and ECC logic according to claim 5, characterized in that: The ECC error correction verification module also includes an encoder and a decoder. The encoder is used to encode the data to be written generated by the address generation module and then write it into the RAM to be tested; the decoder is used to decode the data to be read in the RAM to be tested and output the data to be read.

7. The function verification device compatible with RAM read / write logic and ECC logic according to claim 5, characterized in that: The number of the input error-injected addresses obtained in the random address generator is 1 bit, 2 bits, or 3 bits.

8. A functional verification device for compatible RAM read / write logic and ECC logic according to any one of claims 1 to 7, characterized in that: It also includes a clock reset module, which is used to reset the clock of the functional verification device compatible with RAM read and write logic and ECC logic.

9. A functional verification system compatible with RAM read / write logic and ECC logic, characterized in that: The method comprises a functional verification device compatible with RAM read / write logic and ECC logic as described in any one of claims 1 to 8, RAM, and an AXI bus, wherein the functional verification device compatible with RAM read / write logic and ECC logic obtains a user functional verification request through the AXI bus, determines a functional verification type of the RAM to be tested according to the user functional verification request signal, and performs functional verification of the RAM read / write logic and ECC logic on the RAM to be tested respectively according to the determined functional verification type of the RAM to be tested.

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