Pixel structure, method for manufacturing pixel structure and shared pixel layout structure

Abstract

This invention provides a pixel structure, a method for fabricating the pixel structure, and a shared pixel layout structure. The pixel structure includes: a substrate; a photoelectric conversion region located in the substrate; a charge collection region disposed in the substrate; a first current-guiding structure extending from a first surface of the substrate towards a second surface into the interior of the substrate, wherein the charge collection region and the photoelectric conversion region are disposed on the same side of the first current-guiding structure; a second current-guiding structure disposed on the first surface of the substrate, connected to the first current-guiding structure, and extending to the charge collection region; and an electrical isolation layer disposed at the interface between the first current-guiding structure, the second current-guiding structure, and the substrate. This invention enables the photoelectric conversion region to achieve higher full-well capacity and sensitivity while better compatibility with a compact shared pixel layout structure.

Description

Technical Field

[0001] This invention belongs to the field of image sensing, and specifically relates to a pixel structure, a method for fabricating the pixel structure, and a shared pixel layout structure. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on their components, they can be broadly categorized into CCD (Charge-Coupled Device) and CMOS (Metal-Oxide-Semiconductor) sensors. With the continuous development of CMOS integrated circuit manufacturing processes, especially the design and manufacturing processes of CMOS image sensors, CMOS image sensors have gradually replaced CCD image sensors as the mainstream. Compared to CCD sensors, CMOS image sensors offer advantages such as higher industrial integration and lower power consumption.

[0003] Based on the needs of practical applications, image sensors require photoelectric conversion areas with high full-well capacity. However, due to limitations in pixel size and transmission, it is difficult to effectively improve the full-well capacity of traditional planar CMOS image sensors. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a pixel structure, a method for manufacturing the pixel structure, and a shared pixel layout structure to solve the problems of difficulty in effectively improving the full-well capacity and charge transfer of CMOS image sensors in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a pixel structure comprising: a substrate having a first surface and a second surface opposite to each other; a photoelectric conversion region located in the substrate; a charge collection region disposed in the substrate; a first current-guiding structure extending from the first surface of the substrate toward the second surface into the interior of the substrate, wherein the charge collection region and the photoelectric conversion region are disposed on the same side of the first current-guiding structure; a second current-guiding structure disposed on the first surface of the substrate, wherein the second current-guiding structure is connected to the first current-guiding structure and extends to the charge collection region; and an electrical isolation layer disposed at the interface between the first current-guiding structure and the substrate and at the interface between the second current-guiding structure and the substrate.

[0006] Optionally, the charge collection region and the first current guiding structure are disposed on the longest line connecting any two points on the edge of the photoelectric conversion region.

[0007] Optionally, the pixel structure further includes an isolation region extending from the first surface of the substrate toward the second surface into the interior of the substrate. The isolation region is disposed around the photoelectric conversion region, wherein the first current guiding structure is disposed within the isolation region.

[0008] Optionally, the charge collection region is disposed in the substrate and arranged around the first corner of the photoelectric conversion region, and the first current guiding structure is disposed in the isolation region around the second corner of the photoelectric conversion region, with the first corner and the second corner located on the same diagonal of the photoelectric conversion region.

[0009] Optionally, the lateral distance between the first flow guiding structure and the sidewall of the isolation region near the photoelectric conversion region is 0~0.1 micrometers.

[0010] Optionally, the lateral distance between the photoelectric conversion region and the isolation region is 0 to 0.1 micrometers.

[0011] Optionally, the isolation region is an ion-implanted isolation region, which has opposite electrical doping to the photoelectric conversion region.

[0012] Optionally, the photoelectric conversion area includes an upper conversion area and a lower conversion area. The upper conversion area is surrounded by the isolation area. The width of the lower conversion area is greater than the width of the upper conversion area, and the outer edge of the lower conversion area extends laterally beyond the inner edge of the isolation area. A back-side deep trench isolation structure is also formed around the lower conversion area.

[0013] Optionally, the upper conversion area includes a first conversion portion and a second conversion portion stacked vertically, the width of the second conversion portion being greater than the width of the first conversion portion, and the isolation area includes a first isolation portion disposed around the first conversion portion and a second isolation portion disposed around the second conversion portion, the width of the first isolation portion being greater than the width of the second isolation portion, and the outer edge of the second conversion portion extending laterally beyond the inner edge of the first isolation portion.

[0014] Optionally, the projection shape of the first flow guiding structure on the substrate surface includes at least one of square, circle, triangle, polygonal, and irregular shapes, and the width of the second flow guiding structure is such that it at least completely covers the projection of the first flow guiding structure on the substrate surface.

[0015] Optionally, the projection shape of the second flow guiding structure on the substrate surface is an axisymmetric figure.

[0016] Optionally, the pixel structure includes two or more first flow guiding structures, and the width of the second flow guiding structure is such that it at least simultaneously covers the projections of multiple first flow guiding structures on the substrate surface.

[0017] Optionally, the cross-sectional shape of the first flow guiding structure includes one of a square, an inverted trapezoid, and an irregular shape.

[0018] Optionally, the first flow guiding structure includes n flow guiding control zones arranged from top to bottom, where n is a positive integer greater than or equal to 2, wherein, among two adjacent flow guiding control zones, the minimum width of the longitudinal cross-sectional shape of the upper flow guiding control zone is greater than the maximum width of the longitudinal cross-sectional shape of the lower flow guiding control zone.

[0019] The present invention also provides a shared pixel layout structure, the shared pixel layout structure comprising: at least two pixel structures arranged in a matrix as described in any of the above; wherein two adjacent pixel structures share a charge collection region; a source follower transistor, wherein at least two pixel structures sharing the same charge collection region share the source follower transistor, and the gate of the source follower transistor is electrically connected to the corresponding charge collection region.

[0020] Optionally, the shared pixel layout structure includes: four pixel structures arranged in a matrix, the four pixel structures sharing two charge collection regions and the two charge collection regions facing each other in the middle of the matrix, wherein two adjacent first pixel structures share a first charge collection region, and two adjacent second pixel structures share a second charge collection region; the source follower transistor is disposed between the first charge collection region and the second charge collection region.

[0021] Optionally, the shared pixel layout structure further includes a reset transistor disposed between two rows of pixel structures and arranged along the row direction; and / or, the shared pixel layout structure further includes a selection transistor disposed between two columns of pixel structures and arranged along the column direction; and / or, the shared pixel layout structure further includes a conversion gain transistor, wherein when the shared pixel layout structure further includes a reset transistor, the conversion gain transistor is disposed between the reset transistor and the corresponding charge collection region.

[0022] The present invention also provides an electronic device, the electronic device comprising the pixel structure as described in any of the above claims or the shared pixel layout structure as described in any of the above claims.

[0023] The present invention also provides a method for fabricating a pixel structure, comprising the steps of: providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other; forming a photoelectric conversion region in the substrate; forming a first current-guiding structure, a second current-guiding structure and an electrical isolation layer, wherein the first current-guiding structure extends from the first surface of the substrate toward the second surface into the interior of the substrate, the second current-guiding structure is disposed on the first surface of the substrate and connected to the first current-guiding structure, and the electrical isolation layer is disposed at the interface between the first current-guiding structure and the substrate and the interface between the second current-guiding structure and the substrate; forming a charge-collecting region in the substrate, the charge-collecting region being arranged around a corner of the photoelectric conversion region and adjacent to the second current-guiding structure, and the charge-collecting region and the photoelectric conversion region being disposed on the same side of the first current-guiding structure.

[0024] Optionally, the steps of forming the first current-guiding structure, the second current-guiding structure, and the electrical isolation layer include: forming a first electrical isolation layer on a first surface of the substrate; forming a mask pattern on the first electrical isolation layer, and then forming a trench in the isolation region based on the mask pattern; forming a second electrical isolation layer on the inner surface of the trench; forming a first current-guiding structure in the trench; removing the mask pattern; and forming a second current-guiding structure on the first surface of the substrate.

[0025] Optionally, after removing the mask pattern and before forming the second flow guiding structure, the method further includes the step of removing the first electrical isolation layer and forming a reset electrical isolation layer at the corresponding location, wherein the material of the reset electrical isolation layer is the same as or different from the material of the first electrical isolation layer.

[0026] Optionally, the steps of the pixel structure fabrication method further include: before forming the photoelectric conversion region, forming an isolation region in the substrate extending from a first surface of the substrate toward a second surface into the interior of the substrate; wherein the isolation region is located outside the photoelectric conversion region, and the first current guiding structure is disposed within the isolation region.

[0027] As described above, the pixel structure, the method for manufacturing the pixel structure, and the shared pixel layout structure of the present invention have the following beneficial effects:

[0028] This invention uses a first current-guiding structure and a second current-guiding structure to jointly transport charge carriers to the charge collection region. Furthermore, this invention can also place the charge collection region and the photoelectric conversion region on the same side of the first current-guiding structure, which is beneficial for charge transport. This invention can also place the first current-guiding structure at the location of the isolation region. By doping a shallower region of the photoelectric conversion region, a photoelectric conversion region can also be formed in the shallower region between the first current-guiding structure and the charge collection region, thereby increasing the depth range of the photoelectric conversion region. This invention can enable the photoelectric conversion region to achieve a higher full-well capacity.

[0029] This invention, while maintaining the junction capacitance of the charge collection region unchanged, can better accommodate the shared pixel layout structure. The shared pixel layout structure of this invention is compact and effectively shortens the connection length between the charge collection region and the gate of the source follower transistor, thereby effectively improving the conversion gain of the shared pixel layout structure. Attached Figure Description

[0030] Figures 1-11 The diagram shows the structural schematics of each step in the pixel structure fabrication method according to an embodiment of the present invention. Figure 11 The diagram shown is a structural schematic of the pixel structure according to an embodiment of the present invention.

[0031] Figures 12-15 The diagram shown is a structural example of the first flow guiding structure of the pixel structure according to an embodiment of the present invention.

[0032] Figures 16-19 The diagram shown is a structural example of the second flow guiding structure of the pixel structure in an embodiment of the present invention.

[0033] Figure 20 The diagram shown is a structural schematic of the shared pixel layout structure according to an embodiment of the present invention.

[0034] Component labeling: 1 Pixel structure, 10 Substrate, 11 Isolation region, 12 Shallow trench isolation structure, 111 First isolation section, 112 Second isolation section, 13 Photoelectric conversion region, 131 First conversion section, 132 Second conversion section, 133 Lower conversion region, 141 First electrical isolation layer, 151 Mask pattern, 152 Trench, 142 Second electrical isolation layer, 143 First current conduction structure, 144 Second current conduction structure, 16 Charge collection region, 17 Back deep trench isolation structure, 20 First charge collection region, 21 Second charge collection region, SF Source follower transistor, RST Reset transistor, DCG Conversion gain transistor. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0038] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] This invention, through the design of a first current-guiding structure and related structures, can increase the depth and width of the photoelectric conversion region, thereby improving the full-well capacity and charge transport performance of the photoelectric conversion region. The first current-guiding structure design can actually improve electron transport capability. During electron transport, electrons in the photoelectric conversion region (PD) are transported through the transport channel to the floating node (FD) for collection. Therefore, the first current-guiding structure can improve the full-well capacity of the photoelectric conversion region of the CMOS sensor.

[0041] like Figures 11-19 As shown, this embodiment provides a pixel structure 1, which includes: a substrate 10, a photoelectric conversion region 13, a charge collection region 16, a first current guiding structure 143, a second current guiding structure 144, and an electrical isolation layer.

[0042] The substrate 10 includes a first surface and a second surface facing each other. The material of the substrate 10 can be silicon, germanium, germanium-silicon, silicon carbide, group III-V semiconductor compounds, etc. In this embodiment, the material of the substrate 10 is silicon.

[0043] The photoelectric conversion region 13 is located in the substrate 10.

[0044] In a further example, the pixel structure 1 also includes an isolation region 11, which extends from the first surface of the substrate 10 toward the second surface into the interior of the substrate 10, and is disposed around the photoelectric conversion region 13. Of course, the photoelectric conversion region 13 can also be configured to have a gap from the first surface of the substrate 10, that is, the top surface of the photoelectric conversion region 13 is located below the first surface of the substrate 10, and does not necessarily need to be flush with the first surface.

[0045] In one embodiment, a shallow trench isolation structure (STI) 12 may also be formed in the isolation zone 11.

[0046] In one embodiment, the isolation region 11 is an ion-implanted isolation region 11, which has opposite electrical doping to the photoelectric conversion region 13. For example, in this embodiment, for an n-type MOS structure, the photoelectric conversion region 13 can be an n-type doped region of a photodiode, and the isolation region 11 can be p-type doped. Of course, in other embodiments, for a p-type MOS structure, the isolation region 11 can be n-type doped.

[0047] In one embodiment, the lateral spacing D2 between the photoelectric conversion region 13 and the isolation region 11 is 0~0.1 micrometers, for example, 0.01 micrometers, 0.02 micrometers, 0.05 micrometers, or 0.08 micrometers. With the above setting, the present invention can set the photoelectric conversion region 13 in most of the area enclosed by the isolation region 11, thereby improving the full-well capacity of the pixel structure 1.

[0048] In one embodiment, the photoelectric conversion region 13 includes an upper conversion region and a lower conversion region 133. The upper conversion region is surrounded by the isolation region 11. The width of the lower conversion region 133 is greater than the width of the upper conversion region, and the outer edge of the lower conversion region 133 extends laterally beyond the inner edge of the isolation region 11. A back-side deep trench isolation structure 17 is also formed around the lower conversion region. Since the electric field is mainly concentrated in the upper region of the substrate 10 during the operation of the pixel structure 1, this embodiment can set the width of the isolation region 11 to be greater than the width of the back-side deep trench isolation structure 17, which can effectively increase the effective area of ​​the lower conversion region 133, thereby increasing the full-well capacity.

[0049] In yet another embodiment, such as Figure 11As shown, the photoelectric conversion region 13 includes an upper conversion region and a lower conversion region 133. The upper conversion region is surrounded by the isolation region 11. The width of the lower conversion region 133 is greater than the width of the upper conversion region, and the outer edge of the lower conversion region 133 extends laterally beyond the inner edge of the isolation region 11. A back-side deep trench isolation structure 17 is also formed around the lower conversion region. Furthermore, in this embodiment, the upper conversion region is further configured to include a first conversion portion 131 and a second conversion portion 132 stacked vertically. The width of the second conversion portion 132 is greater than the width of the first conversion portion 131. In a further example, the isolation region 11 includes a first isolation portion 111 disposed around the first conversion portion 131 and a second isolation portion 112 disposed around the second conversion portion 132. The width of the first isolation portion 111 is greater than the width of the second isolation portion 112, and the outer edge of the second conversion portion 132 extends laterally beyond the inner edge of the first isolation portion 111.

[0050] On the one hand, since the electric field is mainly concentrated in the upper region of the substrate 10 during the operation of the pixel structure 1, this embodiment can set the width of the isolation region 11 to be greater than the width of the back deep trench isolation structure 17, which can effectively increase the effective area of ​​the lower conversion region 133, thereby increasing the full-well capacity. On the other hand, since the electric field is mainly concentrated in the surface region of the substrate 10, this embodiment sets the width of the first isolation portion 111 to be greater than the width of the second isolation portion 112, which can make the configuration of the isolation region 11 more adaptable to the working electric field isolation requirements of the pixel structure 1 and improve the process window of the shallow trench isolation structure 12. At the same time, the upper conversion region is further configured to include a first conversion portion 131 and a second conversion portion 132 stacked vertically, and the width of the second conversion portion 132 is greater than the width of the first conversion portion 131, which can effectively maximize the full-well capacity of the pixel structure 1 under this isolation region 11 configuration.

[0051] like Figures 11-19 As shown, the charge collection region is disposed in the substrate. In one embodiment, the charge collection region may be disposed around a corner of the photoelectric conversion region. Of course, in other embodiments, the charge collection region may be disposed in the substrate above the photoelectric conversion region. Further optionally, the second current guiding structure is arranged in a ring around the periphery of the charge collection region.

[0052] In one embodiment, the charge collection region and the photoelectric conversion region are disposed on the same side of the first current guiding structure. This same-side arrangement facilitates the transfer of charge generated in the photoelectric conversion region from the first current guiding structure to the charge collection region. Furthermore, it avoids the drawback of the charge collection region increasing the area required for the device's peripheral region when the charge collection region and the photoelectric conversion region are disposed on opposite sides of the first current guiding structure. The charge collection region 16 and the photoelectric conversion region 13 are disposed on the same side of the first current guiding structure 143, and the line connecting the photoelectric conversion region and the charge collection region can be configured so that it does not cross the first current guiding structure 143. In one embodiment, the line connecting the center of the charge collection region 16 and the center of the first current guiding structure 143 can be defined as the x-axis direction, and a y-axis direction perpendicular to the x-axis direction can be defined. The center of the first current guiding structure 143 is the intersection of the x-axis and the y-axis. The photoelectric conversion region 13 and the charge collection region 16 are disposed on the same side of the y-axis, ensuring that the charge collection region 16 and the photoelectric conversion region 13 are on the same side of the first current guiding structure 143.

[0053] In one embodiment, the charge collection region and the first current-conducting structure are disposed on the longest line connecting any two points on the edge of the photoelectric conversion region.

[0054] In one embodiment, the charge collection region 16 may be disposed in the substrate 10 and arranged around a corner of the photoelectric conversion region 13. The first current-guiding structure 143 extends from a first surface of the substrate 10 toward a second surface into the interior of the substrate 10. In one embodiment, the first current-guiding structure 143 is disposed within the isolation region 11. The second current-guiding structure 144 is disposed on the first surface of the substrate 10, connected to the first current-guiding structure 143, and extends to the charge collection region 16. The electrical isolation layer is disposed at the interface between the first current-guiding structure 143 and the substrate 10, and at the interface between the second current-guiding structure 144 and the substrate 10.

[0055] In one embodiment, the charge collection region 16 is disposed in the middle of the isolation region 11 and partially overlaps with the second current guiding structure 144. The placement of the charge collection region 16 in the middle of the isolation region 11 ensures that it does not occupy the area of ​​the photoelectric conversion region 13. Furthermore, this embodiment places the charge collection region 16 in the isolation region 11 surrounding a corner of the photoelectric conversion region 13. While maintaining the junction capacitance of the charge collection region 16 unchanged, this allows for better compatibility with shared pixel layout structures.

[0056] In one embodiment, the charge collection region 16 is disposed in the substrate 10 and arranged around the first corner of the photoelectric conversion region 13, and the first current guiding structure 143 is disposed in the isolation region 11 around the second corner of the photoelectric conversion region 13. The first corner and the second corner are located on the same diagonal of the photoelectric conversion region 13.

[0057] The first corner and the second corner are located on the same diagonal of the photoelectric conversion area 13. On the one hand, this can facilitate the subsequent use of the pixel structure 1 to form a shared pixel layout structure. On the other hand, after forming the shared pixel layout structure, the second flow guiding structures 144 of the four pixel structures 1 extend in a direction away from the center of the shared pixel layout structure, which can facilitate the extraction of the second flow guiding structures 144. Furthermore, it is beneficial to further improve the full-well coverage and sensitivity based on the layout design of the first corner and the second corner.

[0058] In one embodiment, the lateral distance D1 between the first flow guiding structure 143 and the sidewall of the isolation region 11 near the photoelectric conversion region 13 is 0~0.1 micrometers, for example, it can be 0.01 micrometers, 0.02 micrometers, 0.05 micrometers, or 0.08 micrometers, so that the first flow guiding structure 143 is closer to the photoelectric conversion region 13, which can effectively improve its ability to attract and transport charge carriers in the photoelectric conversion region 13.

[0059] In some embodiments, such as Figures 12-14 As shown, the projected shape of the first flow guiding structure 143 on the surface of the substrate 10 includes a square shape (e.g., Figure 12 As shown), circular (as shown) Figure 13 As shown), broken line shape (such as...) Figure 14 The cross-sectional shape of the first flow guide structure is one of the following: (as shown), triangle, other polygons, and irregular shapes. In some other embodiments, the cross-sectional shape of the first flow guide structure includes one of a square and an inverted trapezoid. Of course, in other embodiments, its cross-sectional shape may also be irregular.

[0060] In some embodiments, the first flow guiding structure includes n flow guiding control regions arranged from top to bottom, where n is a positive integer greater than or equal to 2. In two adjacent flow guiding control regions, the minimum width of the longitudinal cross-sectional shape of the upper flow guiding control region is greater than the maximum width of the longitudinal cross-sectional shape of the lower flow guiding control region, thereby improving the control capability of the first flow guiding structure for charge carriers. The width of the second flow guiding structure 144 is such that it at least completely covers the projection of the first flow guiding structure 143 onto the surface of the substrate 10. In one example, the materials of each flow guiding control region can be designed to be the same or different, depending on actual needs. In an optional example, the materials of each flow guiding control region are identical; for example, after preparing trenches of the designed shape, the first flow guiding structure including n flow guiding control regions can be obtained based on the same filling process. Furthermore, it should be noted that "minimum width" here refers to the smallest of multiple lateral dimensions for the longitudinal cross-section of each flow guiding control region; similarly, "maximum width" refers to the largest of multiple lateral dimensions.

[0061] In a further alternative example, for each of the aforementioned flow control regions, the width of its longitudinal cross-sectional shape gradually increases from bottom to top, thereby facilitating a gradual improvement in the control of the first flow control structure over the charge carriers.

[0062] In some other embodiments, the projection shape of the second current-guiding structure 144 on the surface of the substrate 10 is an axisymmetric figure. For example, in one example, the charge collection region is arranged around the first corner of the photoelectric conversion region, and the first current-guiding structure is disposed in the isolation region around the second corner of the photoelectric conversion region. The first corner and the second corner are disposed on the same diagonal of the photoelectric conversion region, and the second current-guiding structure 144 is axisymmetric about this diagonal.

[0063] In other embodiments, such as Figure 15 As shown, the pixel structure 1 includes two or more first flow guiding structures 143, and the width of the second flow guiding structure 144 is such that it at least simultaneously covers the projections of multiple first flow guiding structures 143 on the surface of the substrate 10; in a further example, the projection shape of the second flow guiding structure 144 on the surface of the substrate 10 may be an axisymmetric figure.

[0064] In some embodiments, such as Figures 16-19As shown, one end of the second current guiding structure 144 completely covers the projection of the first current guiding structure 143 on the surface of the substrate 10, and the other end extends to the charge collection region 16. The second current guiding structure 144 may partially overlap with the charge collection region 16 to facilitate the transport of charge carriers to the charge collection region 16. The other end of the second current guiding structure 144 may be configured to form an inclined angle with the edge of the photoelectric conversion region 13 to facilitate the compatibility of its subsequent formation into a shared pixel layout structure.

[0065] As an example, the pixel structure of the present invention further includes a current-guiding auxiliary layer disposed between the photoelectric conversion region and the first current-guiding structure, wherein the potential of the current-guiding auxiliary layer decreases from the first surface of the substrate toward the second surface.

[0066] In one embodiment, the current-guiding auxiliary layer is disposed in the isolation region. On one hand, the current-guiding auxiliary layer can be fabricated based on the isolation region. The isolation regions of the current-guiding auxiliary layer are configured with the same ion doping type. The structure of the present invention can simplify the process and improve the stability between various components and the overall performance of the device.

[0067] In one embodiment, the current-conducting auxiliary layer includes a plurality of ion-doped regions arranged from the first surface of the substrate toward the second surface. For example, in an n-type MOS structure, these are p-type doped regions; however, this can be adjusted in other structures as needed. The doping concentration of the plurality of ion-doped regions increases sequentially from the first surface of the substrate toward the second surface. For example, taking a p-type ion-doped region as an example, the current-conducting auxiliary layer may include a first p-type doped region, a second p-type doped region, and a third p-type doped region from bottom to top. The doping concentration of the first p-type doped region is greater than that of the second p-type doped region, and the doping concentration of the second p-type doped region is greater than that of the third p-type doped region.

[0068] In one embodiment, the current guiding auxiliary layer further includes a lateral current guiding auxiliary layer extending laterally below the second current guiding structure, the lateral current guiding auxiliary layer being disposed adjacent to the second current guiding structure, and the potential of the lateral current guiding auxiliary layer increasing from the first current guiding structure toward the charge collection region.

[0069] As an example, the lateral current-conducting auxiliary layer includes a plurality of ion-doped regions arranged from the first current-conducting structure toward the charge-collecting region, and the doping concentration of the plurality of ion-doped regions decreases sequentially from the first current-conducting structure toward the charge-collecting region. For example, taking a p-type doped region as an example, the lateral current-conducting auxiliary layer first shares a third p-type doped region with the current-conducting auxiliary layer located on the sidewall of the first current-conducting structure. The third p-type doped region is configured as an inverted L-shaped structure. The lateral current-conducting auxiliary layer then includes a fourth p-type doped region and a fifth p-type doped region sequentially from the first current-conducting structure toward the charge-collecting region, wherein the doping concentration of the third p-type doped region is greater than the doping concentration of the fourth p-type doped region, and the doping concentration of the fourth p-type doped region is greater than the doping concentration of the fifth p-type doped region.

[0070] In one embodiment, regions for the first and second current-guiding structures can be defined first. Then, a current-guiding auxiliary layer is formed on the sidewall of the first current-guiding structure adjacent to the photoelectric conversion region using an ion implantation process, ultimately completing the structure formed after the fabrication of the first and second current-guiding structures. Alternatively, in other embodiments, an isolation region can be formed first, having the same ion doping type as the current-guiding auxiliary region. After forming the isolation region, the current-guiding auxiliary structure layer is formed in the isolation region using a mask. In a further optional example, the first current-guiding structure can be formed after the current-guiding auxiliary structure layer is formed. This method is preferred in this invention for fabricating the current-guiding auxiliary layer to simplify the process and improve the performance of each component. In one embodiment, the lateral current-guiding auxiliary layer can be fabricated in the substrate by ion doping using a mask after the isolation region is formed and before the first current-guiding structure is formed.

[0071] like Figure 20As shown, this embodiment also provides a shared pixel layout structure, which includes: at least two pixel structures 1 arranged in a matrix as described in the previous embodiment; wherein two adjacent pixel structures 1 share a charge collection region 16; a source follower transistor SF, wherein at least two pixel structures 1 sharing the same charge collection region 16 share the source follower transistor SF, and the gate of the source follower transistor SF is electrically connected to the corresponding charge collection region 16. The shared pixel layout structure further includes a reset transistor RST, disposed between two rows of pixel structures and arranged along the row direction; and / or, the shared pixel layout structure further includes a select transistor, disposed between two columns of pixel structures and arranged along the column direction; and / or, the shared pixel layout structure further includes a conversion gain transistor DCG, wherein when the shared pixel layout structure further includes a reset transistor RST, the conversion gain transistor DCG is disposed between the reset transistor RST and the corresponding charge collection region 16.

[0072] In one embodiment, the shared pixel layout structure includes four pixel structures 1 arranged in a matrix as described in the above embodiment. The four pixel structures 1 share two charge collection regions 16, which are arranged facing each other in the middle of the matrix. Two adjacent first pixel structures share a first charge collection region 20, and two adjacent second pixel structures share a second charge collection region 21. A source follower transistor SF is disposed between the first charge collection region 20 and the second charge collection region 21. The shared pixel layout structure of this embodiment is compact, effectively shortening the connection length between the charge collection region 16 and the gate of the source follower transistor SF, thereby effectively improving the conversion gain of the shared pixel layout structure. In one embodiment, the shared pixel layout structure further includes a reset transistor RST, disposed between two first pixel structures and connected to the first charge collection region 20, or disposed between two second pixel structures and connected to the second charge collection region 21. In one embodiment, the shared pixel layout structure further includes a conversion gain transistor DCG, disposed between the reset transistor RST and the first charge collection region 20, or disposed between the reset transistor RST and the second charge collection region 21. For example, in this embodiment, the reset transistor RST and the conversion gain transistor DCG are disposed between the two first pixel structures and connected to the first charge collection region 20 near the transistor.

[0073] In one embodiment, the source follower transistor SF is symmetrically disposed between the first charge collection region 20 and the second charge collection region 21. In one embodiment, the shared pixel layout structure further includes a selection transistor RS disposed between adjacent first and second pixel structures. For example, in one embodiment, the selection transistor RS is located between two adjacent columns of pixel structures, and the reset transistor RST and the conversion gain transistor DCG are located between two adjacent rows of pixel structures.

[0074] This embodiment also provides an electronic device, which includes a pixel structure 1 as described in the above-described scheme or a shared pixel layout structure as described in the above-described scheme.

[0075] In one embodiment, the pixel structure 1 or the shared pixel layout structure is included in surveillance equipment, cameras, mobile phones, drones, machine vision devices, and similar products. Alternatively, the pixel structure 1 or the shared pixel layout structure can also be configured in other hardware components, such as robotic vacuum cleaners and toys.

[0076] like Figures 1-11 As shown, this embodiment also provides a method for fabricating pixel structure 1. The pixel structure of the present invention can be fabricated using the method described herein. The specific structure, features, and positional relationships of each structure in this fabrication method can be found in the descriptions of the pixel structure and pixel layout structure in this embodiment. Furthermore, it should be noted that the order of the steps in the fabrication method described in the claims is not specifically limited, and those skilled in the art can adjust the order of the process steps according to actual circumstances.

[0077] In one embodiment, the manufacturing method includes the steps of:

[0078] like Figure 1 As shown, step 1) is performed first to provide a substrate 10, which includes a first surface and a second surface disposed opposite to each other; a photoelectric conversion region 13 is formed in the substrate 10;

[0079] In a further example, an isolation region 11 extending from a first surface of the substrate 10 toward a second surface into the interior of the substrate 10 may be formed in the substrate 10 before the photoelectric conversion region 13 is formed; then, the photoelectric conversion region 13 is formed in the area enclosed by the isolation region 11 and in the substrate 10 below the isolation region 11.

[0080] The substrate 10 includes a first surface and a second surface facing each other. The material of the substrate 10 can be silicon, germanium, germanium-silicon, silicon carbide, group III-V semiconductor compounds, etc. In this embodiment, the material of the substrate 10 is silicon.

[0081] The photoelectric conversion region 13 extends from the first surface of the substrate 10 toward the second surface into the interior of the substrate 10. Additionally, the isolation region 11 extends from the first surface of the substrate 10 toward the second surface into the interior of the substrate 10, and the isolation region 11 is disposed around the periphery of the photoelectric conversion region 13. Of course, the photoelectric conversion region 13 can also be configured to have a gap from the first surface of the substrate 10, that is, the top surface of the photoelectric conversion region 13 is located below the first surface of the substrate 10, and does not necessarily need to be flush with the first surface.

[0082] In one embodiment, a shallow trench isolation structure 12 may also be formed in the isolation zone 11.

[0083] In one embodiment, the isolation region 11 is an ion-implanted isolation region 11, and the photoelectric conversion region 13 can be formed by ion implantation. The ion-implanted isolation region 11 and the photoelectric conversion region 13 have opposite electrical doping properties. For example, the photoelectric conversion region 13 can be an n-type doped region of a photodiode, and the isolation region 11 can be p-type doped.

[0084] In one embodiment, the lateral spacing between the photoelectric conversion region 13 and the isolation region 11 is 0 to 0.1 micrometers, for example, 0.1 micrometers. With the above setting, the present invention can place the photoelectric conversion region 13 in most areas within the isolation region 11, thereby improving the full-well capacity of the pixel structure 1.

[0085] In one embodiment, by different ion implantations, the photoelectric conversion region 13 includes an upper conversion region and a lower conversion region 133, the upper conversion region being surrounded by the isolation region 11, the width of the lower conversion region 133 being greater than the width of the upper conversion region, and the outer edge of the lower conversion region 133 extending laterally beyond the inner edge of the isolation region 11.

[0086] In yet another embodiment, such as Figure 1As shown, the photoelectric conversion region 13 includes an upper conversion region and a lower conversion region 133. The upper conversion region is surrounded by the isolation region 11. The width of the lower conversion region 133 is greater than the width of the upper conversion region, and the outer edge of the lower conversion region 133 extends laterally beyond the inner edge of the isolation region 11. Furthermore, in this embodiment, the upper conversion region is further configured to include a first conversion portion 131 and a second conversion portion 132 stacked vertically. The width of the second conversion portion 132 is greater than the width of the first conversion portion 131. The isolation region 11 includes a first isolation portion 111 disposed around the first conversion portion 131 and a second isolation portion 112 disposed around the second conversion portion 132. The width of the first isolation portion 111 is greater than the width of the second isolation portion 112, and the outer edge of the second conversion portion 132 extends laterally beyond the inner edge of the first isolation portion 111. Since the electric field is mainly concentrated in the surface area of ​​the substrate 10, in this embodiment, the width of the first isolation portion 111 is set to be greater than the width of the second isolation portion 112. This makes the configuration of the isolation region 11 more adaptable to the working electric field isolation requirements of the pixel structure 1. At the same time, the upper conversion region is further configured to include a first conversion portion 131 and a second conversion portion 132 stacked on top of each other, and the width of the second conversion portion 132 is greater than the width of the first conversion portion 131. This can effectively increase the full-well capacity of the pixel structure 1 as much as possible under this isolation region 11 configuration.

[0087] like Figures 2-9 As shown, then step 2) is performed to form a first current-guiding structure 143, a second current-guiding structure 144, and an electrical isolation layer. The first current-guiding structure 143 extends from the first surface of the substrate 10 toward the second surface into the interior of the substrate 10. The second current-guiding structure 144 is disposed on the first surface of the substrate 10 and is connected to the first current-guiding structure 143. The electrical isolation layer is disposed at the interface between the first current-guiding structure 143 and the substrate 10 and at the interface between the second current-guiding structure 144 and the substrate 10.

[0088] In one embodiment, the specific steps include:

[0089] like Figure 2 As shown, in step 2-1), a first electrical isolation layer 141 is formed on the first surface of the substrate 10, which can be formed by a deposition process or a thermal oxidation process.

[0090] like Figures 2-3As shown, in step 2-2), a mask pattern 151 is formed on the first electrical isolation layer 141 of the substrate 10. The mask pattern 151 can be a photoresist pattern, or the hard mask pattern 151 can be other mask layers that can be used for etching, such as silicon dioxide, silicon nitride, or the above-mentioned stack. Then, based on the mask pattern 151, a trench 152 is formed in the isolation region 11 by an etching process.

[0091] like Figure 5 As shown, in steps 2-3), a second electrical isolation layer 142 is formed on the inner surface of the trench 152, which can be formed by a process such as deposition or thermal oxidation.

[0092] It should be noted that steps 2-1) to 2-3) above can also be replaced by: forming a mask pattern 151 on the first surface of the substrate 10, forming a trench 152 in the isolation region 11 by etching, and removing the mask pattern 151; then simultaneously forming a first electrical isolation layer 141 and a second electrical isolation layer 142 on the first surface of the substrate 10 and the inner surface of the trench 152, wherein the first electrical isolation layer 141 and the second electrical isolation layer 142 can be, for example, silicon dioxide.

[0093] like Figures 6-7 As shown, steps 2-4 are then performed to form a first flow guiding structure 143 in the trench 152 by a deposition process. The first flow guiding structure 143 can be, for example, polysilicon. Then, the mask pattern 151 is removed.

[0094] like Figures 8-9 Then, steps 2-5 are performed to form a second current-conducting structure 144 on the first surface of the substrate 10 through a deposition process and a photolithography-etching process. The second current-conducting structure 144 can be, for example, polycrystalline silicon.

[0095] In an optional example, after removing the mask pattern 151 and before forming the second flow guiding structure 144, the method further includes the step of removing the first electrical isolation layer 141 and forming a reset electrical isolation layer at a corresponding location, wherein the second flow guiding structure 144 is formed on the exposed surfaces of the first electrical isolation layer 141 and the reset electrical isolation layer. The material of the reset electrical isolation layer may be the same as or different from the material of the first electrical isolation layer.

[0096] Additionally, it should be noted that in other embodiments, after forming the trench 152, the mask pattern 151 can be removed, and then deposition can be performed to form the first flow guiding structure 143 and the second flow guiding structure 144.

[0097] like Figures 10-11As shown, in step 3), a charge collection region 16 is formed in the substrate 10. The charge collection region 16 is arranged around one corner of the photoelectric conversion region 13 and is adjacent to the second current guiding structure 144. The second current guiding structure is connected to the first current guiding structure and extends to the charge collection region. The charge collection region and the photoelectric conversion region are located on the same side of the first current guiding structure.

[0098] For example, a charge collection region 16 can be formed in the substrate 10 by ion implantation. At the same time, the charge collection region 16 can be diffused to the underside of the second current guiding structure 144 by annealing, so that the charge collection region 16 and the second current guiding structure 144 partially overlap to facilitate the transport of charge carriers.

[0099] like Figure 11 As shown, in one embodiment, the substrate 10 can be flipped over, and a back deep trench isolation structure 17 can be formed in the second surface of the substrate 10. Since the electric field is mainly concentrated in the upper region of the substrate 10 during the operation of the pixel structure 1, the width of the back deep trench isolation structure 17 can be set to be smaller than the width of the isolation region 11, which can effectively increase the effective area of ​​the lower conversion region 133, thereby increasing the full-well capacity.

[0100] As described above, the pixel structure 1, the method for manufacturing the pixel structure 1, and the shared pixel layout structure of the present invention have the following beneficial effects:

[0101] This invention increases the full-well capacity by using a first current-guiding structure. The charge collection region is not positioned above the photoelectric conversion region (PD) but rather on the periphery of a corner of the PD. Simultaneously, the first current-guiding structure is positioned away from the charge collection region (FD), and the first current-guiding structure and the second current-guiding structure (planar gate) work together to transport charge carriers to the charge collection region. This invention also increases the depth of the PD by doping a shallower region within the PD, thus forming a PD region in the shallower area between the first current-guiding structure and the charge collection region, thereby achieving a higher full-well capacity.

[0102] The present invention places the charge collection region on the periphery of one corner of the photoelectric conversion region. While keeping the junction capacitance of the charge collection region 16 unchanged, it can better accommodate the shared pixel layout structure. The shared pixel layout structure of the present invention is compact and effectively shortens the connection length between the charge collection region and the gate of the source follower transistor, thereby effectively improving the conversion gain of the shared pixel layout structure.

[0103] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A pixel structure, characterized by, The pixel structure includes: The substrate includes a first surface and a second surface that are opposite each other; The photoelectric conversion region is located in the substrate; A charge collection region is disposed in the substrate; The first current-guiding structure extends from the first surface of the substrate toward the second surface into the interior of the substrate, and the charge collection region and the photoelectric conversion region are disposed on the same side of the first current-guiding structure, and the line connecting the photoelectric conversion region and the charge collection region does not cross the first current-guiding structure. A second current-guiding structure is disposed on a first surface of the substrate, the second current-guiding structure is connected to the first current-guiding structure and extends to the charge collection region; An electrical isolation layer is disposed at the interface between the first current-conducting structure and the substrate and at the interface between the second current-conducting structure and the substrate; An isolation region extends from a first surface of the substrate toward a second surface into the interior of the substrate. The isolation region is disposed around the photoelectric conversion region and is an ion-implanted isolation region. The charge collection region is arranged around the first corner of the photoelectric conversion region, the first current guiding structure is disposed in the isolation region around the second corner of the photoelectric conversion region, and the second current guiding structure is disposed on the line connecting the first corner and the second corner.

2. The pixel structure of claim 1, wherein: The charge collection region and the first current guiding structure are located on the longest line connecting any two points on the edge of the photoelectric conversion region.

3. The pixel structure according to claim 1, characterized in that: The lateral distance between the first flow guiding structure and the sidewall of the isolation zone near the photoelectric conversion zone is 0~0.1 micrometers.

4. The pixel structure according to claim 1, characterized in that: The lateral distance between the photoelectric conversion region and the isolation region is 0~0.1 micrometers.

5. The pixel structure according to claim 1, characterized in that: The ion-implanted isolation region has opposite electrical doping to the photoelectric conversion region.

6. The pixel structure according to claim 1, characterized in that: The photoelectric conversion area includes an upper conversion area and a lower conversion area. The upper conversion area is surrounded by the isolation area. The width of the lower conversion area is greater than the width of the upper conversion area, and the outer edge of the lower conversion area extends laterally beyond the inner edge of the isolation area. A back-side deep trench isolation structure is also formed on the periphery of the lower conversion area.

7. The pixel structure according to claim 6, characterized in that: The upper conversion area includes a first conversion portion and a second conversion portion stacked vertically. The width of the second conversion portion is greater than the width of the first conversion portion. The isolation area includes a first isolation portion disposed around the first conversion portion and a second isolation portion disposed around the second conversion portion. The width of the first isolation portion is greater than the width of the second isolation portion. The outer edge of the second conversion portion extends laterally beyond the inner edge of the first isolation portion.

8. The pixel structure according to claim 1, characterized in that: The projection shape of the first flow guiding structure on the substrate surface includes at least one of square, circle, triangle, polygon, and irregular shape; the width of the second flow guiding structure is such that it at least completely covers the projection of the first flow guiding structure on the substrate surface; and / or, the projection shape of the second flow guiding structure on the substrate surface is an axisymmetric figure.

9. The pixel structure according to claim 1, characterized in that: The pixel structure includes two or more first flow guiding structures, the width of the second flow guiding structure being such that it at least simultaneously covers the projections of multiple first flow guiding structures on the substrate surface; and / or, the projection shape of the second flow guiding structure on the substrate surface is an axisymmetric figure.

10. The pixel structure according to claim 1, characterized in that: The cross-sectional shape of the first flow guiding structure includes one of the following: square, inverted trapezoid, and irregular shape.

11. The pixel structure according to claim 1, characterized in that: The first flow guiding structure includes n flow guiding control zones arranged from top to bottom, where n is a positive integer greater than or equal to 2. Among two adjacent flow guiding control zones, the minimum width of the longitudinal cross-sectional shape of the upper flow guiding control zone is greater than the maximum width of the longitudinal cross-sectional shape of the lower flow guiding control zone.

12. A shared pixel layout structure, characterized in that, The shared pixel layout structure includes: At least two pixel structures arranged in a matrix as described in any one of claims 1 to 11; wherein two adjacent pixel structures share one charge collection region; A source follower transistor is used in at least two pixel structures that share the same charge collection region, and the gate of the source follower transistor is electrically connected to the corresponding charge collection region.

13. The shared pixel layout structure according to claim 12, characterized in that, The shared pixel layout structure includes: The four pixel structures are arranged in a matrix, and the four pixel structures share two charge collection areas, which are arranged facing each other in the middle of the matrix. Two adjacent first pixel structures share one first charge collection area, and two adjacent second pixel structures share one second charge collection area. The source follower transistor is disposed between the first charge collection region and the second charge collection region.

14. The shared pixel layout structure according to claim 12, characterized in that: The shared pixel layout structure further includes a reset transistor disposed between two rows of pixel structures and arranged along the row direction; and / or, the shared pixel layout structure further includes a selection transistor disposed between two columns of pixel structures and arranged along the column direction; and / or, the shared pixel layout structure further includes a conversion gain transistor, wherein when the shared pixel layout structure further includes a reset transistor, the conversion gain transistor is disposed between the reset transistor and the corresponding charge collection region.

15. An electronic device, characterized in that, The electronic device includes the pixel structure as described in any one of claims 1 to 11 or the shared pixel layout structure as described in any one of claims 12 to 14.

16. A method for fabricating a pixel structure as described in any one of claims 1-11, characterized in that, Including the following steps: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; An isolation region is formed, which extends from a first surface of the substrate toward a second surface into the interior of the substrate, and the isolation region is an ion-implanted isolation region; A photoelectric conversion region is formed in the substrate, and the isolation region is disposed around the photoelectric conversion region; A first current-guiding structure, a second current-guiding structure, and an electrical isolation layer are formed. The first current-guiding structure extends from a first surface of the substrate toward a second surface into the interior of the substrate. The second current-guiding structure is disposed on the first surface of the substrate and is connected to the first current-guiding structure. The electrical isolation layer is disposed at the interface between the first current-guiding structure and the substrate and at the interface between the second current-guiding structure and the substrate. The first current-guiding structure is disposed within the isolation region. A charge collection region is formed in the substrate. The second current-guiding structure is connected to the first current-guiding structure and extends to the charge collection region. The charge collection region and the photoelectric conversion region are disposed on the same side of the first current-guiding structure. The line connecting the photoelectric conversion region and the charge collection region does not cross the first current-guiding structure. The charge collection region is arranged around the first corner of the photoelectric conversion region. The first current-guiding structure is disposed in the isolation region around the second corner of the photoelectric conversion region. The second current-guiding structure is disposed on the line connecting the first corner and the second corner.

17. The method for fabricating a pixel structure according to claim 16, characterized in that, The steps of forming the first current-guiding structure, the second current-guiding structure, and the electrical isolation layer include: A first electrical isolation layer is formed on the first surface of the substrate; A mask pattern is formed on the first electrical isolation layer, and a trench is formed in the isolation region based on the mask pattern; A second electrical isolation layer is formed on the inner surface of the trench; The first flow guiding structure is formed in the trench, and the mask pattern is removed; The second flow-guiding structure is formed on the first surface of the substrate.

18. The method for fabricating a pixel structure according to claim 17, characterized in that, After removing the mask pattern and before forming the second flow guiding structure, the method further includes the step of removing the first electrical isolation layer and forming a reset electrical isolation layer at the corresponding location, wherein the material of the reset electrical isolation layer is the same as or different from the material of the first electrical isolation layer.

19. The method for fabricating a pixel structure according to any one of claims 16-18, characterized in that, The steps of the method for fabricating the pixel structure also include: Before forming the photoelectric conversion region, an isolation region is formed in the substrate, extending from the first surface of the substrate toward the second surface and into the interior of the substrate; wherein the isolation region is located on the periphery of the photoelectric conversion region, and the first current guiding structure is disposed within the isolation region.

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