An intelligent reset circuit for MCU chip

Abstract

The present invention discloses an intelligent reset circuit for an MCU chip, which relates to the field of reset technology and includes a signal generation module for generating bias current and voltage detection; a shaping processing module for signal shaping and inversion processing; a signal latch module for generating a power-on reset signal; a manual reset module for manual reset control; an RC filter module for signal filtering and anti-interference processing; a hold control module for signal hold; a reset control module for controlling the operation of the signal generation module; and an MCU module for resetting the MCU chip. The intelligent reset circuit of the MCU chip of the present invention comprises a signal generation module for detecting the electrical energy input to the MCU module and cooperating with the shaping processing module for signal processing, so that the signal latch module generates a power-on reset signal when power is on, filters the signal and performs anti-interference processing, and simultaneously shuts down the signal generation module after reset and holds the power-on reset signal to complete reset control.

Description

Technical Field

[0001] The present invention relates to the field of reset technology, in particular to an intelligent reset circuit for an MCU chip. Background Art

[0002] With the development of digital technology, the integration of MCU chips has been continuously improved, and the ability of a single MCU chip to integrate complex modules has been enhanced. Among them, the reset circuit is an indispensable part of the MCU chip, providing a reset signal for the MCU chip to ensure the normal startup of the entire system. Most of the existing MCU chip reset circuits use a voltage sampling circuit to detect the power supply voltage and determine whether the MCU chip enters the initial working state based on the change of the power supply voltage. In addition, the reset circuit of the existing MCU chip is relatively simple, and the reset signal changes with the change of the jump voltage, resulting in repeated resets and erroneous operations. Moreover, after the reset is completed, the reset circuit is still in the working state, resulting in unnecessary power consumption, so it needs to be improved. Summary of the Invention

[0003] An embodiment of the present invention provides an intelligent reset circuit for an MCU chip to solve the problems raised in the above background technology.

[0004] According to an embodiment of the present invention, an intelligent reset circuit for an MCU chip is provided. The intelligent reset circuit for the MCU chip includes: a power supply module, a signal generating module, a shaping processing module, a signal latch module, an RC filtering module, a holding control module, a manual reset module, a reset control module, and an MCU module;

[0005] The power supply module is used to provide the required working power;

[0006] The signal generating module is connected to the power module, and is used to generate a bias current and transmit it through a current mirror circuit, and is used to detect the electric energy output by the power module through a voltage detection circuit and output a detection voltage signal;

[0007] The shaping processing module is connected to the signal generating module and is used to shape and invert the detection voltage signal through a Schmidt inversion circuit and output a step signal;

[0008] The signal latch module is connected to the shaping processing module and the signal generating module, and is used to receive the step signal through the logic control circuit and output a level signal, and is used to input the level signal and the bias current into the D trigger circuit and generate a power-on reset signal;

[0009] The manual reset module is connected to the reset control module, the RC filter module and the hold control module, and is used to manually input a reset control signal and transmit the reset control signal to the reset control module, the RC filter module and the hold control module;

[0010] The RC filter module is connected to the signal latch module, and is used to filter and perform anti-interference processing on the power-on reset signal and reset control signal through the RC filter circuit and transmit the processed power-on reset signal and reset control signal to the MCU module;

[0011] The holding control module is connected to the signal latch module and is used to receive the power-on reset signal and the reset control signal and to perform holding control on the power-on reset signal and the reset control signal through a holding control circuit;

[0012] The reset control module is connected to the signal generating module and the signal latch module, receives the power-on reset signal and the reset control signal and controls the working state of the signal generating module;

[0013] The MCU module is connected to the RC filter module and the holding control module, and is used to receive signals from the RC filter module and the holding control module and control the reset of the MCU chip.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: the intelligent reset circuit of the MCU chip of the present invention detects the power status of the input MCU module through the voltage detection circuit by the signal generating module, and shapes and inverts the detected voltage signal according to the voltage change and cooperates with the Schmidt inversion circuit to output a step signal, so as to generate a power-on reset signal when power is turned on through the D trigger circuit, and the RC filter module performs filtering and anti-interference processing to improve the accuracy of the power-on reset signal. At the same time, the reset control module shuts down the operation of the signal generating module, reduces the power loss of the circuit after the reset is generated, and maintains the signal by the control module to avoid the erroneous operation of repeated reset due to power jump, and can also directly perform manual reset control through the manual reset module, and the circuit is convenient and effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 The present invention provides a block diagram of the principle of an intelligent reset circuit for an MCU chip.

[0017] Figure 2 This is a circuit diagram of an intelligent reset circuit for an MCU chip provided by an example of the present invention.

[0018] Figure 3 This is a connection circuit diagram of the manual reset module provided by an example of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0020] Example 1, please refer to Figure 1 , an intelligent reset circuit of an MCU chip includes: a power supply module 1, a signal generating module 2, a shaping processing module 3, a signal latch module 4, an RC filtering module 5, a holding control module 6, a manual reset module 7, a reset control module 8, and an MCU module 9;

[0021] Specifically, the power module 1 is used to provide the required working power;

[0022] a signal generating module 2 connected to the power module 1, configured to generate a bias current and transmit the bias current through a current mirror circuit, and to detect the power output by the power module 1 through a voltage detection circuit and output a detection voltage signal;

[0023] a shaping processing module 3 connected to the signal generating module 2, configured to shape and invert the detection voltage signal through a Schmidt inversion circuit and output a step signal;

[0024] a signal latch module 4 connected to the shaping processing module 3 and the signal generating module 2, configured to receive the step signal through a logic control circuit and output a level signal, and to input the level signal and a bias current into a D trigger circuit and generate a power-on reset signal;

[0025] A manual reset module 7 is connected to the reset control module 8, the RC filter module 5 and the hold control module 6, and is used to manually input a reset control signal and transmit the reset control signal to the reset control module 8, the RC filter module 5 and the hold control module 6;

[0026] An RC filter module 5 is connected to the signal latch module 4 and is used to filter and perform anti-interference processing on the power-on reset signal and reset control signal through an RC filter circuit and transmit the processed power-on reset signal and reset control signal to the MCU module 9;

[0027] A holding control module 6, connected to the signal latch module 4, for receiving the power-on reset signal and the reset control signal and performing holding control on the power-on reset signal and the reset control signal through a holding control circuit;

[0028] A reset control module 8 is connected to the signal generating module 2 and the signal latch module 4, and receives the power-on reset signal and the reset control signal and controls the working state of the signal generating module 2;

[0029] The MCU module 9 is connected to the RC filter module 5 and the holding control module 6, and is used to receive signals from the RC filter module 5 and the holding control module 6 and control the reset of the MCU chip.

[0030] In a specific embodiment, the power supply module 1 can use a regulated DC power supply to provide the required electrical energy for the circuit, which will not be elaborated here; the signal generating module 2 can use a current mirror circuit and a voltage detection circuit, the current mirror circuit generates the bias current required by the circuit, and the voltage detection circuit detects and determines the change of electrical energy input to the MCU module 9; the shaping processing module 3 can use a Schmidt inversion circuit to shape and invert the detected voltage signal and output a step signal; the signal latch module 4 can use a logic control circuit and a D trigger circuit, the logic control circuit converts the input step signal into a level signal, and the D trigger circuit generates a power-on signal. Reset signal; the above-mentioned RC filter module 5 can adopt an RC filter circuit composed of an RC adjustment circuit and a signal conditioning module to filter and shape the input power-on reset signal; the above-mentioned hold control module 6 can adopt a hold control circuit composed of a negative edge trigger circuit and a logic control circuit to hold the power-on reset signal for output; the above-mentioned manual reset module 7 can adopt a button-type signal generating circuit to manually output the reset control signal; the above-mentioned reset control module 8 can adopt a power tube circuit to control the working state of the above-mentioned signal generating module 2; the above-mentioned MCU module 9 adopts an MCU circuit for receiving the power-on reset signal and the reset control signal, which will not be repeated here.

[0031] Example 2, based on Example 1, please refer to Figure 2 and Figure 3 The power supply module 1 includes a first power supply VCC1; the signal generating module 2 includes a first resistor R1, a first power tube M1, a second power tube M2, an eighth power tube M8, and an eleventh power tube M11;

[0032] Specifically, the first power supply VCC1 is connected to one end of the first resistor R1, the source of the first power tube M1, the source of the second power tube M2, the source of the eighth power tube M8, and the source of the eleventh power tube M11; the drain of the first power tube M1 is connected to the other end of the first resistor R1; the gate of the first power tube M1 is connected to the gate of the second power tube M2, the gate of the eighth power tube M8, and the gate of the eleventh power tube M11; and the drain of the eleventh power tube M11 is connected to the signal latch module 4.

[0033] In a specific embodiment, the first resistor R1, the first power tube M1, the second power tube M2, the eighth power tube M8, and the eleventh power tube M11 form a current mirror circuit to generate a bias current and replicate and transmit the bias current in a depletion mode. The first power tube M1, the second power tube M2, the eighth power tube M8, and the eleventh power tube M11 can all be P-channel depletion-type MOS tubes.

[0034] Furthermore, the signal generating module 2 further includes a sixth power tube M6, a fifth power tube M5, a seventh power tube M7, and a second resistor R2;

[0035] Specifically, the drain of the sixth power tube M6 is connected to the gate of the fifth power tube M5 and the reset control module 8, the drain of the fifth power tube M5 is connected to the drain of the second power tube M2, the source of the fifth power tube M5 is connected to the gate of the sixth power tube M6, the gate of the seventh power tube M7 and the first end of the second resistor R2, the source of the sixth power tube M6, the second end of the second resistor R2 and the source of the seventh power tube M7 are all grounded, and the drain of the seventh power tube M7 is connected to the drain of the eighth power tube M8 and the shaping processing module 3.

[0036] In a specific embodiment, the sixth power tube M6, the fifth power tube M5, and the seventh power tube M7 may all be N-channel depletion-type MOS tubes to form a voltage detection circuit. The sixth power tube M6, the fifth power tube M5, and the seventh power tube M7 are controlled to be turned on and off according to the change of the power supply voltage after power-on, thereby controlling the potential of the input shaping processing module 3.

[0037] Furthermore, the shaping processing module 3 includes a first shaper U1;

[0038] Specifically, a first end of the first shaper U1 is connected to the drain of the eighth power tube M8 and the drain of the seventh power tube M7 , and a second end of the first shaper U1 intercepts the signal latch module 4 .

[0039] In a specific embodiment, the first shaper U1 may be a Schmitt inverter, with no limitation on the specific model, which shapes and inverts the input voltage signal and outputs a step signal.

[0040] Furthermore, the signal latch module 4 includes a first logic chip U2, a tenth power tube M10, a first capacitor C1 and a first trigger J1;

[0041] Specifically, a first input terminal of the first logic chip U2 is connected to the second terminal of the first shaper U1, a second input terminal of the first logic chip U2 is connected to the fifth terminal of the first trigger J1, a first output terminal of the first logic chip U2 is connected to the gate of the tenth power transistor M10, a drain terminal of the tenth power transistor M10 is connected to the drain terminal of the eleventh power transistor M11, one terminal of the first capacitor C1, and the second terminal of the first trigger J1. The source terminal of the tenth power transistor M10 and the other terminal of the first capacitor C1 are both grounded, a first terminal of the first trigger J1 is connected to the first power supply VCC1, a fourth terminal of the first trigger J1 is connected to the reset control module 8, the RC filter module 5, and the hold control module 6, and a third terminal of the first trigger J1 is connected to the second terminal of the first shaper U1.

[0042] In a specific embodiment, the first logic chip U2 can be a NAND gate logic chip to control the working state of the tenth power tube M10 and the potential voltage of the first capacitor C1; the first trigger J1 can be a D trigger to output a high level signal, that is, a power-on reset signal.

[0043] Furthermore, the reset control module 8 includes a first inverter INV1, a ninth power tube M9 and a third power tube M3;

[0044] Specifically, a first end of the first inverter INV1 is connected to the fourth end of the first trigger J1 and the gate of the third power tube M3, a second end of the first inverter INV1 is connected to the gate of the ninth power tube M9, a source of the ninth power tube M9 is connected to the first power supply VCC1, a drain of the ninth power tube M9 is connected to the gate of the eighth power tube M8, a source of the third power tube M3 is connected to the drain of the first power tube M1, and a drain of the third power tube M3 is connected to the gate of the fifth power tube M5.

[0045] In a specific embodiment, both the ninth power tube M9 and the third power tube M3 can be P-channel depletion-type MOS tubes, which are used to control the operation of the signal generating module 2 .

[0046] Furthermore, the RC filter module 5 includes a second inverter INV2, a first control tube Q1, a third resistor R3, a second control tube Q2, and a second capacitor C2;

[0047] Specifically, the first end of the second inverter INV2 is connected to the fourth end of the first trigger J1, the second end of the second inverter INV2 is connected to the gate of the first control tube Q1 and the gate of the second control tube Q2, the drain of the first control tube Q1 is connected to the drain of the second control tube Q2 and the first end of the second capacitor C2 through the third resistor R3, the source of the first power tube M1 is connected to the first power supply VCC1, and the source of the second control tube Q2 and the second end of the second capacitor C2 are both grounded.

[0048] In a specific embodiment, the first control transistor Q1 and the second control transistor Q2 can both be P-channel enhancement mode MOS transistors, which cooperate with the third resistor R3 and the second capacitor C2 to filter out interference signals with a certain pulse width.

[0049] Furthermore, the RC filter module 5 further includes a second trigger J2, a third inverter INV3 and a fourth inverter INV4; the MCU module 9 includes an MCU chip;

[0050] Specifically, the first end of the second trigger J2 is connected to the first end of the second capacitor C2, the second end of the second trigger J2 is connected to the first end of the third inverter INV3, the second end of the third inverter INV3 is connected to the first end of the fourth inverter INV4, the second end of the fourth inverter INV4 is connected to the reset end of the MCU chip, and the power end of the MCU chip is connected to the first power supply VCC1.

[0051] In a specific embodiment, the second trigger J2 can be a Schmitt trigger, with no limitation on the specific model, which cooperates with the third inverter INV3 and the fourth inverter INV4 to eliminate the pulse signal in the circuit and transmit it as a level signal.

[0052] Furthermore, the holding control module 6 includes a third trigger J3 and a second logic chip U3;

[0053] Specifically, the first input terminal and the second input terminal of the third trigger J3 are respectively connected to the first terminal and the second terminal of the first inverter INV1, the first output terminal and the second output terminal of the third trigger J3 are respectively connected to the first input terminal and the second input terminal of the second logic chip U3, and the first output terminal of the second logic chip U3 is connected to the reset terminal of the MCU chip.

[0054] In a specific embodiment, the third trigger J3 can be a negative-edge trigger, and the second logic chip U3 can be an XOR gate logic chip to stabilize the output signal.

[0055] Furthermore, the manual reset module 7 includes a second power supply VCC2, a first diode D1, a first key switch S1, a fourth resistor R4, a third capacitor C3, a fifth inverter INV5, and a sixth inverter INV6;

[0056] Specifically, the second power supply VCC2 is connected to the cathode of the first diode D1 and one end of the fourth resistor R4, the anode of the first diode D1 is connected to the other end of the fourth resistor R4, one end of the first push switch S1, one end of the third capacitor C3 and the first end of the sixth inverter INV6, the other end of the first push switch S1 and the other end of the third capacitor C3 are both grounded, the second end of the sixth inverter INV6 is connected to the first end of the fifth inverter INV5, and the second end of the fifth inverter INV5 is connected to the first input end of the third trigger J3, the gate of the third power tube M3 and the first end of the second inverter INV2.

[0057] In a specific embodiment, the first key switch S1 is used to control the power input to the sixth inverter INV6. The sixth inverter INV6 and the fifth inverter INV5 perform inversion processing to convert the unstable voltage signal into a level signal, namely, a reset control signal.

[0058] The present invention provides an intelligent reset circuit for an MCU chip. A first power supply VCC1 provides power to the MCU chip. Before power-on, the fourth terminal of the first trigger J1 is at a low level, and the third power tube M3 is turned on. After power-on, the first power tube M1, the second power tube M2, the eighth power tube M8, and the eleventh power tube M11 generate a bias current. The second resistor R2, the sixth power tube M6, the fifth power tube M5, and the seventh power tube M7 detect the power-on power. When the power reaches a set required power-on voltage, the potential of the potential point between the drain of the seventh power tube M7 and the drain of the eighth power tube M8 is pulled down to ground. The first shaper U1 shapes and inverts the potential point and outputs a high-level signal. At the same time, the high-level signal controls the first trigger J1 to reset, so that the fifth terminal of the first trigger J1 cooperates with the high-level signal to control the output of the first logic chip U2. Low level, controls the tenth power tube M10 to be turned off, and the first capacitor C1 starts to charge, so that the potential of the second end of the first trigger J1 increases, and the first trigger J1 outputs a power-on reset signal, controls the third power tube M3 to be turned off, and controls the ninth power tube M9 to be turned on through the first inverter INV1, and shuts down the operation of the signal generating module 2. At the same time, the output power-on reset signal is filtered out of the pulse interference signal through the RC filter module 5, and the processed signal is transmitted to the reset end of the MCU chip to complete the reset control of the MCU chip. At the same time, in order to avoid the situation where the power output by the power module 1 is powered off and powered on again, the third trigger J3 and the second logic chip U3 will stably output the power-on reset signal to avoid repeated reset control of the MCU chip. In addition, by pressing the first button switch S1, the fifth inverter INV5 outputs a reset control signal to manually control the reset work of the MCU chip.

[0059] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0060] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An intelligent reset circuit for an MCU chip, characterized in that: The intelligent reset circuit of the MCU chip includes: a power supply module, a signal generation module, a shaping processing module, a signal latch module, an RC filter module, a hold control module, a manual reset module, a reset control module, and an MCU module; The power supply module is used to provide the required working power; The signal generating module is connected to the power module, and is used to generate a bias current and transmit it through a current mirror circuit, and is used to detect the electric energy output by the power module through a voltage detection circuit and output a detection voltage signal; The shaping processing module is connected to the signal generating module and is used to shape and invert the detection voltage signal through a Schmidt inversion circuit and output a step signal; The signal latch module is connected to the shaping processing module and the signal generating module, and is used to receive the step signal through the logic control circuit and output a level signal, and is used to input the level signal and the bias current into the D trigger circuit and generate a power-on reset signal; The manual reset module is connected to the reset control module, the RC filter module and the hold control module, and is used to manually input a reset control signal and transmit the reset control signal to the reset control module, the RC filter module and the hold control module; The RC filter module is connected to the signal latch module, and is used to filter and perform anti-interference processing on the power-on reset signal and reset control signal through the RC filter circuit and transmit the processed power-on reset signal and reset control signal to the MCU module; The holding control module is connected to the signal latch module and is used to receive the power-on reset signal and the reset control signal and to perform holding control on the power-on reset signal and the reset control signal through a holding control circuit; The reset control module is connected to the signal generating module and the signal latch module, receives the power-on reset signal and the reset control signal and controls the working state of the signal generating module; The MCU module is connected to the RC filter module and the holding control module, and is used to receive signals from the RC filter module and the holding control module and control the reset of the MCU chip.

2. The intelligent reset circuit of an MCU chip according to claim 1, characterized in that: The power supply module includes a first power supply; the signal generating module includes a first resistor, a first power tube, a second power tube, an eighth power tube, and an eleventh power tube; The first power supply is connected to one end of the first resistor, the source of the first power tube, the source of the second power tube, the source of the eighth power tube and the source of the eleventh power tube, the drain of the first power tube is connected to the other end of the first resistor, the gate of the first power tube is connected to the gate of the second power tube, the gate of the eighth power tube and the gate of the eleventh power tube, and the drain of the eleventh power tube is connected to the signal latch module.

3. The intelligent reset circuit of an MCU chip according to claim 2, characterized in that: The signal generating module further includes a sixth power tube, a fifth power tube, a seventh power tube, and a second resistor; The drain of the sixth power tube is connected to the gate of the fifth power tube and the reset control module, the drain of the fifth power tube is connected to the drain of the second power tube, the source of the fifth power tube is connected to the gate of the sixth power tube, the gate of the seventh power tube and the first end of the second resistor, the source of the sixth power tube, the second end of the second resistor and the source of the seventh power tube are all grounded, and the drain of the seventh power tube is connected to the drain of the eighth power tube and the shaping processing module.

4. The intelligent reset circuit of an MCU chip according to claim 3, characterized in that: The shaping processing module includes a first shaper; The first end of the first shaper is connected to the drain of the eighth power tube and the drain of the seventh power tube, and the second end of the first shaper intercepts the signal latch module.

5. The intelligent reset circuit of an MCU chip according to claim 4, characterized in that: The signal latch module includes a first logic chip, a tenth power tube, a first capacitor and a first trigger; The first input terminal of the first logic chip is connected to the second terminal of the first shaper, the second input terminal of the first logic chip is connected to the fifth terminal of the first trigger, the first output terminal of the first logic chip is connected to the gate of the tenth power tube, and the drain of the tenth power tube is connected to the drain of the eleventh power tube, one terminal of the first capacitor, and the second terminal of the first trigger; The source of the tenth power tube and the other end of the first capacitor are both grounded, the first end of the first trigger is connected to the first power supply, the fourth end of the first trigger is connected to the reset control module, the RC filter module and the hold control module, and the third end of the first trigger is connected to the second end of the first shaper.

6. The intelligent reset circuit of an MCU chip according to claim 5, characterized in that: The reset control module includes a first inverter, a ninth power tube and a third power tube; The first end of the first inverter is connected to the fourth end of the first trigger and the gate of the third power tube, the second end of the first inverter is connected to the gate of the ninth power tube, the source of the ninth power tube is connected to the first power supply, the drain of the ninth power tube is connected to the gate of the eighth power tube, the source of the third power tube is connected to the drain of the first power tube, and the drain of the third power tube is connected to the gate of the fifth power tube.

7. The intelligent reset circuit of an MCU chip according to claim 6, characterized in that: The RC filter module includes a second inverter, a first control tube, a third resistor, a second control tube, and a second capacitor; The first end of the second inverter is connected to the fourth end of the first trigger, the second end of the second inverter is connected to the gate of the first control tube and the gate of the second control tube, the drain of the first control tube is connected to the drain of the second control tube and the first end of the second capacitor through the third resistor, the source of the first power tube is connected to the first power supply, and the source of the second control tube and the second end of the second capacitor are both grounded.

8. The intelligent reset circuit of an MCU chip according to claim 7, characterized in that: The RC filter module further includes a second trigger, a third inverter and a fourth inverter; the MCU module includes an MCU chip; The first end of the second trigger is connected to the first end of the second capacitor, the second end of the second trigger is connected to the first end of the third inverter, the second end of the third inverter is connected to the first end of the fourth inverter, the second end of the fourth inverter is connected to the reset end of the MCU chip, and the power end of the MCU chip is connected to the first power supply.

9. The intelligent reset circuit of an MCU chip according to claim 8, characterized in that: The holding control module includes a third trigger and a second logic chip; The first input terminal and the second input terminal of the third trigger are respectively connected to the first terminal and the second terminal of the first inverter, the first output terminal and the second output terminal of the third trigger are respectively connected to the first input terminal and the second input terminal of the second logic chip, and the first output terminal of the second logic chip is connected to the reset terminal of the MCU chip.

10. The intelligent reset circuit of an MCU chip according to claim 9, characterized in that: The manual reset module includes a second power supply, a first diode, a first key switch, a fourth resistor, a third capacitor, a fifth inverter, and a sixth inverter; The second power supply is connected to the cathode of the first diode and one end of the fourth resistor, the anode of the first diode is connected to the other end of the fourth resistor, one end of the first push switch, one end of the third capacitor and the first end of the sixth inverter, the other end of the first push switch and the other end of the third capacitor are both grounded, the second end of the sixth inverter is connected to the first end of the fifth inverter, and the second end of the fifth inverter is connected to the first input end of the third trigger, the gate of the third power tube and the first end of the second inverter.

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