1.5T one-time programmable memory and method of making the same

Abstract

The present application relates to a 1.5T one-time programmable memory and a manufacturing method thereof. The 1.5T one-time programmable memory comprises at least one 1.5T memory cell formed in an active region of a semiconductor substrate, the 1.5T memory cell comprises a half of a select transistor and a ground transistor, the structure is simple, and a part of a thin gate dielectric layer in the ground transistor is clamped between a junction doped region connected to a source region of the select transistor and a ground gate, during programming of the corresponding 1.5T memory cell, a drain region voltage of the select transistor can be coupled to the junction doped region, and the thin gate dielectric layer clamped between the junction doped region and the ground gate is broken down, and the programming voltage is smaller.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a 1.5T one-time programmable memory and its manufacturing method. Background Technology

[0002] One-Time Programmable (OTP) memory technology has been adopted in post-silicon verification, memory repair, in-circuit testing, and secure information storage. For example, during memory repair, defective addresses can be recorded in OTP memory. When an externally provided address is a defective address, the semiconductor circuit can repair the device by accessing a redundant memory cell instead of the defective one. Furthermore, to address security issues such as potential information leaks, unauthorized access, or malware attacks in IoT devices, OTP memory can be used to store information to prevent reprogramming.

[0003] Commonly used OTP memory uses the antifuse mechanism for programming, which uses two conductors and a dielectric layer sandwiched between them to form an antifuse. The antifuse is not conductive in the unprogrammed state. During programming, a high voltage is applied between the two conductors, causing the dielectric layer to break down and generate current to conduct electricity.

[0004] However, conventional OTP memory uses a more complex structure and manufacturing process, which increases the difficulty of reducing chip area and cost, and the programming voltage that breaks down the dielectric layer between conductors is relatively large. Summary of the Invention

[0005] To address the issues of complex structure and manufacturing process, as well as high programming voltage in existing OTP memories, this invention provides a method for manufacturing a 1.5T one-time programmable memory and a 1.5T one-time programmable memory.

[0006] On one hand, the present invention provides a method for manufacturing a 1.5T one-time programmable memory, comprising:

[0007] A semiconductor substrate is provided, the semiconductor substrate including an active region;

[0008] A gate dielectric layer is formed on the surface of the semiconductor substrate;

[0009] A barrier material layer is formed on the gate dielectric layer, and the barrier material layer is etched to form a barrier element;

[0010] The portion of the gate dielectric layer not covered by the barrier is thickened to form a thick gate dielectric layer, while the portion of the gate dielectric layer not thickened forms a thin gate dielectric layer;

[0011] The barrier is etched to narrow its width, thereby exposing portions of the thin gate dielectric layer on both sides of the barrier.

[0012] Junction-doped regions are formed in the active regions on both sides of the barrier;

[0013] A grounding grid is formed, the grounding grid covering the barrier and the exposed portions of the thin grid dielectric layer on both sides of the barrier;

[0014] Selective gates are formed on both sides of the grounding gate, the selective gates being located on the thick gate dielectric layer; and

[0015] A source region and a drain region are formed in the active region. The source region is located between the ground gate and the select gate. The drain region is located on the other side of the select gate relative to the source region. The source region is doped with the same type as and connected to a junction doped region.

[0016] Optionally, the barrier can be etched using an isotropic wet etching process to narrow the width of the barrier.

[0017] Optionally, the exposed portions of the thin gate dielectric layer on both sides of the barrier are of equal width.

[0018] Optionally, the width of the portion of the thin gate dielectric layer exposed on both sides of the barrier is 2nm to 100nm.

[0019] Optionally, the barrier element includes at least one of silicon nitride, silicon oxynitride, and silicon carbide.

[0020] Optionally, the thickness of the thin gate dielectric layer ranges from 1 nm to 5 nm, and the thickness of the thick gate dielectric layer ranges from 3 nm to 15 nm.

[0021] Optionally, forming the junction doped region includes:

[0022] A patterned photoresist layer is formed on the thick gate dielectric layer, the patterned photoresist layer exposing the barrier, the thin gate dielectric layers on both sides of the barrier, and a portion of the thick gate dielectric layer connected to the thin gate dielectric layer;

[0023] Phosphorus ion implantation is performed at an energy of 30 keV to 40 keV and a dose of 5 E12 / cm². 2 ~5E13 / cm 2 ;as well as

[0024] Arsenic ion implantation is performed at an energy of 15 keV to 30 keV and a dose of 1E15 / cm². 2 ~5E15 / cm 2 .

[0025] Optionally, after forming the source region and the drain region, the fabrication method further includes:

[0026] Remove the thick gate dielectric layer exposed on both sides of the ground gate and both sides of the select gate, and form a self-aligned metal silicide layer on the exposed semiconductor substrate surface, the ground gate surface and the select gate surface;

[0027] An interlayer dielectric layer is formed, which fills the gap between the ground gate and the select gate and covers the ground gate and the select gate; and

[0028] A bit line is formed on the interlayer dielectric layer, and the drain region is connected to the bit line through a contact plug that penetrates the interlayer dielectric layer.

[0029] On one hand, the present invention provides a 1.5T one-time programmable memory, comprising at least one 1.5T memory cell formed in an active region of a semiconductor substrate. The 1.5T memory cell includes a select transistor and half of a ground transistor. The select transistor includes a thick gate dielectric layer formed on the semiconductor substrate, a select gate located on the thick gate dielectric layer, and a drain region and a source region respectively formed in the active region on both sides of the select gate. The ground transistor includes:

[0030] Thin gate dielectric layer;

[0031] A barrier element is formed on the thin gate dielectric layer, with portions of the thin gate dielectric layer exposed on both sides of the barrier element;

[0032] A grounding grid is formed on the barrier and the exposed thin grid dielectric layer;

[0033] Junction doped regions are formed in the active regions on both sides of the barrier, and the source region of the select transistor is of the same doping type as and connected to one of the junction doped regions.

[0034] Optionally, the 1.5T one-time programmable memory includes multiple pairs of the 1.5T memory cells to form a memory array; and the ground gate connection in the multiple pairs of the 1.5T memory cells forms at least one ground gate line, the select gate connection in the multiple pairs of the 1.5T memory cells forms at least two word lines, and the drain region of the select transistor in the multiple pairs of the 1.5T memory cells is connected to at least one bit line.

[0035] The manufacturing method of the 1.5T one-time programmable memory provided by this invention has a simple process flow and low cost. The manufactured 1.5T one-time programmable memory has a simple layout. The select gate and the source region and drain region on both sides constitute the select transistor of the 1.5T memory cell. The ground gate corresponds to the ground transistor of the 1.5T memory cell. Part of the thin gate dielectric layer is sandwiched between the junction doped region connecting the source region and the ground gate. When programming the corresponding 1.5T memory cell, one-time programming can be achieved by coupling the drain voltage of the select transistor to the junction doped region below the ground transistor and causing the thin gate dielectric layer sandwiched between the junction doped region and the ground gate line to break down. The programming voltage is relatively small.

[0036] The 1.5T one-time programmable memory provided by the present invention includes at least one 1.5T memory cell formed in the active region of a semiconductor substrate. The 1.5T memory cell includes a select transistor and half of a ground transistor, with a simple structure. Furthermore, a portion of the thin gate dielectric layer in the ground transistor is sandwiched between the junction doped region connecting the source region of the select transistor and the ground gate. When programming the corresponding 1.5T memory cell, the drain voltage of the select transistor can be coupled to the junction doped region, causing the thin gate dielectric layer sandwiched between the junction doped region and the ground gate to break down, resulting in a lower programming voltage. Attached Figure Description

[0037] Figure 1 This is a circuit diagram of a 1.5T one-time programmable memory according to an embodiment of the present invention.

[0038] Figure 2 This is a planar schematic diagram of a 1.5T one-time programmable memory according to an embodiment of the present invention.

[0039] Figures 3 to 8 This is a schematic cross-sectional view of the fabrication method of a 1.5T one-time programmable memory in one embodiment of the present invention, showing the structure formed at different steps.

[0040] Figure 9 yes Figure 8 The circuit diagram shown is of a pair of mirrored 1.5T storage cells.

[0041] Figure 10 This is a cross-sectional structural diagram of a 1.5T storage cell selected for programming and another 1.5T storage cell in one embodiment of the present invention. Detailed Implementation

[0042] The 1.5T one-time programmable memory and its manufacturing method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, intended only to facilitate clear explanation of the embodiments of the present invention. Furthermore, spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships. While components in the figures are easily identifiable in all figures if they are identical to those already labeled, not all identical components will be labeled and described in the figures and hereinafter to make the description clearer.

[0043] This invention relates to a method for fabricating a 1.5T one-time programmable memory. The 1.5T one-time programmable memory includes at least one 1.5T memory cell formed in an active region of a semiconductor substrate. Each 1.5T memory cell includes one select transistor and half of a ground transistor (a total of 1.5 transistors, abbreviated as 1.5T). The 1.5T one-time programmable memory may include a memory array composed of multiple 1.5T memory cells, such as... Figure 1 As shown, the area within the dashed box represents a 1.5T memory cell. The gates (i.e., select gates) of each select transistor are connected to word lines (WL0, WL1, ...), the drain regions are connected to bit lines (BL0, BL1, BL2, BL3, BL4, BL5, ...), and the source regions are connected to ground transistors. The gates (i.e., ground gates) of the ground transistors are connected to ground gate lines (GND).

[0044] The following combination Figures 2 to 8 The manufacturing method is explained, including Figures 3 to 8 The cross-sectional structure shown corresponds to Figure 2 Longitudinal section along the AA' direction.

[0045] Reference Figure 2 and Figure 3First, a semiconductor substrate 100 is provided, which includes an isolation region (such as shallow trench isolation, STI) and a plurality of active areas 10 defined by the isolation region. The semiconductor substrate 100 may be a silicon substrate or other suitable substrate, such as an N-type doped silicon substrate (N-Si, doped with phosphorus or arsenic) or a P-type doped silicon substrate (P-Si, doped with boron, boron difluoride, or indium). N-type or P-type doped well regions may also be selectively formed within the semiconductor substrate 100. The 1.5T one-time programmable memory of this embodiment can be formed on the N-type or P-type doped regions of the semiconductor substrate 100. The following description uses a P-type doped silicon substrate (P-Si) on which an N-channel transistor is formed. It is understood that a P-channel transistor can be obtained by interchangeing N-type and P-type doping.

[0046] Reference Figure 3 Next, a gate dielectric layer 101 and a barrier material layer 102 located on the gate dielectric layer 101 are sequentially formed on the surface of the semiconductor substrate 100. The gate dielectric layer 101 may include silicon oxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO), or other suitable materials; in this embodiment, silicon oxide is used for example. The barrier material layer 102 may include silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), or other suitable materials; here, the barrier material layer 102 is, for example, silicon nitride, with a thickness of approximately 50 nm to 200 nm. If necessary, after forming the gate dielectric layer 101 and before depositing the barrier material layer 102, ion implantation can be performed on the channel region within the semiconductor substrate 100 to adjust the threshold voltage (Vth) of the transistor to be fabricated. For example, the implanted material is boron (B) or boron difluoride (BF2), the energy is 10 keV to 20 keV, and the dose is 1E12 / cm². 2 ~1E13 / cm 2 .

[0047] Reference Figure 2 and Figure 4 Next, the barrier material layer 102 is etched to form at least one barrier element 110, each barrier element 110 extending on the surface of the gate dielectric layer 101 and spanning a plurality of active regions 10 in the semiconductor substrate 100. Specifically, a patterned photoresist layer PR1 can first be formed on the barrier material layer 102 using a photolithography process to define the position of the barrier element 110, and then an anisotropic dry etching process ETCH1 is performed to remove the exposed barrier material layer 102, after which the photoresist layer PR1 is removed.

[0048] Reference Figure 2 and Figure 5Next, the gate dielectric layer 101 not covered by the barrier 110 is thickened to form a thick gate dielectric layer 120, and the unthickened gate dielectric layer 101 (covered by the barrier 110) becomes a thin gate dielectric layer 130. Exemplarily, a local oxidation process is used to increase the thickness of the portion of the gate dielectric layer 101 not covered by the barrier 110 by 2 nm to 10 nm. The thickness range of the thin gate dielectric layer 130 is, for example, 1 nm to 5 nm, and the thickness range of the thick gate dielectric layer 120 is, for example, 3 nm to 15 nm.

[0049] Reference Figure 6 Next, the barrier 110 is etched to narrow the width of the thin gate dielectric layer 130 covered by the barrier 110, exposing portions of the thin gate dielectric layer 130 on both sides of the barrier 110. The barrier 110 can be reduced in size entirely by isotropic etching (e.g., isotropic wet etching), so that the widths of the portions of the thin gate dielectric layer 130 exposed on both sides of the narrowed barrier 110 are, for example, equal. This process does not require a photomask to obtain a self-aligned thin gate dielectric layer 130 of a preset width, resulting in a simple process and cost savings. The width of the exposed thin gate dielectric layer 130 can be changed by adjusting the etching amount of the barrier 110, providing flexibility. For example, the width of the portions of the thin gate dielectric layer 130 exposed on both sides of the barrier 110 is 2 nm to 100 nm. In this embodiment, the barrier 110 is made of silicon nitride and can be wet-etched using phosphoric acid. For example, after this etching step, the barrier 110 is reduced to 30% to 70% of its original size. Figure 6 The dashed box outside the middle barrier 110 represents the outer contour of the barrier 110 before etching.

[0050] Reference Figure 6 and Figure 7 The fabrication method further includes the step of ion implantation on the active regions 10 on both sides of the barrier 110 to form a junction-doped region 140. The doping type of the junction-doped region 140 is opposite to that of the semiconductor substrate 100; here, the doping type of the junction-doped region 140 is N-type, specifically heavily doped N-type (N+). The junction-doped region 140 is preferably a graded junction to improve the junction breakdown voltage. The junction-doped region 140 is formed below the thin gate dielectric layer 130 exposed in the narrowing step of the barrier 110, with the aim of causing the thin gate dielectric layer 130 exposed by the narrowed barrier 110 to partially break down during programming of the corresponding 1.5T memory cell, thereby reducing the programming voltage.

[0051] Reference Figure 6 and Figure 7For example, to fabricate the junction-doped region 140, firstly, a patterned photoresist layer PR2 is formed on the thick gate dielectric layer 120 to define the implantation range of the junction-doped region 140. Specifically, the photoresist layer PR2 exposes the barrier 110, the thin gate dielectric layer 130 on both sides of the barrier 110, and a portion of the thick gate dielectric layer 120 connected to the thin gate dielectric layer 130; then, N-type ion implantation IMP1 is performed, with the implantation positions in each active region 10 as follows: Figure 6 As shown by the thick dashed line, this N-type ion implantation IMP1 is performed, for example, in two stages. Exemplarily, phosphorus ion implantation is performed first, with an energy of 30 keV to 40 keV and a dose of 5 E12 / cm². 2 ~5E13 / cm 2 Then, arsenic ion implantation is performed, with an energy of 15 keV to 30 keV and a dose of 1E15 / cm². 2 ~5E15 / cm 2 After N-type ion implantation (IMP1) is completed, the photoresist layer PR2 is removed, and rapid thermal annealing (RTA) or furnace tube annealing is performed to form the junction-doped region 140. (Refer to...) Figure 7 In this embodiment, there are multiple junction doped regions 140, which are located in the active regions 10 on both sides of each barrier 110. For the same junction doped region 140, it extends from below the thin gate dielectric layer 130 on one side of the barrier 110 to below the thick gate dielectric layer 120 to which the thin gate dielectric layer 130 is connected.

[0052] Reference Figure 2 and Figure 7Next, a ground gate line 150 (GND) is formed corresponding to each of the barrier elements 110, and word lines 160 (WL) are formed on both sides of the ground gate line. Specifically, this may include: depositing a gate material layer (thickness approximately 80nm to 150nm) on the semiconductor substrate 100, such as N-type doped polysilicon, silicide, metal, or other suitable materials, with a thickness of approximately 80nm to 150nm; then, forming a patterned photoresist layer PR3 on the gate material layer to define the range of the ground gate line and the word line. In this embodiment, the ground gate line and the word line serve as different gates of each 1.5T memory cell in the memory, and the photoresist layer PR3 is used to define the location of the gate; then, the gate material layer exposed by the photoresist layer PR3 is removed using an anisotropic etching process ETCH2, and then the photoresist layer PR3 is removed. In this embodiment, this step forms at least one ground gate line 150 and at least two word lines 160. Both the ground gate line 150 and the word line 160 span multiple active regions 10 of the semiconductor substrate 100. The ground gate line 150 is formed corresponding to each barrier 110 and covers the corresponding barrier 110 and the thin gate dielectric layer 130 exposed on both sides of the barrier 110. The word line 160 is formed on both sides of each ground gate line 150, specifically on the thick gate dielectric layer 120. Thus, the circuit from the junction doped region 140 to the ground gate line 150 is defined to pass through the portion of the thin gate dielectric layer 130 exposed on both sides of the barrier 110, which constitutes a breakdown voltage band.

[0053] Reference Figure 8 Then, a source region 170 and a drain region 180 are formed in each of the active regions 10, wherein the source region 170 is located between the ground gate line 150 and the word lines 160 on both sides, and the drain region 180 is located on the other side of each word line 160 relative to the source region 170. The source region 170 has the same doping type (N+) as the junction doped region 140 located on the same side of the barrier member 110 and is connected to it.

[0054] After forming the ground gate line 150 and word line 160, and before forming the source region 170 and drain region 180, an LDD region (not shown) can be formed in the active region 10 of the semiconductor substrate 100. The LDD region is located between the ground gate line 150 and the word lines 160 on both sides, and on the side of the word line 160 away from the corresponding ground gate line 150. Sidewalls 190 are formed on both sides of the ground gate line 150 and the two sides of the word line 160. In this embodiment, when forming the source region 170 and drain region 180, N-type heavily doped ion implantation can be performed on the portion of the active region 10 between each ground gate line 150 and the word lines 160 on both sides, and on the portion of the active region 10 on the side of each word line 160 away from the ground gate line 150. The energy is, for example, 20 keV to 50 keV, and the dose is, for example, 2E15cm. -2 ~8E15cm -2 .

[0055] Reference Figure 8 After forming the source region 170 and the drain region 180, the fabrication method may further include: removing the thick gate dielectric layer 120 exposed on both sides of the ground gate line 150 and both sides of the word line 160, and forming a self-aligned metal silicide layer 103 on the exposed surfaces of the semiconductor substrate 100, the ground gate line 150, and the word line 160; then, forming an interlayer dielectric layer 200, which fills the gap between the ground gate line 150 and the word line 160 and covers the ground gate line 150 and the word line 160; then, forming at least one bit line 300 (BL) on the interlayer dielectric layer 200, and connecting the drain region 180 to the corresponding bit line 300 through a contact plug 210 passing through the interlayer dielectric layer 200.

[0056] The above steps can be followed to form the following: Figure 2 The illustrated 1.5T one-time programmable memory includes at least one 1.5T storage cell. The fabrication method is simple, low-cost, and produces a concise layout for the resulting 1.5T one-time programmable memory. (Refer to...) Figure 2 , Figure 8 and Figure 9In the 1.5T one-time programmable memory formed by the above manufacturing method, the word line 160 located on the active region 10 and the source region 170 and drain region 180 on both sides constitute the selection transistor of the 1.5T memory cell. The ground gate line 150 located on the active region 10 corresponds to the ground transistor of the 1.5T memory cell. Part of the thin gate dielectric layer 130 is sandwiched between the junction doped region 140 connected to the source region 170 and the ground gate line 150. When programming the corresponding 1.5T memory cell, one-time programming can be achieved by coupling the drain voltage of the selection transistor to the junction doped region below the ground transistor and causing the thin gate dielectric layer sandwiched between the junction doped region and the ground gate line to break down. The programming voltage is relatively small.

[0057] This invention includes a 1.5T one-time programmable memory, which can be fabricated using the method described above. (Refer to...) Figure 1-2 and Figure 8-9 The 1.5T one-time programmable memory includes at least one 1.5T memory cell formed in the active region 10 of the semiconductor substrate 100. The 1.5T memory cell includes a select transistor and half of a ground transistor. The select transistor includes a thick gate dielectric layer 120 formed on the semiconductor substrate 100, a select gate (which can be implemented by a corresponding word line 160) located on the thick gate dielectric layer 120, and a drain region 180 and a source region 170 respectively formed in the active region 10 on both sides of the select gate. The ground transistor includes a thin gate dielectric layer 130 and a barrier element. The barrier 110 and the ground gate (which may be implemented by a corresponding ground gate line 150) are provided. The barrier 110 is formed on the thin gate dielectric layer 130, and portions of the thin gate dielectric layer 130 are exposed on both sides of the barrier 110. The ground gate is formed on the barrier 110 and the exposed thin gate dielectric layer 130. The ground transistor also includes a junction doped region 140, which is formed in the active regions 10 on both sides of the barrier 110. The source region 170 of the select transistor has the same doping type as and is connected to one of the junction doped regions 140.

[0058] On the other hand, the 1.5T one-time programmable memory may include multiple pairs of the 1.5T memory cells, each pair having two 1.5T memory cells. Each pair of the 1.5T memory cells includes two select transistors arranged in a mirror configuration and a ground transistor shared by the two 1.5T memory cells. The multiple pairs of the 1.5T memory cells may form a memory array, and the ground gates in the multiple pairs of the 1.5T memory cells may be connected to form at least one ground gate line 150 (GND), the select gates may be connected to form at least two word lines 160 (WL), and the drain region 180 of the select transistor may be connected to at least one bit line 300 (BL), wherein the drain region 180 in each pair of mirror-arranged 1.5T memory cells is connected to the same bit line 300 (BL).

[0059] The following is for reference Figure 10 The process of one-time programming and reading using the 1.5T one-time programmable memory is described. For example... Figure 2 The storage array shown allows for the selection of specific 1.5T memory cells for programming or reading operations by setting the bias voltage on each word line and bit line. This is used as an example to illustrate the selection... Figure 10 The 1.5T storage unit located on the left is selected for programming or reading operations, while the 1.5T storage unit located on the right is not selected for any corresponding operations.

[0060] Table 1 shows the bias conditions used in an embodiment of the present invention when programming a selected 1.5T memory cell. Referring to Table 1, the programming operation includes: applying a first specified voltage (e.g., 3V to 10V) to the drain region 180 of the selected 1.5T memory cell through the corresponding bit line 300 (BL); applying a second specified voltage (e.g., 3V to 10V) to the gate of the selected transistor in the selected 1.5T memory cell through the corresponding word line 160 (WL); grounding other word lines 160; grounding or floating other bit lines 300; and grounding the semiconductor substrate 100. Under the action of the first specified voltage and the second specified voltage, the channel region of the selected transistor in the selected 1.5T memory cell opens. The first specified voltage is coupled to the source region 170. Since the source region 170 is connected to the junction doped region 140 and the ground gate 150 is grounded (GND), the thin gate dielectric layer 130 sandwiched between the junction doped region 140 and the ground gate 150 is permanently broken down under the action of the first specified voltage (e.g., ...). Figure 10 (As shown in the diagram, "breakdown"), forming a conductive path.

[0061] Table 1

[0062]

[0063] Table 2 shows the bias conditions used in an embodiment of the present invention when performing a read operation on a selected 1.5T memory cell. Referring to Table 2, the read operation includes: applying a third specified voltage (e.g., 0.5V to 1.5V) to the drain region 180 of the selected 1.5T memory cell through the corresponding bit line 300 (BL), and applying a fourth specified voltage (e.g., 1V to 3V) to the gate of the select transistor of the selected 1.5T memory cell through the corresponding word line 160 (WL); wherein, when the selected 1.5T memory cell has been programmed to form a conductive path at the thin gate dielectric layer 130 between the junction doped region 140 and the ground gate 150, under the action of the third specified voltage and the fourth specified voltage, a channel will be formed from the drain region 180 through the select transistor. The cell current flowing from the channel region, source region 170, and junction doped region 140 to the ground gate 150 will not form when the selected 1.5T memory cell is not programmed and the thin gate dielectric layer 130 sandwiched between the junction doped region 140 and the ground gate 150 is not broken down. Therefore, the cell current can be detected to determine whether the selected 1.5T memory cell has been programmed. When the cell current is detected, the 1.5T memory cell is determined to be in a programmed state (state "1"). When the cell current is not detected, the 1.5T memory cell is determined to be in an unprogrammed state (state "0").

[0064] Table 2

[0065]

[0066] The 1.5T one-time programmable memory provided by the present invention includes at least one 1.5T memory cell formed in the active region 10 of a semiconductor substrate 100. The 1.5T memory cell includes a select transistor and half of a ground transistor, with a simple structure. In the ground transistor, a portion of the thin gate dielectric layer 130 is sandwiched between the junction doped region 140 connecting the source region 170 of the select transistor and the ground gate 150. When programming the corresponding 1.5T memory cell, the voltage of the drain region 180 of the select transistor can be coupled to the junction doped region 140, causing the thin gate dielectric layer sandwiched between the junction doped region 140 and the ground gate 150 to break down, resulting in a smaller programming voltage.

[0067] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0068] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a 1.5T one-time programmable memory, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including an active region; A gate dielectric layer is formed on the surface of the semiconductor substrate; A barrier material layer is formed on the gate dielectric layer, and the barrier material layer is etched to form a barrier element; The portion of the gate dielectric layer not covered by the barrier is thickened to form a thick gate dielectric layer, while the portion of the gate dielectric layer not thickened forms a thin gate dielectric layer; The barrier is etched to narrow its width, thereby exposing portions of the thin gate dielectric layer on both sides of the barrier. Junction-doped regions are formed in the active regions on both sides of the barrier; A grounding grid is formed, the grounding grid covering the barrier and the exposed portions of the thin grid dielectric layer on both sides of the barrier; Selective gates are formed on both sides of the grounding gate, and the selective gates are located on the thick gate dielectric layer; as well as A source region and a drain region are formed in the active region. The source region is located between the ground gate and the select gate. The drain region is located on the other side of the select gate relative to the source region. The source region is doped with the same type as and connected to a junction doped region.

2. The manufacturing method as described in claim 1, characterized in that, The barrier is etched using an isotropic wet etching process to narrow its width.

3. The manufacturing method as described in claim 1, characterized in that, The exposed portions of the thin gate dielectric layer on both sides of the barrier are of equal width.

4. The manufacturing method as described in claim 3, characterized in that, The width of the thin gate dielectric layer exposed on both sides of the barrier is 2nm to 100nm.

5. The manufacturing method as described in claim 1, characterized in that, The barrier element includes at least one of silicon nitride, silicon oxynitride, and silicon carbide.

6. The manufacturing method as described in claim 1, characterized in that, The thickness of the thin gate dielectric layer ranges from 1 nm to 5 nm, and the thickness of the thick gate dielectric layer ranges from 3 nm to 15 nm.

7. The manufacturing method as described in claim 1, characterized in that, The formation of the junction doped region includes: A patterned photoresist layer is formed on the thick gate dielectric layer, the patterned photoresist layer exposing the barrier, portions of the thin gate dielectric layer on both sides of the barrier, and portions of the thick gate dielectric layer connected to the thin gate dielectric layer; Phosphorus ion implantation is performed at an energy of 30 keV to 40 keV and a dose of 5 E12 / cm². 2 ~5E13 / cm 2 ;as well as Arsenic ion implantation is performed at an energy of 15 keV to 30 keV and a dose of 1E15 / cm². 2 ~5E15 / cm 2 .

8. The manufacturing method as described in claim 1, characterized in that, After forming the source region and the drain region, the fabrication method further includes: Remove the thick gate dielectric layer exposed on both sides of the ground gate and both sides of the select gate, and form a self-aligned metal silicide layer on the exposed semiconductor substrate surface, the ground gate surface and the select gate surface; An interlayer dielectric layer is formed, which fills the gap between the ground gate and the select gate and covers the ground gate and the select gate; and A bit line is formed on the interlayer dielectric layer, and the drain region is connected to the bit line through a contact plug that penetrates the interlayer dielectric layer.

9. A 1.5T one-time programmable memory, characterized in that, The invention includes at least one 1.5T memory cell formed in an active region on a semiconductor substrate, the 1.5T memory cell comprising a select transistor and half of a ground transistor, wherein the select transistor comprises a thick gate dielectric layer formed on the semiconductor substrate, a select gate located on the thick gate dielectric layer, and a drain region and a source region respectively formed in the active region on both sides of the select gate, and the ground transistor comprises: Thin gate dielectric layer; A barrier element is formed on the thin gate dielectric layer, with portions of the thin gate dielectric layer exposed on both sides of the barrier element; A grounding grid is formed on the barrier and the exposed thin grid dielectric layer; and Junction doped regions are formed in the active regions on both sides of the barrier, and the source region of the select transistor is of the same doping type as and connected to one of the junction doped regions.

10. The 1.5T one-time programmable memory as described in claim 9, characterized in that, The array comprises multiple pairs of the 1.5T memory cells to form a memory array; and the ground gate connection in the multiple pairs of the 1.5T memory cells forms at least one ground gate line, the select gate connection in the multiple pairs of the 1.5T memory cells forms at least two word lines, and the drain regions of the select transistors in the multiple pairs of the 1.5T memory cells are connected to at least one bit line.

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