Optical sensor readout circuit and chip

Abstract

This application provides a light sensor readout circuit and chip for reading the current of a light sensing module. The light sensor readout circuit includes an oscillation module, a comparison module, a charge output module, and an integration module. The oscillation module outputs an oscillation signal, the comparison module compares a reference signal with the oscillation signal and outputs a comparison signal, the charge output module outputs a charge based on the comparison signal, and the integration module changes the oscillation frequency of the oscillation module based on the charge output by the charge output module. The amount of charge output by the charge output module is equal to the amount of charge passing through the light sensing module. This application can accurately measure the current of the light sensing module, overcoming the difficulty of detecting the small photocurrent generated by the light sensing module using conventional current detection methods.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a light sensor readout circuit and chip. Background Technology

[0002] Light sensors detect the intensity of ambient light and instruct the processing chip to automatically adjust the display backlight brightness, reducing power consumption. For example, in mobile applications such as smartphones, laptops, and tablets, the screen consumes up to 30% of the total battery power. Using light sensors to collect ambient light intensity and adjust screen brightness not only maximizes battery life but also allows the screen brightness to change with the ambient light, providing a softer visual experience. However, light sensors generate a relatively small photocurrent, making it difficult to detect using conventional current detection methods. Summary of the Invention

[0003] This application provides a light sensor readout circuit and chip, aiming to solve the technical problem that current light sensors have low current and are difficult to detect.

[0004] In a first aspect, this application provides a light sensor readout circuit for reading the current of a light sensing module, comprising:

[0005] Oscillating module; the oscillation module is used to output oscillation signals.

[0006] The comparison module compares the reference signal with the oscillation signal and outputs a comparison signal.

[0007] A charge output module, which is used to output charge according to the comparison signal;

[0008] An integration module is used to change the oscillation frequency of the oscillation module according to the charge output by the charge output module;

[0009] The amount of charge output by the charge output module is equal to the amount of charge passing through the optical sensing module.

[0010] In some embodiments, the control terminal of the charge output module is connected to the output terminal of the comparison module, and the charge output module is used to alternately output charge according to the comparison signal; the input terminal of the integration module is connected to the output terminal of the charge output module, and the output terminal of the integration module is connected to the control terminal of the oscillation module, and the integration module is used to change the oscillation frequency of the oscillation module according to the charge output by the charge output module; the optical sensing module is connected to the integration module; wherein, after the integration module receives the charge output by the charge output module, the integration module outputs the charge to the optical sensing module, and the amount of charge output by the charge output module is equal to the amount of charge passing through the optical sensing module.

[0011] In some embodiments, the charge output module alternately outputs charges based on a comparison signal;

[0012] The integration module alternately controls the oscillation frequency of the oscillation module to increase or decrease based on the alternating charges output by the charge output module;

[0013] Specifically, after the integration module receives the charge output by the charge output module, the integration module outputs the charge to the optical sensing module.

[0014] In some embodiments, the charge output module has a first operating state and a second operating state, and the charge output module switches back and forth between the first operating state and the second operating state based on a comparison signal.

[0015] When the charge output module is in the first working state, the charge output module provides charge to the integration module, and the integration module controls the oscillation module to increase the oscillation frequency based on the accumulated charge.

[0016] When the charge output module is in the second working state, the charge output module stops supplying charge to the integration module, and the integration module releases charge to the optical sensing module.

[0017] In some embodiments, the optical sensing module is connected to the charge output module. When the charge output module is in the first working state, the charge output module simultaneously provides charge to the integration module and the optical sensing module.

[0018] When the charge output module is in the second working state, the charge output module stops supplying charge to the integration module and the optical sensing module.

[0019] In some embodiments, the integration module includes an integrator, and the optical sensing module includes a photodiode;

[0020] The inverting input of the integrator is connected to the negative terminal of the photodiode, the non-inverting input of the integrator is used to connect to the first preset voltage, the output of the integrator is connected to the oscillation module, and the positive terminal of the photodiode is used to ground.

[0021] In some embodiments, the charge output module includes a control switch;

[0022] One end of the control switch is connected to the inverting input of the integrator, and the other end is used to connect to a fixed current source. The control terminal of the control switch is used to connect to a comparison signal and change the switch state based on the comparison signal, so that the charge output module switches back and forth between the first working state and the second working state.

[0023] In some embodiments, the current of the optical sensing module satisfies the following relationship:

[0024] I1 = I2 * T1 / (T1 + T2)

[0025] Where I1 is the current of the photosensitive module, I2 is the current of the charge output module, T1 is the time for the control switch to close, and T2 is the time for the control switch to open.

[0026] In some embodiments, the comparison module includes a phase comparison submodule and a pulse width adjustment submodule;

[0027] The phase comparison submodule is used to compare the phase difference between the reference signal and the oscillation signal, and output the signal to be processed. The pulse width of the signal to be processed is equal to the phase difference between the oscillation signal and the reference signal.

[0028] The pulse width adjustment submodule is used to adjust the pulse width of the signal to be processed in order to generate a comparison signal with a fixed pulse width.

[0029] In some embodiments, the current of the optical sensing module satisfies the following relationship:

[0030] I1 = I2 * T * N

[0031] Where I1 is the current of the optical sensing module, I2 is the current of the charge output module, T is the fixed pulse width of the comparison signal, and N is the number of times the control switch is closed per unit time.

[0032] In some embodiments, the phase comparison submodule includes a first flip-flop, a second flip-flop, a first AND gate, and a first delay unit, and the pulse width adjustment submodule includes a pulse generator;

[0033] The control terminal of the first flip-flop is used to connect to the reference signal, the input terminal of the first flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate.

[0034] The control terminal of the second flip-flop is used to connect to the oscillation signal, the input terminal of the second flip-flop is used to connect to the working voltage, and the output terminal of the first flip-flop is connected to the second input terminal of the first AND gate.

[0035] The input terminal of the first delay is connected to the output terminal of the first AND gate, and the reset terminals of the first and second flip-flops are connected to the output terminal of the delay.

[0036] The input terminal of the pulse generator is connected to the output terminal of the first or second flip-flop, and the output terminal of the pulse generator is connected to the control terminal of the control switch.

[0037] In some embodiments, the integration module includes an integrator, and the optical sensing module includes a photodiode;

[0038] The charge output module includes a first sub-switch and a second sub-switch;

[0039] The non-inverting input of the integrator is used to connect to the first preset voltage, and the output of the integrator is connected to the oscillation module.

[0040] One end of the second sub-switch is connected to the inverting input of the integrator, and the other end is connected to the negative terminal of the photodiode. The positive terminal of the photodiode is used for grounding.

[0041] One end of the first sub-switch is used to connect to the working voltage, and the other end is connected to the third node between the second sub-switch and the inverting input of the integrator;

[0042] The control terminal of the first sub-switch is used to receive a comparison signal and change the switch state based on the comparison signal, and the switch state of the first sub-switch is opposite to that of the second sub-switch.

[0043] In some embodiments, the current of the optical sensing module satisfies the following relationship:

[0044] I1 = I2 * t01 / t02

[0045] Where I1 is the current of the optical sensing module, I2 is the current of the charge output module, t01 is the time when the first sub-switch is closed, and t02 is the time when the second sub-switch is open.

[0046] In some embodiments, the comparison module includes a first flip-flop, a second flip-flop, a first AND gate, and a first delay;

[0047] The control terminal of the first flip-flop is used to connect to the reference signal, the input terminal of the first flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate.

[0048] The control terminal of the second flip-flop is used to connect to the oscillation signal, the input terminal of the second flip-flop is used to connect to the working voltage, and the output terminal of the first flip-flop is connected to the second input terminal of the first AND gate.

[0049] The input terminal of the first delay is connected to the output terminal of the first AND gate, and the reset terminals of the first and second flip-flops are connected to the output terminal of the delay.

[0050] The control terminal of the first sub-switch is connected to the output terminal of the first trigger.

[0051] In some embodiments, the ratio of the current of the optical sensing module to the current of the charge output module is in the range of 1:5000 to 1:100.

[0052] In some embodiments, the charge output module includes a first switch, a second switch, a third switch, a fourth switch, and a control capacitor;

[0053] One end of the first switch is connected to the first end of the control capacitor, and the other end is used to connect to the second preset voltage;

[0054] One end of the second switch is connected to the second end of the control capacitor, and the other end is connected to the inverting input of the integrator;

[0055] One end of the third switch is connected to the first node between the first switch and the control capacitor, and the other end is used for grounding;

[0056] One end of the fourth switch is connected to the second node between the second switch and the control capacitor, and the other end is used for the first preset voltage;

[0057] The control terminals of the first and second switches are used to receive the comparison signal and change the switch state based on the comparison signal; the control terminals of the third and fourth switches are used to receive the control signal that is inversely related to the comparison signal and change the switch state based on the control signal.

[0058] In some embodiments, the current of the optical sensing module satisfies the following relationship:

[0059] I1=Cc*V2*N

[0060] Where I1 is the current of the optical sensing module, Cc is the capacitance value of the control capacitor, V1 is the first preset voltage, V2 is the second preset voltage, and N is the number of times the second switch is closed per unit time.

[0061] In some embodiments, the comparison module includes a first flip-flop, a second flip-flop, a first AND gate, a first delay, and a first inverter;

[0062] The control terminal of the first flip-flop is used to connect to the reference signal, the input terminal of the first flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate.

[0063] The control terminal of the second flip-flop is used to connect to the oscillation signal, the input terminal of the second flip-flop is used to connect to the working voltage, and the output terminal of the first flip-flop is connected to the second input terminal of the first AND gate.

[0064] The input terminal of the first delay is connected to the output terminal of the first AND gate, and the reset terminals of the first and second flip-flops are connected to the output terminal of the delay.

[0065] The input terminal of the first inverter is connected to the output terminal of the first flip-flop;

[0066] The control terminals of the first and second switches are connected to the output terminal of the first trigger, and the control terminals of the third and fourth switches are connected to the output terminal of the first inverter.

[0067] In some embodiments, the comparison module includes a first resistor, a first comparator, an equivalent capacitor, a fifth switch, and a sixth switch;

[0068] The first resistor, the fifth switch, and the equivalent capacitor are connected in series. The end of the first resistor away from the fifth switch is used to connect to the working voltage, and the end of the equivalent capacitor away from the fifth switch is used to ground.

[0069] One end of the sixth switch is connected to the fourth node between the fifth switch and the equivalent capacitor, and the other end is used for grounding;

[0070] The inverting input of the first comparator is used to connect to the third preset voltage, the non-inverting input of the first comparator is connected to the fifth node between the first resistor and the fifth switch, and the output of the first comparator is used to output a comparison signal.

[0071] The control terminal of the fifth switch is used to receive the oscillation signal and change the switch state based on the oscillation signal. The switch state of the sixth switch is the opposite of that of the fifth switch.

[0072] In some embodiments, the oscillation module includes a ring oscillator and an acceleration switch;

[0073] The ring oscillator consists of multiple ring-connected inverters, and the control terminal of the acceleration switch is connected to the output terminal of the integrator.

[0074] One end of the accelerator switch is used to connect to the operating voltage, and the other end is connected to the power supply terminal of the inverter.

[0075] Secondly, this application provides a chip including the optical sensor readout circuit as described in the first aspect.

[0076] This application utilizes a comparison module to compare a reference signal with an oscillation signal and generate a comparison signal. The comparison signal causes the charge output module to alternately output charge, while the integration module can alternately control the oscillation frequency of the oscillation module to increase or decrease according to the changing amount of charge.

[0077] Because the reference signal and the oscillation signal are dynamically balanced during the above alternation process, the comparison module can continuously output a comparison signal. Since the average amount of charge flowing into the integration module is equal to 0 when the oscillation frequency of the oscillation module is dynamically changed, the amount of charge output by the charge output module is equal to the amount of charge passing through the optical sensing module. Therefore, the cumulative measurement of the amount of charge flowing through the optical sensing module can be achieved by using the comparison signal (e.g., the product of the high-level time of the comparison signal and the current of the optical sensing module), and the current of the optical sensing module can be calculated. Finally, the light intensity can be obtained by the relationship between the current of the optical sensing module and the light intensity. Attached Figure Description

[0078] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0079] Figure 1 This is a schematic diagram of a module structure of the optical sensor readout circuit provided in the embodiments of this application;

[0080] Figure 2 This is a schematic diagram of a circuit structure of the optical sensor readout circuit provided in the embodiments of this application;

[0081] Figure 3 This is a schematic diagram of another circuit structure of the optical sensor readout circuit provided in the embodiments of this application;

[0082] Figure 4 This is a pulse signal timing diagram of the optical sensor readout circuit provided in the embodiments of this application;

[0083] Figure 5 This is a pulse signal timing diagram of the optical sensor readout circuit provided in the embodiments of this application;

[0084] Figure 6 This is a pulse signal timing diagram of the optical sensor readout circuit provided in the embodiments of this application;

[0085] Figure 7 This is a schematic diagram of a high-level time measurement of the comparison signal provided in an embodiment of this application;

[0086] Figure 8 This is a schematic diagram of a module structure of the optical sensor readout circuit provided in the embodiments of this application;

[0087] Figure 9 This is a schematic diagram of another circuit structure of the optical sensor readout circuit provided in the embodiments of this application;

[0088] Figure 10 This is another pulse signal timing diagram of the optical sensor readout circuit provided in the embodiments of this application;

[0089] Figure 11 This is a schematic diagram of a module structure of the optical sensor readout circuit provided in the embodiments of this application;

[0090] Figure 12 This is a schematic diagram of another circuit structure of the optical sensor readout circuit provided in the embodiments of this application;

[0091] Figure 13This is another pulse signal timing diagram of the optical sensor readout circuit provided in the embodiments of this application;

[0092] Figure 14 This is a schematic diagram of another circuit structure of the optical sensor readout circuit provided in the embodiments of this application;

[0093] Figure 15 This is another pulse signal timing diagram of the optical sensor readout circuit provided in the embodiments of this application;

[0094] Figure 16 This is a schematic diagram of another circuit structure of the optical sensor readout circuit provided in the embodiments of this application;

[0095] Figure 17 This is a schematic diagram of another circuit structure of the optical sensor readout circuit provided in the embodiments of this application. Detailed Implementation

[0096] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0097] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0098] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0099] This application provides an optical sensor readout circuit and chip, which will be described in detail below.

[0100] First, refer to Figure 1 , Figure 1 This illustration shows a schematic diagram of a module structure of a light sensor readout circuit according to an embodiment of this application. The light sensor readout circuit is used to read the current of the light sensing module 50, and includes:

[0101] Oscillating module 10, oscillation module 10 is used to output oscillation signal F RET ;

[0102] Comparison module 20 is used to compare the reference signal F. REF With oscillation signal F RET And output the comparison signal Dout;

[0103] The charge output module 30 has its control terminal connected to the output terminal of the comparison module 20. The charge output module 30 is used to alternately output charge according to the comparison signal Dout.

[0104] The integral module 40 has its input terminal connected to the output terminal of the charge output module 30 and its output terminal connected to the control terminal of the oscillation module 10. The integral module 40 is used to alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the charge alternately output by the charge output module 30.

[0105] Optical sensing module 50, which is connected to integration module 40;

[0106] In this process, after receiving the charge output by the charge output module 30, the integration module 40 outputs the charge to the optical sensing module 50, and the amount of charge output by the charge output module 30 is equal to the amount of charge passing through the optical sensing module 50.

[0107] Specifically, the oscillation module 10 is used to convert a DC voltage signal into an AC voltage signal with a certain frequency (e.g., a sine wave or square wave signal). The oscillation frequency of the oscillation module 10 can be controlled and changed by the integrator module 40, thereby making the oscillation signal F output by the oscillation module 10... RET With reference signal F REF The phase difference changes. For example, the oscillation excitation mode of the oscillation module 10 can be a self-excited oscillation mode or an externally excited oscillation mode. For example, the oscillation module 10 may include a resistor-capacitor oscillator, an inductor-capacitor oscillator, a crystal oscillator, a tuning fork oscillator, etc.

[0108] Comparison module 20 is used to compare reference signal F REF With oscillation signal F RET The comparison module 20 outputs a comparison signal Dout, so that the charge output module 30 can alternately output charges according to the comparison signal Dout. In some embodiments of this application, the comparison module 20 can compare a reference signal F. REF With oscillation signal F RET The phase difference. In some other embodiments of this application, the comparison module 20 can compare the reference signal F. REF With oscillation signal F RET The frequency. For example, the comparison module 20 may include a frequency phase detector, a gate phase detector, or a three-state phase detector, etc.

[0109] In some embodiments of this application, the first input terminal of the comparison module 20 is used to receive the reference signal F. REF The second input terminal is connected to the output terminal of the oscillation module to facilitate the input of the oscillation signal F. RET Understandably, the reference signal F REF It can also be generated by the comparison module 20 itself, for example, by using an oscillator to generate the reference signal.

[0110] The charge output module 30 is used to alternately output charge according to the comparison signal Dout, so that the integration module 40 alternately controls the oscillation frequency of the oscillation module 10 to increase or decrease according to the changing amount of charge. In some embodiments of this application, the charge output module 30 has a first operating state and a second operating state. The charge output module 30 switches back and forth between the first operating state and the second operating state based on the comparison signal Dout, thereby causing the charge output module 30 to alternately output charge. Exemplarily, the alternation between the first operating state and the second operating state of the charge output module 30 can be implemented by a switch, for example, by providing a fixed current source. When the switch is closed, the charge output module 30 inputs charge to the integration module 40; and when the switch is closed, the charge output module 30 stops inputting charge to the integration module 40. The amount of charge output by the charge output module 30 can be calculated by multiplying the fixed current by the switch closing time.

[0111] Understandably, the charge output module 30 can also control a current source with a changing current value through a switch, and calculate the corresponding charge by integrating the changing current.

[0112] The integrator module 40 can alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the changing amount of charge. Specifically, the integrator module 40 can alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the alternating charge output by the charge output module 30. After receiving the charge output by the charge output module 30, the integrator module 40 outputs the charge to the optical sensing module 50. In some embodiments of this application, for example, for embodiments where the charge output module 30 has a first working state and a second working state, when the charge output module 30 is in the first working state, the charge output module 30 provides charge to the integrator module 40, and the integrator module 40 controls the oscillation module 10 to increase the oscillation frequency based on the accumulated charge; when the charge output module 30 is in the second working state, the charge output module 30 stops providing charge to the integrator module 40, and the integrator module 40 releases charge to the optical sensing module 50, and the integrator module 40 controls the oscillation module 10 to decrease the oscillation frequency based on the released charge.

[0113] In some embodiments of this application, for example, the comparison module can compare the reference signal F. REF With oscillation signal F RET In an embodiment of the phase difference, when the charge output module 30 is in the first operating state, the charge output module 30 provides charge to the integration module 40. The integration module 40 controls the oscillation module 10 to increase the oscillation frequency based on the accumulated charge, thereby reducing the input signal F. REF With feedback signal F RET The phase difference; when the charge output module 30 is in the second working state, the charge output module 30 stops providing charge to the integration module 40, and the integration module 40 releases charge to the optical sensing module 50. Based on the released charge, the integration module 40 controls the oscillation module 10 to reduce the oscillation frequency, so as to amplify the input signal F. REF With feedback signal F RET The phase difference.

[0114] During the above process, as the oscillation frequency of the oscillation module 10 alternately increases or decreases, the input signal F... REF With feedback signal F RET Maintaining the corresponding phase difference allows the comparison module 20 to continuously output a comparison signal Dout associated with the phase difference, ensuring that the optical sensor readout circuit can perform current measurement under non-steady-state conditions.

[0115] It should be noted that during the operation of the integration module 40 in the first and second working states, since it cannot carry charge, the amount of charge output by the charge output module 30 to the integration module 40 during the multiple alternations of the first and second working states is equal to the amount of charge released by the integration module 40 to the optical sensing module 50.

[0116] As an example, see Figure 2 , Figure 2 This illustration shows a schematic diagram of a circuit structure for a light sensor readout circuit in an embodiment of this application. The integration module 40 includes a capacitor C, one end of which is connected to the charge output module 30, and the other end to the oscillation module 10. When the charge output module 30 charges the capacitor C, charge accumulates on one end of the capacitor, while the voltage on the other end gradually decreases, controlling the oscillation module 10 to increase the oscillation frequency, thereby increasing the oscillation frequency of the reference signal F. REF With oscillation signal F RET The phase difference decreases; and when the charge output module 30 stops charging the capacitor C, the charge accumulated on one end of the capacitor plate is released to the photosensitive module 50, while the voltage on the other end plate gradually increases and controls the oscillation module 10 to reduce the oscillation frequency, thereby making the reference signal F... REF With oscillation signal F RET The phase difference increases.

[0117] In this embodiment of the application, the comparison module 20 is used to compare the reference signal F. REF With oscillation signal F RET A comparison signal Dout is generated, which causes the charge output module 30 to output charge alternately, while the integration module 40 can alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the changing amount of charge.

[0118] Because the reference signal F during the above alternation process REF And oscillation signal F RET Dynamic balance is achieved, so the comparison module 20 can continuously output the comparison signal Dout. Since the average amount of charge flowing into the integration module 40 is equal to 0 when the oscillation frequency of the oscillation module 10 is dynamically changed, the amount of charge output by the charge output module 30 is equal to the amount of charge passing through the optical sensing module 50. Therefore, the cumulative measurement of the amount of charge flowing through the optical sensing module 50 can be achieved by using the comparison signal Dout (e.g., the product of the high level time of the comparison signal Dout and the fixed current of the charge output module 30), and the current of the optical sensing module 50 can be calculated. Finally, the light intensity can be obtained by the relationship between the current of the optical sensing module 50 and the light intensity.

[0119] In some embodiments of this application, see Figure 1 , Figure 3 as well as Figure 4, Figure 3 This illustration shows another circuit structure diagram of the optical sensor readout circuit in an embodiment of this application. Figure 4 This diagram illustrates a pulse signal timing diagram of the optical sensor readout circuit in an embodiment of this application. The optical sensing module 50 is connected between the charge output module 30 and the integration module 40. Specifically, the optical sensing module 50 is connected to the output terminal of the charge output module 30 and to the input terminal of the integration module 40. When the charge output module 30 is in a first operating state, it simultaneously provides charge to both the integration module 40 and the optical sensing module 50. When the charge output module 30 is in a second operating state, it stops providing charge to both the integration module 40 and the optical sensing module 50. In other words, in the first operating state, the charge output module 30 provides charge Q1 and charge Q2 to the optical sensing module 50 and the integration module 40, respectively. In the second operating state, the charge Q2 accumulated by the integration module 40 flows to the optical sensing module 50. Therefore, the accumulated charge Q output by the charge output module 30 is equal to the charge flowing through the optical sensing module 50, which is equal to the sum of charge Q1 and charge Q2.

[0120] In some embodiments of this application, such as the embodiment where the optical sensing module 50 is connected between the charge output module 30 and the integration module 40, see further details. Figure 1 , Figure 3 as well as Figure 4 The integrating module 40 includes an integrator IN1, and the optical sensing module 50 includes a photodiode PD. The inverting input terminal of the integrator IN1 is connected to the negative terminal of the photodiode PD, the non-inverting input terminal of the integrator IN1 is used to connect to a first preset voltage V1, the output terminal of the integrator IN1 is connected to the oscillation module 10, and the positive terminal of the photodiode PD is used to ground.

[0121] It should be noted that the integrator module 40 uses integrator IN1. Firstly, the voltages at the non-inverting and inverting input terminals of integrator IN1 are equal due to their virtual short characteristics, thus ensuring the voltage stability of the photodiode PD and preventing changes in the photocurrent caused by voltage fluctuations in the photodiode PD. Secondly, the capacitor C0 of integrator IN1 cannot pass charge, ensuring that the charge output by the charge output module 30 is equal to the current flowing through the photodiode PD. Thirdly, the integrator IN1 outputs a linear voltage signal Vout based on changes in the charge of capacitor C0, which facilitates the control of the oscillation module 10 to increase or decrease the oscillation frequency.

[0122] Understandably, the optical sensing module 50 can also use semiconductor devices made with the same photoelectric effect as the photodiode PD, and is not limited to photodiodes.

[0123] Furthermore, in some embodiments of this application, see further reference. Figure 1 , Figure 3 as well as Figure 4 The charge output module 30 includes a control switch Sc. One end of the control switch Sc is connected to the inverting input of the integrator IN1, and the other end is used to connect to a fixed current source. The control terminal of the control switch Sc is used to connect to the comparison signal Dout and change the switch state based on the comparison signal Dout, so that the charge output module 30 switches back and forth between the first working state and the second working state.

[0124] For example, the control switch Sc can be a MOSFET, and the control terminal of the control switch Sc is the gate of the MOSFET. For instance, when the control switch Sc is an NMOS transistor, a high level comparison signal Dout causes the control switch Sc to close, meaning the charge output module 30 is in a first operating state. Conversely, a low level comparison signal Dout causes the control switch Sc to open, meaning the charge output module 30 is in a second operating state. Understandably, the control switch Sc can also be a PMOS transistor or an IGBT, or other electronic components with switching functions.

[0125] In some embodiments of this application, such as an embodiment where the charge output module 30 simultaneously provides charge to both the integration module 40 and the optical sensing module 50 when the charge output module 30 is in a first operating state, see further description. Figure 1 , Figure 3 as well as Figure 4 When the control switch Sc is closed, the charge output module 30 simultaneously supplies charge to both the integration module 40 and the optical sensing module 50. However, when the control switch Sc is open, only the integration module 40 supplies charge to the optical sensing module 50. Simultaneously, the currents of both the charge output module 30 and the optical sensing module 50 remain stable. According to the principle of charge conservation, the current of the optical sensing module 50 satisfies the following relationship:

[0126] I1 = I2 * T1 / (T1 + T2)

[0127] Where I1 is the current of the optical sensing module 50, i.e. the fixed current output by the fixed current source, I2 is the current of the charge output module 30, T1 is the time for the control switch Sc to close, and T2 is the time for the control switch Sc to open.

[0128] It should be noted that the time T2 for the control switch Sc to open refers to the time corresponding to the control switch Sc being open during the working state, and does not include the time corresponding to the control switch Sc being open when the overall circuit is not in the working state. In some embodiments of this application, such as embodiments where the control switch Sc is an NMOS transistor, the time T1 for the control switch Sc to close refers to the high level time of the comparison signal Dout, and the time T2 for the control switch Sc to open refers to the low level time of the comparison signal Dout.

[0129] Understandably, the control switch Sc can also be connected to a current source with varying current magnitude, and the amount of charge output after the control switch Sc is closed can be obtained by integration.

[0130] Further, see Figure 5 , Figure 5 This illustrates another pulse signal timing diagram of the optical sensor readout circuit in an embodiment of this application, due to the reference signal F REF With oscillation signal F RET The phase difference is usually not a fixed value and there are extremely small phase differences. In some embodiments of this application, the comparison module 20 can filter out small phase differences to avoid the comparison signal Dout frequently causing the control switch Sc to open or close.

[0131] Further reading Figure 6 as well as Figure 7 , Figure 6 Another pulse signal timing diagram of the optical sensor readout circuit in an embodiment of this application is shown. Figure 7 This illustration shows a schematic diagram of measuring the high-level time of the comparison signal Dout in an embodiment of this application, for the reference signal F. REF With oscillation signal F RET The phase difference is usually not a fixed value (e.g., ... Figure 6 The phase differences t1, t2, and t3 shown can be used to compare a high-frequency reference signal with a comparison signal Dout, which has a fixed period. A counter measures the number of pulses of the high-frequency reference signal corresponding to the high-level time of the comparison signal Dout (e.g., ...). Figure 7 The high-level time of the comparison signal Dout can be obtained by multiplying the number of pulses by the fixed period of the high-frequency reference signal (N1, N2, N3 shown), which is the time T1 when the control switch Sc is closed or the time T2 when the control switch Sc is opened.

[0132] However, the above method of measuring the number of pulses of the high-frequency reference signal may not have a complete count of pulses of the high-frequency reference signal during the high-level time of the comparison signal Dout, which leads to a certain error in the measurement of the high-level time of the comparison signal Dout.

[0133] For this purpose, please refer to further information. Figure 8 , 9 as well as Figure 10 , Figure 8 This illustration shows another schematic diagram of the module structure of the optical sensor readout circuit in an embodiment of this application. Figure 9 This illustration shows another circuit structure diagram of the optical sensor readout circuit in an embodiment of this application. Figure 10Another pulse signal timing diagram of the optical sensor readout circuit in this embodiment is shown, wherein the comparison module 20 includes a phase comparison submodule 21 and a pulse width adjustment submodule 22. The phase comparison submodule 21 is used to compare the reference signal F. REF With oscillation signal F RET The phase difference is calculated, and the output signal to be processed, out, is given. The pulse width of the signal to be processed, out, is equal to the oscillation signal F. RET With reference signal F REF The phase difference. The pulse width adjustment submodule 22 is used to adjust the pulse width of the signal to be processed out to generate a comparison signal Dout with a fixed pulse width T.

[0134] It should be noted that since the pulse width adjustment submodule 22 generates a comparison signal Dout with a fixed pulse width, a counter can be used to measure the number of pulses of the comparison signal Dout, and the product of the number of pulses and the corresponding fixed pulse width can be used to obtain the closing time T1 of the control switch Sc, thereby making the high-level time of the comparison signal Dout accurate and ensuring the accuracy of the photodiode PD current measurement.

[0135] Furthermore, in some embodiments of this application, such as for embodiments where the comparison module 20 includes a phase comparison submodule 21 and a pulse width adjustment submodule 22, the current of the optical sensing module 50 satisfies the following relationship:

[0136] I1 = I2 * T * N

[0137] Where I1 is the current of the optical sensing module 50, I2 is the current of the charge output module 30, T is the fixed pulse width of the comparison signal Dout, and N is the number of times the control switch Sc is closed per unit time (e.g., 1 second).

[0138] It should be noted that the number of times the control switch Sc is closed, N, can be obtained by counting the number of pulses of the comparison signal Dout using a counter. Understandably, the pulse width adjustment submodule 22 adjusts the high-level time of the comparison signal Dout. In some embodiments of this application, such as embodiments where the control switch Sc is a PMOS transistor, the pulse width adjustment submodule 22 can also adjust the low-level time of the comparison signal Dout.

[0139] Furthermore, in some embodiments of this application, see further reference. Figure 9 as well as Figure 10 The phase comparison submodule 21 includes a first flip-flop DT1, a second flip-flop DT2, a first AND gate AND1, and a first delay De. The pulse width adjustment submodule 22 includes a pulse generator PR. The control terminal of the first flip-flop DT1 is used to input the reference signal F. REFThe input of the first flip-flop DT1 is connected to the operating voltage VDD, and the output of the first flip-flop DT1 is connected to the first input of the first AND gate AND1. The control terminal of the second flip-flop DT2 is connected to the oscillation signal F. RET The input of the second flip-flop DT2 is connected to the operating voltage VDD. The output of the first flip-flop DT1 is connected to the second input of the first AND gate AND1. The input of the first delay unit De is connected to the output of the first AND gate AND1. The reset terminals of the first flip-flop DT1 and the second flip-flop DT2 are connected to the output of the delay unit. The input of the pulse generator PR is connected to the output of either the first flip-flop DT1 or the second flip-flop DT2. The output of the pulse generator PR is connected to the control terminal of the control switch Sc.

[0140] It should be noted that, due to the presence of the first AND gate AND1, when there is a time difference (i.e., a phase difference) between the rising edges of the signals input to the first flip-flop DT1 and the second flip-flop DT2, the first AND gate AND1 will control the reset terminals of the first flip-flop DT1 and the second flip-flop DT2 to reset the flip-flop states. This causes the first flip-flop DT1 to generate a high-level signal corresponding to the signal to be processed, 'out'. Between the reset of the first flip-flop DT1 and the arrival of the next rising edge, a low-level signal corresponding to the signal to be processed, 'out', is generated, thus producing an oscillation signal F. RET With reference signal F REF The phase difference is associated with the unprocessed signal out. The first delay unit De can delay the time when the output signal of the first AND gate AND1 controls the reset state of the first flip-flop DT1 and the second flip-flop DT2, thus filtering out small phase differences and avoiding frequent system responses.

[0141] Understandably, in the above embodiments, the signal to be processed out is the signal output by the output terminal of the first flip-flop DT1. In fact, for some embodiments of this application, such as the embodiment where the control switch Sc is a PMOS transistor, the signal to be processed out can also be the signal output by the output terminal of the second flip-flop DT2.

[0142] In other embodiments of this application, the charge output module 30 may provide charge only to the integration module 40 in the first operating state, for example, see [reference needed]. Figure 11 , Figure 12 as well as Figure 13 , Figure 11 This illustration shows another schematic diagram of the module structure of the optical sensor readout circuit in an embodiment of this application. Figure 12 This illustration shows another circuit structure diagram of the optical sensor readout circuit in an embodiment of this application. Figure 13This illustration shows another pulse signal timing diagram of the optical sensor readout circuit in an embodiment of this application. The integration module 40 includes an integrator IN1, and the optical sensing module 50 includes a photodiode PD. The charge output module 30 includes a first sub-switch S01 and a second sub-switch S02. The non-inverting input of the integrator IN1 is used to connect to a first preset voltage V1, and the output of the integrator IN1 is connected to the oscillation module 10. One end of the second sub-switch S02 is connected to the inverting input of the integrator IN1, and the other end is connected to the negative terminal of the photodiode PD. The positive terminal of the photodiode PD is grounded. One end of the first sub-switch S01 is used to connect to the operating voltage VDD, and the other end is connected to a third node M3 between the second sub-switch S02 and the inverting input of the integrator IN1. The control terminal of the first sub-switch S01 is used to connect to a comparison signal Dout and change the switching state based on the comparison signal Dout. The switching state of the first sub-switch S01 is opposite to the switching state of the second sub-switch S02.

[0143] It should be noted that in the above embodiment, since the switching state of the first sub-switch S01 is opposite to that of the second sub-switch S02, when the charge output module 30 is in the first working state, it only provides a charge Q to the integration module 40. When the charge output module 30 is in the second working state, the integration module 40 provides an equal amount of charge Q to the optical sensing module 50. Under this circuit structure, the charge output by the charge output module 30 is still equal to the charge flowing through the optical sensing module 50. At the same time, the current of the optical sensing module 50 satisfies the following relationship:

[0144] I1 = I2 * t01 / t02

[0145] Where I1 is the current of the optical sensing module 50, I2 is the current of the charge output module 30, t01 is the time when the first sub-switch S01 is closed, and t02 is the time when the second sub-switch S02 is open.

[0146] Understandably, the closing time of the first sub-switch S01 and the opening time of the second sub-switch S02 are both t01, and the closing time of the first sub-switch S01 and the closing time of the second sub-switch S02 are both t02. t01 can refer to the high level time of the comparison signal Dout, and t02 can refer to the low level time of the comparison signal Dout. The first sub-switch S01 and the second sub-switch S02 can be MOS transistors, such as PMOS transistors or NMOS transistors.

[0147] Further reading Figure 11 , Figure 12 as well as Figure 13The comparison module 20 includes a first flip-flop DT1, a second flip-flop DT2, a first AND gate AND1, and a first delay De. The control terminal of the first flip-flop DT1 is used to connect to the reference signal F. REF The input of the first flip-flop DT1 is connected to the operating voltage VDD, and the output of the first flip-flop DT1 is connected to the first input of the first AND gate AND1. The control terminal of the second flip-flop DT2 is connected to the oscillation signal F. RET The input of the second flip-flop DT2 is connected to the operating voltage VDD. The output of the first flip-flop DT1 is connected to the second input of the first AND gate AND1. The input of the first delay unit De is connected to the output of the first AND gate AND1. The reset terminals of the first flip-flop DT1 and the second flip-flop DT2 are connected to the output of the delay unit. The control terminal of the first sub-switch S01 is connected to the output of the first flip-flop DT1.

[0148] It should be noted that when the first sub-switch S01 and the second sub-switch S02 are both NMOS or PMOS transistors, the second sub-switch S02 can be controlled simply by using an inverter to invert the comparison signal Dout. Under the control of the signal output by the first flip-flop DT1, the switching states of the first sub-switch S01 and the second sub-switch S02 are opposite, that is, when one is open, the other is closed.

[0149] Understandably, the first sub-switch S01 and the second sub-switch S02 can also be either an NMOS transistor or a PMOS transistor, meaning that the output signal of either the first flip-flop DT1 or the second flip-flop DT2 can be used to control both the first sub-switch S01 and the second sub-switch S02 simultaneously.

[0150] In some embodiments of this application, the ratio of the current of the optical sensing module 50 to the current of the charge output module 30 is in the range of 1:5000 to 1:100, so as to use the current of the charge output module 30 with a larger current value to measure the current of the optical sensing module 50 with a smaller current value.

[0151] In some embodiments of this application, such as an embodiment where the charge output module 30 simultaneously provides charge to both the integration module 40 and the optical sensing module 50 when the charge output module 30 is in a first operating state, see [reference]. Figure 14 as well as Figure 15 , Figure 14 This illustration shows another circuit structure diagram of the optical sensor readout circuit in an embodiment of this application. Figure 15Another pulse signal timing diagram of the optical sensor readout circuit in this embodiment is shown. The charge output module 30 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a control capacitor Cc. One end of the first switch S1 is connected to the first end of the control capacitor Cc, and the other end is used to connect to a second preset voltage V2. One end of the second switch S2 is connected to the second end of the control capacitor Cc, and the other end is connected to the inverting input of the integrator IN1. One end of the third switch S3 is connected to the first node M1 between the first switch S1 and the control capacitor Cc, and the other end is used to ground. One end of the fourth switch S4 is connected to the second node M2 ​​between the second switch S2 and the control capacitor Cc, and the other end is used to connect to the first preset voltage V1. The control terminals of the first and second switches S1 and S2 are used to connect to a comparison signal Dout, and the switch states are changed based on the comparison signal Dout. The control terminals of the third and fourth switches S3 and S4 are used to connect to a control signal Dout2, which is inversely phase to the comparison signal Dout, and the switch states are changed based on the control signal Dout2.

[0152] It should be noted that when the charge output module 30 is in the second operating state, the first switch S1 and the second switch S2 are in the open state, while the third switch S3 and the fourth switch S4 are in the closed state. The charge accumulated on the plate of the control capacitor Cc near the second switch S2 is -Cc*V1. When the charge output module 30 is in the first operating state, the first switch S1 and the second switch S2 are in the closed state, while the third switch S3 and the fourth switch S4 are in the open state. The charge accumulated on the plate of the control capacitor Cc near the second switch S2 is Cc*(V2-V1), thus making the charge output by the charge output module 30 Cc*V2. Therefore, the current of the optical sensing module 50 satisfies the following relationship:

[0153] I1=Cc*V2*N

[0154] Where I1 is the current of the optical sensing module 50, Cc is the capacitance value of the control capacitor Cc, V1 is the first preset voltage V1, V2 is the second preset voltage V2, and N is the number of times the second switch S2 is closed per unit time (e.g., 1 second).

[0155] Understandably, the number of times the second switch S2 is closed can be obtained by counting the number of pulses of the comparison signal Dout using a counter.

[0156] Furthermore, in some embodiments of this application, see further reference. Figure 14 as well as Figure 15The comparison module 20 includes a first flip-flop DT1, a second flip-flop DT2, a first AND gate AND1, a first delay De, and a first inverter PI0. The control terminal of the first flip-flop DT1 is used to input the reference signal F. REF The input of the first flip-flop DT1 is connected to the operating voltage VDD, and the output of the first flip-flop DT1 is connected to the first input of the first AND gate AND1. The control terminal of the second flip-flop DT2 is connected to the oscillation signal F. RET The input of the second flip-flop DT2 is connected to the operating voltage VDD. The output of the first flip-flop DT1 is connected to the second input of the first AND gate AND1. The input of the first delay unit De is connected to the output of the first AND gate AND1. The reset terminals of the first flip-flop DT1 and the second flip-flop DT2 are connected to the output of the delay unit. The input of the first inverter PI0 is connected to the output of the first flip-flop DT1. The control terminals of the first switch S1 and the second switch S2 are connected to the output of the first flip-flop DT1. The control terminals of the third switch S3 and the fourth switch S4 are connected to the output of the first inverter PI0.

[0157] It should be noted that since the signals controlling the switching states of the first switch S1 and the second switch S2 are inversely phase with those of the third switch S3 and the fourth switch S4, when the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all PMOS transistors or NMOS transistors, under the control of the signals output by the first flip-flop DT1 and the second flip-flop DT2, the switching states of the first switch S1 and the second switch S2 are opposite to those of the third switch S3 and the fourth switch S4.

[0158] Understandably, the first switch S1 and the second switch S2 can also be NMOS transistors, while the third switch S3 and the fourth switch S4 can be PMOS transistors. The control terminals of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 can be connected to the output terminal of the first flip-flop DT1.

[0159] In some embodiments of this application, the rising edge of the control signal Dout2 and the falling edge of the comparison signal Dout are not at the same time, and the falling edge of the control signal Dout2 and the rising edge of the comparison signal Dout are not at the same time, so as to avoid the phenomenon of simultaneously turning on or off the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.

[0160] In some embodiments of this application, for example, the comparison module 20 can compare the reference signal F. REF With oscillation signal F RET For an example of the frequency, see [link to example]. Figure 16 as well as Figure 17 , Figure 16This illustration shows another circuit structure diagram of the optical sensor readout circuit in an embodiment of this application. Figure 17 This diagram illustrates another circuit structure of the optical sensor readout circuit in an embodiment of this application. The comparison module includes a first resistor R1, a first comparator op, an equivalent capacitor Ct, a fifth switch S5, and a sixth switch S6. The first resistor R1, the fifth switch S5, and the equivalent capacitor Ct are connected in series. The end of the first resistor R1 facing away from the fifth switch S5 is used to connect to the operating voltage, and the end of the equivalent capacitor Ct facing away from the fifth switch S5 is used to ground. One end of the sixth switch S6 is connected to the fourth node M4 between the fifth switch S5 and the equivalent capacitor Ct, and the other end is used to ground. The inverting input of the first comparator op is used to connect to a third preset voltage V. div The non-inverting input of the first comparator op is connected to the fifth node M5 between the first resistor R1 and the fifth switch S5. The output of the first comparator op is used to output a comparison signal. The control terminal of the fifth switch S5 is used to input the oscillation signal F. RET And based on the oscillation signal F RET The switching state is changed so that the switching state of the sixth switch S6 is opposite to that of the fifth switch S5.

[0161] Specifically, the equivalent capacitance Ct, the fifth switch S5, and the sixth switch S6 constitute the equivalent resistance, and the third preset voltage V div That is, the reference signal; the higher the frequency of the oscillation signal, the higher the voltage V at the non-inverting input of the first comparator op. f2v The lower the voltage, the better, when the voltage at the non-inverting input of the first comparator op is lower than the third preset voltage V. div When the frequency of the oscillation signal is low, the first comparator op outputs a low-level signal; conversely, when the frequency of the oscillation signal is lower, the voltage V at the non-inverting input of the first comparator op increases. f2v The higher the voltage, the higher the voltage at the non-inverting input of the first comparator (op) is compared to the third preset voltage. Vdiv When the first comparator op outputs a low-level signal, it outputs a high-level signal.

[0162] In some embodiments of this application, such as for the embodiment where the charge output module 30 includes a control switch Sc, see [reference]. Figure 16 The comparison signal Dout output by the first comparator op can directly control the control switch Sc to change its switching state. In other embodiments of this application, such as embodiments where the charge output module 30 includes a control capacitor Cc, see [reference needed]. Figure 17 The comparison signal Dout output by the first comparator op can directly control the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4.

[0163] Understandably, the fifth switch S5 and the sixth switch S6 can both be PMOS transistors or NMOS transistors, to transmit the oscillation signal F. RET Control the first switch S5, and transmit the oscillation signal F. RET By inverting the sixth switch S6, the fifth switch S5 and the sixth switch S6 can be reversed. Furthermore, the third preset voltage V... div It is possible Figure 16 or Figure 17 The voltage shown is generated by the voltage divider between the first resistor R1 and the resistor RT. It can also be generated in other ways, such as by providing a separate power supply voltage.

[0164] It should be noted that the above embodiment uses an equivalent capacitor Ct, a fifth switch S5, and a sixth switch S6 to form an equivalent resistance for voltage comparison. In fact, the equivalent capacitor Ct, a fifth switch S5, and a sixth switch S6 can also be used to form an equivalent resistance for current comparison to output the comparison signal Dout.

[0165] In some embodiments of this application, see Figure 2 , Figure 3 or Figure 12 The oscillation module 10 includes a ring oscillator and an acceleration switch Sv. The ring oscillator includes multiple series-connected inverters PI. The control terminal of the acceleration switch Sv is connected to the output terminal of the integrator IN1. One end of the acceleration switch Sv is connected to the operating voltage VDD, and the other end is connected to the power supply terminal of the inverters PI. When the acceleration switch Sv is turned on, the charging rate of the capacitors between the inverters PI increases, thereby accelerating the oscillation of the multiple series-connected inverters PI and increasing the oscillation signal F. RET The oscillation frequency of the inverter PI is reduced; however, when the acceleration switch Sv is turned off, the charging rate of the capacitors between the inverters PI decreases, which correspondingly reduces the oscillation frequency of the multiple series-connected inverters PI and decreases the oscillation signal F. RET The oscillation frequency.

[0166] For example, the acceleration switch Sv is a PMOS transistor. When the output signal Vout voltage of the integrator decreases, the acceleration switch Sv is turned on, and vice versa. Understandably, the oscillation module 10 may also include a level shifter LS to convert the high-level signal voltage output by the ring oscillator into the operating voltage VDD.

[0167] In some embodiments of this application, the control capacitor Cc and the integrator capacitor C0 can be variable capacitors to facilitate current measurement for different types of photodiodes.

[0168] It is worth noting that the above description of the optical sensor readout circuit is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can make equivalent modifications under the guidance of this application. For example, the control capacitor Cc and the integrator capacitor C0 are fixed capacitors; and the acceleration switch Sv is an NMOS transistor or an IGBT transistor.

[0169] Furthermore, to better implement the optical sensor readout circuit in the embodiments of this application, this application also provides a chip based on the optical sensor readout circuit, the chip including the optical sensor readout circuit described in any of the above embodiments. Since the chip in the embodiments of this application includes the optical sensor readout circuit in the above embodiments, it possesses all the beneficial effects of the optical sensor readout circuit in the above embodiments, and will not be repeated here.

[0170] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0171] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0172] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0173] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0174] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0175] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this application, the entire contents of that patent application are incorporated herein by reference, except for historical application documents that are inconsistent with or conflict with the content of this application, and documents that limit the broadest scope of the claims of this application (currently or subsequently appended to this application). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terminology used in the supplementary materials of this application and the content of this application, the descriptions, definitions, and / or terminology used in this application shall prevail.

[0176] The above provides a detailed description of the optical sensor readout circuit and chip provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A light sensor readout circuit for reading the current of a light sensing module, characterized in that, include: An oscillation module, which is used to output an oscillation signal; The comparison module is used to compare the reference signal with the oscillation signal and output a comparison signal; A charge output module, wherein the charge output module is used to output charge according to the comparison signal; An integration module is used to change the oscillation frequency of the oscillation module according to the charge output by the charge output module; The comparison module includes a phase comparison submodule, which is used to compare the phase difference between the reference signal and the oscillation signal. The charge output module outputs a charge equal to the charge passing through the optical sensing module.

2. The optical sensor readout circuit as described in claim 1, characterized in that, The charge output module alternately outputs charges according to the comparison signal; The integration module alternately controls the oscillation frequency of the oscillation module to increase or decrease according to the charges alternately output by the charge output module; The integration module accumulates charge during the period when the charge output module outputs charge, and releases the accumulated charge through the optical sensing module when the charge output module stops outputting charge.

3. The optical sensor readout circuit as described in claim 2, characterized in that, The charge output module has a first operating state and a second operating state, and the charge output module switches back and forth between the first operating state and the second operating state based on the comparison signal. When the charge output module is in the first working state, the charge output module provides charge to the integration module, and the integration module controls the oscillation module to increase the oscillation frequency based on the accumulated charge; When the charge output module is in the second working state, the charge output module stops providing charge to the integration module, and the integration module releases charge to the optical sensing module. The integration module controls the oscillation module to reduce the oscillation frequency based on the released charge.

4. The optical sensor readout circuit as described in claim 3, characterized in that, The optical sensing module is connected to the output terminal of the charge output module. When the charge output module is in the first working state, the charge output module simultaneously provides charge to the integration module and the optical sensing module. When the charge output module is in the second working state, the charge output module stops providing charge to the integration module and the optical sensing module.

5. The optical sensor readout circuit as described in claim 4, characterized in that, The integration module includes an integrator, and the optical sensing module includes a photodiode. The inverting input of the integrator is connected to the negative terminal of the photodiode, the non-inverting input of the integrator is used to connect to a first preset voltage, the output of the integrator is connected to the oscillation module, and the positive terminal of the photodiode is used to ground.

6. The optical sensor readout circuit as described in claim 5, characterized in that, The charge output module includes a control switch; One end of the control switch is connected to the inverting input of the integrator, and the other end is used to connect to a fixed current source. The control terminal of the control switch is used to connect to the comparison signal and change the switch state based on the comparison signal, so that the charge output module switches back and forth between the first working state and the second working state.

7. The optical sensor readout circuit as described in claim 6, characterized in that, The current of the optical sensing module satisfies the following relationship: I1 = I2 * T1 / (T1 + T2) Wherein, I1 is the current of the optical sensing module, I2 is the current of the charge output module, T1 is the time for the control switch to close, and T2 is the time for the control switch to open.

8. The optical sensor readout circuit as described in claim 6, characterized in that, The comparison module further includes a pulse width adjustment submodule; The phase comparison submodule outputs a signal to be processed based on the phase difference between the reference signal and the oscillation signal, wherein the pulse width of the signal to be processed is equal to the phase difference between the oscillation signal and the reference signal; The pulse width adjustment submodule is used to adjust the pulse width of the signal to be processed in order to generate a comparison signal with a fixed pulse width.

9. The optical sensor readout circuit as described in claim 8, characterized in that, The current of the optical sensing module satisfies the following relationship: I1=I2*T*N Wherein, I1 is the current of the optical sensing module, I2 is the current of the charge output module, T is the fixed pulse width of the comparison signal, and N is the number of times the control switch is closed per unit time.

10. The optical sensor readout circuit as described in claim 8, characterized in that, The phase comparison submodule includes a first flip-flop, a second flip-flop, a first AND gate, and a first delay unit; the pulse width adjustment submodule includes a pulse generator. The control terminal of the first flip-flop is used to connect to the reference signal, the input terminal of the first flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate. The control terminal of the second flip-flop is used to connect to the oscillation signal, the input terminal of the second flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the second input terminal of the first AND gate. The input terminal of the first delay is connected to the output terminal of the first AND gate, and the reset terminals of the first flip-flop and the second flip-flop are connected to the output terminal of the delay. The input terminal of the pulse generator is connected to the output terminal of the first trigger or the second trigger, and the output terminal of the pulse generator is connected to the control terminal of the control switch.

11. The optical sensor readout circuit as described in claim 3, characterized in that, The integration module includes an integrator, and the optical sensing module includes a photodiode. The charge output module includes a first sub-switch and a second sub-switch; The non-inverting input of the integrator is used to connect to a first preset voltage, and the output of the integrator is connected to the oscillation module. One end of the second sub-switch is connected to the inverting input of the integrator, and the other end is connected to the negative terminal of the photodiode, with the positive terminal of the photodiode used for grounding; One end of the first sub-switch is used to connect to the working voltage, and the other end is connected to the third node between the second sub-switch and the inverting input terminal of the integrator; The control terminal of the first sub-switch is used to receive the comparison signal and change the switch state based on the comparison signal, and the switch state of the first sub-switch is opposite to that of the second sub-switch.

12. The optical sensor readout circuit as described in claim 11, characterized in that, The current of the optical sensing module satisfies the following relationship: I1 = I2 * t01 / t02 Wherein, I1 is the current of the optical sensing module, I2 is the current of the charge output module, t01 is the time when the first sub-switch is closed, and t02 is the time when the second sub-switch is opened.

13. The optical sensor readout circuit as described in claim 12, characterized in that, The phase comparison submodule includes a first flip-flop, a second flip-flop, a first AND gate, and a first delay. The control terminal of the first flip-flop is used to connect to the reference signal, the input terminal of the first flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate. The control terminal of the second flip-flop is used to connect to the oscillation signal, the input terminal of the second flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the second input terminal of the first AND gate. The input terminal of the first delay is connected to the output terminal of the first AND gate, and the reset terminals of the first flip-flop and the second flip-flop are connected to the output terminal of the delay. The control terminal of the first sub-switch is connected to the output terminal of the first trigger.

14. The optical sensor readout circuit as described in any one of claims 7, 9, or 12, characterized in that, The ratio of the current of the optical sensing module to the current of the charge output module ranges from 1:5000 to 1:

100.

15. The optical sensor readout circuit as described in claim 5, characterized in that, The charge output module includes a first switch, a second switch, a third switch, a fourth switch, and a control capacitor; One end of the first switch is connected to the first end of the control capacitor, and the other end is used to connect to the second preset voltage; One end of the second switch is connected to the second end of the control capacitor, and the other end is connected to the inverting input of the integrator; One end of the third switch is connected to the first node between the first switch and the control capacitor, and the other end is used for grounding; One end of the fourth switch is connected to the second node between the second switch and the control capacitor, and the other end is used for the first preset voltage; The control terminals of the first and second switches are used to receive the comparison signal and change the switch state based on the comparison signal; the control terminals of the third and fourth switches are used to receive a control signal that is inversely related to the comparison signal and change the switch state based on the control signal.

16. The optical sensor readout circuit as described in claim 15, characterized in that, The current of the optical sensing module satisfies the following relationship: I1=Cc*V2*N Wherein, I1 is the current of the optical sensing module, Cc is the capacitance value of the control capacitor, V2 is the second preset voltage, and N is the number of times the second switch is closed per unit time.

17. The optical sensor readout circuit as described in claim 15, characterized in that, The phase comparison submodule includes a first flip-flop, a second flip-flop, a first AND gate, a first delay unit, and a first inverter. The control terminal of the first flip-flop is used to connect to the reference signal, the input terminal of the first flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate. The control terminal of the second flip-flop is used to connect to the oscillation signal, the input terminal of the second flip-flop is used to connect to the operating voltage, and the output terminal of the first flip-flop is connected to the second input terminal of the first AND gate. The input terminal of the first delay is connected to the output terminal of the first AND gate, and the reset terminals of the first flip-flop and the second flip-flop are connected to the output terminal of the delay. The input terminal of the first inverter is connected to the output terminal of the first flip-flop; The control terminals of the first and second switches are connected to the output terminal of the first trigger, and the control terminals of the third and fourth switches are connected to the output terminal of the first inverter.

18. The optical sensor readout circuit as described in claim 5 or 11, characterized in that, The oscillation module includes a ring oscillator and an acceleration switch; The ring oscillator includes multiple ring-connected inverters, and the control terminal of the acceleration switch is connected to the output terminal of the integrator. One end of the acceleration switch is used to connect to the operating voltage, and the other end is connected to the power supply terminal of the inverter.

19. A chip, characterized in that, Includes the optical sensor readout circuit as described in any one of claims 1 to 18.

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