An apparatus and method for improving the predictive action rate of high-voltage direct current commutation failure.

Abstract

This invention provides an apparatus and method for improving the prediction and response rate of high-voltage direct current (HVDC) commutation failure. The apparatus includes a first execution unit and a second execution unit. The first execution unit has a fast task execution cycle, and the second execution unit has a slow task execution cycle, wherein the fast task execution cycle is shorter than the slow task execution cycle. The first execution unit includes an AC synchronization voltage input and signal processing module, a commutation failure prediction module, a minimum commutation margin control module, and a pulse signal generation and processing module. The second execution unit includes other analog input and signal processing modules, a communication interface signal processing module, a main controller logic module, a main logic processing module, and other logic processing modules. Under limited processor performance conditions, this invention maximizes the prediction and response rate of HVDC commutation failure by optimizing the execution cycles of various functional modules, thus facilitating the handling of commutation failures.

Description

Technical Field

[0001] This invention relates to the field of ultra-high voltage direct current transmission. Background Technology

[0002] High-voltage direct current (HVDC) transmission is widely used to address the problem of geographically inverse distribution of energy and electricity load. Currently, my country has built dozens of HVDC transmission systems, transmitting energy from the west to high-load areas in the east and central regions. HVDC transmission uses grid-commutated converters with thyristor devices. When disturbances or faults occur in the inverter-side AC system, the converter faces the risk of commutation failure. Commutation failure will cause fluctuations in transmitted power and problems with AC system stability.

[0003] Commutation failure predictive control is a primary control strategy for high-voltage direct current (HVDC) transmission control systems to address commutation failures. This strategy involves acquiring the AC bus synchronization voltage and, upon meeting certain criteria, outputting an advance trigger angle command. Its response rate reflects how quickly the control system responds to changes in the AC system. The main factors determining the response rate are as follows:

[0004] (1) Criteria for predictive control logic of commutation failure;

[0005] (2) AC bus synchronous voltage sampling rate and transmission rate;

[0006] (3) Execution rate of commutation failure prediction control logic;

[0007] (4) Processor performance.

[0008] Regarding point (1), the current device uses mature logic criteria. The other three points are closely related to the performance of the device's hardware processor. In particular, given the current chip shortage, domestically produced mid-to-high-end chips are just starting out, and their performance cannot yet match that of currently used high-end imported chips. Therefore, under the condition of limited processor performance, it is of great significance to study methods and devices for maximizing the prediction speed of high-voltage DC commutation failure. Summary of the Invention

[0009] To address the above problems, this invention provides an apparatus and method for improving the prediction rate of high-voltage DC commutation failure.

[0010] To achieve the above objectives, the technical solution of the present invention is as follows:

[0011] An apparatus for improving the prediction speed of high voltage direct current commutation failure includes a first execution unit and a second execution unit. The first execution unit has a fast task execution cycle, and the second execution unit has a slow task execution cycle. The fast task execution cycle is shorter than the slow task execution cycle.

[0012] The first execution unit includes an AC synchronization voltage input and signal processing module, a commutation failure prediction module, a minimum commutation margin control module, and a pulse signal generation and processing module;

[0013] The second execution unit includes other analog input and signal processing modules, communication interface signal processing modules, main controller logic modules, main logic processing modules and other logic processing modules.

[0014] Preferably, the AC synchronization voltage input and signal processing module is configured to acquire the original AC synchronization voltage signal in the power grid phase-commutator through the AC synchronization voltage acquisition board and convert it into an AC synchronization voltage processed signal.

[0015] The commutation failure prediction module is configured to analyze whether the AC synchronization voltage processing signal meets the high voltage DC commutation failure prediction action criterion and output a command signal.

[0016] The minimum commutation margin control module is configured to receive a command signal and compare the command signal to obtain a trigger command;

[0017] The pulse signal generation and processing module is configured to receive trigger commands, output trigger pulse signals to the VBE control valve device according to the trigger commands, and receive feedback pulse signals sent by the VBE control valve device.

[0018] Preferably, the slow task execution cycle is a multi-level task execution cycle; wherein, the other analog input and signal processing modules and the communication interface signal processing module have a first-level slow task execution cycle; the main controller logic module and the main logic processing module have a second-level slow task execution cycle; the other auxiliary logic processing modules have a third-level slow task execution cycle; the first-level slow task execution cycle is shorter than the second-level slow task execution cycle, and the second-level slow task execution cycle is shorter than the third-level slow task execution cycle.

[0019] Preferably, the fast task execution cycle is 10-20 microseconds, and the slow task execution cycle is greater than or equal to 100 microseconds.

[0020] Preferably, the other analog input and signal processing modules are configured to receive analog valve-side commutation current, analog DC voltage, and analog DC current.

[0021] The communication interface signal processing module is configured to process inter-host communication, inter-system communication, IO communication, and station-level control network communication.

[0022] The main controller logic module includes a current controller, a voltage controller, and a constant off-angle controller.

[0023] The main logic processing module is configured to implement switch and disconnector interlocking control, sequence control, and mode control.

[0024] A method for improving the prediction speed of high-voltage DC commutation failure first determines the fast task execution cycle and completes the following steps within the fast task execution cycle:

[0025] Acquire the raw AC synchronization voltage signal in the power grid phase-commutation converter;

[0026] The original AC synchronization voltage signal is converted to obtain the processed AC synchronization voltage signal;

[0027] The command signal is obtained by analyzing the AC synchronization voltage processing signal;

[0028] The command signal is compared to obtain the trigger command;

[0029] A trigger pulse signal is generated according to the trigger command and sent to the VBE valve control device, which then generates a feedback pulse signal to provide feedback on the pulse execution result.

[0030] Preferably, the conversion of the original AC synchronization voltage signal includes differential compensation of the original AC synchronization voltage signal, and the differential compensation algorithm is as follows:

[0031] or

[0032]

[0033] Among them, Time t Uac t These are the real-time clock and AC synchronization voltage values ​​of the field-programmable gate array, respectively; Time ts Uac ts These are the real-time clock and the voltage value of the current acquisition point for the AC synchronous voltage, respectively; Time ts-n Uac ts-n These are the real-time clocks and voltage values ​​corresponding to n sampling points of AC synchronous voltage, respectively, where n ≥ 3.

[0034] Preferably, in the present invention, the difference in the difference compensation is the time delay caused by the secondary link when obtaining the original AC synchronization voltage signal and pulse execution.

[0035] Preferably, the analysis of the AC synchronization voltage processing signal includes determining whether the AC synchronization voltage processing signal meets the prediction action criterion, wherein the prediction action criterion is...

[0036] | UacL1 +Uac L2 +Uac L3 |≥Z_DIFF_SET or

[0037] |U αβ -U αβ_f |≥ABZ_DET_SET

[0038] Among them, Uac L1 Uac L2 Uac L3 For three-phase synchronous voltage, Z_DIFF_SET is the zero-sequence start-up setting, U αβ U is the effective value of the three-phase synchronous voltage. αβ_f ABZ_DET_SET represents the effective value of the three-phase synchronous voltage after passing through a low-pass filter, and ABZ_DET_SET represents the three-phase start-up setting.

[0039] Preferably, the comparison of the instruction signal includes superimposing the instruction signal with a set value and performing logical operations, and comparing the operation result with the set value. If the operation result is less than or equal to the set value, a trigger command is output; if the operation result is greater than the set value, no trigger command is output.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] This invention, under limited processor performance conditions, optimizes the execution cycle of each functional module in the configuration program, thereby maximizing the speed of high-voltage DC commutation failure prediction and improving the response when commutation failure occurs.

[0042] The technical solution provided by this invention operates on a high-speed execution cycle, encompassing AC synchronization voltage acquisition, logic processing, and subsequent execution output. Therefore, when the AC synchronization voltage changes, AC voltage sampling, signal processing, logic judgment, and execution output can be completed within a relatively short execution cycle. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the device structure for improving the prediction speed of high voltage DC commutation failure in Embodiment 1 of the present invention;

[0044] Figure 2 This is a schematic diagram of the execution flow of the method for improving the prediction action rate of high voltage DC commutation failure in Embodiment 2 of the present invention; Detailed Implementation

[0045] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0046] Example 1:

[0047] Please refer to Figure 1Embodiment 1 of the present invention provides a device for improving the action rate of high voltage DC commutation failure prediction, including an AC synchronous voltage input and signal processing module with a fast task execution cycle, a commutation failure prediction module, a minimum commutation margin control module, and a pulse signal generation and processing module.

[0048] It also includes other analog input and signal processing modules with slow task execution cycles, communication interface signal processing modules, main controller logic modules, and main logic processing modules.

[0049] Among them, the AC synchronization voltage input and signal processing module acquires the original AC synchronization voltage signal in the grid commutator through the AC synchronization voltage acquisition board and converts it into an AC synchronization voltage processed signal.

[0050] The commutation failure prediction module analyzes whether the AC synchronization voltage processing signal meets the high voltage DC commutation failure prediction action criterion and outputs a command signal.

[0051] The minimum commutation margin control module receives the command signal and compares the command signal to obtain the trigger command;

[0052] The pulse signal generation and processing module receives a trigger command and outputs a trigger pulse signal to the VBE control valve device according to the trigger command, and also receives a feedback pulse signal sent by the VBE control valve device.

[0053] Other analog input and signal processing modules are configured to receive analog valve-side commutation current, analog DC voltage, and analog DC current.

[0054] The communication interface signal processing module is configured to handle inter-host communication, inter-system communication, IO communication, and station-level control network communication. Its first-level slow task execution cycle is 100 microseconds; this ensures rapid processing of signal input and output.

[0055] The main controller logic module includes a current controller, a voltage controller, and a constant off-angle controller. Its second-level slow task execution cycle is 1 millisecond. Due to the presence of smoothing reactors and long overhead lines, the overall control inertia of HVDC transmission is relatively large; therefore, a 1-millisecond execution cycle can meet the logic requirements of the main controller. Except for the converter valves, the operation time of other primary equipment is on the order of tens of milliseconds or seconds; a 1-millisecond execution cycle can meet the requirements of the main logic processing module.

[0056] The main logic processing module is configured to implement interlocking control of switches and disconnectors, sequence control, and mode control, with a second-level slow task execution cycle of 1 millisecond. Additionally, the device in this embodiment includes other auxiliary modules, with a third-level slow task execution cycle of 4 milliseconds.

[0057] Example 2:

[0058] Please refer to Figure 2 Embodiment 2 of the present invention provides a method for improving the prediction speed of high voltage DC commutation failure, which involves determining a fast task execution cycle and completing the following steps within the fast task execution cycle:

[0059] S1: Obtain the raw AC synchronization voltage signal in the grid commutator converter;

[0060] S2: Convert the original AC synchronization voltage signal to obtain the processed AC synchronization voltage signal;

[0061] S3: Analyze the AC synchronization voltage processing signal to obtain the command signal;

[0062] S4: Compare the command signal to obtain the trigger command;

[0063] S5: Generate a trigger pulse signal to the VBE valve control device according to the trigger command, and the VBE valve control device generates a feedback pulse signal to the pulse signal generation and processing module.

[0064] The conversion of the original AC synchronization voltage signal includes difference compensation of the original AC synchronization voltage signal. The algorithm for difference compensation is as follows:

[0065]

[0066] Among them, Time t Uac t These are the real-time clock and AC synchronization voltage values ​​of the field-programmable gate array, respectively; Time ts Uac ts These are the real-time clock and the voltage value of the current acquisition point for AC synchronous voltage, respectively.

[0067] The difference in the difference compensation refers to the time delay caused by the secondary link when acquiring the original AC synchronization voltage signal.

[0068] Analyzing the AC synchronization voltage processing signal includes determining whether the AC synchronization voltage processing signal meets the prediction action criterion, wherein the prediction action criterion is...

[0069] | Uac L1 +Uac L2 +Uac L3 |≥Z_DIFF_SET

[0070] Among them, Uac L1 Uac L2 Uac L3Z_DIFF_SET is the three-phase synchronous voltage, Z_DIFF_SET is the zero-sequence start-up setting, and ABZ_DET_SET is the three-phase start-up setting.

[0071] The comparison of the command signal includes superimposing the command signal with the set value and performing logical operations, and comparing the result with the set value. If the result is less than or equal to the set value, a trigger command is output; if the result is greater than the set value, no trigger command is output.

[0072] Specifically, the original AC synchronization voltage signal is converted into an AC synchronization voltage processed signal after differential compensation, and then sent to the commutation failure prediction module for analysis and comparison. The commutation failure prediction module outputs a command signal and sends it to the minimum commutation margin control module. The output of the minimum commutation margin control module is sent to the pulse signal generation and processing module to generate a CP (trigger signal pulse) signal and send it to the VBE valve control device. The VBE valve control device returns the FP (feedback signal pulse) to the pulse signal generation and processing module. This process is completed in one fast task execution cycle, and the fast task execution cycle is 20 microseconds.

[0073] Therefore, it is easy to obtain the sensitivity of the action rate in this embodiment, converted into electrical angles as follows: It can be seen that this embodiment greatly improves the prediction speed of high voltage DC commutation failure compared with the prior art.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Those skilled in the art can still make modifications or equivalent substitutions to the specific implementation of the present invention by referring to the above embodiments. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the present invention pending approval.

Claims

1. A device for improving the prediction and response rate of high-voltage direct current commutation failure, characterized in that, It includes a first execution unit and a second execution unit. The first execution unit has a fast task execution cycle, and the second execution unit has a slow task execution cycle. The fast task execution cycle is shorter than the slow task execution cycle. The first execution unit includes an AC synchronization voltage input and signal processing module, a commutation failure prediction module, a minimum commutation margin control module, and a pulse signal generation and processing module; The second execution unit includes other analog input and signal processing modules, communication interface signal processing module, main controller logic module, main logic processing module and other logic processing modules; The AC synchronization voltage input and signal processing module is configured to acquire the original AC synchronization voltage signal in the grid phase-commutator through the AC synchronization voltage acquisition board and convert it into an AC synchronization voltage processing signal. The commutation failure prediction module is configured to analyze whether the AC synchronization voltage processing signal meets the high voltage DC commutation failure prediction action criterion and output a command signal. The minimum commutation margin control module is configured to receive a command signal and compare the command signal to obtain a trigger command; The pulse signal generation and processing module is configured to receive trigger commands, output trigger pulse signals to the VBE control valve device according to the trigger commands, and receive feedback pulse signals sent by the VBE control valve device. The AC synchronization voltage input and signal processing module is configured to acquire the raw AC synchronization voltage signal from the grid phase-change converter via an AC synchronization voltage acquisition board and convert it into a processed AC synchronization voltage signal. This includes performing difference compensation on the raw AC synchronization voltage signal, with the difference compensation algorithm being as follows: or ， in, Time t , Uac t These are the real-time clock and AC synchronization voltage values ​​of the field-programmable gate array, respectively. Time ts , Uac ts These are the real-time clock corresponding to the current acquisition point of the AC synchronous voltage and the voltage value of the current acquisition point, respectively. Time ts-n , Uac ts-n AC synchronization voltage n The real-time clock corresponding to each data collection point and n The voltage value corresponding to each sampling point n ≥3.

2. The device for improving the prediction and response rate of high-voltage DC commutation failure according to claim 1, characterized in that: The slow task execution cycle is a multi-level task execution cycle; wherein, the other analog input and signal processing modules and the communication interface signal processing module have a first-level slow task execution cycle; the main controller logic module and the main logic processing module have a second-level slow task execution cycle; the other logic processing modules have a third-level slow task execution cycle; the first-level slow task execution cycle is shorter than the second-level slow task execution cycle, and the second-level slow task execution cycle is shorter than the third-level slow task execution cycle.

3. The device for improving the prediction and response rate of high-voltage DC commutation failure according to claim 1, characterized in that: The fast task execution cycle is 10-20 microseconds, and the slow task execution cycle is greater than or equal to 100 microseconds.

4. The device for improving the prediction and response rate of high-voltage DC commutation failure according to claim 1, characterized in that: The other analog input and signal processing modules are configured to receive analog valve-side commutation current, analog DC voltage, and analog DC current. The communication interface signal processing module is configured to process inter-host communication, inter-system communication, IO communication, and station-level control network communication. The main controller logic module includes a current controller, a voltage controller, and a constant off-angle controller. The main logic processing module is configured to implement switch and disconnector interlocking control, sequence control, and mode control.

5. A method for improving the prediction speed of high-voltage direct current commutation failure, characterized in that, Determine the fast task execution cycle, and complete the following steps within the fast task execution cycle: Acquire the raw AC synchronization voltage signal in the power grid phase-commutation converter; The original AC synchronization voltage signal is converted to obtain the processed AC synchronization voltage signal; The command signal is obtained by analyzing the AC synchronization voltage processing signal; The command signal is compared to obtain the trigger command; A trigger pulse signal is generated according to the trigger command and sent to the VBE valve control device, and the VBE valve control device generates a feedback pulse signal to provide feedback on the pulse execution result. The conversion of the original AC synchronization voltage signal includes differential compensation of the original AC synchronization voltage signal, and the algorithm for differential compensation is as follows: or ， in, Time t , Uac t These are the real-time clock and AC synchronization voltage values ​​of the field-programmable gate array, respectively. Time ts , Uac ts These are the real-time clock corresponding to the current acquisition point of the AC synchronous voltage and the voltage value of the current acquisition point, respectively. Time ts-n , Uac ts-n AC synchronization voltage n The real-time clock corresponding to each data collection point and n The voltage value corresponding to each sampling point n ≥3.

6. The method for improving the prediction and response rate of high-voltage direct current commutation failure according to claim 5, characterized in that: The difference in the difference compensation refers to the time delay caused by the secondary link when acquiring the original AC synchronization voltage signal and executing the pulse.

7. The method for improving the prediction and response rate of high-voltage direct current commutation failure according to claim 5, characterized in that: The analysis of the AC synchronization voltage processing signal includes determining whether the AC synchronization voltage processing signal meets the prediction action criterion, wherein the prediction action criterion is... or ， in, Uac L1 , Uac L2 , Uac L3 It is a three-phase synchronous voltage. UZ _ DIFF _ SET Set the zero-sequence start value. U αβ This is the effective value of the three-phase synchronous voltage. U αβ_f The effective value of the three-phase synchronous voltage after passing through a low-pass filter. ABZ _ DET _ SET Set as the three-phase start-up value.

8. The method for improving the prediction and response rate of high-voltage direct current commutation failure according to claim 5, characterized in that: The comparison of the command signal includes superimposing the command signal with the set value and performing logical operations, and comparing the operation result with the set value. If the operation result is less than or equal to the set value, a trigger command is output; if the operation result is greater than the set value, no trigger command is output.

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