Fault detection method and plasma processing device

Abstract

This disclosure relates to a fault detection method and a plasma processing apparatus. The method describes a fault detection method for an impedance adjustment section located between multiple local windows and ground in a plasma processing apparatus. The apparatus includes: a metal window dividing a processing container into an antenna chamber and a processing chamber, the metal window having multiple local windows; an antenna for generating inductively coupled plasma; and an electrostatic chuck. The impedance adjustment section includes multiple capacitive elements located between the multiple local windows and ground. The method includes the following steps: applying a DC voltage to the electrostatic chuck; initiating the supply of high-frequency power for power supply and / or high-frequency power for bias; stabilizing the supply of high-frequency power for power supply and high-frequency power for bias; measuring the capacitive element voltage generated in each of the multiple capacitive elements during substrate processing; and determining a fault in the multiple impedance adjustment sections based on a comparison of the capacitive element voltages of each of the multiple capacitive elements with a threshold value.

Description

Technical Field

[0001] This disclosure relates to a fault detection method and a plasma processing apparatus. Background Technology

[0002] For example, Patent Document 1 discloses an inductively coupled plasma (ICP) processing apparatus comprising: a processing chamber for housing a substrate to be processed for plasma processing; and a high-frequency antenna for generating an induced electric field within the processing chamber. A non-magnetic metal window is formed in the ICP processing apparatus between the high-frequency antenna and the processing chamber, insulated from the main container constituting the processing chamber.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-29584 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] This disclosure provides a technique for detecting faults in components used to adjust the impedance of a plasma processing apparatus.

[0008] Solution for solving the problem

[0009] According to one aspect of this disclosure, a fault detection method is provided for detecting faults in multiple impedance adjustment units in a plasma processing apparatus, the plasma processing apparatus comprising: a processing container; a metal window dividing the processing container into an antenna chamber and a processing chamber, the metal window having multiple partial windows; an inductively coupled antenna for generating inductively coupled plasma by high-frequency power supplied to the antenna chamber; an electrostatic chuck for electrostatically adsorbing a substrate to be processed within the processing chamber; and a lower electrode supporting the electrostatic chuck, the lower electrode being supplied with a bias voltage using high-frequency power, wherein the multiple impedance adjustment units include those disposed in the multiple... Multiple capacitive elements between a local window and ground are used to adjust the impedance in the multiple local windows. The fault detection method includes the following steps: applying a DC voltage to the electrostatic chuck; starting the supply of at least one of the high-frequency power for power supply and the high-frequency power for bias voltage; stabilizing the supply of the high-frequency power for power supply and the high-frequency power for bias voltage; measuring the capacitive element voltage generated in each of the multiple capacitive elements during the processing of the substrate; and determining the fault of the multiple impedance adjustment units based on the comparison result of the capacitive element voltage of each of the multiple capacitive elements with a predetermined threshold.

[0010] The effects of the invention

[0011] Based on one aspect, it is possible to detect faults in components used to adjust the impedance of the plasma processing device. Attached Figure Description

[0012] Figure 1 This is a cross-sectional schematic diagram illustrating an example of the plasma processing apparatus according to the embodiment.

[0013] Figure 2 This is a diagram illustrating an example of the impedance adjustment circuit involved in the embodiment.

[0014] Figure 3 This is a diagram illustrating an example of the configuration of multiple local windows and impedance adjustment circuits involved in the embodiment.

[0015] Figure 4 This is a diagram showing the hardware structure of the control unit involved in the embodiment.

[0016] Figure 5 This is a diagram showing the functional structure of the control unit involved in the embodiment.

[0017] Figure 6 This is a flowchart illustrating the fault detection method involved in the implementation.

[0018] Figure 7 This is a diagram illustrating an example of the measurement results of the voltage of the capacitor element involved in the embodiment.

[0019] Figure 8 It is an example of a table that stores the maximum voltage value of a capacitor element and the judgment result.

[0020] Figure 9 This is a flowchart illustrating the anomaly determination method involved in the implementation method. Detailed Implementation

[0021] The manner in which this disclosure is carried out will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals are sometimes used to refer to the same structural parts, and repeated descriptions are omitted.

[0022] [Plasma Processing Device]

[0023] use Figures 1-3 This describes the plasma processing apparatus involved in the implementation method. Figure 1 This is a cross-sectional schematic diagram showing an example of the plasma processing apparatus 100 according to the embodiment. Figure 2 This is a diagram illustrating an example of the impedance adjustment circuit 18 involved in the embodiment. Figure 3 This is a diagram illustrating an example of the configuration of multiple local windows and impedance adjustment circuit 18 involved in the embodiment.

[0024] The plasma processing apparatus 100 described in the embodiments is used, for example, for etching metal films, ITO films, oxide films, etc., and for ashing of resist films when forming thin-film transistors on glass substrates for FPDs (Flat Panel Displays). Here, examples of FPDs include liquid crystal displays (LCDs), electroluminescent (EL) displays, and plasma display panels (PDPs).

[0025] The plasma processing apparatus 100, for example, has a cylindrical, airtight processing container 1 with an inner wall surface made of a conductive material such as aluminum that has undergone anodizing (aluminum anodizing). This processing container 1 is grounded via a grounding wire 1a. The processing container 1 is divided into an upper antenna chamber 3 and a lower processing chamber 4 by a metal window 2 formed in an insulated manner from the processing container 1. In this example, the metal window 2 forms the top wall of the processing chamber 4. The metal window 2 is, for example, made of a non-magnetic and conductive metal. Examples of metals disclosed herein are aluminum or alloys containing aluminum. The metal window 2 can be supported on the side wall of the processing container 1, or it can be suspended from the top of the antenna chamber 3.

[0026] A gas supply pipe 20a running vertically through the antenna chamber 3 is provided. Multiple branch pipes (not shown) branch out from the gas flow path 12 within the gas supply pipe 20a, and connect to local windows 22a, 22b, and 22c, which are formed by dividing the metal window 2 into multiple sections by the insulating material 6, to supply gas to each local window. Local windows 22a, 22b, and 22c are part of the local windows of the metal window 2, and are collectively referred to as local windows 22.

[0027] Each local window 22 has a gas space (not shown) inside and multiple gas outlets on its surface facing the processing chamber 4, supplying gas into the processing chamber 4 from these outlets. A gas supply pipe 20a extends from the top of the processing container 1 to the outside of the processing container 1, connecting to the processing gas supply unit 20. With this structure, when plasma processing is performed on the substrate G (hereinafter also referred to as substrate G), the processing gas supplied from the processing gas supply unit 20 is ejected into the processing chamber 4 via the gas supply pipe 20a.

[0028] Inside the antenna chamber 3, a high-frequency (RF) antenna 13 is mounted on the metal window 2, facing the metal window 2. The RF antenna 13 is separated from the metal window 2 by a spacer 17 made of insulating material. The RF antenna 13 is a vortex-shaped antenna. The metal window 2 is divided into, for example, 24 partial windows 22 at the bottom of the vortex-shaped antenna (see reference). Figure 3However, the number of local windows 22 is not limited to this; it can also be 40 or more. The high-frequency antenna 13 is an example of an inductively coupled antenna used to generate inductively coupled plasma using high-frequency power supplied to the antenna chamber 3.

[0029] During plasma processing, high-frequency power (hereinafter referred to as power RF power) for generating an induced electric field, for example at a frequency of 13.56 MHz, is supplied to the high-frequency antenna 13 from the first high-frequency power supply 15 via the matching unit 14 and the power supply component 16. Although not shown, the high-frequency antenna 13 in this example is constructed concentrically from an outer loop antenna, a middle loop antenna, and an inner loop antenna, and has power supply sections 41, 42, and 43 respectively connected to the power supply component 16. Antenna lines extend circumferentially from these power supply sections 41, 42, and 43, forming a three-loop high-frequency antenna 13. A capacitor (not shown) is connected to the end of each antenna line, and each antenna line is grounded via the capacitor. There may be one power supply section 41, 42, and 43, or two or more. Through the high-frequency antenna 13, which is supplied with power RF power in this way, an induced electric field is formed in the processing chamber 4 via the metal window 2, and plasma of the supplied processing gas is generated in the processing chamber 4 through this induced electric field. Therefore, after supplying power (RF) to the high-frequency antenna 13, plasma treatment is performed on the substrate G using plasma generated from the processing gas.

[0030] A worktable ST, separated from the high-frequency antenna 13 by a metal window 2, is disposed below the processing chamber 4. The worktable ST has a lower electrode 23 and an insulating frame 24. The lower electrode 23 is made of a conductive material, such as aluminum with an anodized surface. A substrate G is placed on an electrostatic chuck 48 disposed on the upper surface of the lower electrode 23. An adsorption electrode 49 is disposed inside the electrostatic chuck 48. The adsorption electrode 49 is connected to a DC power supply 47 via a power supply line 46. By applying a DC voltage from the DC power supply 47 to the adsorption electrode 49, the substrate G is held in place by electrostatic adsorption on the electrostatic chuck 48.

[0031] The lower electrode 23 is housed within the insulating frame 24 and supported on the bottom surface of the processing chamber 4. Additionally, a loading / unloading outlet 27a for loading and unloading the substrate G and a gate valve 27 for opening and closing the outlet are provided on the side wall 4a of the processing chamber 4.

[0032] The lower electrode 23 is connected to the second high-frequency power supply 29 via a matching device 28 through a power supply line 25a disposed within the hollow support 25. The second high-frequency power supply 29 applies a bias voltage (hereinafter also referred to as bias RF power) of, for example, 3.2 MHz to the lower electrode 23 during plasma processing. The bias RF power effectively attracts ions from the plasma generated within the processing chamber 4 to the substrate G.

[0033] Furthermore, a temperature sensor and a temperature control mechanism (not shown) consisting of a heating unit such as a ceramic heater and a refrigerant flow path are installed inside the lower electrode 23 to control the temperature of the substrate G. The piping and wiring for these mechanisms and components are led out of the processing container 1 through the hollow support column 25.

[0034] Between the workbench ST and the side wall 4a of the processing chamber 4, a partition 32 composed of multiple components arranged in a ring is provided to surround the workbench ST, allowing gas to pass through multiple through holes provided in at least a portion of the partition 32 to the exhaust space. An exhaust pipe 31 is provided at the bottom of the processing chamber 4, and an exhaust device 30, including a vacuum pump, is connected to the exhaust pipe 31. The exhaust device 30 exhausts the gas in the processing chamber 4, controlling the processing chamber 4 to a specified vacuum atmosphere (e.g., 1.33 Pa). A He gas flow path (not shown) is provided at the lower electrode 23, through which He gas is supplied to the back side of the substrate G placed on the lower electrode 23.

[0035] Each structural component of the plasma processing apparatus 100 is connected to and controlled by a control unit 50, which is composed of a computer. Under the control of the control unit 50, the desired processing is performed in the plasma processing apparatus 100.

[0036] [Impedance Adjustment Circuit]

[0037] Impedance adjustment circuits 18a, 18b, and 18c are connected to the side of the metal window 2 near the antenna chamber 3. Potential detectors C1, C2, and C3 are installed at the connection points that connect the impedance adjustment circuits 18a, 18b, and 18c to the local windows 22a, 22b, and 22c. Thus, potential detectors C1, C2, C3… are arranged one-to-one near each impedance adjustment circuit 18. Potential detectors C1, C2, C3… are collectively referred to as potential detectors VC.

[0038] Impedance adjustment circuits 18a, 18b, and 18c are examples of impedance adjustment units used to adjust the impedance between multiple local windows of the metal window 2 and ground, and are also collectively referred to as impedance adjustment circuit 18.

[0039] Reference Figure 2 and Figure 3 To illustrate impedance adjustment circuit 18. Figure 2 The cross-section of one of the multiple partial windows 22 of the metal window 2 is shown, as well as the impedance adjustment circuit 18 connected to the partial window 22.

[0040] As in Figure 3As shown in the example, the metal window 2 is divided into 24 partial windows 22. These partial windows 22 are portions of the metal window 2, arranged adjacent to each other via an insulator 6, and these partial windows 22 constitute the metal window 2. Each partial window can be, for example, suspended and fixed from the top of the antenna chamber 3 by a support member (not shown). In this example, the top of the processing chamber 4, which is the wall facing the lower electrode 23, i.e., the entire shape of the metal window 2, is rectangular, and divided into an inner peripheral region at the center of the rectangle, an annular middle region, and an annular outer peripheral region. The inner peripheral region has four partial windows 22 obtained by dividing the rectangular inner peripheral region approximately diagonally. The four partial windows 22 of the inner peripheral region are composed of two triangles facing each other with their shorter sides as bases, and two trapezoids facing each other with their longer sides as bases. Furthermore, the intermediate region has a total of eight local windows 22 obtained by dividing the annular intermediate region radially along each edge, and further dividing the annular intermediate region radially by bisecting each edge. Additionally, the outer peripheral region has a total of twelve local windows 22 obtained by dividing the annular outer peripheral region radially along each edge, and further dividing the annular outer peripheral region radially by trisecting each edge. Moreover, in this embodiment, although not shown, the configuration is such that the inner annular antenna corresponds to the inner peripheral region, the middle annular antenna corresponds to the intermediate region, and the outer annular antenna corresponds to the outer peripheral region.

[0041] Each local window 22 is configured via an insulator 6, thus insulated from the processing container 1, and the local windows 22 are also insulated from each other. The material of the insulator 6 is, for example, ceramic or polytetrafluoroethylene (PTFE).

[0042] exist Figure 2 and Figure 3 In the example, one impedance adjustment circuit 18 is provided for each of the local windows 22a, 22b, 22c... That is, in this example, 24 impedance adjustment circuits 18 are connected one-to-one for each of the 24 local windows 22. However, this is not a limitation; one impedance adjustment circuit 18 can also be provided for multiple local windows 22. That is, multiple local windows 22 can be divided into one or more regions, and multiple local windows 22 can be connected to the impedance adjustment circuit in one region or according to each of the multiple regions. For example, one impedance adjustment circuit can be connected to each of the three regions of the 24 local windows 22: the inner peripheral region, the middle region, and the outer peripheral region.

[0043] like Figure 2As shown, the impedance adjustment circuit 18 includes a capacitor element 60 to adjust the impedance between the local window 22 and ground. The impedance adjustment circuit 18 is an R+C parallel circuit with a capacitor element 60 and a resistor element 61. In this example, one capacitor element 60 and one resistor element 61 are connected in parallel with each local window 22. The capacitor element 60 is connected to the local window 22 at one end and to ground at the other end. The resistor element 61 is connected to the local window 22 at one end in parallel with the capacitor element 60 and to ground at the other end.

[0044] Capacitor element 60 can be a variable capacitor element or a fixed capacitor element. However, by making capacitor element 60 a variable capacitor element, the impedance between the metal window 2, which functions as an anode electrode when bias RF power is applied to the lower electrode 23, and ground (hereinafter also referred to as anode impedance) can be adjusted variably, thereby enabling impedance adjustment with higher precision.

[0045] When the impedance adjustment circuit 18 is set up for each of the multiple regions, the capacitor element 60 and the resistor element 61 can also be connected to the multiple local windows 22 for each region. Furthermore, Figure 2 The capacitance component C0 shown represents stray capacitance other than the capacitance component C of capacitor element 60. It is mainly the sum of capacitance components caused by the space between the metal window and other conductive components, which are directly or indirectly connected to ground.

[0046] An insulating temperature-regulating medium flows through the flow path formed in the metal window 2, thereby adjusting the temperature of the metal window 2. Triboelectric charging occurs during the flow of the insulating temperature-regulating medium, and charge accumulates in the metal window 2, resulting in charge buildup. Sometimes, a portion of the electrons in the plasma also accumulates in the metal window 2, causing charge buildup. If the metal window 2 becomes charged, the plasma becomes unstable, affecting the processing of the substrate G. Therefore, it is important to prevent the metal window 2 from accumulating uncontrollable charges. Therefore, the impedance adjustment circuit 18 connects a resistor element 61 in parallel with a capacitor element 60 to the metal window 2. As a result, the charge accumulated in the metal window 2 is released to ground through the resistor element 61, thus eliminating charge buildup caused by uncontrollable charges in the metal window 2 and ensuring plasma stability.

[0047] Potential detectors VC (C1, C2, C3...) are respectively placed near impedance adjustment circuits 18a, 18b, 18c... to detect the potential generated in capacitor element 60 (hereinafter also referred to as capacitor element voltage). Figure 1In the example, potential detector C1 is located near impedance adjustment circuit 18a, potential detector C2 is located near impedance adjustment circuit 18b, and potential detector C3 is located near impedance adjustment circuit 18c. During the processing of the substrate G, potential detectors C1, C2, and C3 measure the potential difference generated by the movement of charge in each capacitor element 60 of the impedance adjustment circuits 18a, 18b, and 18c, and use this difference as the capacitor element voltage.

[0048] According to this structure, high-frequency power for bias voltage is supplied to the lower electrode 23, which serves as the cathode electrode, and the metal window 2 serves as the anode electrode, which is the opposing electrode facing the lower electrode 23. The impedance adjustment circuit 18 adjusts the anode impedance. Thus, the desired potential difference is generated between the metal window 2 and the plasma through the capacitance of the capacitor element 60, thereby enabling the removal of deposits of byproducts adhering to the metal window 2 due to plasma sputtering. Furthermore, when high-frequency power for bias voltage is supplied to the lower electrode 23, although other parts within the processing container 1 can also function as anodes, the metal window 2 is made to function more actively as an anode, strengthening the coupling between the metal window 2 and the cathode electrode, i.e., the lower electrode 23. This suppresses the consumption of other parts within the processing container 1 caused by plasma sputtering.

[0049] If the potential difference in metal window 2 is too large, not only will the byproducts attached to metal window 2 be removed, but metal window 2 itself will also be consumed. If the potential difference is too small, the removal of byproducts attached to metal window 2 will be insufficient. Therefore, it is important to adjust the capacitance of capacitor element 60 within a range that allows for the removal of byproducts attached to metal window 2 while suppressing excessive consumption of metal window 2 and other parts within the processing container 1 during cleaning. This suppresses particulate matter, extends the lifespan of each part, and prolongs the maintenance cycle.

[0050] [Structure of the Control Department]

[0051] Next, refer to Figure 4 and Figure 5 The hardware and functional structure of the control unit 50, which controls the fault detection method of the impedance adjustment circuit 18 described later, will be explained. Figure 4 This is a diagram showing the hardware structure of the control unit 50 involved in the embodiment. Figure 5 This is a diagram showing the functional structure of the control unit 50 involved in the embodiment.

[0052] The control unit 50 includes a CPU (Central Processing Unit) 101, a ROM (Read-Only Memory) 102, a RAM (Random Access Memory) 103, an I / O port 104, an operation panel 105, and an HDD 106 (Hard Disk Drive). All units are connected via bus B.

[0053] The CPU 101 controls various operations and processes of the plasma processing apparatus 100 based on various programs read into the RAM 103, which define the processing procedures for the substrate G, such as etching, film formation, and cleaning. The processing of the substrate G (substrate processing) includes not only plasma treatment of the substrate G, but also electrostatic adsorption treatment such as applying a DC voltage to the adsorption electrode 49 before plasma treatment. The programs include a program for executing a fault detection method. The CPU 101 executes the fault detection method based on these programs read into the RAM 103.

[0054] ROM 102 consists of EEPROM (Electrically Erasable Programmable ROM), flash memory, hard disk, etc., and is the storage medium for storing the program, process, etc. of CPU 101. RAM 103 functions as the working area of ​​CPU 101.

[0055] I / O port 104 acquires values ​​from various sensors installed in the plasma processing apparatus 100, such as those detecting capacitor element voltage, temperature, pressure, and gas flow rate, and sends these values ​​to CPU 101. Additionally, I / O port 104 outputs control signals from CPU 101 to various parts of the plasma processing apparatus 100. Furthermore, an operation panel 105 for operator (user) operation of the plasma processing apparatus 100 is connected to I / O port 104.

[0056] HDD 106 serves as an auxiliary storage device, capable of storing process data, programs, and other information. Additionally, HDD 106 can also retain log information of measurements taken by various sensors.

[0057] illustrate Figure 5The functional structure of the control unit 50 is shown. The control unit 50 is connected to the potential detectors VC, namely 24 potential detectors C1 to C24, via wires. The control unit 50 includes an acquisition unit 51, an A / D conversion unit 52, an anomaly detection and determination unit 53, an anomaly determination unit 54, a display unit 55, a process execution unit 56, and a storage unit 57. The potential detectors VC measure the capacitor element voltage during the processing of the substrate G. Alternatively, the potential detectors VC measure the capacitor element voltage generated in each of the multiple capacitor elements 60 during a processing of the substrate G consisting of multiple processing steps. Or, the potential detectors VC measure the capacitor element voltage throughout one or more of the multiple processing steps of the substrate G.

[0058] The storage unit 57 stores the process settings for processing the substrate G. The storage unit 57 also stores Table 57a (see below) used in the fault detection method described later. Figure 8 ).

[0059] The process execution unit 56 processes the substrate G based on the process. The processing includes electrostatic adsorption processing and plasma processing. During the processing of the substrate G, the process execution unit 56 applies a DC voltage to the adsorption electrode 49 of the electrostatic chuck 48 to perform electrostatic adsorption processing to adsorb the substrate G onto the electrostatic chuck 48, and supplies power supply RF power and bias voltage RF power to perform plasma processing on the substrate G.

[0060] During the processing of the substrate G, the acquisition unit 51 acquires the measured capacitor element voltage from the potential detector VC. For example, the acquisition unit 51 acquires the measured capacitor element voltage and the number (No.) of the impedance adjustment circuit 18 including the corresponding capacitor element 60. The acquisition unit 51 may also acquire the measured capacitor element voltage, the number (No.) of the impedance adjustment circuit 18 including the corresponding capacitor element 60, and the processing step number (No.) of the processing step when the capacitor element voltage is measured.

[0061] The A / D conversion unit 52 converts the analog signal of the capacitor element voltage acquired by the acquisition unit 51 into a digital signal. The anomaly detection and determination unit 53 determines the fault of each impedance adjustment circuit 18 of the plurality of impedance adjustment circuits 18 based on the comparison result of the capacitor element voltage of each capacitor element 60 after digital conversion with a predetermined threshold.

[0062] In the event of a fault, each of the multiple capacitor elements 60 becomes short-circuited. At this time, the local window 22, which is the opposite electrode of the lower electrode 23 to which bias RF power is supplied, becomes substantially grounded relative to the lower electrode due to the short-circuited capacitor element 60. Therefore, when a DC voltage is applied to the electrostatic chuck 48 or when the supply of either the power supply RF power or the bias RF power is initiated, the potential of the local window 22 does not change, and no substantial potential difference is generated across the capacitor element 60. Therefore, if the measured capacitor element voltage is below a threshold, it can be determined that a short circuit (fault) has occurred in the corresponding capacitor element 60.

[0063] The anomaly detection and determination unit 53 may determine the fault of each impedance adjustment circuit 18 of the plurality of impedance adjustment circuits 18 based on at least one or more timing measurements of the capacitor element voltage at the start time of DC voltage application, the start time of power supply RF power supply, the stable supply of power supply RF power, the start time of bias RF power supply, the stable supply of bias RF power, and the stop time of DC voltage application.

[0064] For example, the anomaly detection and determination unit 53 can compare the voltage of each capacitor element 60 connected to the plurality of local windows 22 with a threshold, and determine a fault in each impedance adjustment circuit 18 including each capacitor element 60 based on the comparison result of each capacitor element 60.

[0065] Alternatively, if the voltage of the capacitor element measured during one or more of the multiple processing steps does not exceed the threshold, the anomaly detection determination unit 53 will determine the impedance adjustment circuit 18, which includes the corresponding capacitor element, as faulty.

[0066] The anomaly determination unit 54 can determine the impedance adjustment circuit 18, which includes the capacitor element 60 whose voltage does not exceed a threshold, or the local window 22 connected to the impedance adjustment circuit 18 among a plurality of local windows 22. Therefore, it is possible not only to detect faults in the impedance adjustment circuit 18, but also to determine the part where the fault occurred.

[0067] When the processing of substrate G is completed, the display unit 55 issues an alarm on the operator monitoring screen to notify the operator that an abnormality has occurred during the processing of substrate G. In the case of an unmanned system where no operator monitoring is required, the judgment flag of the faulty impedance adjustment circuit 18 in Table 57a can be rewritten as abnormal and stored in the storage unit 57.

[0068] The control unit 50 can also notify the main computer 59 of the fault in the impedance adjustment circuit 18, as well as the information of the impedance adjustment circuit 18 or the local window 22 that has been determined to be faulty.

[0069] The acquisition unit 51 can be implemented via I / O port 104. The A / D conversion unit 52, the anomaly detection and determination unit 53, the anomaly determination unit 54, and the process execution unit 56 can be implemented via CPU 101 or an A / D conversion circuit embedded in CPU 101. The display unit 55 can be implemented via operation panel 105. The storage unit 57 can be implemented via ROM 102, RAM 103, and HDD 106.

[0070] [Fault Detection Methods]

[0071] Next, refer to Figures 6-8 This will illustrate the fault detection method involved in the implementation method. Figure 6 This is a flowchart illustrating the fault detection method involved in the implementation. Figure 7 This is a diagram illustrating an example of the measurement results of the voltage of the capacitor element involved in the embodiment. Figure 8 Is Figure 6 Table 57a, used in the fault detection method, stores the voltage (MAX value) of the capacitor element and the judgment result.

[0072] Figure 6 The fault detection method is executed by the respective units of the control unit 50. The fault detection method is started in parallel when the process execution unit 56 starts processing of the substrate G. When processing of the substrate G starts according to the process, in step S1, the process execution unit 56 prepares the lower electrode 23 to place the substrate G in the processing container 1. When processing of the substrate G starts, the potential detectors VC (potential detectors C1, C2, C3...) measure the voltage of the capacitor elements near each of the impedance adjustment circuits 18 (impedance adjustment circuits 18a, 18b, 18c...).

[0073] Next, in step S3, the process execution unit 56 applies a DC voltage to the adsorption electrode 49 of the electrostatic chuck 48. As a result, the substrate G is held in place by electrostatic adsorption on the electrostatic chuck 48.

[0074] Next, in step S5, the process execution unit 56 initiates the supply of at least one of the power supply RF power and the bias RF power. Depending on the contents of the processing substrate G, the supply of the power supply RF power and the bias RF power can be initiated simultaneously or either one can be initiated first. Next, in step S7, the process execution unit 56 uses the power supply RF power supplied to the antenna chamber 3 to plasmaize the gas supplied from the processing gas supply unit 20, generating inductively coupled plasma, and performs plasma processing on the substrate G.

[0075] Next, in step S9, the acquisition unit 51 acquires the capacitor element voltage as the potential detection value measured by the potential detector VC. The acquisition unit 51 acquires the voltages of the 24 capacitor elements measured by the 24 potential detectors VC. Furthermore, in Figure 6 For ease of illustration, step S9 is depicted as being performed simultaneously with or immediately after step S7. However, in reality, the acquisition of capacitor element voltages begins at least simultaneously with or before step S3. The acquisition unit 51 periodically or irregularly acquires the capacitor element voltages, i.e., the voltages of the 24 capacitor elements, from the potential detectors VC respectively located near the impedance adjustment circuit 18.

[0076] Next, in step S11, the A / D conversion unit 52 converts the analog signal of the capacitor element voltage acquired by the acquisition unit 51 into a digital signal.

[0077] Next, in step S13, the anomaly detection determination unit 53 determines whether the digitally converted capacitor voltage is greater than the capacitor voltage MAX value. The initial value of the capacitor voltage MAX value (hereinafter also simply referred to as MAX value) is set to 0 for each potential detector of the potential detector VC. If the anomaly detection determination unit 53 determines that the capacitor voltage is below the MAX value, it skips step S15 and proceeds to step 17. If the anomaly detection determination unit 53 determines that the capacitor voltage is greater than the MAX value, it updates the MAX value to the value of the capacitor voltage. Therefore, the maximum value of the capacitor voltage measured by the potential detector VC during the substrate processing is stored in the storage unit 57 as the capacitor voltage MAX value (see reference). Figure 8 ).

[0078] Next, in step S17, the anomaly detection determination unit 53 determines whether the processing step has ended. If the anomaly detection determination unit 53 determines that the processing step has not ended, it returns to step S9 and repeats the processing of steps S9 to S15. Thus, the maximum value of the capacitor element voltage measured by the potential detector VC during the substrate processing in each processing step is stored in the MAX value at that time point.

[0079] If the anomaly detection determination unit 53 determines that the processing step has ended, it proceeds to step S19 to determine whether the processing of the substrate G has ended. If the anomaly detection determination unit 53 determines that the processing of the substrate G has not ended, it returns to step S9 and repeats the processing of steps S9 to S15 for the next processing step. Therefore, the maximum value of the capacitor element voltage measured by the potential detector VC during the substrate processing in the next processing step is stored as the capacitor element voltage MAX value for the next processing step.

[0080] If the anomaly detection determination unit 53 determines that the processing of the substrate G has ended, it proceeds to step S21 and executes... Figure 9 The abnormality determination and handling are shown, and this process ends.

[0081] For example, in Figure 7 In the example shown, the processing of substrate G consists of processing steps 1 and 2. Processing step 1 includes plasma processing, and processing step 2 includes de-energizing processing of substrate G and the like. Figure 7 The horizontal axis shows the time from the start of substrate processing at 0 seconds, and the vertical axis (left) shows the power supply RF power and bias RF power, as well as the DC voltage (V). Figure 7 The vertical axis (right) shows the capacitor element voltage (V) measured at each time point shown on the horizontal axis.

[0082] In processing step 1, at the beginning of substrate processing (0 seconds), at the point in time when a DC voltage is supplied to the electrostatic chuck 48 as shown by line d, the voltage of the capacitor element shown by line e changes. This is as follows: since the capacitor element 60 is not short-circuited but normal, the potential detector VC detects the movement of charge charging the capacitor element 60 due to the change in the DC voltage at the point of application of the DC voltage, and measures it as the capacitor element voltage.

[0083] The power supply RF power, shown by line a, begins to be supplied at time t1 and continues until time t4. Similarly, the bias RF power, shown by line b, begins to be supplied at time t2 and continues until time t4. The potential detector VC detects the changes in RF power at the power supply RF power supply time point, the bias RF power supply time point, and the time points t1 to t2 in between, to determine the voltage of the capacitor element shown by line e.

[0084] Time intervals t3 to t4 represent the stable supply of RF power (as shown in line a) and the stable supply of bias RF power (as shown in line b). The potential detector VC measures the voltage of the capacitor element (as shown in line e) between time intervals t3 and t4.

[0085] The output of the potential detector VC includes information such as the processing step number (No.), the impedance adjustment circuit number (No.), and the measured voltage of the capacitive element. The acquisition unit 51 acquires this information. For example... Figure 8 As shown, in the storage unit 57, the impedance adjustment circuit number (No.) of each of the 24 impedance adjustment circuits 18 is stored, corresponding to the processing step number (No.), and the impedance adjustment circuit number (No.) of each impedance adjustment circuit 18 is also stored. Figure 6 The MAX value of the capacitor element voltage is obtained through processing.

[0086] exist Figure 7In processing step 1, for the capacitor element voltage MAX value, the capacitor element voltage (approximately 80V) shown on line e immediately following the start of substrate processing is stored as the capacitor element voltage MAX value.

[0087] The capacitor voltage measured in step 2 is also processed by... Figure 6 The processing is used to store the MAX value of the capacitor element voltage in the storage unit 57. In processing step 2, at the time point t5 when the DC voltage supplied to the electrostatic chuck 48 stops being applied, at the time point t6 when the power supply RF starts being supplied, and at the time point when the power supply RF is stably supplied, the voltage of the capacitor element shown on the line e by the potential detector VC measures.

[0088] exist Figure 7 In processing step 2, for the MAX value of the capacitor element voltage, the capacitor element voltage shown on line e at the DC voltage application stop time point t5 is stored as the MAX value of the capacitor element voltage. Sometimes the capacitor element voltage measured by the potential detector VC has a negative value. Therefore, in Figure 6 The capacitor voltage used in the processing refers to the absolute value of the capacitor voltage. That is to say, in... Figure 7 In processing step 2, the absolute value of the capacitor element voltage (approximately 40V) supplied at the stop time point t5 is stored as the capacitor element voltage MAX value.

[0089] Alternatively, the maximum value of the capacitor element voltage can be calculated without dividing it into processing steps 1 and 2. Alternatively, the maximum value of the capacitor element voltage can be calculated for each impedance adjustment circuit 18 of the impedance adjustment circuit 18 at the end of the substrate processing and stored in the storage unit 57.

[0090] In this way, the potential detector VC outputs a potential difference as the voltage of the capacitor element. This potential difference is generated by the movement of charge charging the capacitor element 60 in response to the transient phenomena of the DC voltage supplied to the electrostatic chuck 48, the power supply RF power, and the bias RF power.

[0091] Therefore, if the maximum voltage value of the capacitor element is greater than a predetermined threshold, it can be determined that the capacitor element 60 is not short-circuited and is normal. On the other hand, if the maximum voltage value of the capacitor element is lower than the predetermined threshold, it can be determined that the capacitor element 60 is short-circuited and is abnormal. For example, although in Figure 7 The threshold is not shown in the figure, but considering noise, the threshold can be a value greater than 0 volts and less than a few volts. The voltage of the capacitor element in line f is 0 in processing steps 1 and 2. In this case, it is determined that the capacitor element 60 of the impedance adjustment circuit 18 (near the measured potential detector VC) is short-circuited and abnormal.

[0092] In the anomaly determination method described below, the normality or abnormality of capacitor element 60 (impedance adjustment circuit 18) is determined based on whether there is a change in the capacitor element voltage in response to the transient phenomenon. Furthermore, it is preferable to... Figure 6 As shown, the anomaly detection method is performed after the substrate is processed, but it can also be performed at the end of each processing step.

[0093] [Anomaly Detection Method]

[0094] Figure 9 This is a flowchart illustrating the anomaly determination method involved in the implementation method. Figure 9 The anomaly detection method is through Figure 6 Step S21 is initiated upon recall. That is, it begins when it is determined that the processing of substrate G has ended. Figure 9 The execution of the exception detection method.

[0095] In step S23, the anomaly detection determination unit 53 determines whether all impedance adjustment circuits 18 have been determined. If the determination is "no" during the first execution of step S23, the process proceeds to step S25, where the anomaly detection determination unit 53 determines whether the MAX value of the capacitor element of the undetermined impedance adjustment circuit 18 is above a predetermined threshold. Here, the MAX value of the capacitor element refers to its absolute value.

[0096] In step S25, if the anomaly detection determination unit 53 determines that the MAX value of the capacitor element voltage is above a predetermined threshold, it proceeds to step S27 and determines that the impedance adjustment circuit 18 is normal. The storage unit 57 stores a "0" indicating normal in the determination flag corresponding to the impedance adjustment circuit 18 in the determination flags of Table 57a, and returns to step S23.

[0097] In step S25, if the anomaly detection determination unit 53 determines that the MAX value of the capacitor element voltage is lower than a predetermined threshold, it proceeds to step S29 and determines that the impedance adjustment circuit 18 is abnormal. The storage unit 57 stores a "1" indicating an anomaly in the determination flag corresponding to the impedance adjustment circuit 18 in the determination flags of Table 57a, and returns to step S23.

[0098] In step S23, the anomaly detection determination unit 53 repeats the processing of steps S25 to S29 until it is determined that the determination of the MAX value of the capacitor element corresponding to all impedance adjustment circuits 18 has been completed. In step S23, if the anomaly detection determination unit 53 determines that the determination of all impedance adjustment circuits 18 has been completed, it proceeds to step S31 and extracts the determination flags of all processing steps for each impedance adjustment circuit 18.

[0099] Next, in step S33, the anomaly detection determination unit 53 determines for each impedance adjustment circuit 18 whether the values ​​of the determination flags for all processing steps are all 1. The anomaly detection determination unit 53 can refer to Table 57a in the storage unit 57 to determine whether all determination flags for each impedance adjustment circuit 18 are 1. If the anomaly detection determination unit 53 determines that all determination flags are 1, it proceeds to step S37, determines that the impedance adjustment circuit 18 is abnormal, and identifies the part where the anomaly has been found. As the part where the anomaly has been found, it can determine either the number of the impedance adjustment circuit 18 with the determination flag "1" or the local window 22 where the impedance adjustment circuit 18 with the determination flag "1" is installed. The processing step number can also be determined together with this information.

[0100] Next, in step S39, the anomaly detection and determination unit 53 notifies the anomaly and ends the process. As an example of notifying an anomaly, the anomaly detection and determination unit 53 notifies the host computer 59 of an anomaly in the impedance adjustment circuit 18 and information about the local window 22 where the anomaly was detected. As another example of notifying an anomaly, the display unit 55 issues an alarm on the operator-monitored screen to notify the operator. In the case of an unmanned system where the operator is not monitoring, the anomaly detection and determination unit 53 may also send table 57a to the host computer 59 or other devices to notify of a fault.

[0101] In step S33, if the anomaly detection determination unit 53 determines that at least one of the determination flags of all processing steps is 0 for each impedance adjustment circuit 18, it proceeds to step S35, determines that the impedance adjustment circuit 18 is normal, and ends the processing.

[0102] In the above-described anomaly determination method, the impedance adjustment circuit 18 is determined to be abnormal only when the flag indicates an anomaly in all processing steps, but it is not limited to this. The impedance adjustment section 18 of a capacitor element whose capacitor element voltage does not exceed a threshold value during the entire period of one or more processing steps may also be determined to be faulty. For example, in a substrate processing consisting of multiple processing steps, the impedance adjustment circuit 18 may also be determined to be abnormal when the flag indicates an anomaly in one processing step.

[0103] As explained above, the fault detection method and plasma processing apparatus of this embodiment can detect faults in the impedance adjustment circuit 18 of the plasma processing apparatus 100. Furthermore, it is possible to identify the faulty impedance adjustment circuit 18 or to provide a local window 22 for the faulty impedance adjustment circuit 18.

[0104] For example, if the capacitor element voltage is measured by detecting the potential difference generated in capacitor element 60 corresponding to one of the three transient phenomena (the start of DC voltage application, the start of power supply RF power supply, and the start of bias RF power supply), the two stable RF power supplies (stable power supply RF power supply and stable bias RF power supply), and the cessation of DC voltage application using a potential detector VC, then misjudgments may occur in determining normal and abnormal conditions. However, in the fault detection method described above, in Figure 7 In the example of processing step 1, the voltage of the capacitor element is measured by detecting the potential difference generated in the capacitor element 60 corresponding to three transient phenomena—the start of applying DC voltage to the electrostatic chuck, the start of supplying power RF, and the start of supplying bias RF—as well as the two stable RF supplies—the stable supply of power RF and the stable supply of bias RF. Figure 7 In the example of processing step 2, the capacitor element voltage is measured by detecting the potential difference generated in the capacitor element 60 corresponding to the two transient phenomena of the cessation of the application of DC voltage supplied to the electrostatic chuck and the start of the supply of RF power by the potential detector VC. Therefore, according to the fault detection method and anomaly determination method of this embodiment, the capacitor element voltage is measured by detecting at least two transient phenomena of DC voltage and multiple RF powers by the potential detector VC. As a result, faults in the impedance adjustment circuit 18 can be detected with high accuracy.

[0105] It should be considered that all aspects of the fault detection method and plasma processing apparatus disclosed herein are illustrative rather than limiting. The embodiments can be modified and improved in various ways without departing from the appended claims and their spirit. The matters described in the above embodiments can be further structured in other ways without contradiction, and can also be combined without contradiction.

[0106] In the plasma processing apparatus 100 disclosed herein, the objects subjected to plasma processing can be, for example, a 1.5m × 1.85m substrate G to be processed and rectangular substrates G of other sizes, but are not limited thereto, and can also be various components such as disk-shaped wafers.

[0107] Explanation of reference numerals in the attached figures

[0108] 1: Processing container; 2: Metal window; 3: Antenna chamber; 4: Processing chamber; 6: Insulator; 13: High-frequency antenna; 15: First high-frequency power supply; 16: Power supply component; 18: Impedance adjustment circuit; 20: Processing gas supply unit; 22: Local window; 23: Lower electrode; 29: Second high-frequency power supply; 30: Exhaust device; 32: Partition; 60: Capacitor element; 61: Resistor element; G: Processed substrate; C1, C2, C3: Potential detectors; ST: Worktable.

Claims

1. A fault detection method for detecting faults in multiple impedance adjustment sections of a plasma processing apparatus, the plasma processing apparatus comprising: a processing container; A metal window that divides the interior of the processing container into an antenna chamber and a processing chamber, the metal window having multiple partial windows; an inductively coupled antenna for generating inductively coupled plasma using high-frequency power supplied to the antenna chamber; An electrostatic chuck is used to electrostatically attract a substrate to be processed within the processing chamber; and a lower electrode supports the electrostatic chuck, the lower electrode being supplied with a bias voltage using high-frequency power. The plurality of impedance adjustment sections include a plurality of capacitive elements disposed between the plurality of local windows and ground, for adjusting the impedance between the plurality of local windows and ground. The fault detection method includes the following steps: Apply a DC voltage to the electrostatic chuck; Start supplying at least one of the high-frequency power for the power supply and the high-frequency power for the bias voltage; A stable supply of high-frequency power for the power source and high-frequency power for the bias voltage is provided; During the processing of the substrate being processed, the capacitor voltage generated in each of the plurality of capacitor elements is measured; and The fault of the plurality of impedance adjustment units is determined based on the comparison result of the capacitor voltage of each capacitor element with a predetermined threshold.

2. The fault detection method according to claim 1, characterized in that, Each of the multiple capacitor elements becomes short-circuited in the event of a fault. In the fault determination process, the impedance adjustment section, which includes the capacitor element whose voltage does not exceed the threshold, is determined to be faulty.

3. The fault detection method according to claim 2, characterized in that, In the process of measuring the voltage of the capacitor element, during the processing of the substrate consisting of multiple processing steps, the voltage generated in each of the plurality of capacitor elements is measured. In the fault determination process, the impedance adjustment section of a capacitor element whose voltage does not exceed the threshold value during the entire period of one or more of the plurality of processing steps is determined to be faulty.

4. The fault detection method according to any one of claims 1 to 3, characterized in that, In the fault determination process, the fault of the plurality of impedance adjustment units is determined based on the voltage of the capacitor element measured at at least one or two of the following time points: the start time of the DC voltage application, the start time of the high-frequency power supply, the stable supply of the high-frequency power supply, the start time of the high-frequency power supply for the bias voltage, the stable supply of the high-frequency power supply for the bias voltage, and the stop time of the DC voltage application.

5. The fault detection method according to any one of claims 1 to 3, characterized in that, In the fault determination process, for each of the capacitor elements connected to the plurality of local windows, the voltage of the capacitor element is compared with the threshold, and based on the comparison result of each capacitor element, a fault is determined for each of the impedance adjustment units including the capacitor element.

6. The fault detection method according to any one of claims 1 to 3, characterized in that, Identify the local window among the plurality of local windows that is connected to the capacitor element whose voltage does not exceed the threshold.

7. A plasma processing apparatus, comprising: A processing container; a metal window that divides the interior of the processing container into an antenna chamber and a processing chamber, the metal window having multiple partial windows; an inductively coupled antenna for generating inductively coupled plasma using high-frequency power supplied to the antenna chamber; An electrostatic chuck is provided in the processing chamber to electrostatically attract the substrate to be processed; a lower electrode supports the electrostatic chuck and is supplied with a bias voltage using high-frequency power; multiple impedance adjustment units, each including multiple capacitive elements disposed between the multiple local windows and ground, are used to adjust the impedance between the multiple local windows and ground; and a control unit is provided. The control unit controls the following processes: Apply a DC voltage to the electrostatic chuck; Start supplying at least one of the high-frequency power for the power supply and the high-frequency power for the bias voltage; A stable supply of high-frequency power for the power source and high-frequency power for the bias voltage is provided; During the processing of the substrate being processed, the capacitor voltage generated in each of the plurality of capacitor elements is measured; and The fault of the plurality of impedance adjustment units is determined based on the comparison result of the capacitor voltage of each capacitor element with a predetermined threshold.

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